1
//===- TableGen'erated file -------------------------------------*- C++ -*-===//
3
// Assembly Writer Source Fragment
5
// Automatically generated file, do not edit!
7
//===----------------------------------------------------------------------===//
9
/// printInstruction - This method is automatically generated by tablegen
10
/// from the instruction set description.
11
void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
12
static const unsigned OpInfo[] = {
23
0U, // COPY_TO_REGCLASS
37
69206046U, // ADJCALLSTACKDOWN
38
69206066U, // ADJCALLSTACKUP
42
271056968U, // ATOMIC_CMP_SWAP_I16
43
271581256U, // ATOMIC_CMP_SWAP_I32
44
272105544U, // ATOMIC_CMP_SWAP_I8
45
272629832U, // ATOMIC_LOAD_ADD_I16
46
273154120U, // ATOMIC_LOAD_ADD_I32
47
273678408U, // ATOMIC_LOAD_ADD_I8
48
274202696U, // ATOMIC_LOAD_AND_I16
49
274726984U, // ATOMIC_LOAD_AND_I32
50
275251272U, // ATOMIC_LOAD_AND_I8
51
275775560U, // ATOMIC_LOAD_NAND_I16
52
276299848U, // ATOMIC_LOAD_NAND_I32
53
276824136U, // ATOMIC_LOAD_NAND_I8
54
277348424U, // ATOMIC_LOAD_OR_I16
55
277872712U, // ATOMIC_LOAD_OR_I32
56
278397000U, // ATOMIC_LOAD_OR_I8
57
278921288U, // ATOMIC_LOAD_SUB_I16
58
279445576U, // ATOMIC_LOAD_SUB_I32
59
279969864U, // ATOMIC_LOAD_SUB_I8
60
280494152U, // ATOMIC_LOAD_XOR_I16
61
281018440U, // ATOMIC_LOAD_XOR_I32
62
281542728U, // ATOMIC_LOAD_XOR_I8
63
282067016U, // ATOMIC_SWAP_I16
64
282591304U, // ATOMIC_SWAP_I32
65
283115592U, // ATOMIC_SWAP_I8
76
337150054U, // BL_pred
78
337150054U, // BLr9_pred
80
67108973U, // BR_JTadd
100
806903994U, // CMPzrs
101
872415304U, // CONSTPOOL_ENTRY
121
755556676U, // FCONSTD
122
756080964U, // FCONSTS
123
555221321U, // FMSTAT
125
85983570U, // Int_MemBarrierV6
126
351U, // Int_MemBarrierV7
127
86507858U, // Int_SyncBarrierV6
128
355U, // Int_SyncBarrierV7
129
87032167U, // Int_eh_sjlj_setjmp
130
221831537U, // LDC2L_OFFSET
131
825819505U, // LDC2L_OPTION
132
221839729U, // LDC2L_POST
133
221831537U, // LDC2L_PRE
134
217653617U, // LDC2_OFFSET
135
821633393U, // LDC2_OPTION
136
217653617U, // LDC2_POST
137
217653617U, // LDC2_PRE
138
221831542U, // LDCL_OFFSET
139
825819510U, // LDCL_OPTION
140
221839734U, // LDCL_POST
141
221831542U, // LDCL_PRE
142
217653622U, // LDC_OFFSET
143
821633398U, // LDC_OPTION
144
217653622U, // LDC_POST
145
217653622U, // LDC_PRE
147
1027686778U, // LDM_RET
151
202924418U, // LDRB_POST
152
202924418U, // LDRB_PRE
154
605577613U, // LDRD_POST
155
605577613U, // LDRD_PRE
157
739795352U, // LDREXB
158
135815583U, // LDREXD
159
739795366U, // LDREXH
162
202924461U, // LDRH_POST
163
202924461U, // LDRH_PRE
165
202924478U, // LDRSBT
166
202924472U, // LDRSB_POST
167
202924472U, // LDRSB_PRE
169
202924491U, // LDRSHT
170
202924485U, // LDRSH_POST
171
202924485U, // LDRSH_PRE
173
202924414U, // LDR_POST
174
202924414U, // LDR_PRE
176
1095238103U, // LEApcrel
177
1095762391U, // LEApcrelJT
184
135815677U, // MOVCCi
185
135815677U, // MOVCCr
186
202924541U, // MOVCCs
187
135815681U, // MOVTi16
189
739795462U, // MOVi16
190
739795453U, // MOVi2pieces
191
739795462U, // MOVi32imm
195
739795467U, // MOVsra_flag
196
739795467U, // MOVsrl_flag
202
337142312U, // MRSsys
205
359686700U, // MSRsys
206
359768620U, // MSRsysi
215
1165492800U, // PICADD
216
1233125952U, // PICLDR
217
1233650240U, // PICLDRB
218
1234174528U, // PICLDRH
219
1234698816U, // PICLDRSB
220
1235223104U, // PICLDRSH
221
1235747392U, // PICSTR
222
1236271680U, // PICSTRB
223
1236795968U, // PICSTRH
233
135815798U, // QADD16
240
135815838U, // QSUB16
248
135815876U, // RSBSri
249
202924740U, // RSBSrs
256
135815895U, // SADD16
259
67109609U, // SBCSSri
260
67109609U, // SBCSSrr
261
67109609U, // SBCSSrs
270
135815956U, // SHADD16
271
135815964U, // SHADD8
274
135815983U, // SHSUB16
275
135815991U, // SHSUB8
277
806904642U, // SMLABB
278
806904649U, // SMLABT
280
806904662U, // SMLADX
282
806904675U, // SMLALBB
283
806904683U, // SMLALBT
284
806904691U, // SMLALD
285
806904698U, // SMLALDX
286
806904706U, // SMLALTB
287
806904714U, // SMLALTT
288
806904722U, // SMLATB
289
806904729U, // SMLATT
290
806904736U, // SMLAWB
291
806904743U, // SMLAWT
293
806904756U, // SMLSDX
294
806904763U, // SMLSLD
295
806904770U, // SMLSLDX
297
806904784U, // SMMLAR
299
806904797U, // SMMLSR
301
135816170U, // SMMULR
303
135816183U, // SMUADX
304
135816190U, // SMULBB
305
135816197U, // SMULBT
307
135816210U, // SMULTB
308
135816217U, // SMULTT
309
135816224U, // SMULWB
310
135816231U, // SMULWT
312
135816244U, // SMUSDX
315
135816255U, // SSAT16
316
806904902U, // SSATasr
317
806904902U, // SSATlsl
319
135816272U, // SSUB16
321
221832285U, // STC2L_OFFSET
322
825820253U, // STC2L_OPTION
323
221840477U, // STC2L_POST
324
221832285U, // STC2L_PRE
325
217654365U, // STC2_OFFSET
326
821634141U, // STC2_OPTION
327
217654365U, // STC2_POST
328
217654365U, // STC2_PRE
329
221832290U, // STCL_OFFSET
330
825820258U, // STCL_OPTION
331
221840482U, // STCL_POST
332
221832290U, // STCL_PRE
333
217654370U, // STC_OFFSET
334
821634146U, // STC_OPTION
335
217654370U, // STC_POST
336
217654370U, // STC_PRE
341
202900590U, // STRB_POST
342
202900590U, // STRB_PRE
344
605553785U, // STRD_POST
345
605553785U, // STRD_PRE
347
135816324U, // STREXB
348
806904971U, // STREXD
349
135816338U, // STREXH
352
202900633U, // STRH_POST
353
202900633U, // STRH_PRE
355
202900586U, // STR_POST
356
202900586U, // STR_PRE
357
135816361U, // SUBSri
358
135816361U, // SUBSrr
359
202925225U, // SUBSrs
366
135816383U, // SXTAB16rr
367
806905023U, // SXTAB16rr_rot
368
135816391U, // SXTABrr
369
806905031U, // SXTABrr_rot
370
135816397U, // SXTAHrr
371
806905037U, // SXTAHrr_rot
372
739796179U, // SXTB16r
373
135816403U, // SXTB16r_rot
375
135816410U, // SXTBr_rot
377
135816415U, // SXTHr_rot
386
135816452U, // UADD16
390
135816475U, // UHADD16
391
135816483U, // UHADD8
394
135816502U, // UHSUB16
395
135816510U, // UHSUB8
399
135816535U, // UQADD16
400
135816543U, // UQADD8
403
135816562U, // UQSUB16
404
135816570U, // UQSUB8
406
806905223U, // USADA8
407
135816590U, // USAT16
408
806905237U, // USATasr
409
806905237U, // USATlsl
411
135816607U, // USUB16
413
135816620U, // UXTAB16rr
414
806905260U, // UXTAB16rr_rot
415
135816628U, // UXTABrr
416
806905268U, // UXTABrr_rot
417
135816634U, // UXTAHrr
418
806905274U, // UXTAHrr_rot
419
739796416U, // UXTB16r
420
135816640U, // UXTB16r_rot
422
135816647U, // UXTBr_rot
424
135816652U, // UXTHr_rot
425
835732945U, // VABALsv2i64
426
836257233U, // VABALsv4i32
427
836781521U, // VABALsv8i16
428
837305809U, // VABALuv2i64
429
837830097U, // VABALuv4i32
430
838354385U, // VABALuv8i16
431
836781527U, // VABAsv16i8
432
835732951U, // VABAsv2i32
433
836257239U, // VABAsv4i16
434
835732951U, // VABAsv4i32
435
836257239U, // VABAsv8i16
436
836781527U, // VABAsv8i8
437
838354391U, // VABAuv16i8
438
837305815U, // VABAuv2i32
439
837830103U, // VABAuv4i16
440
837305815U, // VABAuv4i32
441
837830103U, // VABAuv8i16
442
838354391U, // VABAuv8i8
443
164627932U, // VABDLsv2i64
444
165152220U, // VABDLsv4i32
445
165676508U, // VABDLsv8i16
446
166200796U, // VABDLuv2i64
447
166725084U, // VABDLuv4i32
448
167249372U, // VABDLuv8i16
449
152102370U, // VABDfd
450
152102370U, // VABDfq
451
165676514U, // VABDsv16i8
452
164627938U, // VABDsv2i32
453
165152226U, // VABDsv4i16
454
164627938U, // VABDsv4i32
455
165152226U, // VABDsv8i16
456
165676514U, // VABDsv8i8
457
167249378U, // VABDuv16i8
458
166200802U, // VABDuv2i32
459
166725090U, // VABDuv4i16
460
166200802U, // VABDuv4i32
461
166725090U, // VABDuv8i16
462
167249378U, // VABDuv8i8
465
756082151U, // VABSfd
466
756082151U, // VABSfd_sfp
467
756082151U, // VABSfq
468
769656295U, // VABSv16i8
469
768607719U, // VABSv2i32
470
769132007U, // VABSv4i16
471
768607719U, // VABSv4i32
472
769132007U, // VABSv8i16
473
769656295U, // VABSv8i8
474
152102380U, // VACGEd
475
152102380U, // VACGEq
476
152102386U, // VACGTd
477
152102386U, // VACGTq
479
167773693U, // VADDHNv2i32
480
168297981U, // VADDHNv4i16
481
168822269U, // VADDHNv8i8
482
164627972U, // VADDLsv2i64
483
165152260U, // VADDLsv4i32
484
165676548U, // VADDLsv8i16
485
166200836U, // VADDLuv2i64
486
166725124U, // VADDLuv4i32
487
167249412U, // VADDLuv8i16
489
164627978U, // VADDWsv2i64
490
165152266U, // VADDWsv4i32
491
165676554U, // VADDWsv8i16
492
166200842U, // VADDWuv2i64
493
166725130U, // VADDWuv4i32
494
167249418U, // VADDWuv8i16
495
152102392U, // VADDfd
496
152102392U, // VADDfd_sfp
497
152102392U, // VADDfq
498
169346552U, // VADDv16i8
499
167773688U, // VADDv1i64
500
168297976U, // VADDv2i32
501
167773688U, // VADDv2i64
502
168822264U, // VADDv4i16
503
168297976U, // VADDv4i32
504
168822264U, // VADDv8i16
505
169346552U, // VADDv8i8
516
152102441U, // VCEQfd
517
152102441U, // VCEQfq
518
169346601U, // VCEQv16i8
519
168298025U, // VCEQv2i32
520
168822313U, // VCEQv4i16
521
168298025U, // VCEQv4i32
522
168822313U, // VCEQv8i16
523
169346601U, // VCEQv8i8
524
773326377U, // VCEQzv16i8
525
756082217U, // VCEQzv2f32
526
772277801U, // VCEQzv2i32
527
756082217U, // VCEQzv4f32
528
772802089U, // VCEQzv4i16
529
772277801U, // VCEQzv4i32
530
772802089U, // VCEQzv8i16
531
773326377U, // VCEQzv8i8
532
152102446U, // VCGEfd
533
152102446U, // VCGEfq
534
165676590U, // VCGEsv16i8
535
164628014U, // VCGEsv2i32
536
165152302U, // VCGEsv4i16
537
164628014U, // VCGEsv4i32
538
165152302U, // VCGEsv8i16
539
165676590U, // VCGEsv8i8
540
167249454U, // VCGEuv16i8
541
166200878U, // VCGEuv2i32
542
166725166U, // VCGEuv4i16
543
166200878U, // VCGEuv4i32
544
166725166U, // VCGEuv8i16
545
167249454U, // VCGEuv8i8
546
769656366U, // VCGEzv16i8
547
756082222U, // VCGEzv2f32
548
768607790U, // VCGEzv2i32
549
756082222U, // VCGEzv4f32
550
769132078U, // VCGEzv4i16
551
768607790U, // VCGEzv4i32
552
769132078U, // VCGEzv8i16
553
769656366U, // VCGEzv8i8
554
152102451U, // VCGTfd
555
152102451U, // VCGTfq
556
165676595U, // VCGTsv16i8
557
164628019U, // VCGTsv2i32
558
165152307U, // VCGTsv4i16
559
164628019U, // VCGTsv4i32
560
165152307U, // VCGTsv8i16
561
165676595U, // VCGTsv8i8
562
167249459U, // VCGTuv16i8
563
166200883U, // VCGTuv2i32
564
166725171U, // VCGTuv4i16
565
166200883U, // VCGTuv4i32
566
166725171U, // VCGTuv8i16
567
167249459U, // VCGTuv8i8
568
769656371U, // VCGTzv16i8
569
756082227U, // VCGTzv2f32
570
768607795U, // VCGTzv2i32
571
756082227U, // VCGTzv4f32
572
769132083U, // VCGTzv4i16
573
768607795U, // VCGTzv4i32
574
769132083U, // VCGTzv8i16
575
769656371U, // VCGTzv8i8
576
769656376U, // VCLEzv16i8
577
756082232U, // VCLEzv2f32
578
768607800U, // VCLEzv2i32
579
756082232U, // VCLEzv4f32
580
769132088U, // VCLEzv4i16
581
768607800U, // VCLEzv4i32
582
769132088U, // VCLEzv8i16
583
769656376U, // VCLEzv8i8
584
769656381U, // VCLSv16i8
585
768607805U, // VCLSv2i32
586
769132093U, // VCLSv4i16
587
768607805U, // VCLSv4i32
588
769132093U, // VCLSv8i16
589
769656381U, // VCLSv8i8
590
769656386U, // VCLTzv16i8
591
756082242U, // VCLTzv2f32
592
768607810U, // VCLTzv2i32
593
756082242U, // VCLTzv4f32
594
769132098U, // VCLTzv4i16
595
768607810U, // VCLTzv4i32
596
769132098U, // VCLTzv8i16
597
769656386U, // VCLTzv8i8
598
773326407U, // VCLZv16i8
599
772277831U, // VCLZv2i32
600
772802119U, // VCLZv4i16
601
772277831U, // VCLZv4i32
602
772802119U, // VCLZv8i16
603
773326407U, // VCLZv8i8
605
755557969U, // VCMPED
606
756082257U, // VCMPES
607
352962129U, // VCMPEZD
608
353486417U, // VCMPEZS
610
352962124U, // VCMPZD
611
353486412U, // VCMPZS
614
774375004U, // VCVTBHS
615
774899292U, // VCVTBSH
616
775423586U, // VCVTDS
617
775947874U, // VCVTSD
618
774375015U, // VCVTTHS
619
774899303U, // VCVTTSH
620
776595042U, // VCVTf2sd
621
776595042U, // VCVTf2sd_sfp
622
776595042U, // VCVTf2sq
623
777119330U, // VCVTf2ud
624
777119330U, // VCVTf2ud_sfp
625
777119330U, // VCVTf2uq
626
172549730U, // VCVTf2xsd
627
172549730U, // VCVTf2xsq
628
173074018U, // VCVTf2xud
629
173074018U, // VCVTf2xuq
630
777643618U, // VCVTs2fd
631
777643618U, // VCVTs2fd_sfp
632
777643618U, // VCVTs2fq
633
778167906U, // VCVTu2fd
634
778167906U, // VCVTu2fd_sfp
635
778167906U, // VCVTu2fq
636
173598306U, // VCVTxs2fd
637
173598306U, // VCVTxs2fq
638
174122594U, // VCVTxu2fd
639
174122594U, // VCVTxu2fq
642
778593906U, // VDUP16d
643
778593906U, // VDUP16q
644
779118194U, // VDUP32d
645
779118194U, // VDUP32q
646
773875314U, // VDUP8d
647
773875314U, // VDUP8q
648
174614130U, // VDUPLN16d
649
174614130U, // VDUPLN16q
650
175138418U, // VDUPLN32d
651
175138418U, // VDUPLN32q
652
169895538U, // VDUPLN8d
653
169895538U, // VDUPLN8q
654
175138418U, // VDUPLNfd
655
175138418U, // VDUPLNfq
656
779118194U, // VDUPfd
657
779118194U, // VDUPfdf
658
779118194U, // VDUPfq
659
779118194U, // VDUPfqf
662
845702780U, // VEXTd16
663
846227068U, // VEXTd32
664
840984188U, // VEXTd8
665
846227068U, // VEXTdf
666
845702780U, // VEXTq16
667
846227068U, // VEXTq32
668
840984188U, // VEXTq8
669
846227068U, // VEXTqf
670
175137092U, // VGETLNi32
671
165151044U, // VGETLNs16
672
165675332U, // VGETLNs8
673
166723908U, // VGETLNu16
674
167248196U, // VGETLNu8
675
165676673U, // VHADDsv16i8
676
164628097U, // VHADDsv2i32
677
165152385U, // VHADDsv4i16
678
164628097U, // VHADDsv4i32
679
165152385U, // VHADDsv8i16
680
165676673U, // VHADDsv8i8
681
167249537U, // VHADDuv16i8
682
166200961U, // VHADDuv2i32
683
166725249U, // VHADDuv4i16
684
166200961U, // VHADDuv4i32
685
166725249U, // VHADDuv8i16
686
167249537U, // VHADDuv8i8
687
165676679U, // VHSUBsv16i8
688
164628103U, // VHSUBsv2i32
689
165152391U, // VHSUBsv4i16
690
164628103U, // VHSUBsv4i32
691
165152391U, // VHSUBsv8i16
692
165676679U, // VHSUBsv8i8
693
167249543U, // VHSUBuv16i8
694
166200967U, // VHSUBuv2i32
695
166725255U, // VHSUBuv4i16
696
166200967U, // VHSUBuv4i32
697
166725255U, // VHSUBuv8i16
698
167249543U, // VHSUBuv8i8
699
242771597U, // VLD1d16
700
1316513421U, // VLD1d16Q
701
1383622285U, // VLD1d16T
702
243295885U, // VLD1d32
703
1317037709U, // VLD1d32Q
704
1384146573U, // VLD1d32T
705
243820173U, // VLD1d64
706
244344461U, // VLD1d8
707
1318086285U, // VLD1d8Q
708
1385195149U, // VLD1d8T
709
243295885U, // VLD1df
710
241829517U, // VLD1q16
711
242353805U, // VLD1q32
712
244975245U, // VLD1q64
713
237110925U, // VLD1q8
714
242353805U, // VLD1qf
715
1450731154U, // VLD2LNd16
716
1451255442U, // VLD2LNd32
717
1452304018U, // VLD2LNd8
718
1450731154U, // VLD2LNq16a
719
1450731154U, // VLD2LNq16b
720
1451255442U, // VLD2LNq32a
721
1451255442U, // VLD2LNq32b
722
645424786U, // VLD2d16
723
645424786U, // VLD2d16D
724
645949074U, // VLD2d32
725
645949074U, // VLD2d32D
726
646473357U, // VLD2d64
727
646997650U, // VLD2d8
728
646997650U, // VLD2d8D
729
1316513426U, // VLD2q16
730
1317037714U, // VLD2q32
731
1318086290U, // VLD2q8
732
1517840023U, // VLD3LNd16
733
1518364311U, // VLD3LNd32
734
1519412887U, // VLD3LNd8
735
1517840023U, // VLD3LNq16a
736
1517840023U, // VLD3LNq16b
737
1518364311U, // VLD3LNq32a
738
1518364311U, // VLD3LNq32b
739
1383622295U, // VLD3d16
740
1384146583U, // VLD3d32
741
1384670861U, // VLD3d64
742
1385195159U, // VLD3d8
743
1316513431U, // VLD3q16a
744
1316513431U, // VLD3q16b
745
1317037719U, // VLD3q32a
746
1317037719U, // VLD3q32b
747
1318086295U, // VLD3q8a
748
1318086295U, // VLD3q8b
749
1584948892U, // VLD4LNd16
750
1585473180U, // VLD4LNd32
751
1586521756U, // VLD4LNd8
752
1584948892U, // VLD4LNq16a
753
1584948892U, // VLD4LNq16b
754
1585473180U, // VLD4LNq32a
755
1585473180U, // VLD4LNq32b
756
1316513436U, // VLD4d16
757
1317037724U, // VLD4d32
758
1317561997U, // VLD4d64
759
1318086300U, // VLD4d8
760
1450731164U, // VLD4q16a
761
1450731164U, // VLD4q16b
762
1451255452U, // VLD4q32a
763
1451255452U, // VLD4q32b
764
1452304028U, // VLD4q8a
765
1452304028U, // VLD4q8b
766
1610614433U, // VLDMD
767
1610614433U, // VLDMS
771
152102578U, // VMAXfd
772
152102578U, // VMAXfd_sfp
773
152102578U, // VMAXfq
774
165676722U, // VMAXsv16i8
775
164628146U, // VMAXsv2i32
776
165152434U, // VMAXsv4i16
777
164628146U, // VMAXsv4i32
778
165152434U, // VMAXsv8i16
779
165676722U, // VMAXsv8i8
780
167249586U, // VMAXuv16i8
781
166201010U, // VMAXuv2i32
782
166725298U, // VMAXuv4i16
783
166201010U, // VMAXuv4i32
784
166725298U, // VMAXuv8i16
785
167249586U, // VMAXuv8i8
786
152102583U, // VMINfd
787
152102583U, // VMINfd_sfp
788
152102583U, // VMINfq
789
165676727U, // VMINsv16i8
790
164628151U, // VMINsv2i32
791
165152439U, // VMINsv4i16
792
164628151U, // VMINsv4i32
793
165152439U, // VMINsv8i16
794
165676727U, // VMINsv8i8
795
167249591U, // VMINuv16i8
796
166201015U, // VMINuv2i32
797
166725303U, // VMINuv4i16
798
166201015U, // VMINuv4i32
799
166725303U, // VMINuv8i16
800
167249591U, // VMINuv8i8
802
231753409U, // VMLALslsv2i32
803
232277697U, // VMLALslsv4i16
804
233326273U, // VMLALsluv2i32
805
233850561U, // VMLALsluv4i16
806
835733185U, // VMLALsv2i64
807
836257473U, // VMLALsv4i32
808
836781761U, // VMLALsv8i16
809
837306049U, // VMLALuv2i64
810
837830337U, // VMLALuv4i32
811
838354625U, // VMLALuv8i16
813
823191228U, // VMLAfd
814
823191228U, // VMLAfq
815
219211452U, // VMLAslfd
816
219211452U, // VMLAslfq
817
235423420U, // VMLAslv2i32
818
235947708U, // VMLAslv4i16
819
235423420U, // VMLAslv4i32
820
235947708U, // VMLAslv8i16
821
840451772U, // VMLAv16i8
822
839403196U, // VMLAv2i32
823
839927484U, // VMLAv4i16
824
839403196U, // VMLAv4i32
825
839927484U, // VMLAv8i16
826
840451772U, // VMLAv8i8
828
231753420U, // VMLSLslsv2i32
829
232277708U, // VMLSLslsv4i16
830
233326284U, // VMLSLsluv2i32
831
233850572U, // VMLSLsluv4i16
832
835733196U, // VMLSLsv2i64
833
836257484U, // VMLSLsv4i32
834
836781772U, // VMLSLsv8i16
835
837306060U, // VMLSLuv2i64
836
837830348U, // VMLSLuv4i32
837
838354636U, // VMLSLuv8i16
839
823191239U, // VMLSfd
840
823191239U, // VMLSfq
841
219211463U, // VMLSslfd
842
219211463U, // VMLSslfq
843
235423431U, // VMLSslv2i32
844
235947719U, // VMLSslv4i16
845
235423431U, // VMLSslv4i32
846
235947719U, // VMLSslv8i16
847
840451783U, // VMLSv16i8
848
839403207U, // VMLSv2i32
849
839927495U, // VMLSv4i16
850
839403207U, // VMLSv4i32
851
839927495U, // VMLSv8i16
852
840451783U, // VMLSv8i8
854
135815492U, // VMOVDRR
855
151576900U, // VMOVDcc
856
739795268U, // VMOVDneon
857
768607954U, // VMOVLsv2i64
858
769132242U, // VMOVLsv4i32
859
769656530U, // VMOVLsv8i16
860
770180818U, // VMOVLuv2i64
861
770705106U, // VMOVLuv4i32
862
771229394U, // VMOVLuv8i16
863
771753688U, // VMOVNv2i32
864
772277976U, // VMOVNv4i16
865
772802264U, // VMOVNv8i8
867
135815492U, // VMOVRRD
868
806904132U, // VMOVRRS
869
739795268U, // VMOVRS
871
739795268U, // VMOVSR
872
806904132U, // VMOVSRR
873
152101188U, // VMOVScc
874
773472580U, // VMOVv16i8
875
771907908U, // VMOVv1i64
876
772440388U, // VMOVv2i32
877
771907908U, // VMOVv2i64
878
772972868U, // VMOVv4i16
879
772440388U, // VMOVv4i32
880
772972868U, // VMOVv8i16
881
773472580U, // VMOVv8i8
885
178783976U, // VMULLp
886
835716840U, // VMULLslsv2i32
887
836241128U, // VMULLslsv4i16
888
837289704U, // VMULLsluv2i32
889
837813992U, // VMULLsluv4i16
890
164628200U, // VMULLsv2i64
891
165152488U, // VMULLsv4i32
892
165676776U, // VMULLsv8i16
893
166201064U, // VMULLuv2i64
894
166725352U, // VMULLuv4i32
895
167249640U, // VMULLuv8i16
897
152102627U, // VMULfd
898
152102627U, // VMULfd_sfp
899
152102627U, // VMULfq
900
178783971U, // VMULpd
901
178783971U, // VMULpq
902
823191267U, // VMULslfd
903
823191267U, // VMULslfq
904
839386851U, // VMULslv2i32
905
839911139U, // VMULslv4i16
906
839386851U, // VMULslv4i32
907
839911139U, // VMULslv8i16
908
169346787U, // VMULv16i8
909
168298211U, // VMULv2i32
910
168822499U, // VMULv4i16
911
168298211U, // VMULv4i32
912
168822499U, // VMULv8i16
913
169346787U, // VMULv8i8
917
151578355U, // VNEGDcc
919
152102643U, // VNEGScc
920
756082419U, // VNEGf32q
921
756082419U, // VNEGfd
922
756082419U, // VNEGfd_sfp
923
769132275U, // VNEGs16d
924
769132275U, // VNEGs16q
925
768607987U, // VNEGs32d
926
768607987U, // VNEGs32q
927
769656563U, // VNEGs8d
928
769656563U, // VNEGs8q
929
822667000U, // VNMLAD
930
823191288U, // VNMLAS
931
822667006U, // VNMLSD
932
823191294U, // VNMLSS
933
151578372U, // VNMULD
934
152102660U, // VNMULS
939
165693204U, // VPADALsv16i8
940
164644628U, // VPADALsv2i32
941
165168916U, // VPADALsv4i16
942
164644628U, // VPADALsv4i32
943
165168916U, // VPADALsv8i16
944
165693204U, // VPADALsv8i8
945
167266068U, // VPADALuv16i8
946
166217492U, // VPADALuv2i32
947
166741780U, // VPADALuv4i16
948
166217492U, // VPADALuv4i32
949
166741780U, // VPADALuv8i16
950
167266068U, // VPADALuv8i8
951
769656603U, // VPADDLsv16i8
952
768608027U, // VPADDLsv2i32
953
769132315U, // VPADDLsv4i16
954
768608027U, // VPADDLsv4i32
955
769132315U, // VPADDLsv8i16
956
769656603U, // VPADDLsv8i8
957
771229467U, // VPADDLuv16i8
958
770180891U, // VPADDLuv2i32
959
770705179U, // VPADDLuv4i16
960
770180891U, // VPADDLuv4i32
961
770705179U, // VPADDLuv8i16
962
771229467U, // VPADDLuv8i8
963
152102690U, // VPADDf
964
168822562U, // VPADDi16
965
168298274U, // VPADDi32
966
169346850U, // VPADDi8
967
152102696U, // VPMAXf
968
165152552U, // VPMAXs16
969
164628264U, // VPMAXs32
970
165676840U, // VPMAXs8
971
166725416U, // VPMAXu16
972
166201128U, // VPMAXu32
973
167249704U, // VPMAXu8
974
152102702U, // VPMINf
975
165152558U, // VPMINs16
976
164628270U, // VPMINs32
977
165676846U, // VPMINs8
978
166725422U, // VPMINu16
979
166201134U, // VPMINu32
980
167249710U, // VPMINu8
981
769656628U, // VQABSv16i8
982
768608052U, // VQABSv2i32
983
769132340U, // VQABSv4i16
984
768608052U, // VQABSv4i32
985
769132340U, // VQABSv8i16
986
769656628U, // VQABSv8i8
987
165676858U, // VQADDsv16i8
988
179308346U, // VQADDsv1i64
989
164628282U, // VQADDsv2i32
990
179308346U, // VQADDsv2i64
991
165152570U, // VQADDsv4i16
992
164628282U, // VQADDsv4i32
993
165152570U, // VQADDsv8i16
994
165676858U, // VQADDsv8i8
995
167249722U, // VQADDuv16i8
996
179832634U, // VQADDuv1i64
997
166201146U, // VQADDuv2i32
998
179832634U, // VQADDuv2i64
999
166725434U, // VQADDuv4i16
1000
166201146U, // VQADDuv4i32
1001
166725434U, // VQADDuv8i16
1002
167249722U, // VQADDuv8i8
1003
231753536U, // VQDMLALslv2i32
1004
232277824U, // VQDMLALslv4i16
1005
835733312U, // VQDMLALv2i64
1006
836257600U, // VQDMLALv4i32
1007
231753544U, // VQDMLSLslv2i32
1008
232277832U, // VQDMLSLslv4i16
1009
835733320U, // VQDMLSLv2i64
1010
836257608U, // VQDMLSLv4i32
1011
835716944U, // VQDMULHslv2i32
1012
836241232U, // VQDMULHslv4i16
1013
835716944U, // VQDMULHslv4i32
1014
836241232U, // VQDMULHslv8i16
1015
164628304U, // VQDMULHv2i32
1016
165152592U, // VQDMULHv4i16
1017
164628304U, // VQDMULHv4i32
1018
165152592U, // VQDMULHv8i16
1019
835716952U, // VQDMULLslv2i32
1020
836241240U, // VQDMULLslv4i16
1021
164628312U, // VQDMULLv2i64
1022
165152600U, // VQDMULLv4i32
1023
783288160U, // VQMOVNsuv2i32
1024
768608096U, // VQMOVNsuv4i16
1025
769132384U, // VQMOVNsuv8i8
1026
783288168U, // VQMOVNsv2i32
1027
768608104U, // VQMOVNsv4i16
1028
769132392U, // VQMOVNsv8i8
1029
783812456U, // VQMOVNuv2i32
1030
770180968U, // VQMOVNuv4i16
1031
770705256U, // VQMOVNuv8i8
1032
769656687U, // VQNEGv16i8
1033
768608111U, // VQNEGv2i32
1034
769132399U, // VQNEGv4i16
1035
768608111U, // VQNEGv4i32
1036
769132399U, // VQNEGv8i16
1037
769656687U, // VQNEGv8i8
1038
835716981U, // VQRDMULHslv2i32
1039
836241269U, // VQRDMULHslv4i16
1040
835716981U, // VQRDMULHslv4i32
1041
836241269U, // VQRDMULHslv8i16
1042
164628341U, // VQRDMULHv2i32
1043
165152629U, // VQRDMULHv4i16
1044
164628341U, // VQRDMULHv4i32
1045
165152629U, // VQRDMULHv8i16
1046
165676926U, // VQRSHLsv16i8
1047
179308414U, // VQRSHLsv1i64
1048
164628350U, // VQRSHLsv2i32
1049
179308414U, // VQRSHLsv2i64
1050
165152638U, // VQRSHLsv4i16
1051
164628350U, // VQRSHLsv4i32
1052
165152638U, // VQRSHLsv8i16
1053
165676926U, // VQRSHLsv8i8
1054
167249790U, // VQRSHLuv16i8
1055
179832702U, // VQRSHLuv1i64
1056
166201214U, // VQRSHLuv2i32
1057
179832702U, // VQRSHLuv2i64
1058
166725502U, // VQRSHLuv4i16
1059
166201214U, // VQRSHLuv4i32
1060
166725502U, // VQRSHLuv8i16
1061
167249790U, // VQRSHLuv8i8
1062
179308421U, // VQRSHRNsv2i32
1063
164628357U, // VQRSHRNsv4i16
1064
165152645U, // VQRSHRNsv8i8
1065
179832709U, // VQRSHRNuv2i32
1066
166201221U, // VQRSHRNuv4i16
1067
166725509U, // VQRSHRNuv8i8
1068
179308429U, // VQRSHRUNv2i32
1069
164628365U, // VQRSHRUNv4i16
1070
165152653U, // VQRSHRUNv8i8
1071
165676950U, // VQSHLsiv16i8
1072
179308438U, // VQSHLsiv1i64
1073
164628374U, // VQSHLsiv2i32
1074
179308438U, // VQSHLsiv2i64
1075
165152662U, // VQSHLsiv4i16
1076
164628374U, // VQSHLsiv4i32
1077
165152662U, // VQSHLsiv8i16
1078
165676950U, // VQSHLsiv8i8
1079
165676956U, // VQSHLsuv16i8
1080
179308444U, // VQSHLsuv1i64
1081
164628380U, // VQSHLsuv2i32
1082
179308444U, // VQSHLsuv2i64
1083
165152668U, // VQSHLsuv4i16
1084
164628380U, // VQSHLsuv4i32
1085
165152668U, // VQSHLsuv8i16
1086
165676956U, // VQSHLsuv8i8
1087
165676950U, // VQSHLsv16i8
1088
179308438U, // VQSHLsv1i64
1089
164628374U, // VQSHLsv2i32
1090
179308438U, // VQSHLsv2i64
1091
165152662U, // VQSHLsv4i16
1092
164628374U, // VQSHLsv4i32
1093
165152662U, // VQSHLsv8i16
1094
165676950U, // VQSHLsv8i8
1095
167249814U, // VQSHLuiv16i8
1096
179832726U, // VQSHLuiv1i64
1097
166201238U, // VQSHLuiv2i32
1098
179832726U, // VQSHLuiv2i64
1099
166725526U, // VQSHLuiv4i16
1100
166201238U, // VQSHLuiv4i32
1101
166725526U, // VQSHLuiv8i16
1102
167249814U, // VQSHLuiv8i8
1103
167249814U, // VQSHLuv16i8
1104
179832726U, // VQSHLuv1i64
1105
166201238U, // VQSHLuv2i32
1106
179832726U, // VQSHLuv2i64
1107
166725526U, // VQSHLuv4i16
1108
166201238U, // VQSHLuv4i32
1109
166725526U, // VQSHLuv8i16
1110
167249814U, // VQSHLuv8i8
1111
179308451U, // VQSHRNsv2i32
1112
164628387U, // VQSHRNsv4i16
1113
165152675U, // VQSHRNsv8i8
1114
179832739U, // VQSHRNuv2i32
1115
166201251U, // VQSHRNuv4i16
1116
166725539U, // VQSHRNuv8i8
1117
179308458U, // VQSHRUNv2i32
1118
164628394U, // VQSHRUNv4i16
1119
165152682U, // VQSHRUNv8i8
1120
165676978U, // VQSUBsv16i8
1121
179308466U, // VQSUBsv1i64
1122
164628402U, // VQSUBsv2i32
1123
179308466U, // VQSUBsv2i64
1124
165152690U, // VQSUBsv4i16
1125
164628402U, // VQSUBsv4i32
1126
165152690U, // VQSUBsv8i16
1127
165676978U, // VQSUBsv8i8
1128
167249842U, // VQSUBuv16i8
1129
179832754U, // VQSUBuv1i64
1130
166201266U, // VQSUBuv2i32
1131
179832754U, // VQSUBuv2i64
1132
166725554U, // VQSUBuv4i16
1133
166201266U, // VQSUBuv4i32
1134
166725554U, // VQSUBuv8i16
1135
167249842U, // VQSUBuv8i8
1136
167774136U, // VRADDHNv2i32
1137
168298424U, // VRADDHNv4i16
1138
168822712U, // VRADDHNv8i8
1139
770181056U, // VRECPEd
1140
756082624U, // VRECPEfd
1141
756082624U, // VRECPEfq
1142
770181056U, // VRECPEq
1143
152102855U, // VRECPSfd
1144
152102855U, // VRECPSfq
1145
773875662U, // VREV16d8
1146
773875662U, // VREV16q8
1147
778594261U, // VREV32d16
1148
773875669U, // VREV32d8
1149
778594261U, // VREV32q16
1150
773875669U, // VREV32q8
1151
778594268U, // VREV64d16
1152
779118556U, // VREV64d32
1153
773875676U, // VREV64d8
1154
779118556U, // VREV64df
1155
778594268U, // VREV64q16
1156
779118556U, // VREV64q32
1157
773875676U, // VREV64q8
1158
779118556U, // VREV64qf
1159
165677027U, // VRHADDsv16i8
1160
164628451U, // VRHADDsv2i32
1161
165152739U, // VRHADDsv4i16
1162
164628451U, // VRHADDsv4i32
1163
165152739U, // VRHADDsv8i16
1164
165677027U, // VRHADDsv8i8
1165
167249891U, // VRHADDuv16i8
1166
166201315U, // VRHADDuv2i32
1167
166725603U, // VRHADDuv4i16
1168
166201315U, // VRHADDuv4i32
1169
166725603U, // VRHADDuv8i16
1170
167249891U, // VRHADDuv8i8
1171
165677034U, // VRSHLsv16i8
1172
179308522U, // VRSHLsv1i64
1173
164628458U, // VRSHLsv2i32
1174
179308522U, // VRSHLsv2i64
1175
165152746U, // VRSHLsv4i16
1176
164628458U, // VRSHLsv4i32
1177
165152746U, // VRSHLsv8i16
1178
165677034U, // VRSHLsv8i8
1179
167249898U, // VRSHLuv16i8
1180
179832810U, // VRSHLuv1i64
1181
166201322U, // VRSHLuv2i32
1182
179832810U, // VRSHLuv2i64
1183
166725610U, // VRSHLuv4i16
1184
166201322U, // VRSHLuv4i32
1185
166725610U, // VRSHLuv8i16
1186
167249898U, // VRSHLuv8i8
1187
167774192U, // VRSHRNv2i32
1188
168298480U, // VRSHRNv4i16
1189
168822768U, // VRSHRNv8i8
1190
165677047U, // VRSHRsv16i8
1191
179308535U, // VRSHRsv1i64
1192
164628471U, // VRSHRsv2i32
1193
179308535U, // VRSHRsv2i64
1194
165152759U, // VRSHRsv4i16
1195
164628471U, // VRSHRsv4i32
1196
165152759U, // VRSHRsv8i16
1197
165677047U, // VRSHRsv8i8
1198
167249911U, // VRSHRuv16i8
1199
179832823U, // VRSHRuv1i64
1200
166201335U, // VRSHRuv2i32
1201
179832823U, // VRSHRuv2i64
1202
166725623U, // VRSHRuv4i16
1203
166201335U, // VRSHRuv4i32
1204
166725623U, // VRSHRuv8i16
1205
167249911U, // VRSHRuv8i8
1206
770181117U, // VRSQRTEd
1207
756082685U, // VRSQRTEfd
1208
756082685U, // VRSQRTEfq
1209
770181117U, // VRSQRTEq
1210
152102917U, // VRSQRTSfd
1211
152102917U, // VRSQRTSfq
1212
836782093U, // VRSRAsv16i8
1213
850413581U, // VRSRAsv1i64
1214
835733517U, // VRSRAsv2i32
1215
850413581U, // VRSRAsv2i64
1216
836257805U, // VRSRAsv4i16
1217
835733517U, // VRSRAsv4i32
1218
836257805U, // VRSRAsv8i16
1219
836782093U, // VRSRAsv8i8
1220
838354957U, // VRSRAuv16i8
1221
850937869U, // VRSRAuv1i64
1222
837306381U, // VRSRAuv2i32
1223
850937869U, // VRSRAuv2i64
1224
837830669U, // VRSRAuv4i16
1225
837306381U, // VRSRAuv4i32
1226
837830669U, // VRSRAuv8i16
1227
838354957U, // VRSRAuv8i8
1228
167774227U, // VRSUBHNv2i32
1229
168298515U, // VRSUBHNv4i16
1230
168822803U, // VRSUBHNv8i8
1231
845701444U, // VSETLNi16
1232
846225732U, // VSETLNi32
1233
840982852U, // VSETLNi8
1234
168822811U, // VSHLLi16
1235
168298523U, // VSHLLi32
1236
169347099U, // VSHLLi8
1237
164628507U, // VSHLLsv2i64
1238
165152795U, // VSHLLsv4i32
1239
165677083U, // VSHLLsv8i16
1240
166201371U, // VSHLLuv2i64
1241
166725659U, // VSHLLuv4i32
1242
167249947U, // VSHLLuv8i16
1243
169347105U, // VSHLiv16i8
1244
167774241U, // VSHLiv1i64
1245
168298529U, // VSHLiv2i32
1246
167774241U, // VSHLiv2i64
1247
168822817U, // VSHLiv4i16
1248
168298529U, // VSHLiv4i32
1249
168822817U, // VSHLiv8i16
1250
169347105U, // VSHLiv8i8
1251
165677089U, // VSHLsv16i8
1252
179308577U, // VSHLsv1i64
1253
164628513U, // VSHLsv2i32
1254
179308577U, // VSHLsv2i64
1255
165152801U, // VSHLsv4i16
1256
164628513U, // VSHLsv4i32
1257
165152801U, // VSHLsv8i16
1258
165677089U, // VSHLsv8i8
1259
167249953U, // VSHLuv16i8
1260
179832865U, // VSHLuv1i64
1261
166201377U, // VSHLuv2i32
1262
179832865U, // VSHLuv2i64
1263
166725665U, // VSHLuv4i16
1264
166201377U, // VSHLuv4i32
1265
166725665U, // VSHLuv8i16
1266
167249953U, // VSHLuv8i8
1267
167774246U, // VSHRNv2i32
1268
168298534U, // VSHRNv4i16
1269
168822822U, // VSHRNv8i8
1270
165677100U, // VSHRsv16i8
1271
179308588U, // VSHRsv1i64
1272
164628524U, // VSHRsv2i32
1273
179308588U, // VSHRsv2i64
1274
165152812U, // VSHRsv4i16
1275
164628524U, // VSHRsv4i32
1276
165152812U, // VSHRsv8i16
1277
165677100U, // VSHRsv8i8
1278
167249964U, // VSHRuv16i8
1279
179832876U, // VSHRuv1i64
1280
166201388U, // VSHRuv2i32
1281
179832876U, // VSHRuv2i64
1282
166725676U, // VSHRuv4i16
1283
166201388U, // VSHRuv4i32
1284
166725676U, // VSHRuv8i16
1285
167249964U, // VSHRuv8i8
1286
180356706U, // VSHTOD
1287
180880994U, // VSHTOS
1288
785507938U, // VSITOD
1289
777643618U, // VSITOS
1290
840984625U, // VSLIv16i8
1291
848848945U, // VSLIv1i64
1292
846227505U, // VSLIv2i32
1293
848848945U, // VSLIv2i64
1294
845703217U, // VSLIv4i16
1295
846227505U, // VSLIv4i32
1296
845703217U, // VSLIv8i16
1297
840984625U, // VSLIv8i8
1298
181462626U, // VSLTOD
1299
173598306U, // VSLTOS
1300
755558454U, // VSQRTD
1301
756082742U, // VSQRTS
1302
836782140U, // VSRAsv16i8
1303
850413628U, // VSRAsv1i64
1304
835733564U, // VSRAsv2i32
1305
850413628U, // VSRAsv2i64
1306
836257852U, // VSRAsv4i16
1307
835733564U, // VSRAsv4i32
1308
836257852U, // VSRAsv8i16
1309
836782140U, // VSRAsv8i8
1310
838355004U, // VSRAuv16i8
1311
850937916U, // VSRAuv1i64
1312
837306428U, // VSRAuv2i32
1313
850937916U, // VSRAuv2i64
1314
837830716U, // VSRAuv4i16
1315
837306428U, // VSRAuv4i32
1316
837830716U, // VSRAuv8i16
1317
838355004U, // VSRAuv8i8
1318
840984641U, // VSRIv16i8
1319
848848961U, // VSRIv1i64
1320
846227521U, // VSRIv2i32
1321
848848961U, // VSRIv2i64
1322
845703233U, // VSRIv4i16
1323
846227521U, // VSRIv4i32
1324
845703233U, // VSRIv8i16
1325
840984641U, // VSRIv8i8
1326
242927686U, // VST1d16
1327
1316669510U, // VST1d16Q
1328
1383778374U, // VST1d16T
1329
243451974U, // VST1d32
1330
1317193798U, // VST1d32Q
1331
1384302662U, // VST1d32T
1332
243976262U, // VST1d64
1333
244500550U, // VST1d8
1334
1318242374U, // VST1d8Q
1335
1385351238U, // VST1d8T
1336
243451974U, // VST1df
1337
241887302U, // VST1q16
1338
242411590U, // VST1q32
1339
245033030U, // VST1q64
1340
237168710U, // VST1q8
1341
242411590U, // VST1qf
1342
1383778379U, // VST2LNd16
1343
1384302667U, // VST2LNd32
1344
1385351243U, // VST2LNd8
1345
1383778379U, // VST2LNq16a
1346
1383778379U, // VST2LNq16b
1347
1384302667U, // VST2LNq32a
1348
1384302667U, // VST2LNq32b
1349
645580875U, // VST2d16
1350
645580875U, // VST2d16D
1351
646105163U, // VST2d32
1352
646105163U, // VST2d32D
1353
646629446U, // VST2d64
1354
647153739U, // VST2d8
1355
647153739U, // VST2d8D
1356
1316669515U, // VST2q16
1357
1317193803U, // VST2q32
1358
1318242379U, // VST2q8
1359
1316669520U, // VST3LNd16
1360
1317193808U, // VST3LNd32
1361
1318242384U, // VST3LNd8
1362
1316669520U, // VST3LNq16a
1363
1316669520U, // VST3LNq16b
1364
1317193808U, // VST3LNq32a
1365
1317193808U, // VST3LNq32b
1366
1383778384U, // VST3d16
1367
1384302672U, // VST3d32
1368
1384826950U, // VST3d64
1369
1385351248U, // VST3d8
1370
1316685904U, // VST3q16a
1371
1316685904U, // VST3q16b
1372
1317210192U, // VST3q32a
1373
1317210192U, // VST3q32b
1374
1318258768U, // VST3q8a
1375
1318258768U, // VST3q8b
1376
1450887253U, // VST4LNd16
1377
1451411541U, // VST4LNd32
1378
1452460117U, // VST4LNd8
1379
1450887253U, // VST4LNq16a
1380
1450887253U, // VST4LNq16b
1381
1451411541U, // VST4LNq32a
1382
1451411541U, // VST4LNq32b
1383
1316669525U, // VST4d16
1384
1317193813U, // VST4d32
1385
1317718086U, // VST4d64
1386
1318242389U, // VST4d8
1387
1450903637U, // VST4q16a
1388
1450903637U, // VST4q16b
1389
1451427925U, // VST4q32a
1390
1451427925U, // VST4q32b
1391
1452476501U, // VST4q8a
1392
1452476501U, // VST4q8b
1393
1610614874U, // VSTMD
1394
1610614874U, // VSTMS
1395
177760351U, // VSTRD
1396
135932004U, // VSTRQ
1397
175138911U, // VSTRS
1398
151578731U, // VSUBD
1399
167774320U, // VSUBHNv2i32
1400
168298608U, // VSUBHNv4i16
1401
168822896U, // VSUBHNv8i8
1402
164628599U, // VSUBLsv2i64
1403
165152887U, // VSUBLsv4i32
1404
165677175U, // VSUBLsv8i16
1405
166201463U, // VSUBLuv2i64
1406
166725751U, // VSUBLuv4i32
1407
167250039U, // VSUBLuv8i16
1408
152103019U, // VSUBS
1409
164628605U, // VSUBWsv2i64
1410
165152893U, // VSUBWsv4i32
1411
165677181U, // VSUBWsv8i16
1412
166201469U, // VSUBWuv2i64
1413
166725757U, // VSUBWuv4i32
1414
167250045U, // VSUBWuv8i16
1415
152103019U, // VSUBfd
1416
152103019U, // VSUBfd_sfp
1417
152103019U, // VSUBfq
1418
169347179U, // VSUBv16i8
1419
167774315U, // VSUBv1i64
1420
168298603U, // VSUBv2i32
1421
167774315U, // VSUBv2i64
1422
168822891U, // VSUBv4i16
1423
168298603U, // VSUBv4i32
1424
168822891U, // VSUBv8i16
1425
169347179U, // VSUBv8i8
1426
739797123U, // VSWPd
1427
739797123U, // VSWPq
1428
169896072U, // VTBL1
1429
840984712U, // VTBL2
1430
237004936U, // VTBL3
1431
639658120U, // VTBL4
1432
840984717U, // VTBX1
1433
237004941U, // VTBX2
1434
639658125U, // VTBX3
1435
1377855629U, // VTBX4
1436
181929570U, // VTOSHD
1437
182453858U, // VTOSHS
1438
787081362U, // VTOSIRD
1439
776595602U, // VTOSIRS
1440
787080802U, // VTOSIZD
1441
776595042U, // VTOSIZS
1442
183035490U, // VTOSLD
1443
172549730U, // VTOSLS
1444
183502434U, // VTOUHD
1445
184026722U, // VTOUHS
1446
788654226U, // VTOUIRD
1447
777119890U, // VTOUIRS
1448
788653666U, // VTOUIZD
1449
777119330U, // VTOUIZS
1450
184608354U, // VTOULD
1451
173074018U, // VTOULS
1452
845703320U, // VTRNd16
1453
846227608U, // VTRNd32
1454
840984728U, // VTRNd8
1455
845703320U, // VTRNq16
1456
846227608U, // VTRNq32
1457
840984728U, // VTRNq8
1458
169896093U, // VTSTv16i8
1459
175138973U, // VTSTv2i32
1460
174614685U, // VTSTv4i16
1461
175138973U, // VTSTv4i32
1462
174614685U, // VTSTv8i16
1463
169896093U, // VTSTv8i8
1464
185075298U, // VUHTOD
1465
185599586U, // VUHTOS
1466
790226530U, // VUITOD
1467
778167906U, // VUITOS
1468
186181218U, // VULTOD
1469
174122594U, // VULTOS
1470
845703330U, // VUZPd16
1471
846227618U, // VUZPd32
1472
840984738U, // VUZPd8
1473
845703330U, // VUZPq16
1474
846227618U, // VUZPq32
1475
840984738U, // VUZPq8
1476
845703335U, // VZIPd16
1477
846227623U, // VZIPd32
1478
840984743U, // VZIPd8
1479
845703335U, // VZIPq16
1480
846227623U, // VZIPq32
1481
840984743U, // VZIPq8
1484
538970292U, // YIELD
1485
1679319057U, // t2ADCSri
1486
1730207761U, // t2ADCSrr
1487
1797316625U, // t2ADCSrs
1488
1679319057U, // t2ADCri
1489
1730207761U, // t2ADCrr
1490
1797316625U, // t2ADCrs
1491
186703893U, // t2ADDSri
1492
186703893U, // t2ADDSrr
1493
857792533U, // t2ADDSrs
1494
1730207770U, // t2ADDrSPi
1495
135817402U, // t2ADDrSPi12
1496
1797316634U, // t2ADDrSPs
1497
1730207770U, // t2ADDri
1498
1679321274U, // t2ADDri12
1499
1730207770U, // t2ADDrr
1500
1797316634U, // t2ADDrs
1501
1679319108U, // t2ANDri
1502
1730207812U, // t2ANDrr
1503
1797316676U, // t2ANDrs
1504
1730209983U, // t2ASRri
1505
1730209983U, // t2ASRrr
1507
135815244U, // t2BFC
1508
806903888U, // t2BFI
1509
1679319124U, // t2BICri
1510
1730207828U, // t2BICrr
1511
1797316692U, // t2BICrs
1512
120062079U, // t2BR_JT
1513
337141912U, // t2BXJ
1514
388096159U, // t2Bcc
1515
538968236U, // t2CLREX
1516
739795122U, // t2CLZ
1517
790683830U, // t2CMNzri
1518
790683830U, // t2CMNzrr
1519
186704054U, // t2CMNzrs
1520
790683834U, // t2CMPri
1521
790683834U, // t2CMPrr
1522
186704058U, // t2CMPrs
1523
790683834U, // t2CMPzri
1524
790683834U, // t2CMPzrr
1525
186704058U, // t2CMPzrs
1526
939524286U, // t2CPS
1527
337141954U, // t2DBG
1528
590348639U, // t2DMBish
1529
590872927U, // t2DMBishst
1530
591397215U, // t2DMBnsh
1531
591921503U, // t2DMBnshst
1532
592445791U, // t2DMBosh
1533
592970079U, // t2DMBoshst
1534
593494367U, // t2DMBst
1535
590348643U, // t2DSBish
1536
590872931U, // t2DSBishst
1537
591397219U, // t2DSBnsh
1538
591921507U, // t2DSBnshst
1539
592445795U, // t2DSBosh
1540
592970083U, // t2DSBoshst
1541
593494371U, // t2DSBst
1542
1679319360U, // t2EORri
1543
1730208064U, // t2EORrr
1544
1797316928U, // t2EORrs
1545
538968398U, // t2ISBsy
1546
1811941576U, // t2IT
1547
351U, // t2Int_MemBarrierV7
1548
355U, // t2Int_SyncBarrierV7
1549
1879050443U, // t2Int_eh_sjlj_setjmp
1550
1027809658U, // t2LDM
1551
1027809658U, // t2LDM_RET
1552
135815559U, // t2LDRBT
1553
806904194U, // t2LDRB_POST
1554
806904194U, // t2LDRB_PRE
1555
186704258U, // t2LDRBi12
1556
135815554U, // t2LDRBi8
1557
790684034U, // t2LDRBpci
1558
857792898U, // t2LDRBs
1559
806904205U, // t2LDRDi8
1560
135815565U, // t2LDRDpci
1561
739795346U, // t2LDREX
1562
739795352U, // t2LDREXB
1563
135815583U, // t2LDREXD
1564
739795366U, // t2LDREXH
1565
135815602U, // t2LDRHT
1566
806904237U, // t2LDRH_POST
1567
806904237U, // t2LDRH_PRE
1568
186704301U, // t2LDRHi12
1569
135815597U, // t2LDRHi8
1570
790684077U, // t2LDRHpci
1571
857792941U, // t2LDRHs
1572
135815614U, // t2LDRSBT
1573
806904248U, // t2LDRSB_POST
1574
806904248U, // t2LDRSB_PRE
1575
186704312U, // t2LDRSBi12
1576
135815608U, // t2LDRSBi8
1577
790684088U, // t2LDRSBpci
1578
857792952U, // t2LDRSBs
1579
135815627U, // t2LDRSHT
1580
806904261U, // t2LDRSH_POST
1581
806904261U, // t2LDRSH_PRE
1582
186704325U, // t2LDRSHi12
1583
135815621U, // t2LDRSHi8
1584
790684101U, // t2LDRSHpci
1585
857792965U, // t2LDRSHs
1586
135815634U, // t2LDRT
1587
806904190U, // t2LDR_POST
1588
806904190U, // t2LDR_PRE
1589
186704254U, // t2LDRi12
1590
135815550U, // t2LDRi8
1591
790684030U, // t2LDRpci
1592
67111120U, // t2LDRpci_pic
1593
857792894U, // t2LDRs
1594
790841561U, // t2LEApcrel
1595
186861785U, // t2LEApcrelJT
1596
1730210013U, // t2LSLri
1597
1730210013U, // t2LSLrr
1598
1730210017U, // t2LSRri
1599
1730210017U, // t2LSRrr
1600
806904309U, // t2MLA
1601
806904313U, // t2MLS
1602
857794751U, // t2MOVCCasr
1603
186704381U, // t2MOVCCi
1604
857794781U, // t2MOVCClsl
1605
857794785U, // t2MOVCClsr
1606
186704381U, // t2MOVCCr
1607
857794789U, // t2MOVCCror
1608
135815681U, // t2MOVTi16
1609
1967350269U, // t2MOVi
1610
739795462U, // t2MOVi16
1611
739795462U, // t2MOVi32imm
1612
1967350269U, // t2MOVr
1613
1967212777U, // t2MOVrx
1614
67111149U, // t2MOVsra_flag
1615
67111157U, // t2MOVsrl_flag
1616
337142312U, // t2MRS
1617
337142312U, // t2MRSsys
1618
359162412U, // t2MSR
1619
359686700U, // t2MSRsys
1620
135815728U, // t2MUL
1621
1967211060U, // t2MVNi
1622
790684212U, // t2MVNr
1623
186704436U, // t2MVNs
1624
594018872U, // t2NOP
1625
1679321341U, // t2ORNri
1626
1679321341U, // t2ORNrr
1627
1746430205U, // t2ORNrs
1628
1679319612U, // t2ORRri
1629
1730208316U, // t2ORRrr
1630
1797317180U, // t2ORRrs
1631
806904386U, // t2PKHBT
1632
806904392U, // t2PKHTB
1633
740002049U, // t2PLDWi12
1634
740010241U, // t2PLDWi8
1635
795871489U, // t2PLDWpci
1636
796641537U, // t2PLDWr
1637
192669953U, // t2PLDWs
1638
740002054U, // t2PLDi12
1639
740010246U, // t2PLDi8
1640
795871494U, // t2PLDpci
1641
796641542U, // t2PLDr
1642
192669958U, // t2PLDs
1643
740002058U, // t2PLIi12
1644
740010250U, // t2PLIi8
1645
795871498U, // t2PLIpci
1646
796641546U, // t2PLIr
1647
192669962U, // t2PLIs
1648
135815793U, // t2QADD
1649
135815798U, // t2QADD16
1650
135815805U, // t2QADD8
1651
135815811U, // t2QASX
1652
135815816U, // t2QDADD
1653
135815822U, // t2QDSUB
1654
135815828U, // t2QSAX
1655
135815833U, // t2QSUB
1656
135815838U, // t2QSUB16
1657
135815845U, // t2QSUB8
1658
739795627U, // t2RBIT
1659
790684336U, // t2REV
1660
790684340U, // t2REV16
1661
790684346U, // t2REVSH
1662
337144078U, // t2RFEDB
1663
337144084U, // t2RFEDBW
1664
337144090U, // t2RFEIA
1665
337144090U, // t2RFEIAW
1666
1730210021U, // t2RORri
1667
1730210021U, // t2RORrr
1668
2013266633U, // t2RSBSri
1669
1947755209U, // t2RSBSrs
1670
186704585U, // t2RSBri
1671
806904521U, // t2RSBrs
1672
135815895U, // t2SADD16
1673
135815902U, // t2SADD8
1674
135815908U, // t2SASX
1675
1679319791U, // t2SBCSri
1676
1730208495U, // t2SBCSrr
1677
1797317359U, // t2SBCSrs
1678
1679319791U, // t2SBCri
1679
1730208495U, // t2SBCrr
1680
1797317359U, // t2SBCrs
1681
806904563U, // t2SBFX
1682
135817504U, // t2SDIV
1683
135815928U, // t2SEL
1684
594019088U, // t2SEV
1685
135815956U, // t2SHADD16
1686
135815964U, // t2SHADD8
1687
135815971U, // t2SHASX
1688
135815977U, // t2SHSAX
1689
135815983U, // t2SHSUB16
1690
135815991U, // t2SHSUB8
1691
337142590U, // t2SMC
1692
806904642U, // t2SMLABB
1693
806904649U, // t2SMLABT
1694
806904656U, // t2SMLAD
1695
806904662U, // t2SMLADX
1696
806904669U, // t2SMLAL
1697
806904675U, // t2SMLALBB
1698
806904683U, // t2SMLALBT
1699
806904691U, // t2SMLALD
1700
806904698U, // t2SMLALDX
1701
806904706U, // t2SMLALTB
1702
806904714U, // t2SMLALTT
1703
806904722U, // t2SMLATB
1704
806904729U, // t2SMLATT
1705
806904736U, // t2SMLAWB
1706
806904743U, // t2SMLAWT
1707
806904750U, // t2SMLSD
1708
806904756U, // t2SMLSDX
1709
806904763U, // t2SMLSLD
1710
806904770U, // t2SMLSLDX
1711
806904778U, // t2SMMLA
1712
806904784U, // t2SMMLAR
1713
806904791U, // t2SMMLS
1714
806904797U, // t2SMMLSR
1715
135816164U, // t2SMMUL
1716
135816170U, // t2SMMULR
1717
135816177U, // t2SMUAD
1718
135816183U, // t2SMUADX
1719
135816190U, // t2SMULBB
1720
135816197U, // t2SMULBT
1721
806904844U, // t2SMULL
1722
135816210U, // t2SMULTB
1723
135816217U, // t2SMULTT
1724
135816224U, // t2SMULWB
1725
135816231U, // t2SMULWT
1726
135816238U, // t2SMUSD
1727
135816244U, // t2SMUSDX
1728
364931365U, // t2SRSDB
1729
365455653U, // t2SRSDBW
1730
364931371U, // t2SRSIA
1731
365455659U, // t2SRSIAW
1732
135816255U, // t2SSAT16
1733
806904902U, // t2SSATasr
1734
806904902U, // t2SSATlsl
1735
135816267U, // t2SSAX
1736
135816272U, // t2SSUB16
1737
135816279U, // t2SSUB8
1738
1027810406U, // t2STM
1739
135816307U, // t2STRBT
1740
806880366U, // t2STRB_POST
1741
806880366U, // t2STRB_PRE
1742
186705006U, // t2STRBi12
1743
135816302U, // t2STRBi8
1744
857793646U, // t2STRBs
1745
806904953U, // t2STRDi8
1746
135816318U, // t2STREX
1747
135816324U, // t2STREXB
1748
806904971U, // t2STREXD
1749
135816338U, // t2STREXH
1750
135816350U, // t2STRHT
1751
806880409U, // t2STRH_POST
1752
806880409U, // t2STRH_PRE
1753
186705049U, // t2STRHi12
1754
135816345U, // t2STRHi8
1755
857793689U, // t2STRHs
1756
135816356U, // t2STRT
1757
806880362U, // t2STR_POST
1758
806880362U, // t2STR_PRE
1759
186705002U, // t2STRi12
1760
135816298U, // t2STRi8
1761
857793642U, // t2STRs
1762
186705065U, // t2SUBSri
1763
186705065U, // t2SUBSrr
1764
857793705U, // t2SUBSrs
1765
1730208942U, // t2SUBrSPi
1766
135817521U, // t2SUBrSPi12
1767
67111222U, // t2SUBrSPi12_
1768
67111230U, // t2SUBrSPi_
1769
1746429102U, // t2SUBrSPs
1770
67111239U, // t2SUBrSPs_
1771
1730208942U, // t2SUBri
1772
1679321393U, // t2SUBri12
1773
1730208942U, // t2SUBrr
1774
1797317806U, // t2SUBrs
1775
135816383U, // t2SXTAB16rr
1776
806905023U, // t2SXTAB16rr_rot
1777
135816391U, // t2SXTABrr
1778
806905031U, // t2SXTABrr_rot
1779
135816397U, // t2SXTAHrr
1780
806905037U, // t2SXTAHrr_rot
1781
739796179U, // t2SXTB16r
1782
135816403U, // t2SXTB16r_rot
1783
790684890U, // t2SXTBr
1784
186705114U, // t2SXTBr_rot
1785
790684895U, // t2SXTHr
1786
186705119U, // t2SXTHr_rot
1787
2080377166U, // t2TBB
1788
796641619U, // t2TBBgen
1789
2080377175U, // t2TBH
1790
796658012U, // t2TBHgen
1791
790684900U, // t2TEQri
1792
790684900U, // t2TEQrr
1793
186705124U, // t2TEQrs
1795
790684928U, // t2TSTri
1796
790684928U, // t2TSTrr
1797
186705152U, // t2TSTrs
1798
135816452U, // t2UADD16
1799
135816459U, // t2UADD8
1800
135816465U, // t2UASX
1801
806905110U, // t2UBFX
1802
135817568U, // t2UDIV
1803
135816475U, // t2UHADD16
1804
135816483U, // t2UHADD8
1805
135816490U, // t2UHASX
1806
135816496U, // t2UHSAX
1807
135816502U, // t2UHSUB16
1808
135816510U, // t2UHSUB8
1809
806905157U, // t2UMAAL
1810
806905163U, // t2UMLAL
1811
806905169U, // t2UMULL
1812
135816535U, // t2UQADD16
1813
135816543U, // t2UQADD8
1814
135816550U, // t2UQASX
1815
135816556U, // t2UQSAX
1816
135816562U, // t2UQSUB16
1817
135816570U, // t2UQSUB8
1818
135816577U, // t2USAD8
1819
806905223U, // t2USADA8
1820
135816590U, // t2USAT16
1821
806905237U, // t2USATasr
1822
806905237U, // t2USATlsl
1823
135816602U, // t2USAX
1824
135816607U, // t2USUB16
1825
135816614U, // t2USUB8
1826
135816620U, // t2UXTAB16rr
1827
806905260U, // t2UXTAB16rr_rot
1828
135816628U, // t2UXTABrr
1829
806905268U, // t2UXTABrr_rot
1830
135816634U, // t2UXTAHrr
1831
806905274U, // t2UXTAHrr_rot
1832
739796416U, // t2UXTB16r
1833
135816640U, // t2UXTB16r_rot
1834
790685127U, // t2UXTBr
1835
186705351U, // t2UXTBr_rot
1836
790685132U, // t2UXTHr
1837
186705356U, // t2UXTHr_rot
1838
594020524U, // t2WFE
1839
594020528U, // t2WFI
1840
594020532U, // t2YIELD
1841
2206474257U, // tADC
1842
135815194U, // tADDhirr
1843
2206220314U, // tADDi3
1844
2206474266U, // tADDi8
1845
126355813U, // tADDrPCi
1846
67127653U, // tADDrSP
1847
67111269U, // tADDrSPi
1848
2206220314U, // tADDrr
1849
67389797U, // tADDspi
1850
67127653U, // tADDspr
1851
67127658U, // tADDspr_
1852
69208433U, // tADJCALLSTACKDOWN
1853
69208454U, // tADJCALLSTACKUP
1854
2206474308U, // tAND
1855
67127705U, // tANDsp
1856
2206222527U, // tASRri
1857
2206476479U, // tASRrr
1859
2206474324U, // tBIC
1862
402653281U, // tBLXi
1863
402653281U, // tBLXi_r9
1865
69206113U, // tBLXr_r9
1866
402653277U, // tBLr9
1867
69206143U, // tBRIND
1868
126877823U, // tBR_JTr
1871
69206121U, // tBX_RET_vararg
1874
127402077U, // tBfar
1877
739795126U, // tCMNz
1878
739795130U, // tCMPhir
1879
739795130U, // tCMPi8
1880
739795130U, // tCMPr
1881
739795130U, // tCMPzhir
1882
739795130U, // tCMPzi8
1883
739795130U, // tCMPzr
1885
2206474560U, // tEOR
1886
1879050443U, // tInt_eh_sjlj_setjmp
1887
1027686778U, // tLDM
1889
806904194U, // tLDRB
1890
806904194U, // tLDRBi
1891
806904237U, // tLDRH
1892
806904237U, // tLDRHi
1893
135815608U, // tLDRSB
1894
135815621U, // tLDRSH
1895
739795326U, // tLDRcp
1896
806904190U, // tLDRi
1897
799015294U, // tLDRpci
1898
67111351U, // tLDRpci_pic
1899
135815550U, // tLDRspi
1900
739797209U, // tLEApcrel
1901
135817433U, // tLEApcrelJT
1902
2206222557U, // tLSLri
1903
2206476509U, // tLSLrr
1904
2206222561U, // tLSRri
1905
2206476513U, // tLSRrr
1906
135815677U, // tMOVCCi
1907
135815677U, // tMOVCCr
1908
136317376U, // tMOVCCr_pseudo
1909
67111371U, // tMOVSr
1910
67111377U, // tMOVgpr2gpr
1911
67111377U, // tMOVgpr2tgpr
1912
2208948733U, // tMOVi8
1914
67111377U, // tMOVtgpr2gpr
1915
2206474800U, // tMUL
1916
2208948788U, // tMVN
1918
2206474812U, // tORR
1919
1202717248U, // tPICADD
1921
538733014U, // tPOP_RET
1922
538733018U, // tPUSH
1924
739795636U, // tREV16
1925
739795642U, // tREVSH
1926
2206476517U, // tROR
1927
2208940745U, // tRSB
1928
135815550U, // tRestore
1929
2206474991U, // tSBC
1933
1027687526U, // tSTM
1935
806904942U, // tSTRB
1936
806904942U, // tSTRBi
1937
806904985U, // tSTRH
1938
806904985U, // tSTRHi
1939
806904938U, // tSTRi
1940
135816298U, // tSTRspi
1941
2206221486U, // tSUBi3
1942
2206475438U, // tSUBi8
1943
2206221486U, // tSUBrr
1944
67389919U, // tSUBspi
1945
67389767U, // tSUBspi_
1947
739796186U, // tSXTB
1948
739796191U, // tSXTH
1949
135816298U, // tSpill
1953
739796423U, // tUXTB
1954
739796428U, // tUXTH
1957
538970292U, // tYIELD
1961
const char *AsmStrs =
1962
"DBG_VALUE\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@ A"
1963
"DJCALLSTACKUP \000and\000\000b\t\000bfc\000bfi\000bic\000bkpt\000bl\t\000"
1964
"blx\t\000bl\000bx\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, "
1965
"pc\n\tbx\t\000bxj\000bx\000b\000cdp\000cdp2\tp\000clrex\000clz\000cmn\000"
1966
"cmp\000cps\000dbg\000dmb\tish\000dmb\tishst\000dmb\tnsh\000dmb\tnshst\000"
1967
"dmb\tosh\000dmb\toshst\000dmb\tst\000dsb\tish\000dsb\tishst\000dsb\tnsh"
1968
"\000dsb\tnshst\000dsb\tosh\000dsb\toshst\000dsb\tst\000eor\000vmov\000v"
1969
"mrs\000isb\000mcr\tp15, 0, \000dmb\000dsb\000str\tsp, [\000ldc2\000ldc\000"
1970
"ldm\000ldr\000ldrb\000ldrbt\000ldrd\000ldrex\000ldrexb\000ldrexd\000ldr"
1971
"exh\000ldrh\000ldrht\000ldrsb\000ldrsbt\000ldrsh\000ldrsht\000ldrt\000."
1972
"set \000mcr\000mcr2\tp\000mcrr\000mcrr2\tp\000mla\000mls\000mov\000movt"
1973
"\000movw\000movs\000mrc\000mrc2\tp\000mrrc\000mrrc2\tp\000mrs\000msr\000"
1974
"mul\000mvn\000nop\000orr\000\n\000pkhbt\000pkhtb\000pldw\t[\000pldw\t\000"
1975
"pld\t[\000pld\t\000pli\t[\000pli\t\000qadd\000qadd16\000qadd8\000qasx\000"
1976
"qdadd\000qdsub\000qsax\000qsub\000qsub16\000qsub8\000rbit\000rev\000rev"
1977
"16\000revsh\000rfe\000rsbs\000rsb\000rscs\t\000rsc\000sadd16\000sadd8\000"
1978
"sasx\000sbcs\t\000sbc\000sbfx\000sel\000setend\tbe\000setend\tle\000sev"
1979
"\000shadd16\000shadd8\000shasx\000shsax\000shsub16\000shsub8\000smc\000"
1980
"smlabb\000smlabt\000smlad\000smladx\000smlal\000smlalbb\000smlalbt\000s"
1981
"mlald\000smlaldx\000smlaltb\000smlaltt\000smlatb\000smlatt\000smlawb\000"
1982
"smlawt\000smlsd\000smlsdx\000smlsld\000smlsldx\000smmla\000smmlar\000sm"
1983
"mls\000smmlsr\000smmul\000smmulr\000smuad\000smuadx\000smulbb\000smulbt"
1984
"\000smull\000smultb\000smultt\000smulwb\000smulwt\000smusd\000smusdx\000"
1985
"srs\000ssat16\000ssat\000ssax\000ssub16\000ssub8\000stc2\000stc\000stm\000"
1986
"str\000strb\000strbt\000strd\000strex\000strexb\000strexd\000strexh\000"
1987
"strh\000strht\000strt\000subs\000sub\000svc\000swp\000swpb\000sxtab16\000"
1988
"sxtab\000sxtah\000sxtb16\000sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000"
1989
"trap\000tst\000uadd16\000uadd8\000uasx\000ubfx\000uhadd16\000uhadd8\000"
1990
"uhasx\000uhsax\000uhsub16\000uhsub8\000umaal\000umlal\000umull\000uqadd"
1991
"16\000uqadd8\000uqasx\000uqsax\000uqsub16\000uqsub8\000usad8\000usada8\000"
1992
"usat16\000usat\000usax\000usub16\000usub8\000uxtab16\000uxtab\000uxtah\000"
1993
"uxtb16\000uxtb\000uxth\000vabal\000vaba\000vabdl\000vabd\000vabs\000vac"
1994
"ge\000vacgt\000vadd\000vaddhn\000vaddl\000vaddw\000vand\000vbic\000vbif"
1995
"\000vbit\000vbsl\000vceq\000vcge\000vcgt\000vcle\000vcls\000vclt\000vcl"
1996
"z\000vcmp\000vcmpe\000vcnt\000vcvtb\000vcvt\000vcvtt\000vdiv\000vdup\000"
1997
"veor\000vext\000vhadd\000vhsub\000vld1\000vld2\000vld3\000vld4\000vldm\000"
1998
"vldr\000vldmia\000vmax\000vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmo"
1999
"vl\000vmovn\000vmsr\000vmul\000vmull\000vmvn\000vneg\000vnmla\000vnmls\000"
2000
"vnmul\000vorn\000vorr\000vpadal\000vpaddl\000vpadd\000vpmax\000vpmin\000"
2001
"vqabs\000vqadd\000vqdmlal\000vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000"
2002
"vqmovn\000vqneg\000vqrdmulh\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000"
2003
"vqshlu\000vqshrn\000vqshrun\000vqsub\000vraddhn\000vrecpe\000vrecps\000"
2004
"vrev16\000vrev32\000vrev64\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrs"
2005
"qrte\000vrsqrts\000vrsra\000vrsubhn\000vshll\000vshl\000vshrn\000vshr\000"
2006
"vsli\000vsqrt\000vsra\000vsri\000vst1\000vst2\000vst3\000vst4\000vstm\000"
2007
"vstr\000vstmia\000vsub\000vsubhn\000vsubl\000vsubw\000vswp\000vtbl\000v"
2008
"tbx\000vcvtr\000vtrn\000vtst\000vuzp\000vzip\000wfe\000wfi\000yield\000"
2009
"addw\000asr\000b.w\t\000it\000str\t\000@ ldr.w\t\000adr\000lsl\000lsr\000"
2010
"ror\000rrx\000asrs.w\t\000lsrs.w\t\000orn\000pldw\000pld\000pli\000rfea"
2011
"b\000rfedb\000rfeia\000sdiv\000srsdb\000srsia\000subw\000@ subw\t\000@ "
2012
"sub.w\t\000@ sub\t\000tbb\t\000tbb\000tbh\t\000tbh\000udiv\000add\t\000"
2013
"@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCALLSTACKUP \000@ and\t\000bkp"
2014
"t\t\000bx\tlr\000cbnz\t\000cbz\t\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000"
2015
"mov\t\000pop\000push\000sub\t\000";
2019
// Emit the opcode for the instruction.
2020
unsigned Bits = OpInfo[MI->getOpcode()];
2021
assert(Bits != 0 && "Cannot print this instruction.");
2022
O << AsmStrs+(Bits & 4095)-1;
2025
// Fragment 0 encoded into 6 bits for 33 unique commands.
2026
switch ((Bits >> 26) & 63) {
2027
default: // unreachable.
2029
// DBG_VALUE, CLREX, DMBish, DMBishst, DMBnsh, DMBnshst, DMBosh, DMBoshst...
2033
// ADCSSri, ADCSSrr, ADCSSrs, ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, B...
2034
printOperand(MI, 0);
2037
// ADCri, ADCrr, ADDSri, ADDSrr, ADDri, ADDrr, ANDri, ANDrr, BFC, BFI, BI...
2038
printPredicateOperand(MI, 3);
2041
// ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDC2L_OFFSET, LDC2L_POST, L...
2042
printPredicateOperand(MI, 5);
2045
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, ATOMIC_CMP_SWAP_I8, ATOMIC_L...
2046
PrintSpecial(MI, "comment");
2049
// BKPT, BL_pred, BLr9_pred, BXJ, Bcc, DBG, MRS, MRSsys, MSR, MSRi, MSRsy...
2050
printPredicateOperand(MI, 1);
2053
// BL, BLr9, tBL, tBLXi, tBLXi_r9, tBLr9
2054
printOperand(MI, 0, "call");
2058
// BR_JTm, PLDWr, PLDr, PLIr
2059
printAddrMode2Operand(MI, 0);
2062
// BX_RET, FMSTAT, NOP, SEV, TRAP, WFE, WFI, YIELD, t2CLREX, t2DMBish, t2...
2063
printPredicateOperand(MI, 0);
2066
// CDP, LDRD_POST, LDRD_PRE, MCR, MRC, STRD_POST, STRD_PRE, VLD2d16, VLD2...
2067
printPredicateOperand(MI, 6);
2070
// CDP2, MCR2, MCRR2, MRC2, MRRC2
2071
printNoHashImmediate(MI, 0);
2073
printOperand(MI, 1);
2076
// CLZ, CMNzri, CMNzrr, CMPri, CMPrr, CMPzri, CMPzrr, FCONSTD, FCONSTS, L...
2077
printPredicateOperand(MI, 2);
2080
// CMNzrs, CMPrs, CMPzrs, LDC2L_OPTION, LDC2_OPTION, LDCL_OPTION, LDC_OPT...
2081
printPredicateOperand(MI, 4);
2085
printCPInstOperand(MI, 0, "label");
2087
printCPInstOperand(MI, 1, "cpentry");
2092
printOperand(MI, 0, "cps");
2096
// LDM, LDM_RET, RFE, RFEW, SRS, SRSW, STM, t2LDM, t2LDM_RET, t2STM, tLDM...
2097
printAddrMode4Operand(MI, 0, "submode");
2100
// LEApcrel, LEApcrelJT
2101
PrintSpecial(MI, "private");
2103
PrintSpecial(MI, "uid");
2105
printOperand(MI, 1);
2109
printPCLabel(MI, 2);
2112
// PICLDR, PICLDRB, PICLDRH, PICLDRSB, PICLDRSH, PICSTR, PICSTRB, PICSTRH
2113
printAddrModePCOperand(MI, 1, "label");
2116
// VLD1d16Q, VLD1d32Q, VLD1d8Q, VLD2q16, VLD2q32, VLD2q8, VLD3q16a, VLD3q...
2117
printPredicateOperand(MI, 8);
2120
// VLD1d16T, VLD1d32T, VLD1d8T, VLD3d16, VLD3d32, VLD3d64, VLD3d8, VST1d1...
2121
printPredicateOperand(MI, 7);
2124
// VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16a, VLD2LNq16b, VLD2LNq32a, VL...
2125
printPredicateOperand(MI, 9);
2128
// VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16a, VLD3LNq16b, VLD3LNq32a, VL...
2129
printPredicateOperand(MI, 11);
2132
// VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16a, VLD4LNq16b, VLD4LNq32a, VL...
2133
printPredicateOperand(MI, 13);
2136
// VLDMD, VLDMS, VSTMD, VSTMS
2137
printAddrMode5Operand(MI, 0, "submode");
2138
printPredicateOperand(MI, 2);
2140
printAddrMode5Operand(MI, 0, "base");
2142
printRegisterList(MI, 4);
2146
// t2ADCSri, t2ADCSrr, t2ADCri, t2ADCrr, t2ADDrSPi, t2ADDri, t2ADDri12, t...
2147
printSBitModifierOperand(MI, 5);
2148
printPredicateOperand(MI, 3);
2151
// t2ADCSrs, t2ADCrs, t2ADDrSPs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2OR...
2152
printSBitModifierOperand(MI, 6);
2153
printPredicateOperand(MI, 4);
2157
printThumbITMask(MI, 1);
2159
printMandatoryPredicateOperand(MI, 0);
2163
// t2Int_eh_sjlj_setjmp, tInt_eh_sjlj_setjmp
2164
printOperand(MI, 1);
2166
printOperand(MI, 0);
2167
O << ", #8]\t@ begin eh.setjmp\n\tmov\t";
2168
printOperand(MI, 1);
2169
O << ", pc\n\tadds\t";
2170
printOperand(MI, 1);
2171
O << ", #9\n\tstr\t";
2172
printOperand(MI, 1);
2174
printOperand(MI, 0);
2175
O << ", #4]\n\tmovs\tr0, #0\n\tb\t1f\n\tmovs\tr0, #1\t@ end eh.setjmp\n1:";
2179
// t2MOVi, t2MOVr, t2MOVrx, t2MVNi, t2RSBSrs
2180
printSBitModifierOperand(MI, 4);
2184
printSBitModifierOperand(MI, 3);
2186
printOperand(MI, 0);
2188
printOperand(MI, 1);
2190
printOperand(MI, 2);
2195
printTBAddrMode(MI, 0);
2197
printJT2BlockOperand(MI, 1);
2201
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
2202
printSBitModifierOperand(MI, 1);
2207
// Fragment 1 encoded into 7 bits for 119 unique commands.
2208
switch ((Bits >> 19) & 127) {
2209
default: // unreachable.
2211
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MCR2, MCRR2, MRC2, MRRC2, PLDWi, ...
2215
// ADCri, ADCrr, ADDri, ADDrr, ANDri, ANDrr, BICri, BICrr, EORri, EORrr, ...
2216
printSBitModifierOperand(MI, 5);
2218
printOperand(MI, 0);
2220
printOperand(MI, 1);
2224
// ADCrs, ADDrs, ANDrs, BICrs, EORrs, ORRrs, RSBrs, RSCrs, SBCrs, SUBrs
2225
printSBitModifierOperand(MI, 7);
2227
printOperand(MI, 0);
2229
printOperand(MI, 1);
2231
printSORegOperand(MI, 2);
2235
// ADDSri, ADDSrr, ADDSrs, BFC, BFI, BKPT, BL_pred, BLr9_pred, BXJ, Bcc, ...
2239
// ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, BLXr9, BRIND, BX, BXr9, NOP,...
2243
// ATOMIC_CMP_SWAP_I16
2244
O << " ATOMIC_CMP_SWAP_I16 PSEUDO!";
2248
// ATOMIC_CMP_SWAP_I32
2249
O << " ATOMIC_CMP_SWAP_I32 PSEUDO!";
2253
// ATOMIC_CMP_SWAP_I8
2254
O << " ATOMIC_CMP_SWAP_I8 PSEUDO!";
2258
// ATOMIC_LOAD_ADD_I16
2259
O << " ATOMIC_LOAD_ADD_I16 PSEUDO!";
2263
// ATOMIC_LOAD_ADD_I32
2264
O << " ATOMIC_LOAD_ADD_I32 PSEUDO!";
2268
// ATOMIC_LOAD_ADD_I8
2269
O << " ATOMIC_LOAD_ADD_I8 PSEUDO!";
2273
// ATOMIC_LOAD_AND_I16
2274
O << " ATOMIC_LOAD_AND_I16 PSEUDO!";
2278
// ATOMIC_LOAD_AND_I32
2279
O << " ATOMIC_LOAD_AND_I32 PSEUDO!";
2283
// ATOMIC_LOAD_AND_I8
2284
O << " ATOMIC_LOAD_AND_I8 PSEUDO!";
2288
// ATOMIC_LOAD_NAND_I16
2289
O << " ATOMIC_LOAD_NAND_I16 PSEUDO!";
2293
// ATOMIC_LOAD_NAND_I32
2294
O << " ATOMIC_LOAD_NAND_I32 PSEUDO!";
2298
// ATOMIC_LOAD_NAND_I8
2299
O << " ATOMIC_LOAD_NAND_I8 PSEUDO!";
2303
// ATOMIC_LOAD_OR_I16
2304
O << " ATOMIC_LOAD_OR_I16 PSEUDO!";
2308
// ATOMIC_LOAD_OR_I32
2309
O << " ATOMIC_LOAD_OR_I32 PSEUDO!";
2313
// ATOMIC_LOAD_OR_I8
2314
O << " ATOMIC_LOAD_OR_I8 PSEUDO!";
2318
// ATOMIC_LOAD_SUB_I16
2319
O << " ATOMIC_LOAD_SUB_I16 PSEUDO!";
2323
// ATOMIC_LOAD_SUB_I32
2324
O << " ATOMIC_LOAD_SUB_I32 PSEUDO!";
2328
// ATOMIC_LOAD_SUB_I8
2329
O << " ATOMIC_LOAD_SUB_I8 PSEUDO!";
2333
// ATOMIC_LOAD_XOR_I16
2334
O << " ATOMIC_LOAD_XOR_I16 PSEUDO!";
2338
// ATOMIC_LOAD_XOR_I32
2339
O << " ATOMIC_LOAD_XOR_I32 PSEUDO!";
2343
// ATOMIC_LOAD_XOR_I8
2344
O << " ATOMIC_LOAD_XOR_I8 PSEUDO!";
2349
O << " ATOMIC_SWAP_I16 PSEUDO!";
2354
O << " ATOMIC_SWAP_I32 PSEUDO!";
2359
O << " ATOMIC_SWAP_I8 PSEUDO!";
2372
// CDP, LDC2_OFFSET, LDC2_OPTION, LDC2_POST, LDC2_PRE, LDC_OFFSET, LDC_OP...
2374
printNoHashImmediate(MI, 0);
2379
printNoHashImmediate(MI, 2);
2381
printNoHashImmediate(MI, 3);
2383
printNoHashImmediate(MI, 4);
2385
printOperand(MI, 5);
2389
// FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VMLAD, V...
2391
printOperand(MI, 0);
2394
// FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfd_sfp, VABSfq, VACGEd, VA...
2396
printOperand(MI, 0);
2400
O << "\tapsr_nzcv, fpscr";
2405
O << ", c7, c10, 5";
2409
// Int_SyncBarrierV6
2410
O << ", c7, c10, 4";
2414
// Int_eh_sjlj_setjmp
2415
O << ", #+8] @ eh_setjmp begin\n\tadd\t";
2416
printOperand(MI, 1);
2417
O << ", pc, #8\n\tstr\t";
2418
printOperand(MI, 1);
2420
printOperand(MI, 0);
2421
O << ", #+4]\n\tmov\tr0, #0\n\tadd\tpc, pc, #0\n\tmov\tr0, #1 @ eh_setjmp end";
2425
// LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDCL_OFFSET, LDCL_O...
2427
printNoHashImmediate(MI, 0);
2429
printNoHashImmediate(MI, 1);
2432
// LDM, LDM_RET, STM, t2LDM, t2LDM_RET, t2MOVi, t2MOVr, t2MOVrx, t2MVNi, ...
2433
printPredicateOperand(MI, 2);
2438
PrintSpecial(MI, "private");
2440
PrintSpecial(MI, "uid");
2442
PrintSpecial(MI, "private");
2444
PrintSpecial(MI, "uid");
2446
printPredicateOperand(MI, 2);
2448
printOperand(MI, 0);
2450
PrintSpecial(MI, "private");
2452
PrintSpecial(MI, "uid");
2458
printNoHashImmediate(MI, 2);
2460
PrintSpecial(MI, "private");
2462
PrintSpecial(MI, "uid");
2464
PrintSpecial(MI, "private");
2466
PrintSpecial(MI, "uid");
2468
printPredicateOperand(MI, 3);
2470
printOperand(MI, 0);
2472
PrintSpecial(MI, "private");
2474
PrintSpecial(MI, "uid");
2478
// MLA, MOVs, MVNs, SMLAL, SMULL, UMLAL, UMULL
2479
printSBitModifierOperand(MI, 6);
2481
printOperand(MI, 0);
2485
// MOVi, MOVr, MOVrx, MVNi, MVNr
2486
printSBitModifierOperand(MI, 4);
2488
printOperand(MI, 0);
2496
// MSRsys, MSRsysi, t2MSRsys
2502
printPredicateOperand(MI, 3);
2504
printOperand(MI, 0);
2506
printOperand(MI, 1);
2512
printPredicateOperand(MI, 3);
2514
printOperand(MI, 0);
2516
printAddrModePCOperand(MI, 1);
2522
printPredicateOperand(MI, 3);
2524
printOperand(MI, 0);
2526
printAddrModePCOperand(MI, 1);
2532
printPredicateOperand(MI, 3);
2534
printOperand(MI, 0);
2536
printAddrModePCOperand(MI, 1);
2542
printPredicateOperand(MI, 3);
2544
printOperand(MI, 0);
2546
printAddrModePCOperand(MI, 1);
2552
printPredicateOperand(MI, 3);
2554
printOperand(MI, 0);
2556
printAddrModePCOperand(MI, 1);
2562
printPredicateOperand(MI, 3);
2564
printOperand(MI, 0);
2566
printAddrModePCOperand(MI, 1);
2572
printPredicateOperand(MI, 3);
2574
printOperand(MI, 0);
2576
printAddrModePCOperand(MI, 1);
2582
printPredicateOperand(MI, 3);
2584
printOperand(MI, 0);
2586
printAddrModePCOperand(MI, 1);
2590
// SRS, t2SRSDB, t2SRSIA
2594
// SRSW, t2SRSDBW, t2SRSIAW
2598
// VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i...
2600
printOperand(MI, 0);
2604
// VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i...
2606
printOperand(MI, 0);
2610
// VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8...
2612
printOperand(MI, 0);
2616
// VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i...
2618
printOperand(MI, 0);
2622
// VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i...
2624
printOperand(MI, 0);
2628
// VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8...
2630
printOperand(MI, 0);
2634
// VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V...
2636
printOperand(MI, 0);
2640
// VADDHNv4i16, VADDv2i32, VADDv4i32, VCEQv2i32, VCEQv4i32, VCEQzv2i32, V...
2642
printOperand(MI, 0);
2646
// VADDHNv8i8, VADDv4i16, VADDv8i16, VCEQv4i16, VCEQv8i16, VCEQzv4i16, VC...
2648
printOperand(MI, 0);
2652
// VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv...
2654
printOperand(MI, 0);
2658
// VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1...
2664
printOperand(MI, 0);
2666
printOperand(MI, 1);
2672
printOperand(MI, 0);
2674
printOperand(MI, 1);
2680
printOperand(MI, 0);
2682
printOperand(MI, 1);
2688
printOperand(MI, 0);
2690
printOperand(MI, 1);
2694
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSI...
2696
printOperand(MI, 0);
2698
printOperand(MI, 1);
2701
// VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUI...
2703
printOperand(MI, 0);
2705
printOperand(MI, 1);
2708
// VCVTs2fd, VCVTs2fd_sfp, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS
2710
printOperand(MI, 0);
2712
printOperand(MI, 1);
2715
// VCVTu2fd, VCVTu2fd_sfp, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS
2717
printOperand(MI, 0);
2719
printOperand(MI, 1);
2722
// VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1q16, VRE...
2726
// VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VDUPLNfd, VDUPLNfq, VDUPfd, VD...
2730
// VLD1d16, VLD1d16Q, VLD1d16T, VLD2LNd16, VLD2LNq16a, VLD2LNq16b, VLD2d1...
2734
// VLD1d32, VLD1d32Q, VLD1d32T, VLD1df, VLD2LNd32, VLD2LNq32a, VLD2LNq32b...
2738
// VLD1d64, VLD2d64, VLD3d64, VLD4d64, VST1d64, VST2d64, VST3d64, VST4d64
2742
// VLD1d8, VLD1d8Q, VLD1d8T, VLD2LNd8, VLD2d8, VLD2d8D, VLD2q8, VLD3LNd8,...
2746
// VLD1q64, VLDRD, VSLIv1i64, VSLIv2i64, VSRIv1i64, VSRIv2i64, VST1q64, V...
2752
printOperand(MI, 0);
2756
// VMULLp, VMULpd, VMULpq
2758
printOperand(MI, 0);
2760
printOperand(MI, 1);
2762
printOperand(MI, 2);
2766
// VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
2768
printOperand(MI, 0);
2772
// VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ...
2774
printOperand(MI, 0);
2780
printOperand(MI, 0);
2782
printOperand(MI, 1);
2784
printOperand(MI, 2);
2790
printOperand(MI, 0);
2792
printOperand(MI, 1);
2794
printOperand(MI, 2);
2800
printOperand(MI, 0);
2802
printOperand(MI, 1);
2807
printOperand(MI, 0);
2809
printOperand(MI, 1);
2811
printOperand(MI, 2);
2817
printOperand(MI, 0);
2819
printOperand(MI, 1);
2821
printOperand(MI, 2);
2825
// VTOSIRD, VTOSIZD, VTOSLD
2827
printOperand(MI, 0);
2829
printOperand(MI, 1);
2834
printOperand(MI, 0);
2836
printOperand(MI, 1);
2838
printOperand(MI, 2);
2844
printOperand(MI, 0);
2846
printOperand(MI, 1);
2848
printOperand(MI, 2);
2852
// VTOUIRD, VTOUIZD, VTOULD
2854
printOperand(MI, 0);
2856
printOperand(MI, 1);
2861
printOperand(MI, 0);
2863
printOperand(MI, 1);
2865
printOperand(MI, 2);
2871
printOperand(MI, 0);
2873
printOperand(MI, 1);
2875
printOperand(MI, 2);
2881
printOperand(MI, 0);
2883
printOperand(MI, 1);
2886
// t2ADCSrr, t2ADCSrs, t2ADCrr, t2ADCrs, t2ADDSri, t2ADDSrr, t2ADDSrs, t2...
2888
printOperand(MI, 0);
2893
printJT2BlockOperand(MI, 2);
2897
// t2DMBish, t2DSBish
2902
// t2DMBishst, t2DSBishst
2907
// t2DMBnsh, t2DSBnsh
2912
// t2DMBnshst, t2DSBnshst
2917
// t2DMBosh, t2DSBosh
2922
// t2DMBoshst, t2DSBoshst
2932
// t2NOP, t2SEV, t2WFE, t2WFI, t2YIELD
2937
// t2PLDWpci, t2PLDpci, t2PLIpci
2939
printOperand(MI, 1, "negzero");
2944
// t2PLDWr, t2PLDWs, t2PLDr, t2PLDs, t2PLIr, t2PLIs, t2TBBgen, t2TBHgen
2946
printOperand(MI, 0);
2948
printOperand(MI, 1);
2951
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
2952
printPredicateOperand(MI, 4);
2954
printOperand(MI, 0);
2960
printThumbS4ImmOperand(MI, 1);
2965
O << "\n\t.align\t2\n";
2966
printJTBlockOperand(MI, 1);
2971
O << "\t@ far jump";
2977
printOperand(MI, 0);
2979
printOperand(MI, 1);
2983
// tMOVi8, tMVN, tRSB
2984
printPredicateOperand(MI, 3);
2986
printOperand(MI, 0);
2988
printOperand(MI, 2);
2993
printOperand(MI, 0);
3000
// Fragment 2 encoded into 6 bits for 36 unique commands.
3001
switch ((Bits >> 13) & 63) {
3002
default: // unreachable.
3004
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MLA, MOVr, MOVrx, MVNr, PLDWi, PL...
3005
printOperand(MI, 1);
3008
// ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri
3009
printSOImmOperand(MI, 2);
3013
// ADCrr, ADDrr, ANDrr, BICrr, EORrr, MCR2, MCRR2, MRC2, MRRC2, MUL, ORRr...
3014
printOperand(MI, 2);
3017
// ADDSri, ADDSrr, ADDSrs, BFC, BFI, BKPT, BXJ, Bcc, CLZ, CMNzri, CMNzrr,...
3018
printOperand(MI, 0);
3021
// BL_pred, BLr9_pred
3022
printOperand(MI, 0, "call");
3027
printJTBlockOperand(MI, 3);
3032
printJTBlockOperand(MI, 1);
3036
// CDP, FCONSTD, FCONSTS, LDC2L_OFFSET, LDC2L_PRE, LDCL_OFFSET, LDCL_PRE,...
3040
// LDC2L_OPTION, LDC2L_POST, LDCL_OPTION, LDCL_POST, STC2L_OPTION, STC2L_...
3042
printOperand(MI, 2);
3046
// LDC2_OFFSET, LDC2_OPTION, LDC2_POST, LDC2_PRE, LDC_OFFSET, LDC_OPTION,...
3048
printNoHashImmediate(MI, 1);
3051
// LDM, LDM_RET, STM, t2MOVrx, t2MVNi, tLDM, tSTM
3056
printSOImmOperand(MI, 1);
3061
printSORegOperand(MI, 1);
3066
printSOImmOperand(MI, 0);
3070
// VCMPEZD, VCMPEZS, VCMPZD, VCMPZS, tRSB
3075
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VC...
3079
// VLD1q16, VLD1q32, VLD1q64, VLD1q8, VLD1qf
3080
printOperand(MI, 0, "dregpair");
3082
printAddrMode6Operand(MI, 1);
3087
printAddrMode4Operand(MI, 1);
3089
printOperand(MI, 0, "dregpair");
3093
// VMOVv16i8, VMOVv8i8
3094
printHex8ImmOperand(MI, 1);
3098
// VMOVv1i64, VMOVv2i64
3099
printHex64ImmOperand(MI, 1);
3103
// VMOVv2i32, VMOVv4i32
3104
printHex32ImmOperand(MI, 1);
3108
// VMOVv4i16, VMOVv8i16
3109
printHex16ImmOperand(MI, 1);
3113
// VST1d16, VST1d16Q, VST1d16T, VST1d32, VST1d32Q, VST1d32T, VST1d64, VST...
3114
printOperand(MI, 4);
3117
// VST1q16, VST1q32, VST1q64, VST1q8, VST1qf
3118
printOperand(MI, 4, "dregpair");
3120
printAddrMode6Operand(MI, 0);
3124
// VST3q16a, VST3q16b, VST3q32a, VST3q32b, VST3q8a, VST3q8b, VST4q16a, VS...
3125
printOperand(MI, 5);
3127
printOperand(MI, 6);
3129
printOperand(MI, 7);
3132
// t2LDM, t2LDM_RET, t2STM
3133
printAddrMode4Operand(MI, 0, "wide");
3135
printAddrMode4Operand(MI, 0);
3137
printRegisterList(MI, 4);
3141
// t2LEApcrel, t2LEApcrelJT
3143
printOperand(MI, 1);
3148
printOperand(MI, 0);
3150
printOperand(MI, 1);
3154
// t2PLDWi12, t2PLDi12, t2PLIi12
3155
printT2AddrModeImm12Operand(MI, 0);
3159
// t2PLDWi8, t2PLDi8, t2PLIi8
3160
printT2AddrModeImm8Operand(MI, 0);
3164
// t2PLDWr, t2PLDr, t2PLIr, t2TBBgen
3169
// t2PLDWs, t2PLDs, t2PLIs
3171
printOperand(MI, 2);
3181
// tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tMUL, tORR, tR...
3182
printOperand(MI, 3);
3185
// tADDspi, tSUBspi, tSUBspi_
3186
printThumbS4ImmOperand(MI, 2);
3190
// tPOP, tPOP_RET, tPUSH
3191
printRegisterList(MI, 2);
3196
switch (MI->getOpcode()) {
3211
case ARM::LDC2_OFFSET:
3212
case ARM::LDC_OFFSET:
3225
case ARM::MOVi2pieces:
3235
case ARM::STC2_OFFSET:
3236
case ARM::STC_OFFSET:
3253
case ARM::VABALsv2i64:
3254
case ARM::VABALsv4i32:
3255
case ARM::VABALsv8i16:
3256
case ARM::VABALuv2i64:
3257
case ARM::VABALuv4i32:
3258
case ARM::VABALuv8i16:
3259
case ARM::VABAsv16i8:
3260
case ARM::VABAsv2i32:
3261
case ARM::VABAsv4i16:
3262
case ARM::VABAsv4i32:
3263
case ARM::VABAsv8i16:
3264
case ARM::VABAsv8i8:
3265
case ARM::VABAuv16i8:
3266
case ARM::VABAuv2i32:
3267
case ARM::VABAuv4i16:
3268
case ARM::VABAuv4i32:
3269
case ARM::VABAuv8i16:
3270
case ARM::VABAuv8i8:
3271
case ARM::VABDLsv2i64:
3272
case ARM::VABDLsv4i32:
3273
case ARM::VABDLsv8i16:
3274
case ARM::VABDLuv2i64:
3275
case ARM::VABDLuv4i32:
3276
case ARM::VABDLuv8i16:
3277
case ARM::VABDsv16i8:
3278
case ARM::VABDsv2i32:
3279
case ARM::VABDsv4i16:
3280
case ARM::VABDsv4i32:
3281
case ARM::VABDsv8i16:
3282
case ARM::VABDsv8i8:
3283
case ARM::VABDuv16i8:
3284
case ARM::VABDuv2i32:
3285
case ARM::VABDuv4i16:
3286
case ARM::VABDuv4i32:
3287
case ARM::VABDuv8i16:
3288
case ARM::VABDuv8i8:
3289
case ARM::VADDHNv2i32:
3290
case ARM::VADDHNv4i16:
3291
case ARM::VADDHNv8i8:
3292
case ARM::VADDLsv2i64:
3293
case ARM::VADDLsv4i32:
3294
case ARM::VADDLsv8i16:
3295
case ARM::VADDLuv2i64:
3296
case ARM::VADDLuv4i32:
3297
case ARM::VADDLuv8i16:
3298
case ARM::VADDWsv2i64:
3299
case ARM::VADDWsv4i32:
3300
case ARM::VADDWsv8i16:
3301
case ARM::VADDWuv2i64:
3302
case ARM::VADDWuv4i32:
3303
case ARM::VADDWuv8i16:
3304
case ARM::VADDv16i8:
3305
case ARM::VADDv1i64:
3306
case ARM::VADDv2i32:
3307
case ARM::VADDv2i64:
3308
case ARM::VADDv4i16:
3309
case ARM::VADDv4i32:
3310
case ARM::VADDv8i16:
3312
case ARM::VCEQv16i8:
3313
case ARM::VCEQv2i32:
3314
case ARM::VCEQv4i16:
3315
case ARM::VCEQv4i32:
3316
case ARM::VCEQv8i16:
3318
case ARM::VCGEsv16i8:
3319
case ARM::VCGEsv2i32:
3320
case ARM::VCGEsv4i16:
3321
case ARM::VCGEsv4i32:
3322
case ARM::VCGEsv8i16:
3323
case ARM::VCGEsv8i8:
3324
case ARM::VCGEuv16i8:
3325
case ARM::VCGEuv2i32:
3326
case ARM::VCGEuv4i16:
3327
case ARM::VCGEuv4i32:
3328
case ARM::VCGEuv8i16:
3329
case ARM::VCGEuv8i8:
3330
case ARM::VCGTsv16i8:
3331
case ARM::VCGTsv2i32:
3332
case ARM::VCGTsv4i16:
3333
case ARM::VCGTsv4i32:
3334
case ARM::VCGTsv8i16:
3335
case ARM::VCGTsv8i8:
3336
case ARM::VCGTuv16i8:
3337
case ARM::VCGTuv2i32:
3338
case ARM::VCGTuv4i16:
3339
case ARM::VCGTuv4i32:
3340
case ARM::VCGTuv8i16:
3341
case ARM::VCGTuv8i8:
3354
case ARM::VHADDsv16i8:
3355
case ARM::VHADDsv2i32:
3356
case ARM::VHADDsv4i16:
3357
case ARM::VHADDsv4i32:
3358
case ARM::VHADDsv8i16:
3359
case ARM::VHADDsv8i8:
3360
case ARM::VHADDuv16i8:
3361
case ARM::VHADDuv2i32:
3362
case ARM::VHADDuv4i16:
3363
case ARM::VHADDuv4i32:
3364
case ARM::VHADDuv8i16:
3365
case ARM::VHADDuv8i8:
3366
case ARM::VHSUBsv16i8:
3367
case ARM::VHSUBsv2i32:
3368
case ARM::VHSUBsv4i16:
3369
case ARM::VHSUBsv4i32:
3370
case ARM::VHSUBsv8i16:
3371
case ARM::VHSUBsv8i8:
3372
case ARM::VHSUBuv16i8:
3373
case ARM::VHSUBuv2i32:
3374
case ARM::VHSUBuv4i16:
3375
case ARM::VHSUBuv4i32:
3376
case ARM::VHSUBuv8i16:
3377
case ARM::VHSUBuv8i8:
3380
case ARM::VMAXsv16i8:
3381
case ARM::VMAXsv2i32:
3382
case ARM::VMAXsv4i16:
3383
case ARM::VMAXsv4i32:
3384
case ARM::VMAXsv8i16:
3385
case ARM::VMAXsv8i8:
3386
case ARM::VMAXuv16i8:
3387
case ARM::VMAXuv2i32:
3388
case ARM::VMAXuv4i16:
3389
case ARM::VMAXuv4i32:
3390
case ARM::VMAXuv8i16:
3391
case ARM::VMAXuv8i8:
3392
case ARM::VMINsv16i8:
3393
case ARM::VMINsv2i32:
3394
case ARM::VMINsv4i16:
3395
case ARM::VMINsv4i32:
3396
case ARM::VMINsv8i16:
3397
case ARM::VMINsv8i8:
3398
case ARM::VMINuv16i8:
3399
case ARM::VMINuv2i32:
3400
case ARM::VMINuv4i16:
3401
case ARM::VMINuv4i32:
3402
case ARM::VMINuv8i16:
3403
case ARM::VMINuv8i8:
3404
case ARM::VMLALsv2i64:
3405
case ARM::VMLALsv4i32:
3406
case ARM::VMLALsv8i16:
3407
case ARM::VMLALuv2i64:
3408
case ARM::VMLALuv4i32:
3409
case ARM::VMLALuv8i16:
3410
case ARM::VMLAv16i8:
3411
case ARM::VMLAv2i32:
3412
case ARM::VMLAv4i16:
3413
case ARM::VMLAv4i32:
3414
case ARM::VMLAv8i16:
3416
case ARM::VMLSLsv2i64:
3417
case ARM::VMLSLsv4i32:
3418
case ARM::VMLSLsv8i16:
3419
case ARM::VMLSLuv2i64:
3420
case ARM::VMLSLuv4i32:
3421
case ARM::VMLSLuv8i16:
3422
case ARM::VMLSv16i8:
3423
case ARM::VMLSv2i32:
3424
case ARM::VMLSv4i16:
3425
case ARM::VMLSv4i32:
3426
case ARM::VMLSv8i16:
3428
case ARM::VMOVDneon:
3432
case ARM::VMULLsv2i64:
3433
case ARM::VMULLsv4i32:
3434
case ARM::VMULLsv8i16:
3435
case ARM::VMULLuv2i64:
3436
case ARM::VMULLuv4i32:
3437
case ARM::VMULLuv8i16:
3438
case ARM::VMULv16i8:
3439
case ARM::VMULv2i32:
3440
case ARM::VMULv4i16:
3441
case ARM::VMULv4i32:
3442
case ARM::VMULv8i16:
3461
case ARM::VQADDsv16i8:
3462
case ARM::VQADDsv1i64:
3463
case ARM::VQADDsv2i32:
3464
case ARM::VQADDsv2i64:
3465
case ARM::VQADDsv4i16:
3466
case ARM::VQADDsv4i32:
3467
case ARM::VQADDsv8i16:
3468
case ARM::VQADDsv8i8:
3469
case ARM::VQADDuv16i8:
3470
case ARM::VQADDuv1i64:
3471
case ARM::VQADDuv2i32:
3472
case ARM::VQADDuv2i64:
3473
case ARM::VQADDuv4i16:
3474
case ARM::VQADDuv4i32:
3475
case ARM::VQADDuv8i16:
3476
case ARM::VQADDuv8i8:
3477
case ARM::VQDMLALv2i64:
3478
case ARM::VQDMLALv4i32:
3479
case ARM::VQDMLSLv2i64:
3480
case ARM::VQDMLSLv4i32:
3481
case ARM::VQDMULHv2i32:
3482
case ARM::VQDMULHv4i16:
3483
case ARM::VQDMULHv4i32:
3484
case ARM::VQDMULHv8i16:
3485
case ARM::VQDMULLv2i64:
3486
case ARM::VQDMULLv4i32:
3487
case ARM::VQRDMULHv2i32:
3488
case ARM::VQRDMULHv4i16:
3489
case ARM::VQRDMULHv4i32:
3490
case ARM::VQRDMULHv8i16:
3491
case ARM::VQRSHLsv16i8:
3492
case ARM::VQRSHLsv1i64:
3493
case ARM::VQRSHLsv2i32:
3494
case ARM::VQRSHLsv2i64:
3495
case ARM::VQRSHLsv4i16:
3496
case ARM::VQRSHLsv4i32:
3497
case ARM::VQRSHLsv8i16:
3498
case ARM::VQRSHLsv8i8:
3499
case ARM::VQRSHLuv16i8:
3500
case ARM::VQRSHLuv1i64:
3501
case ARM::VQRSHLuv2i32:
3502
case ARM::VQRSHLuv2i64:
3503
case ARM::VQRSHLuv4i16:
3504
case ARM::VQRSHLuv4i32:
3505
case ARM::VQRSHLuv8i16:
3506
case ARM::VQRSHLuv8i8:
3507
case ARM::VQRSHRNsv2i32:
3508
case ARM::VQRSHRNsv4i16:
3509
case ARM::VQRSHRNsv8i8:
3510
case ARM::VQRSHRNuv2i32:
3511
case ARM::VQRSHRNuv4i16:
3512
case ARM::VQRSHRNuv8i8:
3513
case ARM::VQRSHRUNv2i32:
3514
case ARM::VQRSHRUNv4i16:
3515
case ARM::VQRSHRUNv8i8:
3516
case ARM::VQSHLsiv16i8:
3517
case ARM::VQSHLsiv1i64:
3518
case ARM::VQSHLsiv2i32:
3519
case ARM::VQSHLsiv2i64:
3520
case ARM::VQSHLsiv4i16:
3521
case ARM::VQSHLsiv4i32:
3522
case ARM::VQSHLsiv8i16:
3523
case ARM::VQSHLsiv8i8:
3524
case ARM::VQSHLsuv16i8:
3525
case ARM::VQSHLsuv1i64:
3526
case ARM::VQSHLsuv2i32:
3527
case ARM::VQSHLsuv2i64:
3528
case ARM::VQSHLsuv4i16:
3529
case ARM::VQSHLsuv4i32:
3530
case ARM::VQSHLsuv8i16:
3531
case ARM::VQSHLsuv8i8:
3532
case ARM::VQSHLsv16i8:
3533
case ARM::VQSHLsv1i64:
3534
case ARM::VQSHLsv2i32:
3535
case ARM::VQSHLsv2i64:
3536
case ARM::VQSHLsv4i16:
3537
case ARM::VQSHLsv4i32:
3538
case ARM::VQSHLsv8i16:
3539
case ARM::VQSHLsv8i8:
3540
case ARM::VQSHLuiv16i8:
3541
case ARM::VQSHLuiv1i64:
3542
case ARM::VQSHLuiv2i32:
3543
case ARM::VQSHLuiv2i64:
3544
case ARM::VQSHLuiv4i16:
3545
case ARM::VQSHLuiv4i32:
3546
case ARM::VQSHLuiv8i16:
3547
case ARM::VQSHLuiv8i8:
3548
case ARM::VQSHLuv16i8:
3549
case ARM::VQSHLuv1i64:
3550
case ARM::VQSHLuv2i32:
3551
case ARM::VQSHLuv2i64:
3552
case ARM::VQSHLuv4i16:
3553
case ARM::VQSHLuv4i32:
3554
case ARM::VQSHLuv8i16:
3555
case ARM::VQSHLuv8i8:
3556
case ARM::VQSHRNsv2i32:
3557
case ARM::VQSHRNsv4i16:
3558
case ARM::VQSHRNsv8i8:
3559
case ARM::VQSHRNuv2i32:
3560
case ARM::VQSHRNuv4i16:
3561
case ARM::VQSHRNuv8i8:
3562
case ARM::VQSHRUNv2i32:
3563
case ARM::VQSHRUNv4i16:
3564
case ARM::VQSHRUNv8i8:
3565
case ARM::VQSUBsv16i8:
3566
case ARM::VQSUBsv1i64:
3567
case ARM::VQSUBsv2i32:
3568
case ARM::VQSUBsv2i64:
3569
case ARM::VQSUBsv4i16:
3570
case ARM::VQSUBsv4i32:
3571
case ARM::VQSUBsv8i16:
3572
case ARM::VQSUBsv8i8:
3573
case ARM::VQSUBuv16i8:
3574
case ARM::VQSUBuv1i64:
3575
case ARM::VQSUBuv2i32:
3576
case ARM::VQSUBuv2i64:
3577
case ARM::VQSUBuv4i16:
3578
case ARM::VQSUBuv4i32:
3579
case ARM::VQSUBuv8i16:
3580
case ARM::VQSUBuv8i8:
3581
case ARM::VRADDHNv2i32:
3582
case ARM::VRADDHNv4i16:
3583
case ARM::VRADDHNv8i8:
3586
case ARM::VREV32d16:
3588
case ARM::VREV32q16:
3590
case ARM::VREV64d16:
3591
case ARM::VREV64d32:
3594
case ARM::VREV64q16:
3595
case ARM::VREV64q32:
3598
case ARM::VRHADDsv16i8:
3599
case ARM::VRHADDsv2i32:
3600
case ARM::VRHADDsv4i16:
3601
case ARM::VRHADDsv4i32:
3602
case ARM::VRHADDsv8i16:
3603
case ARM::VRHADDsv8i8:
3604
case ARM::VRHADDuv16i8:
3605
case ARM::VRHADDuv2i32:
3606
case ARM::VRHADDuv4i16:
3607
case ARM::VRHADDuv4i32:
3608
case ARM::VRHADDuv8i16:
3609
case ARM::VRHADDuv8i8:
3610
case ARM::VRSHLsv16i8:
3611
case ARM::VRSHLsv1i64:
3612
case ARM::VRSHLsv2i32:
3613
case ARM::VRSHLsv2i64:
3614
case ARM::VRSHLsv4i16:
3615
case ARM::VRSHLsv4i32:
3616
case ARM::VRSHLsv8i16:
3617
case ARM::VRSHLsv8i8:
3618
case ARM::VRSHLuv16i8:
3619
case ARM::VRSHLuv1i64:
3620
case ARM::VRSHLuv2i32:
3621
case ARM::VRSHLuv2i64:
3622
case ARM::VRSHLuv4i16:
3623
case ARM::VRSHLuv4i32:
3624
case ARM::VRSHLuv8i16:
3625
case ARM::VRSHLuv8i8:
3626
case ARM::VRSHRNv2i32:
3627
case ARM::VRSHRNv4i16:
3628
case ARM::VRSHRNv8i8:
3629
case ARM::VRSHRsv16i8:
3630
case ARM::VRSHRsv1i64:
3631
case ARM::VRSHRsv2i32:
3632
case ARM::VRSHRsv2i64:
3633
case ARM::VRSHRsv4i16:
3634
case ARM::VRSHRsv4i32:
3635
case ARM::VRSHRsv8i16:
3636
case ARM::VRSHRsv8i8:
3637
case ARM::VRSHRuv16i8:
3638
case ARM::VRSHRuv1i64:
3639
case ARM::VRSHRuv2i32:
3640
case ARM::VRSHRuv2i64:
3641
case ARM::VRSHRuv4i16:
3642
case ARM::VRSHRuv4i32:
3643
case ARM::VRSHRuv8i16:
3644
case ARM::VRSHRuv8i8:
3645
case ARM::VRSRAsv16i8:
3646
case ARM::VRSRAsv1i64:
3647
case ARM::VRSRAsv2i32:
3648
case ARM::VRSRAsv2i64:
3649
case ARM::VRSRAsv4i16:
3650
case ARM::VRSRAsv4i32:
3651
case ARM::VRSRAsv8i16:
3652
case ARM::VRSRAsv8i8:
3653
case ARM::VRSRAuv16i8:
3654
case ARM::VRSRAuv1i64:
3655
case ARM::VRSRAuv2i32:
3656
case ARM::VRSRAuv2i64:
3657
case ARM::VRSRAuv4i16:
3658
case ARM::VRSRAuv4i32:
3659
case ARM::VRSRAuv8i16:
3660
case ARM::VRSRAuv8i8:
3661
case ARM::VRSUBHNv2i32:
3662
case ARM::VRSUBHNv4i16:
3663
case ARM::VRSUBHNv8i8:
3667
case ARM::VSHLLsv2i64:
3668
case ARM::VSHLLsv4i32:
3669
case ARM::VSHLLsv8i16:
3670
case ARM::VSHLLuv2i64:
3671
case ARM::VSHLLuv4i32:
3672
case ARM::VSHLLuv8i16:
3673
case ARM::VSHLiv16i8:
3674
case ARM::VSHLiv1i64:
3675
case ARM::VSHLiv2i32:
3676
case ARM::VSHLiv2i64:
3677
case ARM::VSHLiv4i16:
3678
case ARM::VSHLiv4i32:
3679
case ARM::VSHLiv8i16:
3680
case ARM::VSHLiv8i8:
3681
case ARM::VSHLsv16i8:
3682
case ARM::VSHLsv1i64:
3683
case ARM::VSHLsv2i32:
3684
case ARM::VSHLsv2i64:
3685
case ARM::VSHLsv4i16:
3686
case ARM::VSHLsv4i32:
3687
case ARM::VSHLsv8i16:
3688
case ARM::VSHLsv8i8:
3689
case ARM::VSHLuv16i8:
3690
case ARM::VSHLuv1i64:
3691
case ARM::VSHLuv2i32:
3692
case ARM::VSHLuv2i64:
3693
case ARM::VSHLuv4i16:
3694
case ARM::VSHLuv4i32:
3695
case ARM::VSHLuv8i16:
3696
case ARM::VSHLuv8i8:
3697
case ARM::VSHRNv2i32:
3698
case ARM::VSHRNv4i16:
3699
case ARM::VSHRNv8i8:
3700
case ARM::VSHRsv16i8:
3701
case ARM::VSHRsv1i64:
3702
case ARM::VSHRsv2i32:
3703
case ARM::VSHRsv2i64:
3704
case ARM::VSHRsv4i16:
3705
case ARM::VSHRsv4i32:
3706
case ARM::VSHRsv8i16:
3707
case ARM::VSHRsv8i8:
3708
case ARM::VSHRuv16i8:
3709
case ARM::VSHRuv1i64:
3710
case ARM::VSHRuv2i32:
3711
case ARM::VSHRuv2i64:
3712
case ARM::VSHRuv4i16:
3713
case ARM::VSHRuv4i32:
3714
case ARM::VSHRuv8i16:
3715
case ARM::VSHRuv8i8:
3716
case ARM::VSRAsv16i8:
3717
case ARM::VSRAsv1i64:
3718
case ARM::VSRAsv2i32:
3719
case ARM::VSRAsv2i64:
3720
case ARM::VSRAsv4i16:
3721
case ARM::VSRAsv4i32:
3722
case ARM::VSRAsv8i16:
3723
case ARM::VSRAsv8i8:
3724
case ARM::VSRAuv16i8:
3725
case ARM::VSRAuv1i64:
3726
case ARM::VSRAuv2i32:
3727
case ARM::VSRAuv2i64:
3728
case ARM::VSRAuv4i16:
3729
case ARM::VSRAuv4i32:
3730
case ARM::VSRAuv8i16:
3731
case ARM::VSRAuv8i8:
3734
case ARM::VSUBHNv2i32:
3735
case ARM::VSUBHNv4i16:
3736
case ARM::VSUBHNv8i8:
3737
case ARM::VSUBLsv2i64:
3738
case ARM::VSUBLsv4i32:
3739
case ARM::VSUBLsv8i16:
3740
case ARM::VSUBLuv2i64:
3741
case ARM::VSUBLuv4i32:
3742
case ARM::VSUBLuv8i16:
3743
case ARM::VSUBWsv2i64:
3744
case ARM::VSUBWsv4i32:
3745
case ARM::VSUBWsv8i16:
3746
case ARM::VSUBWuv2i64:
3747
case ARM::VSUBWuv4i32:
3748
case ARM::VSUBWuv8i16:
3749
case ARM::VSUBv16i8:
3750
case ARM::VSUBv1i64:
3751
case ARM::VSUBv2i32:
3752
case ARM::VSUBv2i64:
3753
case ARM::VSUBv4i16:
3754
case ARM::VSUBv4i32:
3755
case ARM::VSUBv8i16:
3782
case ARM::t2LDRDpci:
3786
case ARM::t2LDRSBi8:
3788
case ARM::t2LDRSHi8:
3791
case ARM::t2MOVTi16:
3801
case ARM::t2SUBrSPi12_:
3802
case ARM::t2SUBrSPi_:
3803
case ARM::t2SUBrSPs_:
3804
case ARM::t2SXTB16r:
3805
case ARM::t2UXTB16r:
3853
switch (MI->getOpcode()) {
3857
case ARM::SBCSSri: printSOImmOperand(MI, 2); break;
3862
case ARM::VABDLsv2i64:
3863
case ARM::VABDLsv4i32:
3864
case ARM::VABDLsv8i16:
3865
case ARM::VABDLuv2i64:
3866
case ARM::VABDLuv4i32:
3867
case ARM::VABDLuv8i16:
3868
case ARM::VABDsv16i8:
3869
case ARM::VABDsv2i32:
3870
case ARM::VABDsv4i16:
3871
case ARM::VABDsv4i32:
3872
case ARM::VABDsv8i16:
3873
case ARM::VABDsv8i8:
3874
case ARM::VABDuv16i8:
3875
case ARM::VABDuv2i32:
3876
case ARM::VABDuv4i16:
3877
case ARM::VABDuv4i32:
3878
case ARM::VABDuv8i16:
3879
case ARM::VABDuv8i8:
3880
case ARM::VADDHNv2i32:
3881
case ARM::VADDHNv4i16:
3882
case ARM::VADDHNv8i8:
3883
case ARM::VADDLsv2i64:
3884
case ARM::VADDLsv4i32:
3885
case ARM::VADDLsv8i16:
3886
case ARM::VADDLuv2i64:
3887
case ARM::VADDLuv4i32:
3888
case ARM::VADDLuv8i16:
3889
case ARM::VADDWsv2i64:
3890
case ARM::VADDWsv4i32:
3891
case ARM::VADDWsv8i16:
3892
case ARM::VADDWuv2i64:
3893
case ARM::VADDWuv4i32:
3894
case ARM::VADDWuv8i16:
3895
case ARM::VADDv16i8:
3896
case ARM::VADDv1i64:
3897
case ARM::VADDv2i32:
3898
case ARM::VADDv2i64:
3899
case ARM::VADDv4i16:
3900
case ARM::VADDv4i32:
3901
case ARM::VADDv8i16:
3903
case ARM::VCEQv16i8:
3904
case ARM::VCEQv2i32:
3905
case ARM::VCEQv4i16:
3906
case ARM::VCEQv4i32:
3907
case ARM::VCEQv8i16:
3909
case ARM::VCGEsv16i8:
3910
case ARM::VCGEsv2i32:
3911
case ARM::VCGEsv4i16:
3912
case ARM::VCGEsv4i32:
3913
case ARM::VCGEsv8i16:
3914
case ARM::VCGEsv8i8:
3915
case ARM::VCGEuv16i8:
3916
case ARM::VCGEuv2i32:
3917
case ARM::VCGEuv4i16:
3918
case ARM::VCGEuv4i32:
3919
case ARM::VCGEuv8i16:
3920
case ARM::VCGEuv8i8:
3921
case ARM::VCGTsv16i8:
3922
case ARM::VCGTsv2i32:
3923
case ARM::VCGTsv4i16:
3924
case ARM::VCGTsv4i32:
3925
case ARM::VCGTsv8i16:
3926
case ARM::VCGTsv8i8:
3927
case ARM::VCGTuv16i8:
3928
case ARM::VCGTuv2i32:
3929
case ARM::VCGTuv4i16:
3930
case ARM::VCGTuv4i32:
3931
case ARM::VCGTuv8i16:
3932
case ARM::VCGTuv8i8:
3933
case ARM::VHADDsv16i8:
3934
case ARM::VHADDsv2i32:
3935
case ARM::VHADDsv4i16:
3936
case ARM::VHADDsv4i32:
3937
case ARM::VHADDsv8i16:
3938
case ARM::VHADDsv8i8:
3939
case ARM::VHADDuv16i8:
3940
case ARM::VHADDuv2i32:
3941
case ARM::VHADDuv4i16:
3942
case ARM::VHADDuv4i32:
3943
case ARM::VHADDuv8i16:
3944
case ARM::VHADDuv8i8:
3945
case ARM::VHSUBsv16i8:
3946
case ARM::VHSUBsv2i32:
3947
case ARM::VHSUBsv4i16:
3948
case ARM::VHSUBsv4i32:
3949
case ARM::VHSUBsv8i16:
3950
case ARM::VHSUBsv8i8:
3951
case ARM::VHSUBuv16i8:
3952
case ARM::VHSUBuv2i32:
3953
case ARM::VHSUBuv4i16:
3954
case ARM::VHSUBuv4i32:
3955
case ARM::VHSUBuv8i16:
3956
case ARM::VHSUBuv8i8:
3957
case ARM::VMAXsv16i8:
3958
case ARM::VMAXsv2i32:
3959
case ARM::VMAXsv4i16:
3960
case ARM::VMAXsv4i32:
3961
case ARM::VMAXsv8i16:
3962
case ARM::VMAXsv8i8:
3963
case ARM::VMAXuv16i8:
3964
case ARM::VMAXuv2i32:
3965
case ARM::VMAXuv4i16:
3966
case ARM::VMAXuv4i32:
3967
case ARM::VMAXuv8i16:
3968
case ARM::VMAXuv8i8:
3969
case ARM::VMINsv16i8:
3970
case ARM::VMINsv2i32:
3971
case ARM::VMINsv4i16:
3972
case ARM::VMINsv4i32:
3973
case ARM::VMINsv8i16:
3974
case ARM::VMINsv8i8:
3975
case ARM::VMINuv16i8:
3976
case ARM::VMINuv2i32:
3977
case ARM::VMINuv4i16:
3978
case ARM::VMINuv4i32:
3979
case ARM::VMINuv8i16:
3980
case ARM::VMINuv8i8:
3981
case ARM::VMULLsv2i64:
3982
case ARM::VMULLsv4i32:
3983
case ARM::VMULLsv8i16:
3984
case ARM::VMULLuv2i64:
3985
case ARM::VMULLuv4i32:
3986
case ARM::VMULLuv8i16:
3987
case ARM::VMULv16i8:
3988
case ARM::VMULv2i32:
3989
case ARM::VMULv4i16:
3990
case ARM::VMULv4i32:
3991
case ARM::VMULv8i16:
4008
case ARM::VQADDsv16i8:
4009
case ARM::VQADDsv1i64:
4010
case ARM::VQADDsv2i32:
4011
case ARM::VQADDsv2i64:
4012
case ARM::VQADDsv4i16:
4013
case ARM::VQADDsv4i32:
4014
case ARM::VQADDsv8i16:
4015
case ARM::VQADDsv8i8:
4016
case ARM::VQADDuv16i8:
4017
case ARM::VQADDuv1i64:
4018
case ARM::VQADDuv2i32:
4019
case ARM::VQADDuv2i64:
4020
case ARM::VQADDuv4i16:
4021
case ARM::VQADDuv4i32:
4022
case ARM::VQADDuv8i16:
4023
case ARM::VQADDuv8i8:
4024
case ARM::VQDMULHv2i32:
4025
case ARM::VQDMULHv4i16:
4026
case ARM::VQDMULHv4i32:
4027
case ARM::VQDMULHv8i16:
4028
case ARM::VQDMULLv2i64:
4029
case ARM::VQDMULLv4i32:
4030
case ARM::VQRDMULHv2i32:
4031
case ARM::VQRDMULHv4i16:
4032
case ARM::VQRDMULHv4i32:
4033
case ARM::VQRDMULHv8i16:
4034
case ARM::VQRSHLsv16i8:
4035
case ARM::VQRSHLsv1i64:
4036
case ARM::VQRSHLsv2i32:
4037
case ARM::VQRSHLsv2i64:
4038
case ARM::VQRSHLsv4i16:
4039
case ARM::VQRSHLsv4i32:
4040
case ARM::VQRSHLsv8i16:
4041
case ARM::VQRSHLsv8i8:
4042
case ARM::VQRSHLuv16i8:
4043
case ARM::VQRSHLuv1i64:
4044
case ARM::VQRSHLuv2i32:
4045
case ARM::VQRSHLuv2i64:
4046
case ARM::VQRSHLuv4i16:
4047
case ARM::VQRSHLuv4i32:
4048
case ARM::VQRSHLuv8i16:
4049
case ARM::VQRSHLuv8i8:
4050
case ARM::VQRSHRNsv2i32:
4051
case ARM::VQRSHRNsv4i16:
4052
case ARM::VQRSHRNsv8i8:
4053
case ARM::VQRSHRNuv2i32:
4054
case ARM::VQRSHRNuv4i16:
4055
case ARM::VQRSHRNuv8i8:
4056
case ARM::VQRSHRUNv2i32:
4057
case ARM::VQRSHRUNv4i16:
4058
case ARM::VQRSHRUNv8i8:
4059
case ARM::VQSHLsiv16i8:
4060
case ARM::VQSHLsiv1i64:
4061
case ARM::VQSHLsiv2i32:
4062
case ARM::VQSHLsiv2i64:
4063
case ARM::VQSHLsiv4i16:
4064
case ARM::VQSHLsiv4i32:
4065
case ARM::VQSHLsiv8i16:
4066
case ARM::VQSHLsiv8i8:
4067
case ARM::VQSHLsuv16i8:
4068
case ARM::VQSHLsuv1i64:
4069
case ARM::VQSHLsuv2i32:
4070
case ARM::VQSHLsuv2i64:
4071
case ARM::VQSHLsuv4i16:
4072
case ARM::VQSHLsuv4i32:
4073
case ARM::VQSHLsuv8i16:
4074
case ARM::VQSHLsuv8i8:
4075
case ARM::VQSHLsv16i8:
4076
case ARM::VQSHLsv1i64:
4077
case ARM::VQSHLsv2i32:
4078
case ARM::VQSHLsv2i64:
4079
case ARM::VQSHLsv4i16:
4080
case ARM::VQSHLsv4i32:
4081
case ARM::VQSHLsv8i16:
4082
case ARM::VQSHLsv8i8:
4083
case ARM::VQSHLuiv16i8:
4084
case ARM::VQSHLuiv1i64:
4085
case ARM::VQSHLuiv2i32:
4086
case ARM::VQSHLuiv2i64:
4087
case ARM::VQSHLuiv4i16:
4088
case ARM::VQSHLuiv4i32:
4089
case ARM::VQSHLuiv8i16:
4090
case ARM::VQSHLuiv8i8:
4091
case ARM::VQSHLuv16i8:
4092
case ARM::VQSHLuv1i64:
4093
case ARM::VQSHLuv2i32:
4094
case ARM::VQSHLuv2i64:
4095
case ARM::VQSHLuv4i16:
4096
case ARM::VQSHLuv4i32:
4097
case ARM::VQSHLuv8i16:
4098
case ARM::VQSHLuv8i8:
4099
case ARM::VQSHRNsv2i32:
4100
case ARM::VQSHRNsv4i16:
4101
case ARM::VQSHRNsv8i8:
4102
case ARM::VQSHRNuv2i32:
4103
case ARM::VQSHRNuv4i16:
4104
case ARM::VQSHRNuv8i8:
4105
case ARM::VQSHRUNv2i32:
4106
case ARM::VQSHRUNv4i16:
4107
case ARM::VQSHRUNv8i8:
4108
case ARM::VQSUBsv16i8:
4109
case ARM::VQSUBsv1i64:
4110
case ARM::VQSUBsv2i32:
4111
case ARM::VQSUBsv2i64:
4112
case ARM::VQSUBsv4i16:
4113
case ARM::VQSUBsv4i32:
4114
case ARM::VQSUBsv8i16:
4115
case ARM::VQSUBsv8i8:
4116
case ARM::VQSUBuv16i8:
4117
case ARM::VQSUBuv1i64:
4118
case ARM::VQSUBuv2i32:
4119
case ARM::VQSUBuv2i64:
4120
case ARM::VQSUBuv4i16:
4121
case ARM::VQSUBuv4i32:
4122
case ARM::VQSUBuv8i16:
4123
case ARM::VQSUBuv8i8:
4124
case ARM::VRADDHNv2i32:
4125
case ARM::VRADDHNv4i16:
4126
case ARM::VRADDHNv8i8:
4127
case ARM::VRHADDsv16i8:
4128
case ARM::VRHADDsv2i32:
4129
case ARM::VRHADDsv4i16:
4130
case ARM::VRHADDsv4i32:
4131
case ARM::VRHADDsv8i16:
4132
case ARM::VRHADDsv8i8:
4133
case ARM::VRHADDuv16i8:
4134
case ARM::VRHADDuv2i32:
4135
case ARM::VRHADDuv4i16:
4136
case ARM::VRHADDuv4i32:
4137
case ARM::VRHADDuv8i16:
4138
case ARM::VRHADDuv8i8:
4139
case ARM::VRSHLsv16i8:
4140
case ARM::VRSHLsv1i64:
4141
case ARM::VRSHLsv2i32:
4142
case ARM::VRSHLsv2i64:
4143
case ARM::VRSHLsv4i16:
4144
case ARM::VRSHLsv4i32:
4145
case ARM::VRSHLsv8i16:
4146
case ARM::VRSHLsv8i8:
4147
case ARM::VRSHLuv16i8:
4148
case ARM::VRSHLuv1i64:
4149
case ARM::VRSHLuv2i32:
4150
case ARM::VRSHLuv2i64:
4151
case ARM::VRSHLuv4i16:
4152
case ARM::VRSHLuv4i32:
4153
case ARM::VRSHLuv8i16:
4154
case ARM::VRSHLuv8i8:
4155
case ARM::VRSHRNv2i32:
4156
case ARM::VRSHRNv4i16:
4157
case ARM::VRSHRNv8i8:
4158
case ARM::VRSHRsv16i8:
4159
case ARM::VRSHRsv1i64:
4160
case ARM::VRSHRsv2i32:
4161
case ARM::VRSHRsv2i64:
4162
case ARM::VRSHRsv4i16:
4163
case ARM::VRSHRsv4i32:
4164
case ARM::VRSHRsv8i16:
4165
case ARM::VRSHRsv8i8:
4166
case ARM::VRSHRuv16i8:
4167
case ARM::VRSHRuv1i64:
4168
case ARM::VRSHRuv2i32:
4169
case ARM::VRSHRuv2i64:
4170
case ARM::VRSHRuv4i16:
4171
case ARM::VRSHRuv4i32:
4172
case ARM::VRSHRuv8i16:
4173
case ARM::VRSHRuv8i8:
4174
case ARM::VRSUBHNv2i32:
4175
case ARM::VRSUBHNv4i16:
4176
case ARM::VRSUBHNv8i8:
4180
case ARM::VSHLLsv2i64:
4181
case ARM::VSHLLsv4i32:
4182
case ARM::VSHLLsv8i16:
4183
case ARM::VSHLLuv2i64:
4184
case ARM::VSHLLuv4i32:
4185
case ARM::VSHLLuv8i16:
4186
case ARM::VSHLiv16i8:
4187
case ARM::VSHLiv1i64:
4188
case ARM::VSHLiv2i32:
4189
case ARM::VSHLiv2i64:
4190
case ARM::VSHLiv4i16:
4191
case ARM::VSHLiv4i32:
4192
case ARM::VSHLiv8i16:
4193
case ARM::VSHLiv8i8:
4194
case ARM::VSHLsv16i8:
4195
case ARM::VSHLsv1i64:
4196
case ARM::VSHLsv2i32:
4197
case ARM::VSHLsv2i64:
4198
case ARM::VSHLsv4i16:
4199
case ARM::VSHLsv4i32:
4200
case ARM::VSHLsv8i16:
4201
case ARM::VSHLsv8i8:
4202
case ARM::VSHLuv16i8:
4203
case ARM::VSHLuv1i64:
4204
case ARM::VSHLuv2i32:
4205
case ARM::VSHLuv2i64:
4206
case ARM::VSHLuv4i16:
4207
case ARM::VSHLuv4i32:
4208
case ARM::VSHLuv8i16:
4209
case ARM::VSHLuv8i8:
4210
case ARM::VSHRNv2i32:
4211
case ARM::VSHRNv4i16:
4212
case ARM::VSHRNv8i8:
4213
case ARM::VSHRsv16i8:
4214
case ARM::VSHRsv1i64:
4215
case ARM::VSHRsv2i32:
4216
case ARM::VSHRsv2i64:
4217
case ARM::VSHRsv4i16:
4218
case ARM::VSHRsv4i32:
4219
case ARM::VSHRsv8i16:
4220
case ARM::VSHRsv8i8:
4221
case ARM::VSHRuv16i8:
4222
case ARM::VSHRuv1i64:
4223
case ARM::VSHRuv2i32:
4224
case ARM::VSHRuv2i64:
4225
case ARM::VSHRuv4i16:
4226
case ARM::VSHRuv4i32:
4227
case ARM::VSHRuv8i16:
4228
case ARM::VSHRuv8i8:
4229
case ARM::VSUBHNv2i32:
4230
case ARM::VSUBHNv4i16:
4231
case ARM::VSUBHNv8i8:
4232
case ARM::VSUBLsv2i64:
4233
case ARM::VSUBLsv4i32:
4234
case ARM::VSUBLsv8i16:
4235
case ARM::VSUBLuv2i64:
4236
case ARM::VSUBLuv4i32:
4237
case ARM::VSUBLuv8i16:
4238
case ARM::VSUBWsv2i64:
4239
case ARM::VSUBWsv4i32:
4240
case ARM::VSUBWsv8i16:
4241
case ARM::VSUBWuv2i64:
4242
case ARM::VSUBWuv4i32:
4243
case ARM::VSUBWuv8i16:
4244
case ARM::VSUBv16i8:
4245
case ARM::VSUBv1i64:
4246
case ARM::VSUBv2i32:
4247
case ARM::VSUBv2i64:
4248
case ARM::VSUBv4i16:
4249
case ARM::VSUBv4i32:
4250
case ARM::VSUBv8i16:
4252
case ARM::t2LDRDpci:
4253
case ARM::t2MOVTi16:
4254
case ARM::t2SUBrSPi12_:
4255
case ARM::t2SUBrSPi_:
4258
case ARM::tMOVCCr: printOperand(MI, 2); break;
4262
case ARM::SBCSSrs: printSORegOperand(MI, 2); break;
4264
case ARM::t2BFC: printBitfieldInvMaskImmOperand(MI, 2); break;
4292
case ARM::VMOVDneon:
4300
case ARM::VREV32d16:
4302
case ARM::VREV32q16:
4304
case ARM::VREV64d16:
4305
case ARM::VREV64d32:
4308
case ARM::VREV64q16:
4309
case ARM::VREV64q32:
4335
case ARM::t2SXTB16r:
4336
case ARM::t2UXTB16r:
4352
case ARM::tUXTH: printOperand(MI, 1); break;
4357
case ARM::TSTri: printSOImmOperand(MI, 1); break;
4362
case ARM::TSTrs: printSORegOperand(MI, 1); break;
4363
case ARM::LDC2_OFFSET:
4364
case ARM::LDC_OFFSET:
4365
case ARM::STC2_OFFSET:
4366
case ARM::STC_OFFSET: printAddrMode2Operand(MI, 2); break;
4371
case ARM::STRB: printAddrMode2Operand(MI, 1); break;
4373
case ARM::STRD: printAddrMode3Operand(MI, 2); break;
4377
case ARM::STRH: printAddrMode3Operand(MI, 1); break;
4378
case ARM::MOVi2pieces: printSOImm2PartOperand(MI, 1); break;
4379
case ARM::VABALsv2i64:
4380
case ARM::VABALsv4i32:
4381
case ARM::VABALsv8i16:
4382
case ARM::VABALuv2i64:
4383
case ARM::VABALuv4i32:
4384
case ARM::VABALuv8i16:
4385
case ARM::VABAsv16i8:
4386
case ARM::VABAsv2i32:
4387
case ARM::VABAsv4i16:
4388
case ARM::VABAsv4i32:
4389
case ARM::VABAsv8i16:
4390
case ARM::VABAsv8i8:
4391
case ARM::VABAuv16i8:
4392
case ARM::VABAuv2i32:
4393
case ARM::VABAuv4i16:
4394
case ARM::VABAuv4i32:
4395
case ARM::VABAuv8i16:
4396
case ARM::VABAuv8i8:
4397
case ARM::VMLALsv2i64:
4398
case ARM::VMLALsv4i32:
4399
case ARM::VMLALsv8i16:
4400
case ARM::VMLALuv2i64:
4401
case ARM::VMLALuv4i32:
4402
case ARM::VMLALuv8i16:
4403
case ARM::VMLAv16i8:
4404
case ARM::VMLAv2i32:
4405
case ARM::VMLAv4i16:
4406
case ARM::VMLAv4i32:
4407
case ARM::VMLAv8i16:
4409
case ARM::VMLSLsv2i64:
4410
case ARM::VMLSLsv4i32:
4411
case ARM::VMLSLsv8i16:
4412
case ARM::VMLSLuv2i64:
4413
case ARM::VMLSLuv4i32:
4414
case ARM::VMLSLuv8i16:
4415
case ARM::VMLSv16i8:
4416
case ARM::VMLSv2i32:
4417
case ARM::VMLSv4i16:
4418
case ARM::VMLSv4i32:
4419
case ARM::VMLSv8i16:
4421
case ARM::VQDMLALv2i64:
4422
case ARM::VQDMLALv4i32:
4423
case ARM::VQDMLSLv2i64:
4424
case ARM::VQDMLSLv4i32:
4425
case ARM::VRSRAsv16i8:
4426
case ARM::VRSRAsv1i64:
4427
case ARM::VRSRAsv2i32:
4428
case ARM::VRSRAsv2i64:
4429
case ARM::VRSRAsv4i16:
4430
case ARM::VRSRAsv4i32:
4431
case ARM::VRSRAsv8i16:
4432
case ARM::VRSRAsv8i8:
4433
case ARM::VRSRAuv16i8:
4434
case ARM::VRSRAuv1i64:
4435
case ARM::VRSRAuv2i32:
4436
case ARM::VRSRAuv2i64:
4437
case ARM::VRSRAuv4i16:
4438
case ARM::VRSRAuv4i32:
4439
case ARM::VRSRAuv8i16:
4440
case ARM::VRSRAuv8i8:
4441
case ARM::VSRAsv16i8:
4442
case ARM::VSRAsv1i64:
4443
case ARM::VSRAsv2i32:
4444
case ARM::VSRAsv2i64:
4445
case ARM::VSRAsv4i16:
4446
case ARM::VSRAsv4i32:
4447
case ARM::VSRAsv8i16:
4448
case ARM::VSRAsv8i8:
4449
case ARM::VSRAuv16i8:
4450
case ARM::VSRAuv1i64:
4451
case ARM::VSRAuv2i32:
4452
case ARM::VSRAuv2i64:
4453
case ARM::VSRAuv4i16:
4454
case ARM::VSRAuv4i32:
4455
case ARM::VSRAuv8i16:
4456
case ARM::VSRAuv8i8:
4463
case ARM::tSUBrr: printOperand(MI, 3); break;
4465
case ARM::VDUPfqf: printOperand(MI, 1, "lane"); break;
4469
case ARM::VSTRS: printAddrMode5Operand(MI, 1); break;
4475
case ARM::t2LDRSBi8:
4477
case ARM::t2LDRSHi8:
4485
case ARM::t2STRi8: printT2AddrModeImm8Operand(MI, 1); break;
4487
case ARM::t2STRDi8: printT2AddrModeImm8s4Operand(MI, 2); break;
4488
case ARM::t2SUBrSPs_: printT2SOOperand(MI, 2); break;
4489
case ARM::tADDrSPi: printThumbS4ImmOperand(MI, 2); break;
4493
case ARM::tSTRi: printThumbAddrModeS4Operand(MI, 1); break;
4497
case ARM::tSTRBi: printThumbAddrModeS1Operand(MI, 1); break;
4501
case ARM::tSTRHi: printThumbAddrModeS2Operand(MI, 1); break;
4503
case ARM::tLDRSH: printThumbAddrModeRROperand(MI, 1); break;
4507
case ARM::tSpill: printThumbAddrModeSPOperand(MI, 1); break;
4508
case ARM::tMUL: printOperand(MI, 0); break;
4534
case ARM::VABSv16i8:
4535
case ARM::VABSv2i32:
4536
case ARM::VABSv4i16:
4537
case ARM::VABSv4i32:
4538
case ARM::VABSv8i16:
4540
case ARM::VCLSv16i8:
4541
case ARM::VCLSv2i32:
4542
case ARM::VCLSv4i16:
4543
case ARM::VCLSv4i32:
4544
case ARM::VCLSv8i16:
4546
case ARM::VCLZv16i8:
4547
case ARM::VCLZv2i32:
4548
case ARM::VCLZv4i16:
4549
case ARM::VCLZv4i32:
4550
case ARM::VCLZv8i16:
4552
case ARM::VMOVLsv2i64:
4553
case ARM::VMOVLsv4i32:
4554
case ARM::VMOVLsv8i16:
4555
case ARM::VMOVLuv2i64:
4556
case ARM::VMOVLuv4i32:
4557
case ARM::VMOVLuv8i16:
4558
case ARM::VMOVNv2i32:
4559
case ARM::VMOVNv4i16:
4560
case ARM::VMOVNv8i8:
4567
case ARM::VPADALsv16i8:
4568
case ARM::VPADALsv2i32:
4569
case ARM::VPADALsv4i16:
4570
case ARM::VPADALsv4i32:
4571
case ARM::VPADALsv8i16:
4572
case ARM::VPADALsv8i8:
4573
case ARM::VPADALuv16i8:
4574
case ARM::VPADALuv2i32:
4575
case ARM::VPADALuv4i16:
4576
case ARM::VPADALuv4i32:
4577
case ARM::VPADALuv8i16:
4578
case ARM::VPADALuv8i8:
4579
case ARM::VPADDLsv16i8:
4580
case ARM::VPADDLsv2i32:
4581
case ARM::VPADDLsv4i16:
4582
case ARM::VPADDLsv4i32:
4583
case ARM::VPADDLsv8i16:
4584
case ARM::VPADDLsv8i8:
4585
case ARM::VPADDLuv16i8:
4586
case ARM::VPADDLuv2i32:
4587
case ARM::VPADDLuv4i16:
4588
case ARM::VPADDLuv4i32:
4589
case ARM::VPADDLuv8i16:
4590
case ARM::VPADDLuv8i8:
4591
case ARM::VQABSv16i8:
4592
case ARM::VQABSv2i32:
4593
case ARM::VQABSv4i16:
4594
case ARM::VQABSv4i32:
4595
case ARM::VQABSv8i16:
4596
case ARM::VQABSv8i8:
4597
case ARM::VQMOVNsuv2i32:
4598
case ARM::VQMOVNsuv4i16:
4599
case ARM::VQMOVNsuv8i8:
4600
case ARM::VQMOVNsv2i32:
4601
case ARM::VQMOVNsv4i16:
4602
case ARM::VQMOVNsv8i8:
4603
case ARM::VQMOVNuv2i32:
4604
case ARM::VQMOVNuv4i16:
4605
case ARM::VQMOVNuv8i8:
4606
case ARM::VQNEGv16i8:
4607
case ARM::VQNEGv2i32:
4608
case ARM::VQNEGv4i16:
4609
case ARM::VQNEGv4i32:
4610
case ARM::VQNEGv8i16:
4611
case ARM::VQNEGv8i8:
4618
case ARM::t2LEApcrel:
4644
case ARM::tMOVgpr2gpr:
4645
case ARM::tMOVgpr2tgpr:
4647
case ARM::tMOVtgpr2gpr:
4700
case ARM::SXTAB16rr:
4723
case ARM::UXTAB16rr:
4738
case ARM::VTSTv16i8:
4739
case ARM::VTSTv2i32:
4740
case ARM::VTSTv4i16:
4741
case ARM::VTSTv4i32:
4742
case ARM::VTSTv8i16:
4746
case ARM::t2ADDrSPi12:
4747
case ARM::t2ADDri12:
4775
case ARM::t2SHADD16:
4779
case ARM::t2SHSUB16:
4797
case ARM::t2SUBrSPi12:
4798
case ARM::t2SUBrSPs:
4799
case ARM::t2SUBri12:
4800
case ARM::t2SXTAB16rr:
4801
case ARM::t2SXTABrr:
4802
case ARM::t2SXTAHrr:
4807
case ARM::t2UHADD16:
4811
case ARM::t2UHSUB16:
4813
case ARM::t2UQADD16:
4817
case ARM::t2UQSUB16:
4824
case ARM::t2UXTAB16rr:
4825
case ARM::t2UXTABrr:
4826
case ARM::t2UXTAHrr:
4828
printOperand(MI, 1);
4830
switch (MI->getOpcode()) {
4833
case ARM::SUBSri: printSOImmOperand(MI, 2); break;
4872
case ARM::SXTAB16rr:
4895
case ARM::UXTAB16rr:
4910
case ARM::VTSTv16i8:
4911
case ARM::VTSTv2i32:
4912
case ARM::VTSTv4i16:
4913
case ARM::VTSTv4i32:
4914
case ARM::VTSTv8i16:
4918
case ARM::t2ADDrSPi12:
4919
case ARM::t2ADDri12:
4944
case ARM::t2SHADD16:
4948
case ARM::t2SHSUB16:
4966
case ARM::t2SUBrSPi12:
4967
case ARM::t2SUBri12:
4968
case ARM::t2SXTAB16rr:
4969
case ARM::t2SXTABrr:
4970
case ARM::t2SXTAHrr:
4975
case ARM::t2UHADD16:
4979
case ARM::t2UHSUB16:
4981
case ARM::t2UQADD16:
4985
case ARM::t2UQSUB16:
4992
case ARM::t2UXTAB16rr:
4993
case ARM::t2UXTABrr:
4994
case ARM::t2UXTAHrr: printOperand(MI, 2); break;
4997
case ARM::SUBSrs: printSORegOperand(MI, 2); break;
4998
case ARM::BFI: printBitfieldInvMaskImmOperand(MI, 2); break;
5002
case ARM::t2SUBrSPs: printT2SOOperand(MI, 2); break;
5008
printJTBlockOperand(MI, 2);
5012
printOperand(MI, 1);
5014
printNoHashImmediate(MI, 2);
5016
printNoHashImmediate(MI, 3);
5018
printNoHashImmediate(MI, 4);
5020
printOperand(MI, 5);
5025
case ARM::LDC2L_OFFSET:
5026
case ARM::LDC2L_OPTION:
5027
case ARM::LDC2L_POST:
5028
case ARM::LDCL_OFFSET:
5029
case ARM::LDCL_OPTION:
5030
case ARM::LDCL_POST:
5038
case ARM::STC2L_OFFSET:
5039
case ARM::STC2L_OPTION:
5040
case ARM::STC2L_POST:
5041
case ARM::STCL_OFFSET:
5042
case ARM::STCL_OPTION:
5043
case ARM::STCL_POST:
5047
case ARM::VABSfd_sfp:
5049
case ARM::VCEQzv16i8:
5050
case ARM::VCEQzv2i32:
5051
case ARM::VCEQzv4i16:
5052
case ARM::VCEQzv4i32:
5053
case ARM::VCEQzv8i16:
5054
case ARM::VCEQzv8i8:
5055
case ARM::VCGEzv16i8:
5056
case ARM::VCGEzv2i32:
5057
case ARM::VCGEzv4i16:
5058
case ARM::VCGEzv4i32:
5059
case ARM::VCGEzv8i16:
5060
case ARM::VCGEzv8i8:
5061
case ARM::VCGTzv16i8:
5062
case ARM::VCGTzv2i32:
5063
case ARM::VCGTzv4i16:
5064
case ARM::VCGTzv4i32:
5065
case ARM::VCGTzv8i16:
5066
case ARM::VCGTzv8i8:
5067
case ARM::VCLEzv16i8:
5068
case ARM::VCLEzv2i32:
5069
case ARM::VCLEzv4i16:
5070
case ARM::VCLEzv4i32:
5071
case ARM::VCLEzv8i16:
5072
case ARM::VCLEzv8i8:
5073
case ARM::VCLTzv16i8:
5074
case ARM::VCLTzv2i32:
5075
case ARM::VCLTzv4i16:
5076
case ARM::VCLTzv4i32:
5077
case ARM::VCLTzv8i16:
5078
case ARM::VCLTzv8i8:
5083
case ARM::VCVTf2xsd:
5084
case ARM::VCVTf2xsq:
5085
case ARM::VCVTf2xud:
5086
case ARM::VCVTf2xuq:
5087
case ARM::VCVTxs2fd:
5088
case ARM::VCVTxs2fq:
5089
case ARM::VCVTxu2fd:
5090
case ARM::VCVTxu2fq:
5102
case ARM::VNEGfd_sfp:
5105
case ARM::VRSQRTEfd:
5106
case ARM::VRSQRTEfq:
5126
case ARM::t2LDRBi12:
5127
case ARM::t2LDRBpci:
5129
case ARM::t2LDRHi12:
5130
case ARM::t2LDRHpci:
5132
case ARM::t2LDRSBi12:
5133
case ARM::t2LDRSBpci:
5135
case ARM::t2LDRSHi12:
5136
case ARM::t2LDRSHpci:
5143
case ARM::t2MOVsra_flag:
5144
case ARM::t2MOVsrl_flag:
5154
case ARM::t2STRBi12:
5156
case ARM::t2STRHi12:
5170
switch (MI->getOpcode()) {
5171
case ARM::FCONSTD: printVFPf64ImmOperand(MI, 1); break;
5172
case ARM::FCONSTS: printVFPf32ImmOperand(MI, 1); break;
5173
case ARM::LDC2L_OFFSET:
5174
case ARM::LDCL_OFFSET:
5175
case ARM::STC2L_OFFSET:
5176
case ARM::STCL_OFFSET: printAddrMode2Operand(MI, 2); break;
5177
case ARM::LDC2L_OPTION:
5178
case ARM::LDCL_OPTION:
5179
case ARM::STC2L_OPTION:
5180
case ARM::STCL_OPTION: printNoHashImmediate(MI, 3); break;
5181
case ARM::LDC2L_POST:
5182
case ARM::LDCL_POST:
5183
case ARM::STC2L_POST:
5184
case ARM::STCL_POST: printAddrMode2OffsetOperand(MI, 3); break;
5185
case ARM::MOVrx: O << ", rrx"; break;
5187
case ARM::t2MRS: O << ", cpsr"; break;
5189
case ARM::t2MRSsys: O << ", spsr"; break;
5192
case ARM::PLIi: O << ']'; break;
5195
case ARM::t2RFEIAW: O << '!'; break;
5199
case ARM::VABSfd_sfp:
5211
case ARM::VNEGfd_sfp:
5214
case ARM::VRSQRTEfd:
5215
case ARM::VRSQRTEfq:
5224
case ARM::t2LDRBpci:
5225
case ARM::t2LDRHpci:
5226
case ARM::t2LDRSBpci:
5227
case ARM::t2LDRSHpci:
5240
case ARM::t2UXTHr: printOperand(MI, 1); break;
5241
case ARM::VCEQzv16i8:
5242
case ARM::VCEQzv2i32:
5243
case ARM::VCEQzv4i16:
5244
case ARM::VCEQzv4i32:
5245
case ARM::VCEQzv8i16:
5246
case ARM::VCEQzv8i8:
5247
case ARM::VCGEzv16i8:
5248
case ARM::VCGEzv2i32:
5249
case ARM::VCGEzv4i16:
5250
case ARM::VCGEzv4i32:
5251
case ARM::VCGEzv8i16:
5252
case ARM::VCGEzv8i8:
5253
case ARM::VCGTzv16i8:
5254
case ARM::VCGTzv2i32:
5255
case ARM::VCGTzv4i16:
5256
case ARM::VCGTzv4i32:
5257
case ARM::VCGTzv8i16:
5258
case ARM::VCGTzv8i8:
5259
case ARM::VCLEzv16i8:
5260
case ARM::VCLEzv2i32:
5261
case ARM::VCLEzv4i16:
5262
case ARM::VCLEzv4i32:
5263
case ARM::VCLEzv8i16:
5264
case ARM::VCLEzv8i8:
5265
case ARM::VCLTzv16i8:
5266
case ARM::VCLTzv2i32:
5267
case ARM::VCLTzv4i16:
5268
case ARM::VCLTzv4i32:
5269
case ARM::VCLTzv8i16:
5270
case ARM::VCLTzv8i8: O << ", #0"; break;
5271
case ARM::VCVTf2xsd:
5272
case ARM::VCVTf2xsq:
5273
case ARM::VCVTf2xud:
5274
case ARM::VCVTf2xuq:
5275
case ARM::VCVTxs2fd:
5276
case ARM::VCVTxs2fq:
5277
case ARM::VCVTxu2fd:
5278
case ARM::VCVTxu2fq:
5292
case ARM::t2MOVCCr: printOperand(MI, 2); break;
5293
case ARM::VMRS: O << ", fpscr"; break;
5299
case ARM::t2TSTrs: printT2SOOperand(MI, 1); break;
5300
case ARM::t2LDRBi12:
5301
case ARM::t2LDRHi12:
5302
case ARM::t2LDRSBi12:
5303
case ARM::t2LDRSHi12:
5305
case ARM::t2STRBi12:
5306
case ARM::t2STRHi12:
5307
case ARM::t2STRi12: printT2AddrModeImm12Operand(MI, 1); break;
5315
case ARM::t2STRs: printT2AddrModeSoRegOperand(MI, 1); break;
5316
case ARM::t2MOVsra_flag:
5317
case ARM::t2MOVsrl_flag: O << ", #1"; break;
5321
case ARM::LDC2L_PRE:
5323
case ARM::STC2L_PRE:
5325
printAddrMode2Operand(MI, 2);
5329
case ARM::LDC2_OPTION:
5330
case ARM::LDC2_POST:
5331
case ARM::LDC_OPTION:
5334
case ARM::LDRB_POST:
5336
case ARM::LDRH_POST:
5338
case ARM::LDRSB_POST:
5340
case ARM::LDRSH_POST:
5343
case ARM::STC2_OPTION:
5344
case ARM::STC2_POST:
5345
case ARM::STC_OPTION:
5348
case ARM::STRB_POST:
5350
case ARM::STRH_POST:
5353
case ARM::t2LDRB_POST:
5354
case ARM::t2LDRH_POST:
5355
case ARM::t2LDRSB_POST:
5356
case ARM::t2LDRSH_POST:
5357
case ARM::t2LDR_POST:
5358
case ARM::t2STRB_POST:
5359
case ARM::t2STRH_POST:
5360
case ARM::t2STR_POST:
5362
printOperand(MI, 2);
5364
switch (MI->getOpcode()) {
5365
case ARM::LDC2_OPTION:
5366
case ARM::LDC_OPTION:
5367
case ARM::STC2_OPTION:
5368
case ARM::STC_OPTION: printOperand(MI, 3); break;
5369
case ARM::LDC2_POST:
5372
case ARM::LDRB_POST:
5376
case ARM::STC2_POST:
5379
case ARM::STRB_POST:
5381
case ARM::STR_POST: printAddrMode2OffsetOperand(MI, 3); break;
5383
case ARM::LDRH_POST:
5384
case ARM::LDRSB_POST:
5386
case ARM::LDRSH_POST:
5388
case ARM::STRH_POST: printAddrMode3OffsetOperand(MI, 3); break;
5389
case ARM::t2LDRB_POST:
5390
case ARM::t2LDRH_POST:
5391
case ARM::t2LDRSB_POST:
5392
case ARM::t2LDRSH_POST:
5393
case ARM::t2LDR_POST:
5394
case ARM::t2STRB_POST:
5395
case ARM::t2STRH_POST:
5396
case ARM::t2STR_POST: printT2AddrModeImm8OffsetOperand(MI, 3); break;
5404
case ARM::LDRSB_PRE:
5405
case ARM::LDRSH_PRE:
5409
case ARM::t2LDRB_PRE:
5410
case ARM::t2LDRH_PRE:
5411
case ARM::t2LDRSB_PRE:
5412
case ARM::t2LDRSH_PRE:
5413
case ARM::t2LDR_PRE:
5415
switch (MI->getOpcode()) {
5421
case ARM::STC_PRE: printAddrMode2Operand(MI, 2); break;
5423
case ARM::LDRSB_PRE:
5424
case ARM::LDRSH_PRE: printAddrMode3Operand(MI, 2); break;
5425
case ARM::t2LDRB_PRE:
5426
case ARM::t2LDRH_PRE:
5427
case ARM::t2LDRSB_PRE:
5428
case ARM::t2LDRSH_PRE:
5429
case ARM::t2LDR_PRE: printT2AddrModeImm8Operand(MI, 2); break;
5439
printAddrMode4Operand(MI, 0);
5441
printRegisterList(MI, 4);
5444
case ARM::LDRD_POST:
5445
case ARM::STRD_POST:
5447
switch (MI->getOpcode()) {
5448
case ARM::LDRD_POST: printOperand(MI, 1); break;
5449
case ARM::STRD_POST: printOperand(MI, 2); break;
5452
printOperand(MI, 3);
5454
printAddrMode3OffsetOperand(MI, 4);
5459
printOperand(MI, 1);
5461
printAddrMode3Operand(MI, 3);
5472
printOperand(MI, 1);
5487
printOperand(MI, 1);
5489
printOperand(MI, 2);
5495
printOperand(MI, 1);
5497
printOperand(MI, 2);
5499
printNoHashImmediate(MI, 3);
5501
printNoHashImmediate(MI, 4);
5503
printOperand(MI, 5);
5509
printNoHashImmediate(MI, 3);
5511
printNoHashImmediate(MI, 4);
5513
printOperand(MI, 5);
5518
printOperand(MI, 1);
5520
printOperand(MI, 2);
5522
printOperand(MI, 3);
5524
printNoHashImmediate(MI, 4);
5530
printOperand(MI, 3);
5532
printNoHashImmediate(MI, 4);
5546
case ARM::VSLIv16i8:
5547
case ARM::VSLIv1i64:
5548
case ARM::VSLIv2i32:
5549
case ARM::VSLIv2i64:
5550
case ARM::VSLIv4i16:
5551
case ARM::VSLIv4i32:
5552
case ARM::VSLIv8i16:
5554
case ARM::VSRIv16i8:
5555
case ARM::VSRIv1i64:
5556
case ARM::VSRIv2i32:
5557
case ARM::VSRIv2i64:
5558
case ARM::VSRIv4i16:
5559
case ARM::VSRIv4i32:
5560
case ARM::VSRIv8i16:
5563
printOperand(MI, 2);
5565
printOperand(MI, 3);
5596
case ARM::SXTAB16rr_rot:
5597
case ARM::SXTABrr_rot:
5598
case ARM::SXTAHrr_rot:
5604
case ARM::UXTAB16rr_rot:
5605
case ARM::UXTABrr_rot:
5606
case ARM::UXTAHrr_rot:
5628
case ARM::t2SMLALBB:
5629
case ARM::t2SMLALBT:
5631
case ARM::t2SMLALDX:
5632
case ARM::t2SMLALTB:
5633
case ARM::t2SMLALTT:
5641
case ARM::t2SMLSLDX:
5647
case ARM::t2SSATasr:
5648
case ARM::t2SSATlsl:
5649
case ARM::t2SXTAB16rr_rot:
5650
case ARM::t2SXTABrr_rot:
5651
case ARM::t2SXTAHrr_rot:
5657
case ARM::t2USATasr:
5658
case ARM::t2USATlsl:
5659
case ARM::t2UXTAB16rr_rot:
5660
case ARM::t2UXTABrr_rot:
5661
case ARM::t2UXTAHrr_rot:
5663
printOperand(MI, 1);
5665
printOperand(MI, 2);
5666
switch (MI->getOpcode()) {
5713
case ARM::t2SMLALBB:
5714
case ARM::t2SMLALBT:
5716
case ARM::t2SMLALDX:
5717
case ARM::t2SMLALTB:
5718
case ARM::t2SMLALTT:
5726
case ARM::t2SMLSLDX:
5736
case ARM::t2USADA8: O << ", "; break;
5741
case ARM::t2SSATlsl:
5742
case ARM::t2USATlsl: O << ", lsl "; break;
5747
case ARM::t2SSATasr:
5748
case ARM::t2USATasr: O << ", asr "; break;
5749
case ARM::SXTAB16rr_rot:
5750
case ARM::SXTABrr_rot:
5751
case ARM::SXTAHrr_rot:
5752
case ARM::UXTAB16rr_rot:
5753
case ARM::UXTABrr_rot:
5754
case ARM::UXTAHrr_rot:
5755
case ARM::t2SXTAB16rr_rot:
5756
case ARM::t2SXTABrr_rot:
5757
case ARM::t2SXTAHrr_rot:
5758
case ARM::t2UXTAB16rr_rot:
5759
case ARM::t2UXTABrr_rot:
5760
case ARM::t2UXTAHrr_rot: O << ", ror "; break;
5762
printOperand(MI, 3);
5765
case ARM::MOVi32imm:
5766
case ARM::t2MOVi32imm:
5768
printOperand(MI, 1, "lo16");
5770
printPredicateOperand(MI, 2);
5772
printOperand(MI, 0);
5774
printOperand(MI, 1, "hi16");
5777
case ARM::MOVsra_flag:
5778
case ARM::MOVsrl_flag:
5780
printOperand(MI, 1);
5781
switch (MI->getOpcode()) {
5782
case ARM::MOVsra_flag: O << ", asr #1"; break;
5783
case ARM::MOVsrl_flag: O << ", lsr #1"; break;
5790
case ARM::t2STRB_PRE:
5791
case ARM::t2STRH_PRE:
5792
case ARM::t2STR_PRE:
5794
printOperand(MI, 2);
5796
switch (MI->getOpcode()) {
5798
case ARM::STR_PRE: printAddrMode2OffsetOperand(MI, 3); break;
5799
case ARM::STRH_PRE: printAddrMode3OffsetOperand(MI, 3); break;
5800
case ARM::t2STRB_PRE:
5801
case ARM::t2STRH_PRE:
5802
case ARM::t2STR_PRE: printT2AddrModeImm8OffsetOperand(MI, 3); break;
5809
printOperand(MI, 2);
5811
printOperand(MI, 3);
5813
printAddrMode3OffsetOperand(MI, 4);
5820
printOperand(MI, 1);
5822
printOperand(MI, 2);
5824
printOperand(MI, 3);
5828
case ARM::SXTB16r_rot:
5829
case ARM::SXTBr_rot:
5830
case ARM::SXTHr_rot:
5831
case ARM::UXTB16r_rot:
5832
case ARM::UXTBr_rot:
5833
case ARM::UXTHr_rot:
5834
case ARM::t2SXTB16r_rot:
5835
case ARM::t2UXTB16r_rot:
5837
printOperand(MI, 1);
5839
printOperand(MI, 2);
5851
case ARM::VADDfd_sfp:
5862
case ARM::VMAXfd_sfp:
5865
case ARM::VMINfd_sfp:
5870
case ARM::VMULfd_sfp:
5879
case ARM::VRSQRTSfd:
5880
case ARM::VRSQRTSfq:
5884
case ARM::VSUBfd_sfp:
5893
case ARM::t2ADDrSPi:
5894
case ARM::t2ADDrSPs:
5922
case ARM::t2SUBrSPi:
5926
printOperand(MI, 1);
5928
switch (MI->getOpcode()) {
5938
case ARM::VADDfd_sfp:
5949
case ARM::VMAXfd_sfp:
5952
case ARM::VMINfd_sfp:
5957
case ARM::VMULfd_sfp:
5966
case ARM::VRSQRTSfd:
5967
case ARM::VRSQRTSfq:
5971
case ARM::VSUBfd_sfp:
5977
case ARM::t2ADDrSPi:
5997
case ARM::t2SUBrSPi:
5999
case ARM::t2SUBrr: printOperand(MI, 2); break;
6003
case ARM::t2ADDrSPs:
6012
case ARM::t2SUBrs: printT2SOOperand(MI, 2); break;
6016
case ARM::VCEQzv2f32:
6017
case ARM::VCEQzv4f32:
6018
case ARM::VCGEzv2f32:
6019
case ARM::VCGEzv4f32:
6020
case ARM::VCGTzv2f32:
6021
case ARM::VCGTzv4f32:
6022
case ARM::VCLEzv2f32:
6023
case ARM::VCLEzv4f32:
6024
case ARM::VCLTzv2f32:
6025
case ARM::VCLTzv4f32:
6026
printOperand(MI, 1);
6030
case ARM::VDUPLN16d:
6031
case ARM::VDUPLN16q:
6032
case ARM::VDUPLN32d:
6033
case ARM::VDUPLN32q:
6038
case ARM::VGETLNi32:
6040
printOperand(MI, 1);
6042
printNoHashImmediate(MI, 2);
6046
case ARM::VGETLNs16:
6048
case ARM::VGETLNu16:
6051
printNoHashImmediate(MI, 2);
6072
switch (MI->getOpcode()) {
6083
case ARM::VST3q8b: printAddrMode6Operand(MI, 1); break;
6088
case ARM::VST1df: printAddrMode6Operand(MI, 0); break;
6109
printOperand(MI, 1);
6111
printOperand(MI, 2);
6113
printOperand(MI, 3);
6115
switch (MI->getOpcode()) {
6125
case ARM::VLD4d8: printAddrMode6Operand(MI, 4); break;
6131
case ARM::VLD4q8b: printAddrMode6Operand(MI, 5); break;
6149
printOperand(MI, 1);
6151
printOperand(MI, 2);
6153
switch (MI->getOpcode()) {
6160
case ARM::VLD3d8: printAddrMode6Operand(MI, 3); break;
6166
case ARM::VLD3q8b: printAddrMode6Operand(MI, 4); break;
6170
case ARM::VLD2LNd16:
6171
case ARM::VLD2LNd32:
6173
case ARM::VLD2LNq16a:
6174
case ARM::VLD2LNq16b:
6175
case ARM::VLD2LNq32a:
6176
case ARM::VLD2LNq32b:
6178
printNoHashImmediate(MI, 8);
6180
printOperand(MI, 1);
6182
printNoHashImmediate(MI, 8);
6184
printAddrMode6Operand(MI, 2);
6195
printOperand(MI, 1);
6197
printAddrMode6Operand(MI, 2);
6200
case ARM::VLD3LNd16:
6201
case ARM::VLD3LNd32:
6203
case ARM::VLD3LNq16a:
6204
case ARM::VLD3LNq16b:
6205
case ARM::VLD3LNq32a:
6206
case ARM::VLD3LNq32b:
6208
printNoHashImmediate(MI, 10);
6210
printOperand(MI, 1);
6212
printNoHashImmediate(MI, 10);
6214
printOperand(MI, 2);
6216
printNoHashImmediate(MI, 10);
6218
printAddrMode6Operand(MI, 3);
6221
case ARM::VLD4LNd16:
6222
case ARM::VLD4LNd32:
6224
case ARM::VLD4LNq16a:
6225
case ARM::VLD4LNq16b:
6226
case ARM::VLD4LNq32a:
6227
case ARM::VLD4LNq32b:
6229
printNoHashImmediate(MI, 12);
6231
printOperand(MI, 1);
6233
printNoHashImmediate(MI, 12);
6235
printOperand(MI, 2);
6237
printNoHashImmediate(MI, 12);
6239
printOperand(MI, 3);
6241
printNoHashImmediate(MI, 12);
6243
printAddrMode6Operand(MI, 4);
6258
case ARM::t2MOVCCasr:
6259
case ARM::t2MOVCClsl:
6260
case ARM::t2MOVCClsr:
6261
case ARM::t2MOVCCror:
6262
printOperand(MI, 2);
6264
printOperand(MI, 3);
6267
case ARM::VMLALslsv2i32:
6268
case ARM::VMLALslsv4i16:
6269
case ARM::VMLALsluv2i32:
6270
case ARM::VMLALsluv4i16:
6271
case ARM::VMLAslv2i32:
6272
case ARM::VMLAslv4i16:
6273
case ARM::VMLAslv4i32:
6274
case ARM::VMLAslv8i16:
6275
case ARM::VMLSLslsv2i32:
6276
case ARM::VMLSLslsv4i16:
6277
case ARM::VMLSLsluv2i32:
6278
case ARM::VMLSLsluv4i16:
6279
case ARM::VMLSslv2i32:
6280
case ARM::VMLSslv4i16:
6281
case ARM::VMLSslv4i32:
6282
case ARM::VMLSslv8i16:
6283
case ARM::VQDMLALslv2i32:
6284
case ARM::VQDMLALslv4i16:
6285
case ARM::VQDMLSLslv2i32:
6286
case ARM::VQDMLSLslv4i16:
6288
printOperand(MI, 3);
6290
printNoHashImmediate(MI, 4);
6298
printOperand(MI, 2);
6300
printOperand(MI, 3);
6302
printNoHashImmediate(MI, 4);
6306
case ARM::VMULLslsv2i32:
6307
case ARM::VMULLslsv4i16:
6308
case ARM::VMULLsluv2i32:
6309
case ARM::VMULLsluv4i16:
6310
case ARM::VMULslv2i32:
6311
case ARM::VMULslv4i16:
6312
case ARM::VMULslv4i32:
6313
case ARM::VMULslv8i16:
6314
case ARM::VQDMULHslv2i32:
6315
case ARM::VQDMULHslv4i16:
6316
case ARM::VQDMULHslv4i32:
6317
case ARM::VQDMULHslv8i16:
6318
case ARM::VQDMULLslv2i32:
6319
case ARM::VQDMULLslv4i16:
6320
case ARM::VQRDMULHslv2i32:
6321
case ARM::VQRDMULHslv4i16:
6322
case ARM::VQRDMULHslv4i32:
6323
case ARM::VQRDMULHslv8i16:
6325
printOperand(MI, 2);
6327
printNoHashImmediate(MI, 3);
6333
printOperand(MI, 1);
6335
printOperand(MI, 2);
6337
printNoHashImmediate(MI, 3);
6341
case ARM::VSETLNi16:
6342
case ARM::VSETLNi32:
6345
printNoHashImmediate(MI, 3);
6347
printOperand(MI, 2);
6361
printOperand(MI, 5);
6363
printOperand(MI, 6);
6365
printOperand(MI, 7);
6367
printAddrMode6Operand(MI, 0);
6378
printOperand(MI, 5);
6380
printOperand(MI, 6);
6382
printAddrMode6Operand(MI, 0);
6385
case ARM::VST2LNd16:
6386
case ARM::VST2LNd32:
6388
case ARM::VST2LNq16a:
6389
case ARM::VST2LNq16b:
6390
case ARM::VST2LNq32a:
6391
case ARM::VST2LNq32b:
6393
printNoHashImmediate(MI, 6);
6395
printOperand(MI, 5);
6397
printNoHashImmediate(MI, 6);
6399
printAddrMode6Operand(MI, 0);
6410
printOperand(MI, 5);
6412
printAddrMode6Operand(MI, 0);
6415
case ARM::VST3LNd16:
6416
case ARM::VST3LNd32:
6418
case ARM::VST3LNq16a:
6419
case ARM::VST3LNq16b:
6420
case ARM::VST3LNq32a:
6421
case ARM::VST3LNq32b:
6423
printNoHashImmediate(MI, 7);
6425
printOperand(MI, 5);
6427
printNoHashImmediate(MI, 7);
6429
printOperand(MI, 6);
6431
printNoHashImmediate(MI, 7);
6433
printAddrMode6Operand(MI, 0);
6436
case ARM::VST4LNd16:
6437
case ARM::VST4LNd32:
6439
case ARM::VST4LNq16a:
6440
case ARM::VST4LNq16b:
6441
case ARM::VST4LNq32a:
6442
case ARM::VST4LNq32b:
6444
printNoHashImmediate(MI, 8);
6446
printOperand(MI, 5);
6448
printNoHashImmediate(MI, 8);
6450
printOperand(MI, 6);
6452
printNoHashImmediate(MI, 8);
6454
printOperand(MI, 7);
6456
printNoHashImmediate(MI, 8);
6458
printAddrMode6Operand(MI, 0);
6468
printOperand(MI, 8);
6470
printAddrMode6Operand(MI, 1);
6475
printOperand(MI, 1);
6477
printOperand(MI, 2);
6482
printOperand(MI, 1);
6484
printOperand(MI, 2);
6486
printOperand(MI, 3);
6491
printOperand(MI, 1);
6493
printOperand(MI, 2);
6495
printOperand(MI, 3);
6497
printOperand(MI, 4);
6502
printOperand(MI, 1);
6504
printOperand(MI, 2);
6506
printOperand(MI, 3);
6508
printOperand(MI, 4);
6510
printOperand(MI, 5);
6515
printOperand(MI, 2);
6517
printOperand(MI, 3);
6522
printOperand(MI, 2);
6524
printOperand(MI, 3);
6526
printOperand(MI, 4);
6531
printOperand(MI, 2);
6533
printOperand(MI, 3);
6535
printOperand(MI, 4);
6537
printOperand(MI, 5);
6542
printOperand(MI, 2);
6544
printOperand(MI, 3);
6546
printOperand(MI, 4);
6548
printOperand(MI, 5);
6550
printOperand(MI, 6);
6553
case ARM::t2LDRpci_pic:
6554
case ARM::tLDRpci_pic:
6556
printPCLabel(MI, 2);
6558
printOperand(MI, 0);
6562
case ARM::t2LEApcrelJT:
6564
printNoHashImmediate(MI, 2);
6569
printOperand(MI, 0);
6571
printOperand(MI, 1);
6574
case ARM::t2SXTBr_rot:
6575
case ARM::t2SXTHr_rot:
6576
case ARM::t2UXTBr_rot:
6577
case ARM::t2UXTHr_rot:
6578
printOperand(MI, 1);
6580
printOperand(MI, 2);
6583
case ARM::tLEApcrel:
6585
printOperand(MI, 1);
6588
case ARM::tLEApcrelJT:
6590
printOperand(MI, 1);
6592
printNoHashImmediate(MI, 2);
6600
/// getRegisterName - This method is automatically generated by tblgen
6601
/// from the register set description. This returns the assembler name
6602
/// for the specified register.
6603
const char *ARMAsmPrinter::getRegisterName(unsigned RegNo) {
6604
assert(RegNo && RegNo < 100 && "Invalid register number!");
6606
static const unsigned RegAsmOffset[] = {
6607
0, 5, 8, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51,
6608
54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 97, 101, 105,
6609
108, 111, 114, 117, 120, 123, 129, 132, 135, 138, 141, 145, 149, 153,
6610
157, 161, 165, 168, 171, 174, 177, 180, 183, 186, 189, 192, 195, 199,
6611
203, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237, 241, 245,
6612
249, 253, 257, 261, 265, 269, 273, 277, 280, 284, 288, 292, 296, 300,
6613
304, 308, 312, 316, 320, 323, 327, 331, 334, 337, 340, 343, 346, 349,
6617
const char *AsmStrs =
6618
"cpsr\000d0\000d1\000d10\000d11\000d12\000d13\000d14\000d15\000d16\000d1"
6619
"7\000d18\000d19\000d2\000d20\000d21\000d22\000d23\000d24\000d25\000d26\000"
6620
"d27\000d28\000d29\000d3\000d30\000d31\000d4\000d5\000d6\000d7\000d8\000"
6621
"d9\000fpscr\000lr\000pc\000q0\000q1\000q10\000q11\000q12\000q13\000q14\000"
6622
"q15\000q2\000q3\000q4\000q5\000q6\000q7\000q8\000q9\000r0\000r1\000r10\000"
6623
"r11\000r12\000r2\000r3\000r4\000r5\000r6\000r7\000r8\000r9\000s0\000s1\000"
6624
"s10\000s11\000s12\000s13\000s14\000s15\000s16\000s17\000s18\000s19\000s"
6625
"2\000s20\000s21\000s22\000s23\000s24\000s25\000s26\000s27\000s28\000s29"
6626
"\000s3\000s30\000s31\000s4\000s5\000s6\000s7\000s8\000s9\000sINVALID\000"
6628
return AsmStrs+RegAsmOffset[RegNo-1];
6632
#ifdef GET_INSTRUCTION_NAME
6633
#undef GET_INSTRUCTION_NAME
6635
/// getInstructionName: This method is automatically generated by tblgen
6636
/// from the instruction set description. This returns the enum name of the
6637
/// specified instruction.
6638
const char *ARMAsmPrinter::getInstructionName(unsigned Opcode) {
6639
assert(Opcode < 1945 && "Invalid instruction number!");
6641
static const unsigned InstAsmOffset[] = {
6642
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 138,
6643
146, 154, 160, 166, 172, 179, 186, 193, 199, 205, 211, 228, 243, 249,
6644
255, 261, 281, 301, 320, 340, 360, 379, 399, 419, 438, 459, 480, 500,
6645
519, 538, 556, 576, 596, 615, 635, 655, 674, 690, 706, 721, 723, 727,
6646
731, 737, 743, 749, 754, 757, 761, 767, 775, 780, 790, 796, 805, 812,
6647
819, 822, 826, 833, 838, 842, 846, 851, 857, 861, 868, 875, 882, 888,
6648
894, 900, 907, 914, 921, 937, 941, 945, 952, 961, 968, 977, 984, 993,
6649
999, 1006, 1015, 1022, 1031, 1038, 1047, 1053, 1059, 1065, 1071, 1079, 1087, 1094,
6650
1100, 1117, 1134, 1152, 1170, 1189, 1202, 1215, 1226, 1236, 1248, 1260, 1270, 1279,
6651
1291, 1303, 1313, 1322, 1333, 1344, 1353, 1361, 1365, 1373, 1377, 1382, 1388, 1398,
6652
1407, 1412, 1422, 1431, 1437, 1444, 1451, 1458, 1463, 1469, 1479, 1488, 1494, 1501,
6653
1512, 1522, 1528, 1535, 1546, 1556, 1561, 1570, 1578, 1584, 1593, 1604, 1608, 1613,
6654
1618, 1624, 1628, 1632, 1639, 1646, 1653, 1661, 1666, 1673, 1685, 1695, 1700, 1706,
6655
1711, 1723, 1735, 1739, 1744, 1749, 1755, 1759, 1766, 1770, 1775, 1782, 1790, 1794,
6656
1799, 1804, 1809, 1813, 1819, 1825, 1831, 1838, 1845, 1853, 1861, 1870, 1879, 1886,
6657
1894, 1902, 1908, 1914, 1920, 1926, 1931, 1936, 1941, 1946, 1951, 1958, 1964, 1969,
6658
1975, 1981, 1986, 1991, 1998, 2004, 2009, 2013, 2019, 2025, 2029, 2034, 2041, 2048,
6659
2054, 2060, 2067, 2074, 2080, 2086, 2093, 2099, 2104, 2112, 2120, 2128, 2134, 2140,
6660
2146, 2151, 2155, 2164, 2173, 2177, 2185, 2192, 2198, 2204, 2212, 2219, 2223, 2230,
6661
2237, 2243, 2250, 2256, 2264, 2272, 2279, 2287, 2295, 2303, 2310, 2317, 2324, 2331,
6662
2337, 2344, 2351, 2359, 2365, 2372, 2378, 2385, 2391, 2398, 2404, 2411, 2418, 2425,
6663
2431, 2438, 2445, 2452, 2459, 2465, 2472, 2476, 2481, 2488, 2496, 2504, 2509, 2516,
6664
2522, 2535, 2548, 2559, 2569, 2581, 2593, 2603, 2612, 2624, 2636, 2646, 2655, 2666,
6665
2677, 2686, 2694, 2698, 2702, 2707, 2713, 2723, 2732, 2737, 2747, 2756, 2762, 2769,
6666
2776, 2783, 2788, 2794, 2804, 2813, 2818, 2827, 2835, 2842, 2849, 2856, 2862, 2868,
6667
2874, 2878, 2882, 2887, 2897, 2911, 2919, 2931, 2939, 2951, 2959, 2971, 2977, 2987,
6668
2993, 3003, 3009, 3015, 3021, 3028, 3033, 3039, 3045, 3051, 3058, 3064, 3069, 3074,
6669
3082, 3089, 3095, 3101, 3109, 3116, 3122, 3128, 3134, 3142, 3149, 3155, 3161, 3169,
6670
3176, 3182, 3189, 3196, 3204, 3212, 3217, 3224, 3230, 3240, 3254, 3262, 3274, 3282,
6671
3294, 3302, 3314, 3320, 3330, 3336, 3346, 3358, 3370, 3382, 3394, 3406, 3418, 3429,
6672
3440, 3451, 3462, 3473, 3483, 3494, 3505, 3516, 3527, 3538, 3548, 3560, 3572, 3584,
6673
3596, 3608, 3620, 3627, 3634, 3645, 3656, 3667, 3678, 3689, 3699, 3710, 3721, 3732,
6674
3743, 3754, 3764, 3770, 3776, 3783, 3794, 3801, 3811, 3821, 3831, 3841, 3851, 3860,
6675
3867, 3874, 3881, 3888, 3894, 3906, 3918, 3929, 3941, 3953, 3965, 3977, 3989, 4001,
6676
4007, 4019, 4031, 4043, 4055, 4067, 4079, 4086, 4097, 4104, 4114, 4124, 4134, 4144,
6677
4154, 4164, 4174, 4183, 4189, 4195, 4201, 4207, 4213, 4219, 4225, 4231, 4237, 4243,
6678
4250, 4257, 4267, 4277, 4287, 4297, 4307, 4316, 4327, 4338, 4349, 4360, 4371, 4382,
6679
4393, 4403, 4410, 4417, 4428, 4439, 4450, 4461, 4472, 4482, 4493, 4504, 4515, 4526,
6680
4537, 4547, 4558, 4569, 4580, 4591, 4602, 4613, 4624, 4634, 4641, 4648, 4659, 4670,
6681
4681, 4692, 4703, 4713, 4724, 4735, 4746, 4757, 4768, 4778, 4789, 4800, 4811, 4822,
6682
4833, 4844, 4855, 4865, 4876, 4887, 4898, 4909, 4920, 4931, 4942, 4952, 4962, 4972,
6683
4982, 4992, 5002, 5011, 5022, 5033, 5044, 5055, 5066, 5077, 5088, 5098, 5108, 5118,
6684
5128, 5138, 5148, 5157, 5163, 5170, 5177, 5185, 5193, 5199, 5206, 5213, 5219, 5225,
6685
5233, 5241, 5248, 5255, 5263, 5271, 5280, 5293, 5302, 5311, 5324, 5333, 5343, 5353,
6686
5363, 5373, 5382, 5395, 5404, 5413, 5426, 5435, 5445, 5455, 5465, 5475, 5481, 5487,
6687
5495, 5503, 5511, 5519, 5526, 5533, 5543, 5553, 5563, 5573, 5582, 5591, 5600, 5609,
6688
5616, 5624, 5631, 5639, 5645, 5651, 5659, 5667, 5674, 5681, 5689, 5697, 5704, 5711,
6689
5721, 5731, 5740, 5750, 5759, 5771, 5783, 5795, 5807, 5819, 5830, 5842, 5854, 5866,
6690
5878, 5890, 5901, 5913, 5925, 5937, 5949, 5961, 5972, 5984, 5996, 6008, 6020, 6032,
6691
6043, 6051, 6060, 6069, 6077, 6086, 6095, 6103, 6110, 6118, 6126, 6133, 6141, 6149,
6692
6157, 6164, 6171, 6181, 6191, 6200, 6211, 6222, 6233, 6244, 6252, 6261, 6269, 6278,
6693
6286, 6293, 6301, 6309, 6317, 6324, 6334, 6344, 6353, 6364, 6375, 6386, 6397, 6405,
6694
6413, 6421, 6428, 6437, 6446, 6455, 6464, 6472, 6480, 6490, 6500, 6509, 6520, 6531,
6695
6542, 6553, 6561, 6569, 6577, 6584, 6593, 6602, 6611, 6620, 6628, 6636, 6642, 6648,
6696
6654, 6660, 6666, 6673, 6684, 6691, 6702, 6713, 6724, 6735, 6746, 6756, 6767, 6778,
6697
6789, 6800, 6811, 6821, 6828, 6839, 6846, 6857, 6868, 6879, 6890, 6901, 6911, 6922,
6698
6933, 6944, 6955, 6966, 6976, 6982, 6996, 7010, 7024, 7038, 7050, 7062, 7074, 7086,
6699
7098, 7110, 7116, 7123, 7130, 7139, 7148, 7160, 7172, 7184, 7196, 7206, 7216, 7226,
6700
7236, 7246, 7255, 7261, 7275, 7289, 7303, 7317, 7329, 7341, 7353, 7365, 7377, 7389,
6701
7395, 7402, 7409, 7418, 7427, 7439, 7451, 7463, 7475, 7485, 7495, 7505, 7515, 7525,
6702
7534, 7540, 7548, 7556, 7566, 7578, 7590, 7602, 7614, 7626, 7638, 7649, 7660, 7670,
6703
7676, 7684, 7692, 7699, 7705, 7712, 7720, 7728, 7738, 7748, 7758, 7768, 7778, 7788,
6704
7798, 7807, 7812, 7817, 7823, 7830, 7844, 7858, 7872, 7886, 7898, 7910, 7922, 7934,
6705
7946, 7958, 7964, 7971, 7982, 7989, 7996, 8003, 8012, 8021, 8033, 8045, 8057, 8069,
6706
8079, 8089, 8099, 8109, 8119, 8128, 8134, 8140, 8146, 8154, 8160, 8168, 8177, 8184,
6707
8195, 8204, 8213, 8222, 8231, 8239, 8247, 8254, 8261, 8268, 8275, 8282, 8289, 8295,
6708
8301, 8307, 8313, 8326, 8339, 8352, 8365, 8378, 8390, 8403, 8416, 8429, 8442, 8455,
6709
8467, 8480, 8493, 8506, 8519, 8532, 8544, 8557, 8570, 8583, 8596, 8609, 8621, 8628,
6710
8637, 8646, 8654, 8661, 8670, 8679, 8687, 8696, 8705, 8713, 8720, 8729, 8738, 8746,
6711
8755, 8764, 8772, 8783, 8794, 8805, 8816, 8827, 8837, 8849, 8861, 8873, 8885, 8897,
6712
8909, 8921, 8932, 8944, 8956, 8968, 8980, 8992, 9004, 9016, 9027, 9042, 9057, 9070,
6713
9083, 9098, 9113, 9126, 9139, 9154, 9169, 9184, 9199, 9212, 9225, 9238, 9251, 9266,
6714
9281, 9294, 9307, 9321, 9335, 9348, 9361, 9374, 9386, 9399, 9412, 9424, 9435, 9446,
6715
9457, 9468, 9479, 9489, 9505, 9521, 9537, 9553, 9567, 9581, 9595, 9609, 9622, 9635,
6716
9648, 9661, 9674, 9687, 9700, 9712, 9725, 9738, 9751, 9764, 9777, 9790, 9803, 9815,
6717
9829, 9843, 9856, 9870, 9884, 9897, 9911, 9925, 9938, 9951, 9964, 9977, 9990, 10003,
6718
10016, 10029, 10041, 10054, 10067, 10080, 10093, 10106, 10119, 10132, 10144, 10156, 10168, 10180,
6719
10192, 10204, 10216, 10228, 10239, 10252, 10265, 10278, 10291, 10304, 10317, 10330, 10342, 10354,
6720
10366, 10378, 10390, 10402, 10414, 10426, 10437, 10450, 10463, 10475, 10488, 10501, 10513, 10526,
6721
10539, 10551, 10563, 10575, 10587, 10599, 10611, 10623, 10635, 10646, 10658, 10670, 10682, 10694,
6722
10706, 10718, 10730, 10741, 10754, 10767, 10779, 10787, 10796, 10805, 10813, 10822, 10831, 10840,
6723
10849, 10859, 10868, 10878, 10887, 10897, 10907, 10916, 10925, 10935, 10945, 10954, 10963, 10976,
6724
10989, 11002, 11015, 11028, 11040, 11053, 11066, 11079, 11092, 11105, 11117, 11129, 11141, 11153,
6725
11165, 11177, 11189, 11201, 11212, 11224, 11236, 11248, 11260, 11272, 11284, 11296, 11307, 11319,
6726
11331, 11342, 11354, 11366, 11378, 11390, 11402, 11414, 11426, 11437, 11449, 11461, 11473, 11485,
6727
11497, 11509, 11521, 11532, 11541, 11551, 11561, 11570, 11580, 11590, 11602, 11614, 11626, 11638,
6728
11650, 11662, 11674, 11685, 11697, 11709, 11721, 11733, 11745, 11757, 11769, 11780, 11793, 11806,
6729
11818, 11828, 11838, 11847, 11856, 11865, 11873, 11885, 11897, 11909, 11921, 11933, 11945, 11956,
6730
11967, 11978, 11989, 12000, 12011, 12022, 12032, 12043, 12054, 12065, 12076, 12087, 12098, 12109,
6731
12119, 12130, 12141, 12152, 12163, 12174, 12185, 12196, 12206, 12217, 12228, 12238, 12249, 12260,
6732
12271, 12282, 12293, 12304, 12315, 12325, 12336, 12347, 12358, 12369, 12380, 12391, 12402, 12412,
6733
12419, 12426, 12433, 12440, 12450, 12460, 12470, 12480, 12490, 12500, 12510, 12519, 12526, 12533,
6734
12540, 12547, 12558, 12569, 12580, 12591, 12602, 12613, 12624, 12634, 12645, 12656, 12667, 12678,
6735
12689, 12700, 12711, 12721, 12731, 12741, 12751, 12761, 12771, 12781, 12791, 12800, 12808, 12817,
6736
12826, 12834, 12843, 12852, 12860, 12867, 12875, 12883, 12890, 12898, 12906, 12914, 12921, 12928,
6737
12938, 12948, 12957, 12968, 12979, 12990, 13001, 13009, 13018, 13026, 13035, 13043, 13050, 13058,
6738
13066, 13074, 13081, 13091, 13101, 13110, 13121, 13132, 13143, 13154, 13162, 13170, 13178, 13185,
6739
13194, 13203, 13212, 13221, 13229, 13237, 13247, 13257, 13266, 13277, 13288, 13299, 13310, 13318,
6740
13326, 13334, 13341, 13350, 13359, 13368, 13377, 13385, 13393, 13399, 13405, 13411, 13417, 13423,
6741
13429, 13441, 13453, 13464, 13476, 13488, 13500, 13512, 13524, 13536, 13542, 13554, 13566, 13578,
6742
13590, 13602, 13614, 13621, 13632, 13639, 13649, 13659, 13669, 13679, 13689, 13699, 13709, 13718,
6743
13724, 13730, 13736, 13742, 13748, 13754, 13760, 13766, 13772, 13778, 13785, 13792, 13800, 13808,
6744
13816, 13824, 13831, 13838, 13845, 13852, 13860, 13868, 13876, 13884, 13891, 13898, 13906, 13914,
6745
13921, 13929, 13937, 13944, 13954, 13964, 13974, 13984, 13994, 14003, 14010, 14017, 14024, 14031,
6746
14038, 14045, 14053, 14061, 14068, 14076, 14084, 14091, 14099, 14107, 14114, 14122, 14130, 14137,
6747
14141, 14145, 14151, 14160, 14169, 14178, 14186, 14194, 14202, 14211, 14220, 14229, 14239, 14251,
6748
14261, 14269, 14279, 14287, 14295, 14303, 14311, 14319, 14327, 14335, 14339, 14345, 14351, 14359,
6749
14367, 14375, 14383, 14389, 14395, 14403, 14409, 14418, 14427, 14436, 14444, 14452, 14460, 14469,
6750
14478, 14487, 14493, 14499, 14508, 14519, 14528, 14539, 14548, 14559, 14567, 14576, 14587, 14596,
6751
14607, 14616, 14627, 14635, 14643, 14651, 14659, 14667, 14672, 14691, 14711, 14732, 14738, 14748,
6752
14756, 14768, 14779, 14789, 14798, 14808, 14816, 14825, 14835, 14843, 14852, 14861, 14870, 14878,
6753
14890, 14901, 14911, 14920, 14930, 14938, 14947, 14960, 14972, 14983, 14993, 15004, 15013, 15022,
6754
15035, 15047, 15058, 15068, 15079, 15088, 15095, 15106, 15116, 15125, 15133, 15142, 15155, 15162,
6755
15173, 15186, 15194, 15202, 15210, 15218, 15224, 15230, 15241, 15250, 15261, 15272, 15281, 15292,
6756
15302, 15309, 15318, 15330, 15337, 15345, 15359, 15373, 15379, 15388, 15394, 15403, 15409, 15416,
6757
15423, 15430, 15436, 15444, 15452, 15460, 15468, 15476, 15484, 15492, 15500, 15510, 15519, 15529,
6758
15537, 15545, 15554, 15562, 15571, 15578, 15585, 15594, 15602, 15611, 15618, 15625, 15632, 15641,
6759
15649, 15656, 15664, 15672, 15679, 15686, 15695, 15703, 15710, 15716, 15724, 15732, 15740, 15749,
6760
15757, 15766, 15774, 15782, 15791, 15800, 15808, 15816, 15825, 15833, 15840, 15849, 15858, 15867,
6761
15875, 15883, 15891, 15898, 15905, 15911, 15917, 15927, 15936, 15944, 15952, 15962, 15971, 15977,
6762
15986, 15995, 16003, 16012, 16020, 16030, 16040, 16049, 16059, 16069, 16079, 16088, 16097, 16106,
6763
16115, 16123, 16132, 16141, 16151, 16159, 16168, 16176, 16185, 16193, 16202, 16210, 16219, 16228,
6764
16237, 16245, 16254, 16263, 16272, 16281, 16289, 16298, 16306, 16315, 16323, 16332, 16341, 16351,
6765
16361, 16368, 16377, 16385, 16391, 16399, 16411, 16422, 16432, 16441, 16449, 16458, 16466, 16475,
6766
16484, 16493, 16501, 16513, 16524, 16534, 16543, 16551, 16558, 16569, 16579, 16588, 16596, 16603,
6767
16612, 16621, 16630, 16640, 16652, 16665, 16676, 16686, 16697, 16705, 16715, 16723, 16731, 16743,
6768
16759, 16769, 16783, 16793, 16807, 16817, 16831, 16839, 16851, 16859, 16871, 16877, 16886, 16892,
6769
16901, 16909, 16917, 16925, 16934, 16942, 16950, 16958, 16967, 16975, 16982, 16989, 16996, 17006,
6770
17015, 17023, 17031, 17041, 17050, 17058, 17066, 17074, 17084, 17093, 17101, 17109, 17119, 17128,
6771
17136, 17145, 17154, 17164, 17174, 17181, 17190, 17198, 17210, 17226, 17236, 17250, 17260, 17274,
6772
17284, 17298, 17306, 17318, 17326, 17338, 17344, 17350, 17358, 17363, 17372, 17379, 17386, 17395,
6773
17403, 17412, 17419, 17427, 17435, 17444, 17462, 17478, 17483, 17490, 17497, 17504, 17507, 17512,
6774
17518, 17522, 17528, 17537, 17543, 17552, 17558, 17565, 17573, 17577, 17585, 17600, 17606, 17611,
6775
17617, 17623, 17628, 17634, 17642, 17649, 17655, 17664, 17672, 17679, 17684, 17689, 17709, 17714,
6776
17719, 17725, 17732, 17738, 17745, 17752, 17759, 17766, 17772, 17780, 17792, 17800, 17810, 17822,
6777
17829, 17836, 17843, 17850, 17858, 17866, 17881, 17888, 17900, 17913, 17920, 17926, 17939, 17944,
6778
17949, 17954, 17959, 17967, 17972, 17981, 17987, 17992, 17999, 18006, 18011, 18016, 18025, 18030,
6779
18040, 18050, 18055, 18060, 18065, 18071, 18078, 18084, 18091, 18097, 18105, 18112, 18119, 18126,
6780
18134, 18143, 18148, 18154, 18160, 18167, 18175, 18181, 18186, 18192, 18198, 18203, 18208, 0
6784
"PHI\000INLINEASM\000DBG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXTRAC"
6785
"T_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_TO_R"
6786
"EGCLASS\000DBG_VALUE\000ADCSSri\000ADCSSrr\000ADCSSrs\000ADCri\000ADCrr"
6787
"\000ADCrs\000ADDSri\000ADDSrr\000ADDSrs\000ADDri\000ADDrr\000ADDrs\000A"
6788
"DJCALLSTACKDOWN\000ADJCALLSTACKUP\000ANDri\000ANDrr\000ANDrs\000ATOMIC_"
6789
"CMP_SWAP_I16\000ATOMIC_CMP_SWAP_I32\000ATOMIC_CMP_SWAP_I8\000ATOMIC_LOA"
6790
"D_ADD_I16\000ATOMIC_LOAD_ADD_I32\000ATOMIC_LOAD_ADD_I8\000ATOMIC_LOAD_A"
6791
"ND_I16\000ATOMIC_LOAD_AND_I32\000ATOMIC_LOAD_AND_I8\000ATOMIC_LOAD_NAND"
6792
"_I16\000ATOMIC_LOAD_NAND_I32\000ATOMIC_LOAD_NAND_I8\000ATOMIC_LOAD_OR_I"
6793
"16\000ATOMIC_LOAD_OR_I32\000ATOMIC_LOAD_OR_I8\000ATOMIC_LOAD_SUB_I16\000"
6794
"ATOMIC_LOAD_SUB_I32\000ATOMIC_LOAD_SUB_I8\000ATOMIC_LOAD_XOR_I16\000ATO"
6795
"MIC_LOAD_XOR_I32\000ATOMIC_LOAD_XOR_I8\000ATOMIC_SWAP_I16\000ATOMIC_SWA"
6796
"P_I32\000ATOMIC_SWAP_I8\000B\000BFC\000BFI\000BICri\000BICrr\000BICrs\000"
6797
"BKPT\000BL\000BLX\000BLXr9\000BL_pred\000BLr9\000BLr9_pred\000BRIND\000"
6798
"BR_JTadd\000BR_JTm\000BR_JTr\000BX\000BXJ\000BX_RET\000BXr9\000Bcc\000C"
6799
"DP\000CDP2\000CLREX\000CLZ\000CMNzri\000CMNzrr\000CMNzrs\000CMPri\000CM"
6800
"Prr\000CMPrs\000CMPzri\000CMPzrr\000CMPzrs\000CONSTPOOL_ENTRY\000CPS\000"
6801
"DBG\000DMBish\000DMBishst\000DMBnsh\000DMBnshst\000DMBosh\000DMBoshst\000"
6802
"DMBst\000DSBish\000DSBishst\000DSBnsh\000DSBnshst\000DSBosh\000DSBoshst"
6803
"\000DSBst\000EORri\000EORrr\000EORrs\000FCONSTD\000FCONSTS\000FMSTAT\000"
6804
"ISBsy\000Int_MemBarrierV6\000Int_MemBarrierV7\000Int_SyncBarrierV6\000I"
6805
"nt_SyncBarrierV7\000Int_eh_sjlj_setjmp\000LDC2L_OFFSET\000LDC2L_OPTION\000"
6806
"LDC2L_POST\000LDC2L_PRE\000LDC2_OFFSET\000LDC2_OPTION\000LDC2_POST\000L"
6807
"DC2_PRE\000LDCL_OFFSET\000LDCL_OPTION\000LDCL_POST\000LDCL_PRE\000LDC_O"
6808
"FFSET\000LDC_OPTION\000LDC_POST\000LDC_PRE\000LDM\000LDM_RET\000LDR\000"
6809
"LDRB\000LDRBT\000LDRB_POST\000LDRB_PRE\000LDRD\000LDRD_POST\000LDRD_PRE"
6810
"\000LDREX\000LDREXB\000LDREXD\000LDREXH\000LDRH\000LDRHT\000LDRH_POST\000"
6811
"LDRH_PRE\000LDRSB\000LDRSBT\000LDRSB_POST\000LDRSB_PRE\000LDRSH\000LDRS"
6812
"HT\000LDRSH_POST\000LDRSH_PRE\000LDRT\000LDR_POST\000LDR_PRE\000LDRcp\000"
6813
"LEApcrel\000LEApcrelJT\000MCR\000MCR2\000MCRR\000MCRR2\000MLA\000MLS\000"
6814
"MOVCCi\000MOVCCr\000MOVCCs\000MOVTi16\000MOVi\000MOVi16\000MOVi2pieces\000"
6815
"MOVi32imm\000MOVr\000MOVrx\000MOVs\000MOVsra_flag\000MOVsrl_flag\000MRC"
6816
"\000MRC2\000MRRC\000MRRC2\000MRS\000MRSsys\000MSR\000MSRi\000MSRsys\000"
6817
"MSRsysi\000MUL\000MVNi\000MVNr\000MVNs\000NOP\000ORRri\000ORRrr\000ORRr"
6818
"s\000PICADD\000PICLDR\000PICLDRB\000PICLDRH\000PICLDRSB\000PICLDRSH\000"
6819
"PICSTR\000PICSTRB\000PICSTRH\000PKHBT\000PKHTB\000PLDWi\000PLDWr\000PLD"
6820
"i\000PLDr\000PLIi\000PLIr\000QADD\000QADD16\000QADD8\000QASX\000QDADD\000"
6821
"QDSUB\000QSAX\000QSUB\000QSUB16\000QSUB8\000RBIT\000REV\000REV16\000REV"
6822
"SH\000RFE\000RFEW\000RSBSri\000RSBSrs\000RSBri\000RSBrs\000RSCSri\000RS"
6823
"CSrs\000RSCri\000RSCrs\000SADD16\000SADD8\000SASX\000SBCSSri\000SBCSSrr"
6824
"\000SBCSSrs\000SBCri\000SBCrr\000SBCrs\000SBFX\000SEL\000SETENDBE\000SE"
6825
"TENDLE\000SEV\000SHADD16\000SHADD8\000SHASX\000SHSAX\000SHSUB16\000SHSU"
6826
"B8\000SMC\000SMLABB\000SMLABT\000SMLAD\000SMLADX\000SMLAL\000SMLALBB\000"
6827
"SMLALBT\000SMLALD\000SMLALDX\000SMLALTB\000SMLALTT\000SMLATB\000SMLATT\000"
6828
"SMLAWB\000SMLAWT\000SMLSD\000SMLSDX\000SMLSLD\000SMLSLDX\000SMMLA\000SM"
6829
"MLAR\000SMMLS\000SMMLSR\000SMMUL\000SMMULR\000SMUAD\000SMUADX\000SMULBB"
6830
"\000SMULBT\000SMULL\000SMULTB\000SMULTT\000SMULWB\000SMULWT\000SMUSD\000"
6831
"SMUSDX\000SRS\000SRSW\000SSAT16\000SSATasr\000SSATlsl\000SSAX\000SSUB16"
6832
"\000SSUB8\000STC2L_OFFSET\000STC2L_OPTION\000STC2L_POST\000STC2L_PRE\000"
6833
"STC2_OFFSET\000STC2_OPTION\000STC2_POST\000STC2_PRE\000STCL_OFFSET\000S"
6834
"TCL_OPTION\000STCL_POST\000STCL_PRE\000STC_OFFSET\000STC_OPTION\000STC_"
6835
"POST\000STC_PRE\000STM\000STR\000STRB\000STRBT\000STRB_POST\000STRB_PRE"
6836
"\000STRD\000STRD_POST\000STRD_PRE\000STREX\000STREXB\000STREXD\000STREX"
6837
"H\000STRH\000STRHT\000STRH_POST\000STRH_PRE\000STRT\000STR_POST\000STR_"
6838
"PRE\000SUBSri\000SUBSrr\000SUBSrs\000SUBri\000SUBrr\000SUBrs\000SVC\000"
6839
"SWP\000SWPB\000SXTAB16rr\000SXTAB16rr_rot\000SXTABrr\000SXTABrr_rot\000"
6840
"SXTAHrr\000SXTAHrr_rot\000SXTB16r\000SXTB16r_rot\000SXTBr\000SXTBr_rot\000"
6841
"SXTHr\000SXTHr_rot\000TEQri\000TEQrr\000TEQrs\000TPsoft\000TRAP\000TSTr"
6842
"i\000TSTrr\000TSTrs\000UADD16\000UADD8\000UASX\000UBFX\000UHADD16\000UH"
6843
"ADD8\000UHASX\000UHSAX\000UHSUB16\000UHSUB8\000UMAAL\000UMLAL\000UMULL\000"
6844
"UQADD16\000UQADD8\000UQASX\000UQSAX\000UQSUB16\000UQSUB8\000USAD8\000US"
6845
"ADA8\000USAT16\000USATasr\000USATlsl\000USAX\000USUB16\000USUB8\000UXTA"
6846
"B16rr\000UXTAB16rr_rot\000UXTABrr\000UXTABrr_rot\000UXTAHrr\000UXTAHrr_"
6847
"rot\000UXTB16r\000UXTB16r_rot\000UXTBr\000UXTBr_rot\000UXTHr\000UXTHr_r"
6848
"ot\000VABALsv2i64\000VABALsv4i32\000VABALsv8i16\000VABALuv2i64\000VABAL"
6849
"uv4i32\000VABALuv8i16\000VABAsv16i8\000VABAsv2i32\000VABAsv4i16\000VABA"
6850
"sv4i32\000VABAsv8i16\000VABAsv8i8\000VABAuv16i8\000VABAuv2i32\000VABAuv"
6851
"4i16\000VABAuv4i32\000VABAuv8i16\000VABAuv8i8\000VABDLsv2i64\000VABDLsv"
6852
"4i32\000VABDLsv8i16\000VABDLuv2i64\000VABDLuv4i32\000VABDLuv8i16\000VAB"
6853
"Dfd\000VABDfq\000VABDsv16i8\000VABDsv2i32\000VABDsv4i16\000VABDsv4i32\000"
6854
"VABDsv8i16\000VABDsv8i8\000VABDuv16i8\000VABDuv2i32\000VABDuv4i16\000VA"
6855
"BDuv4i32\000VABDuv8i16\000VABDuv8i8\000VABSD\000VABSS\000VABSfd\000VABS"
6856
"fd_sfp\000VABSfq\000VABSv16i8\000VABSv2i32\000VABSv4i16\000VABSv4i32\000"
6857
"VABSv8i16\000VABSv8i8\000VACGEd\000VACGEq\000VACGTd\000VACGTq\000VADDD\000"
6858
"VADDHNv2i32\000VADDHNv4i16\000VADDHNv8i8\000VADDLsv2i64\000VADDLsv4i32\000"
6859
"VADDLsv8i16\000VADDLuv2i64\000VADDLuv4i32\000VADDLuv8i16\000VADDS\000VA"
6860
"DDWsv2i64\000VADDWsv4i32\000VADDWsv8i16\000VADDWuv2i64\000VADDWuv4i32\000"
6861
"VADDWuv8i16\000VADDfd\000VADDfd_sfp\000VADDfq\000VADDv16i8\000VADDv1i64"
6862
"\000VADDv2i32\000VADDv2i64\000VADDv4i16\000VADDv4i32\000VADDv8i16\000VA"
6863
"DDv8i8\000VANDd\000VANDq\000VBICd\000VBICq\000VBIFd\000VBIFq\000VBITd\000"
6864
"VBITq\000VBSLd\000VBSLq\000VCEQfd\000VCEQfq\000VCEQv16i8\000VCEQv2i32\000"
6865
"VCEQv4i16\000VCEQv4i32\000VCEQv8i16\000VCEQv8i8\000VCEQzv16i8\000VCEQzv"
6866
"2f32\000VCEQzv2i32\000VCEQzv4f32\000VCEQzv4i16\000VCEQzv4i32\000VCEQzv8"
6867
"i16\000VCEQzv8i8\000VCGEfd\000VCGEfq\000VCGEsv16i8\000VCGEsv2i32\000VCG"
6868
"Esv4i16\000VCGEsv4i32\000VCGEsv8i16\000VCGEsv8i8\000VCGEuv16i8\000VCGEu"
6869
"v2i32\000VCGEuv4i16\000VCGEuv4i32\000VCGEuv8i16\000VCGEuv8i8\000VCGEzv1"
6870
"6i8\000VCGEzv2f32\000VCGEzv2i32\000VCGEzv4f32\000VCGEzv4i16\000VCGEzv4i"
6871
"32\000VCGEzv8i16\000VCGEzv8i8\000VCGTfd\000VCGTfq\000VCGTsv16i8\000VCGT"
6872
"sv2i32\000VCGTsv4i16\000VCGTsv4i32\000VCGTsv8i16\000VCGTsv8i8\000VCGTuv"
6873
"16i8\000VCGTuv2i32\000VCGTuv4i16\000VCGTuv4i32\000VCGTuv8i16\000VCGTuv8"
6874
"i8\000VCGTzv16i8\000VCGTzv2f32\000VCGTzv2i32\000VCGTzv4f32\000VCGTzv4i1"
6875
"6\000VCGTzv4i32\000VCGTzv8i16\000VCGTzv8i8\000VCLEzv16i8\000VCLEzv2f32\000"
6876
"VCLEzv2i32\000VCLEzv4f32\000VCLEzv4i16\000VCLEzv4i32\000VCLEzv8i16\000V"
6877
"CLEzv8i8\000VCLSv16i8\000VCLSv2i32\000VCLSv4i16\000VCLSv4i32\000VCLSv8i"
6878
"16\000VCLSv8i8\000VCLTzv16i8\000VCLTzv2f32\000VCLTzv2i32\000VCLTzv4f32\000"
6879
"VCLTzv4i16\000VCLTzv4i32\000VCLTzv8i16\000VCLTzv8i8\000VCLZv16i8\000VCL"
6880
"Zv2i32\000VCLZv4i16\000VCLZv4i32\000VCLZv8i16\000VCLZv8i8\000VCMPD\000V"
6881
"CMPED\000VCMPES\000VCMPEZD\000VCMPEZS\000VCMPS\000VCMPZD\000VCMPZS\000V"
6882
"CNTd\000VCNTq\000VCVTBHS\000VCVTBSH\000VCVTDS\000VCVTSD\000VCVTTHS\000V"
6883
"CVTTSH\000VCVTf2sd\000VCVTf2sd_sfp\000VCVTf2sq\000VCVTf2ud\000VCVTf2ud_"
6884
"sfp\000VCVTf2uq\000VCVTf2xsd\000VCVTf2xsq\000VCVTf2xud\000VCVTf2xuq\000"
6885
"VCVTs2fd\000VCVTs2fd_sfp\000VCVTs2fq\000VCVTu2fd\000VCVTu2fd_sfp\000VCV"
6886
"Tu2fq\000VCVTxs2fd\000VCVTxs2fq\000VCVTxu2fd\000VCVTxu2fq\000VDIVD\000V"
6887
"DIVS\000VDUP16d\000VDUP16q\000VDUP32d\000VDUP32q\000VDUP8d\000VDUP8q\000"
6888
"VDUPLN16d\000VDUPLN16q\000VDUPLN32d\000VDUPLN32q\000VDUPLN8d\000VDUPLN8"
6889
"q\000VDUPLNfd\000VDUPLNfq\000VDUPfd\000VDUPfdf\000VDUPfq\000VDUPfqf\000"
6890
"VEORd\000VEORq\000VEXTd16\000VEXTd32\000VEXTd8\000VEXTdf\000VEXTq16\000"
6891
"VEXTq32\000VEXTq8\000VEXTqf\000VGETLNi32\000VGETLNs16\000VGETLNs8\000VG"
6892
"ETLNu16\000VGETLNu8\000VHADDsv16i8\000VHADDsv2i32\000VHADDsv4i16\000VHA"
6893
"DDsv4i32\000VHADDsv8i16\000VHADDsv8i8\000VHADDuv16i8\000VHADDuv2i32\000"
6894
"VHADDuv4i16\000VHADDuv4i32\000VHADDuv8i16\000VHADDuv8i8\000VHSUBsv16i8\000"
6895
"VHSUBsv2i32\000VHSUBsv4i16\000VHSUBsv4i32\000VHSUBsv8i16\000VHSUBsv8i8\000"
6896
"VHSUBuv16i8\000VHSUBuv2i32\000VHSUBuv4i16\000VHSUBuv4i32\000VHSUBuv8i16"
6897
"\000VHSUBuv8i8\000VLD1d16\000VLD1d16Q\000VLD1d16T\000VLD1d32\000VLD1d32"
6898
"Q\000VLD1d32T\000VLD1d64\000VLD1d8\000VLD1d8Q\000VLD1d8T\000VLD1df\000V"
6899
"LD1q16\000VLD1q32\000VLD1q64\000VLD1q8\000VLD1qf\000VLD2LNd16\000VLD2LN"
6900
"d32\000VLD2LNd8\000VLD2LNq16a\000VLD2LNq16b\000VLD2LNq32a\000VLD2LNq32b"
6901
"\000VLD2d16\000VLD2d16D\000VLD2d32\000VLD2d32D\000VLD2d64\000VLD2d8\000"
6902
"VLD2d8D\000VLD2q16\000VLD2q32\000VLD2q8\000VLD3LNd16\000VLD3LNd32\000VL"
6903
"D3LNd8\000VLD3LNq16a\000VLD3LNq16b\000VLD3LNq32a\000VLD3LNq32b\000VLD3d"
6904
"16\000VLD3d32\000VLD3d64\000VLD3d8\000VLD3q16a\000VLD3q16b\000VLD3q32a\000"
6905
"VLD3q32b\000VLD3q8a\000VLD3q8b\000VLD4LNd16\000VLD4LNd32\000VLD4LNd8\000"
6906
"VLD4LNq16a\000VLD4LNq16b\000VLD4LNq32a\000VLD4LNq32b\000VLD4d16\000VLD4"
6907
"d32\000VLD4d64\000VLD4d8\000VLD4q16a\000VLD4q16b\000VLD4q32a\000VLD4q32"
6908
"b\000VLD4q8a\000VLD4q8b\000VLDMD\000VLDMS\000VLDRD\000VLDRQ\000VLDRS\000"
6909
"VMAXfd\000VMAXfd_sfp\000VMAXfq\000VMAXsv16i8\000VMAXsv2i32\000VMAXsv4i1"
6910
"6\000VMAXsv4i32\000VMAXsv8i16\000VMAXsv8i8\000VMAXuv16i8\000VMAXuv2i32\000"
6911
"VMAXuv4i16\000VMAXuv4i32\000VMAXuv8i16\000VMAXuv8i8\000VMINfd\000VMINfd"
6912
"_sfp\000VMINfq\000VMINsv16i8\000VMINsv2i32\000VMINsv4i16\000VMINsv4i32\000"
6913
"VMINsv8i16\000VMINsv8i8\000VMINuv16i8\000VMINuv2i32\000VMINuv4i16\000VM"
6914
"INuv4i32\000VMINuv8i16\000VMINuv8i8\000VMLAD\000VMLALslsv2i32\000VMLALs"
6915
"lsv4i16\000VMLALsluv2i32\000VMLALsluv4i16\000VMLALsv2i64\000VMLALsv4i32"
6916
"\000VMLALsv8i16\000VMLALuv2i64\000VMLALuv4i32\000VMLALuv8i16\000VMLAS\000"
6917
"VMLAfd\000VMLAfq\000VMLAslfd\000VMLAslfq\000VMLAslv2i32\000VMLAslv4i16\000"
6918
"VMLAslv4i32\000VMLAslv8i16\000VMLAv16i8\000VMLAv2i32\000VMLAv4i16\000VM"
6919
"LAv4i32\000VMLAv8i16\000VMLAv8i8\000VMLSD\000VMLSLslsv2i32\000VMLSLslsv"
6920
"4i16\000VMLSLsluv2i32\000VMLSLsluv4i16\000VMLSLsv2i64\000VMLSLsv4i32\000"
6921
"VMLSLsv8i16\000VMLSLuv2i64\000VMLSLuv4i32\000VMLSLuv8i16\000VMLSS\000VM"
6922
"LSfd\000VMLSfq\000VMLSslfd\000VMLSslfq\000VMLSslv2i32\000VMLSslv4i16\000"
6923
"VMLSslv4i32\000VMLSslv8i16\000VMLSv16i8\000VMLSv2i32\000VMLSv4i16\000VM"
6924
"LSv4i32\000VMLSv8i16\000VMLSv8i8\000VMOVD\000VMOVDRR\000VMOVDcc\000VMOV"
6925
"Dneon\000VMOVLsv2i64\000VMOVLsv4i32\000VMOVLsv8i16\000VMOVLuv2i64\000VM"
6926
"OVLuv4i32\000VMOVLuv8i16\000VMOVNv2i32\000VMOVNv4i16\000VMOVNv8i8\000VM"
6927
"OVQ\000VMOVRRD\000VMOVRRS\000VMOVRS\000VMOVS\000VMOVSR\000VMOVSRR\000VM"
6928
"OVScc\000VMOVv16i8\000VMOVv1i64\000VMOVv2i32\000VMOVv2i64\000VMOVv4i16\000"
6929
"VMOVv4i32\000VMOVv8i16\000VMOVv8i8\000VMRS\000VMSR\000VMULD\000VMULLp\000"
6930
"VMULLslsv2i32\000VMULLslsv4i16\000VMULLsluv2i32\000VMULLsluv4i16\000VMU"
6931
"LLsv2i64\000VMULLsv4i32\000VMULLsv8i16\000VMULLuv2i64\000VMULLuv4i32\000"
6932
"VMULLuv8i16\000VMULS\000VMULfd\000VMULfd_sfp\000VMULfq\000VMULpd\000VMU"
6933
"Lpq\000VMULslfd\000VMULslfq\000VMULslv2i32\000VMULslv4i16\000VMULslv4i3"
6934
"2\000VMULslv8i16\000VMULv16i8\000VMULv2i32\000VMULv4i16\000VMULv4i32\000"
6935
"VMULv8i16\000VMULv8i8\000VMVNd\000VMVNq\000VNEGD\000VNEGDcc\000VNEGS\000"
6936
"VNEGScc\000VNEGf32q\000VNEGfd\000VNEGfd_sfp\000VNEGs16d\000VNEGs16q\000"
6937
"VNEGs32d\000VNEGs32q\000VNEGs8d\000VNEGs8q\000VNMLAD\000VNMLAS\000VNMLS"
6938
"D\000VNMLSS\000VNMULD\000VNMULS\000VORNd\000VORNq\000VORRd\000VORRq\000"
6939
"VPADALsv16i8\000VPADALsv2i32\000VPADALsv4i16\000VPADALsv4i32\000VPADALs"
6940
"v8i16\000VPADALsv8i8\000VPADALuv16i8\000VPADALuv2i32\000VPADALuv4i16\000"
6941
"VPADALuv4i32\000VPADALuv8i16\000VPADALuv8i8\000VPADDLsv16i8\000VPADDLsv"
6942
"2i32\000VPADDLsv4i16\000VPADDLsv4i32\000VPADDLsv8i16\000VPADDLsv8i8\000"
6943
"VPADDLuv16i8\000VPADDLuv2i32\000VPADDLuv4i16\000VPADDLuv4i32\000VPADDLu"
6944
"v8i16\000VPADDLuv8i8\000VPADDf\000VPADDi16\000VPADDi32\000VPADDi8\000VP"
6945
"MAXf\000VPMAXs16\000VPMAXs32\000VPMAXs8\000VPMAXu16\000VPMAXu32\000VPMA"
6946
"Xu8\000VPMINf\000VPMINs16\000VPMINs32\000VPMINs8\000VPMINu16\000VPMINu3"
6947
"2\000VPMINu8\000VQABSv16i8\000VQABSv2i32\000VQABSv4i16\000VQABSv4i32\000"
6948
"VQABSv8i16\000VQABSv8i8\000VQADDsv16i8\000VQADDsv1i64\000VQADDsv2i32\000"
6949
"VQADDsv2i64\000VQADDsv4i16\000VQADDsv4i32\000VQADDsv8i16\000VQADDsv8i8\000"
6950
"VQADDuv16i8\000VQADDuv1i64\000VQADDuv2i32\000VQADDuv2i64\000VQADDuv4i16"
6951
"\000VQADDuv4i32\000VQADDuv8i16\000VQADDuv8i8\000VQDMLALslv2i32\000VQDML"
6952
"ALslv4i16\000VQDMLALv2i64\000VQDMLALv4i32\000VQDMLSLslv2i32\000VQDMLSLs"
6953
"lv4i16\000VQDMLSLv2i64\000VQDMLSLv4i32\000VQDMULHslv2i32\000VQDMULHslv4"
6954
"i16\000VQDMULHslv4i32\000VQDMULHslv8i16\000VQDMULHv2i32\000VQDMULHv4i16"
6955
"\000VQDMULHv4i32\000VQDMULHv8i16\000VQDMULLslv2i32\000VQDMULLslv4i16\000"
6956
"VQDMULLv2i64\000VQDMULLv4i32\000VQMOVNsuv2i32\000VQMOVNsuv4i16\000VQMOV"
6957
"Nsuv8i8\000VQMOVNsv2i32\000VQMOVNsv4i16\000VQMOVNsv8i8\000VQMOVNuv2i32\000"
6958
"VQMOVNuv4i16\000VQMOVNuv8i8\000VQNEGv16i8\000VQNEGv2i32\000VQNEGv4i16\000"
6959
"VQNEGv4i32\000VQNEGv8i16\000VQNEGv8i8\000VQRDMULHslv2i32\000VQRDMULHslv"
6960
"4i16\000VQRDMULHslv4i32\000VQRDMULHslv8i16\000VQRDMULHv2i32\000VQRDMULH"
6961
"v4i16\000VQRDMULHv4i32\000VQRDMULHv8i16\000VQRSHLsv16i8\000VQRSHLsv1i64"
6962
"\000VQRSHLsv2i32\000VQRSHLsv2i64\000VQRSHLsv4i16\000VQRSHLsv4i32\000VQR"
6963
"SHLsv8i16\000VQRSHLsv8i8\000VQRSHLuv16i8\000VQRSHLuv1i64\000VQRSHLuv2i3"
6964
"2\000VQRSHLuv2i64\000VQRSHLuv4i16\000VQRSHLuv4i32\000VQRSHLuv8i16\000VQ"
6965
"RSHLuv8i8\000VQRSHRNsv2i32\000VQRSHRNsv4i16\000VQRSHRNsv8i8\000VQRSHRNu"
6966
"v2i32\000VQRSHRNuv4i16\000VQRSHRNuv8i8\000VQRSHRUNv2i32\000VQRSHRUNv4i1"
6967
"6\000VQRSHRUNv8i8\000VQSHLsiv16i8\000VQSHLsiv1i64\000VQSHLsiv2i32\000VQ"
6968
"SHLsiv2i64\000VQSHLsiv4i16\000VQSHLsiv4i32\000VQSHLsiv8i16\000VQSHLsiv8"
6969
"i8\000VQSHLsuv16i8\000VQSHLsuv1i64\000VQSHLsuv2i32\000VQSHLsuv2i64\000V"
6970
"QSHLsuv4i16\000VQSHLsuv4i32\000VQSHLsuv8i16\000VQSHLsuv8i8\000VQSHLsv16"
6971
"i8\000VQSHLsv1i64\000VQSHLsv2i32\000VQSHLsv2i64\000VQSHLsv4i16\000VQSHL"
6972
"sv4i32\000VQSHLsv8i16\000VQSHLsv8i8\000VQSHLuiv16i8\000VQSHLuiv1i64\000"
6973
"VQSHLuiv2i32\000VQSHLuiv2i64\000VQSHLuiv4i16\000VQSHLuiv4i32\000VQSHLui"
6974
"v8i16\000VQSHLuiv8i8\000VQSHLuv16i8\000VQSHLuv1i64\000VQSHLuv2i32\000VQ"
6975
"SHLuv2i64\000VQSHLuv4i16\000VQSHLuv4i32\000VQSHLuv8i16\000VQSHLuv8i8\000"
6976
"VQSHRNsv2i32\000VQSHRNsv4i16\000VQSHRNsv8i8\000VQSHRNuv2i32\000VQSHRNuv"
6977
"4i16\000VQSHRNuv8i8\000VQSHRUNv2i32\000VQSHRUNv4i16\000VQSHRUNv8i8\000V"
6978
"QSUBsv16i8\000VQSUBsv1i64\000VQSUBsv2i32\000VQSUBsv2i64\000VQSUBsv4i16\000"
6979
"VQSUBsv4i32\000VQSUBsv8i16\000VQSUBsv8i8\000VQSUBuv16i8\000VQSUBuv1i64\000"
6980
"VQSUBuv2i32\000VQSUBuv2i64\000VQSUBuv4i16\000VQSUBuv4i32\000VQSUBuv8i16"
6981
"\000VQSUBuv8i8\000VRADDHNv2i32\000VRADDHNv4i16\000VRADDHNv8i8\000VRECPE"
6982
"d\000VRECPEfd\000VRECPEfq\000VRECPEq\000VRECPSfd\000VRECPSfq\000VREV16d"
6983
"8\000VREV16q8\000VREV32d16\000VREV32d8\000VREV32q16\000VREV32q8\000VREV"
6984
"64d16\000VREV64d32\000VREV64d8\000VREV64df\000VREV64q16\000VREV64q32\000"
6985
"VREV64q8\000VREV64qf\000VRHADDsv16i8\000VRHADDsv2i32\000VRHADDsv4i16\000"
6986
"VRHADDsv4i32\000VRHADDsv8i16\000VRHADDsv8i8\000VRHADDuv16i8\000VRHADDuv"
6987
"2i32\000VRHADDuv4i16\000VRHADDuv4i32\000VRHADDuv8i16\000VRHADDuv8i8\000"
6988
"VRSHLsv16i8\000VRSHLsv1i64\000VRSHLsv2i32\000VRSHLsv2i64\000VRSHLsv4i16"
6989
"\000VRSHLsv4i32\000VRSHLsv8i16\000VRSHLsv8i8\000VRSHLuv16i8\000VRSHLuv1"
6990
"i64\000VRSHLuv2i32\000VRSHLuv2i64\000VRSHLuv4i16\000VRSHLuv4i32\000VRSH"
6991
"Luv8i16\000VRSHLuv8i8\000VRSHRNv2i32\000VRSHRNv4i16\000VRSHRNv8i8\000VR"
6992
"SHRsv16i8\000VRSHRsv1i64\000VRSHRsv2i32\000VRSHRsv2i64\000VRSHRsv4i16\000"
6993
"VRSHRsv4i32\000VRSHRsv8i16\000VRSHRsv8i8\000VRSHRuv16i8\000VRSHRuv1i64\000"
6994
"VRSHRuv2i32\000VRSHRuv2i64\000VRSHRuv4i16\000VRSHRuv4i32\000VRSHRuv8i16"
6995
"\000VRSHRuv8i8\000VRSQRTEd\000VRSQRTEfd\000VRSQRTEfq\000VRSQRTEq\000VRS"
6996
"QRTSfd\000VRSQRTSfq\000VRSRAsv16i8\000VRSRAsv1i64\000VRSRAsv2i32\000VRS"
6997
"RAsv2i64\000VRSRAsv4i16\000VRSRAsv4i32\000VRSRAsv8i16\000VRSRAsv8i8\000"
6998
"VRSRAuv16i8\000VRSRAuv1i64\000VRSRAuv2i32\000VRSRAuv2i64\000VRSRAuv4i16"
6999
"\000VRSRAuv4i32\000VRSRAuv8i16\000VRSRAuv8i8\000VRSUBHNv2i32\000VRSUBHN"
7000
"v4i16\000VRSUBHNv8i8\000VSETLNi16\000VSETLNi32\000VSETLNi8\000VSHLLi16\000"
7001
"VSHLLi32\000VSHLLi8\000VSHLLsv2i64\000VSHLLsv4i32\000VSHLLsv8i16\000VSH"
7002
"LLuv2i64\000VSHLLuv4i32\000VSHLLuv8i16\000VSHLiv16i8\000VSHLiv1i64\000V"
7003
"SHLiv2i32\000VSHLiv2i64\000VSHLiv4i16\000VSHLiv4i32\000VSHLiv8i16\000VS"
7004
"HLiv8i8\000VSHLsv16i8\000VSHLsv1i64\000VSHLsv2i32\000VSHLsv2i64\000VSHL"
7005
"sv4i16\000VSHLsv4i32\000VSHLsv8i16\000VSHLsv8i8\000VSHLuv16i8\000VSHLuv"
7006
"1i64\000VSHLuv2i32\000VSHLuv2i64\000VSHLuv4i16\000VSHLuv4i32\000VSHLuv8"
7007
"i16\000VSHLuv8i8\000VSHRNv2i32\000VSHRNv4i16\000VSHRNv8i8\000VSHRsv16i8"
7008
"\000VSHRsv1i64\000VSHRsv2i32\000VSHRsv2i64\000VSHRsv4i16\000VSHRsv4i32\000"
7009
"VSHRsv8i16\000VSHRsv8i8\000VSHRuv16i8\000VSHRuv1i64\000VSHRuv2i32\000VS"
7010
"HRuv2i64\000VSHRuv4i16\000VSHRuv4i32\000VSHRuv8i16\000VSHRuv8i8\000VSHT"
7011
"OD\000VSHTOS\000VSITOD\000VSITOS\000VSLIv16i8\000VSLIv1i64\000VSLIv2i32"
7012
"\000VSLIv2i64\000VSLIv4i16\000VSLIv4i32\000VSLIv8i16\000VSLIv8i8\000VSL"
7013
"TOD\000VSLTOS\000VSQRTD\000VSQRTS\000VSRAsv16i8\000VSRAsv1i64\000VSRAsv"
7014
"2i32\000VSRAsv2i64\000VSRAsv4i16\000VSRAsv4i32\000VSRAsv8i16\000VSRAsv8"
7015
"i8\000VSRAuv16i8\000VSRAuv1i64\000VSRAuv2i32\000VSRAuv2i64\000VSRAuv4i1"
7016
"6\000VSRAuv4i32\000VSRAuv8i16\000VSRAuv8i8\000VSRIv16i8\000VSRIv1i64\000"
7017
"VSRIv2i32\000VSRIv2i64\000VSRIv4i16\000VSRIv4i32\000VSRIv8i16\000VSRIv8"
7018
"i8\000VST1d16\000VST1d16Q\000VST1d16T\000VST1d32\000VST1d32Q\000VST1d32"
7019
"T\000VST1d64\000VST1d8\000VST1d8Q\000VST1d8T\000VST1df\000VST1q16\000VS"
7020
"T1q32\000VST1q64\000VST1q8\000VST1qf\000VST2LNd16\000VST2LNd32\000VST2L"
7021
"Nd8\000VST2LNq16a\000VST2LNq16b\000VST2LNq32a\000VST2LNq32b\000VST2d16\000"
7022
"VST2d16D\000VST2d32\000VST2d32D\000VST2d64\000VST2d8\000VST2d8D\000VST2"
7023
"q16\000VST2q32\000VST2q8\000VST3LNd16\000VST3LNd32\000VST3LNd8\000VST3L"
7024
"Nq16a\000VST3LNq16b\000VST3LNq32a\000VST3LNq32b\000VST3d16\000VST3d32\000"
7025
"VST3d64\000VST3d8\000VST3q16a\000VST3q16b\000VST3q32a\000VST3q32b\000VS"
7026
"T3q8a\000VST3q8b\000VST4LNd16\000VST4LNd32\000VST4LNd8\000VST4LNq16a\000"
7027
"VST4LNq16b\000VST4LNq32a\000VST4LNq32b\000VST4d16\000VST4d32\000VST4d64"
7028
"\000VST4d8\000VST4q16a\000VST4q16b\000VST4q32a\000VST4q32b\000VST4q8a\000"
7029
"VST4q8b\000VSTMD\000VSTMS\000VSTRD\000VSTRQ\000VSTRS\000VSUBD\000VSUBHN"
7030
"v2i32\000VSUBHNv4i16\000VSUBHNv8i8\000VSUBLsv2i64\000VSUBLsv4i32\000VSU"
7031
"BLsv8i16\000VSUBLuv2i64\000VSUBLuv4i32\000VSUBLuv8i16\000VSUBS\000VSUBW"
7032
"sv2i64\000VSUBWsv4i32\000VSUBWsv8i16\000VSUBWuv2i64\000VSUBWuv4i32\000V"
7033
"SUBWuv8i16\000VSUBfd\000VSUBfd_sfp\000VSUBfq\000VSUBv16i8\000VSUBv1i64\000"
7034
"VSUBv2i32\000VSUBv2i64\000VSUBv4i16\000VSUBv4i32\000VSUBv8i16\000VSUBv8"
7035
"i8\000VSWPd\000VSWPq\000VTBL1\000VTBL2\000VTBL3\000VTBL4\000VTBX1\000VT"
7036
"BX2\000VTBX3\000VTBX4\000VTOSHD\000VTOSHS\000VTOSIRD\000VTOSIRS\000VTOS"
7037
"IZD\000VTOSIZS\000VTOSLD\000VTOSLS\000VTOUHD\000VTOUHS\000VTOUIRD\000VT"
7038
"OUIRS\000VTOUIZD\000VTOUIZS\000VTOULD\000VTOULS\000VTRNd16\000VTRNd32\000"
7039
"VTRNd8\000VTRNq16\000VTRNq32\000VTRNq8\000VTSTv16i8\000VTSTv2i32\000VTS"
7040
"Tv4i16\000VTSTv4i32\000VTSTv8i16\000VTSTv8i8\000VUHTOD\000VUHTOS\000VUI"
7041
"TOD\000VUITOS\000VULTOD\000VULTOS\000VUZPd16\000VUZPd32\000VUZPd8\000VU"
7042
"ZPq16\000VUZPq32\000VUZPq8\000VZIPd16\000VZIPd32\000VZIPd8\000VZIPq16\000"
7043
"VZIPq32\000VZIPq8\000WFE\000WFI\000YIELD\000t2ADCSri\000t2ADCSrr\000t2A"
7044
"DCSrs\000t2ADCri\000t2ADCrr\000t2ADCrs\000t2ADDSri\000t2ADDSrr\000t2ADD"
7045
"Srs\000t2ADDrSPi\000t2ADDrSPi12\000t2ADDrSPs\000t2ADDri\000t2ADDri12\000"
7046
"t2ADDrr\000t2ADDrs\000t2ANDri\000t2ANDrr\000t2ANDrs\000t2ASRri\000t2ASR"
7047
"rr\000t2B\000t2BFC\000t2BFI\000t2BICri\000t2BICrr\000t2BICrs\000t2BR_JT"
7048
"\000t2BXJ\000t2Bcc\000t2CLREX\000t2CLZ\000t2CMNzri\000t2CMNzrr\000t2CMN"
7049
"zrs\000t2CMPri\000t2CMPrr\000t2CMPrs\000t2CMPzri\000t2CMPzrr\000t2CMPzr"
7050
"s\000t2CPS\000t2DBG\000t2DMBish\000t2DMBishst\000t2DMBnsh\000t2DMBnshst"
7051
"\000t2DMBosh\000t2DMBoshst\000t2DMBst\000t2DSBish\000t2DSBishst\000t2DS"
7052
"Bnsh\000t2DSBnshst\000t2DSBosh\000t2DSBoshst\000t2DSBst\000t2EORri\000t"
7053
"2EORrr\000t2EORrs\000t2ISBsy\000t2IT\000t2Int_MemBarrierV7\000t2Int_Syn"
7054
"cBarrierV7\000t2Int_eh_sjlj_setjmp\000t2LDM\000t2LDM_RET\000t2LDRBT\000"
7055
"t2LDRB_POST\000t2LDRB_PRE\000t2LDRBi12\000t2LDRBi8\000t2LDRBpci\000t2LD"
7056
"RBs\000t2LDRDi8\000t2LDRDpci\000t2LDREX\000t2LDREXB\000t2LDREXD\000t2LD"
7057
"REXH\000t2LDRHT\000t2LDRH_POST\000t2LDRH_PRE\000t2LDRHi12\000t2LDRHi8\000"
7058
"t2LDRHpci\000t2LDRHs\000t2LDRSBT\000t2LDRSB_POST\000t2LDRSB_PRE\000t2LD"
7059
"RSBi12\000t2LDRSBi8\000t2LDRSBpci\000t2LDRSBs\000t2LDRSHT\000t2LDRSH_PO"
7060
"ST\000t2LDRSH_PRE\000t2LDRSHi12\000t2LDRSHi8\000t2LDRSHpci\000t2LDRSHs\000"
7061
"t2LDRT\000t2LDR_POST\000t2LDR_PRE\000t2LDRi12\000t2LDRi8\000t2LDRpci\000"
7062
"t2LDRpci_pic\000t2LDRs\000t2LEApcrel\000t2LEApcrelJT\000t2LSLri\000t2LS"
7063
"Lrr\000t2LSRri\000t2LSRrr\000t2MLA\000t2MLS\000t2MOVCCasr\000t2MOVCCi\000"
7064
"t2MOVCClsl\000t2MOVCClsr\000t2MOVCCr\000t2MOVCCror\000t2MOVTi16\000t2MO"
7065
"Vi\000t2MOVi16\000t2MOVi32imm\000t2MOVr\000t2MOVrx\000t2MOVsra_flag\000"
7066
"t2MOVsrl_flag\000t2MRS\000t2MRSsys\000t2MSR\000t2MSRsys\000t2MUL\000t2M"
7067
"VNi\000t2MVNr\000t2MVNs\000t2NOP\000t2ORNri\000t2ORNrr\000t2ORNrs\000t2"
7068
"ORRri\000t2ORRrr\000t2ORRrs\000t2PKHBT\000t2PKHTB\000t2PLDWi12\000t2PLD"
7069
"Wi8\000t2PLDWpci\000t2PLDWr\000t2PLDWs\000t2PLDi12\000t2PLDi8\000t2PLDp"
7070
"ci\000t2PLDr\000t2PLDs\000t2PLIi12\000t2PLIi8\000t2PLIpci\000t2PLIr\000"
7071
"t2PLIs\000t2QADD\000t2QADD16\000t2QADD8\000t2QASX\000t2QDADD\000t2QDSUB"
7072
"\000t2QSAX\000t2QSUB\000t2QSUB16\000t2QSUB8\000t2RBIT\000t2REV\000t2REV"
7073
"16\000t2REVSH\000t2RFEDB\000t2RFEDBW\000t2RFEIA\000t2RFEIAW\000t2RORri\000"
7074
"t2RORrr\000t2RSBSri\000t2RSBSrs\000t2RSBri\000t2RSBrs\000t2SADD16\000t2"
7075
"SADD8\000t2SASX\000t2SBCSri\000t2SBCSrr\000t2SBCSrs\000t2SBCri\000t2SBC"
7076
"rr\000t2SBCrs\000t2SBFX\000t2SDIV\000t2SEL\000t2SEV\000t2SHADD16\000t2S"
7077
"HADD8\000t2SHASX\000t2SHSAX\000t2SHSUB16\000t2SHSUB8\000t2SMC\000t2SMLA"
7078
"BB\000t2SMLABT\000t2SMLAD\000t2SMLADX\000t2SMLAL\000t2SMLALBB\000t2SMLA"
7079
"LBT\000t2SMLALD\000t2SMLALDX\000t2SMLALTB\000t2SMLALTT\000t2SMLATB\000t"
7080
"2SMLATT\000t2SMLAWB\000t2SMLAWT\000t2SMLSD\000t2SMLSDX\000t2SMLSLD\000t"
7081
"2SMLSLDX\000t2SMMLA\000t2SMMLAR\000t2SMMLS\000t2SMMLSR\000t2SMMUL\000t2"
7082
"SMMULR\000t2SMUAD\000t2SMUADX\000t2SMULBB\000t2SMULBT\000t2SMULL\000t2S"
7083
"MULTB\000t2SMULTT\000t2SMULWB\000t2SMULWT\000t2SMUSD\000t2SMUSDX\000t2S"
7084
"RSDB\000t2SRSDBW\000t2SRSIA\000t2SRSIAW\000t2SSAT16\000t2SSATasr\000t2S"
7085
"SATlsl\000t2SSAX\000t2SSUB16\000t2SSUB8\000t2STM\000t2STRBT\000t2STRB_P"
7086
"OST\000t2STRB_PRE\000t2STRBi12\000t2STRBi8\000t2STRBs\000t2STRDi8\000t2"
7087
"STREX\000t2STREXB\000t2STREXD\000t2STREXH\000t2STRHT\000t2STRH_POST\000"
7088
"t2STRH_PRE\000t2STRHi12\000t2STRHi8\000t2STRHs\000t2STRT\000t2STR_POST\000"
7089
"t2STR_PRE\000t2STRi12\000t2STRi8\000t2STRs\000t2SUBSri\000t2SUBSrr\000t"
7090
"2SUBSrs\000t2SUBrSPi\000t2SUBrSPi12\000t2SUBrSPi12_\000t2SUBrSPi_\000t2"
7091
"SUBrSPs\000t2SUBrSPs_\000t2SUBri\000t2SUBri12\000t2SUBrr\000t2SUBrs\000"
7092
"t2SXTAB16rr\000t2SXTAB16rr_rot\000t2SXTABrr\000t2SXTABrr_rot\000t2SXTAH"
7093
"rr\000t2SXTAHrr_rot\000t2SXTB16r\000t2SXTB16r_rot\000t2SXTBr\000t2SXTBr"
7094
"_rot\000t2SXTHr\000t2SXTHr_rot\000t2TBB\000t2TBBgen\000t2TBH\000t2TBHge"
7095
"n\000t2TEQri\000t2TEQrr\000t2TEQrs\000t2TPsoft\000t2TSTri\000t2TSTrr\000"
7096
"t2TSTrs\000t2UADD16\000t2UADD8\000t2UASX\000t2UBFX\000t2UDIV\000t2UHADD"
7097
"16\000t2UHADD8\000t2UHASX\000t2UHSAX\000t2UHSUB16\000t2UHSUB8\000t2UMAA"
7098
"L\000t2UMLAL\000t2UMULL\000t2UQADD16\000t2UQADD8\000t2UQASX\000t2UQSAX\000"
7099
"t2UQSUB16\000t2UQSUB8\000t2USAD8\000t2USADA8\000t2USAT16\000t2USATasr\000"
7100
"t2USATlsl\000t2USAX\000t2USUB16\000t2USUB8\000t2UXTAB16rr\000t2UXTAB16r"
7101
"r_rot\000t2UXTABrr\000t2UXTABrr_rot\000t2UXTAHrr\000t2UXTAHrr_rot\000t2"
7102
"UXTB16r\000t2UXTB16r_rot\000t2UXTBr\000t2UXTBr_rot\000t2UXTHr\000t2UXTH"
7103
"r_rot\000t2WFE\000t2WFI\000t2YIELD\000tADC\000tADDhirr\000tADDi3\000tAD"
7104
"Di8\000tADDrPCi\000tADDrSP\000tADDrSPi\000tADDrr\000tADDspi\000tADDspr\000"
7105
"tADDspr_\000tADJCALLSTACKDOWN\000tADJCALLSTACKUP\000tAND\000tANDsp\000t"
7106
"ASRri\000tASRrr\000tB\000tBIC\000tBKPT\000tBL\000tBLXi\000tBLXi_r9\000t"
7107
"BLXr\000tBLXr_r9\000tBLr9\000tBRIND\000tBR_JTr\000tBX\000tBX_RET\000tBX"
7108
"_RET_vararg\000tBXr9\000tBcc\000tBfar\000tCBNZ\000tCBZ\000tCMNz\000tCMP"
7109
"hir\000tCMPi8\000tCMPr\000tCMPzhir\000tCMPzi8\000tCMPzr\000tCPS\000tEOR"
7110
"\000tInt_eh_sjlj_setjmp\000tLDM\000tLDR\000tLDRB\000tLDRBi\000tLDRH\000"
7111
"tLDRHi\000tLDRSB\000tLDRSH\000tLDRcp\000tLDRi\000tLDRpci\000tLDRpci_pic"
7112
"\000tLDRspi\000tLEApcrel\000tLEApcrelJT\000tLSLri\000tLSLrr\000tLSRri\000"
7113
"tLSRrr\000tMOVCCi\000tMOVCCr\000tMOVCCr_pseudo\000tMOVSr\000tMOVgpr2gpr"
7114
"\000tMOVgpr2tgpr\000tMOVi8\000tMOVr\000tMOVtgpr2gpr\000tMUL\000tMVN\000"
7115
"tNOP\000tORR\000tPICADD\000tPOP\000tPOP_RET\000tPUSH\000tREV\000tREV16\000"
7116
"tREVSH\000tROR\000tRSB\000tRestore\000tSBC\000tSETENDBE\000tSETENDLE\000"
7117
"tSEV\000tSTM\000tSTR\000tSTRB\000tSTRBi\000tSTRH\000tSTRHi\000tSTRi\000"
7118
"tSTRspi\000tSUBi3\000tSUBi8\000tSUBrr\000tSUBspi\000tSUBspi_\000tSVC\000"
7119
"tSXTB\000tSXTH\000tSpill\000tTPsoft\000tTRAP\000tTST\000tUXTB\000tUXTH\000"
7120
"tWFE\000tWFI\000tYIELD\000";
7121
return Strs+InstAsmOffset[Opcode];