1
//===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3
// The LLVM Compiler Infrastructure
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
8
//===----------------------------------------------------------------------===//
10
// This file describes the Altivec extension to the PowerPC instruction set.
12
//===----------------------------------------------------------------------===//
14
//===----------------------------------------------------------------------===//
15
// Altivec transformation functions and pattern fragments.
19
def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
20
(vector_shuffle node:$lhs, node:$rhs), [{
21
return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
23
def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
24
(vector_shuffle node:$lhs, node:$rhs), [{
25
return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
27
def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
28
(vector_shuffle node:$lhs, node:$rhs), [{
29
return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
31
def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
32
(vector_shuffle node:$lhs, node:$rhs), [{
33
return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
37
def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
38
(vector_shuffle node:$lhs, node:$rhs), [{
39
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
41
def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
42
(vector_shuffle node:$lhs, node:$rhs), [{
43
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
45
def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
46
(vector_shuffle node:$lhs, node:$rhs), [{
47
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
49
def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
50
(vector_shuffle node:$lhs, node:$rhs), [{
51
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
53
def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
54
(vector_shuffle node:$lhs, node:$rhs), [{
55
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
57
def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
58
(vector_shuffle node:$lhs, node:$rhs), [{
59
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
63
def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
64
(vector_shuffle node:$lhs, node:$rhs), [{
65
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
67
def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
68
(vector_shuffle node:$lhs, node:$rhs), [{
69
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
71
def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
72
(vector_shuffle node:$lhs, node:$rhs), [{
73
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
75
def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
76
(vector_shuffle node:$lhs, node:$rhs), [{
77
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
79
def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
80
(vector_shuffle node:$lhs, node:$rhs), [{
81
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
83
def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
84
(vector_shuffle node:$lhs, node:$rhs), [{
85
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
89
def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
90
return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
92
def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
93
(vector_shuffle node:$lhs, node:$rhs), [{
94
return PPC::isVSLDOIShuffleMask(N, false) != -1;
98
/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
99
/// vector_shuffle(X,undef,mask) by the dag combiner.
100
def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
101
return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
103
def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
104
(vector_shuffle node:$lhs, node:$rhs), [{
105
return PPC::isVSLDOIShuffleMask(N, true) != -1;
106
}], VSLDOI_unary_get_imm>;
109
// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
110
def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
111
return getI32Imm(PPC::getVSPLTImmediate(N, 1));
113
def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
114
(vector_shuffle node:$lhs, node:$rhs), [{
115
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
117
def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
118
return getI32Imm(PPC::getVSPLTImmediate(N, 2));
120
def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
121
(vector_shuffle node:$lhs, node:$rhs), [{
122
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
124
def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
125
return getI32Imm(PPC::getVSPLTImmediate(N, 4));
127
def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
128
(vector_shuffle node:$lhs, node:$rhs), [{
129
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
133
// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
134
def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
135
return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
137
def vecspltisb : PatLeaf<(build_vector), [{
138
return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
139
}], VSPLTISB_get_imm>;
141
// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
142
def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
143
return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
145
def vecspltish : PatLeaf<(build_vector), [{
146
return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
147
}], VSPLTISH_get_imm>;
149
// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
150
def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
151
return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
153
def vecspltisw : PatLeaf<(build_vector), [{
154
return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
155
}], VSPLTISW_get_imm>;
157
def V_immneg0 : PatLeaf<(build_vector), [{
158
return PPC::isAllNegativeZeroVector(N);
161
//===----------------------------------------------------------------------===//
162
// Helpers for defining instructions that directly correspond to intrinsics.
164
// VA1a_Int - A VAForm_1a intrinsic definition.
165
class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
166
: VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC),
167
!strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
168
[(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
170
// VX1_Int - A VXForm_1 intrinsic definition.
171
class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
172
: VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
173
!strconcat(opc, " $vD, $vA, $vB"), VecFP,
174
[(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
176
// VX2_Int - A VXForm_2 intrinsic definition.
177
class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
178
: VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB),
179
!strconcat(opc, " $vD, $vB"), VecFP,
180
[(set VRRC:$vD, (IntID VRRC:$vB))]>;
182
//===----------------------------------------------------------------------===//
183
// Instruction Definitions.
185
def DSS : DSS_Form<822, (outs),
186
(ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
187
"dss $STRM", LdStGeneral /*FIXME*/, []>;
188
def DSSALL : DSS_Form<822, (outs),
189
(ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2),
190
"dssall", LdStGeneral /*FIXME*/, []>;
191
def DST : DSS_Form<342, (outs),
192
(ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
193
"dst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
194
def DSTT : DSS_Form<342, (outs),
195
(ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
196
"dstt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
197
def DSTST : DSS_Form<374, (outs),
198
(ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
199
"dstst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
200
def DSTSTT : DSS_Form<374, (outs),
201
(ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
202
"dststt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
204
def DST64 : DSS_Form<342, (outs),
205
(ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
206
"dst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
207
def DSTT64 : DSS_Form<342, (outs),
208
(ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
209
"dstt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
210
def DSTST64 : DSS_Form<374, (outs),
211
(ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
212
"dstst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
213
def DSTSTT64 : DSS_Form<374, (outs),
214
(ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
215
"dststt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>;
217
def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins),
218
"mfvscr $vD", LdStGeneral,
219
[(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>;
220
def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB),
221
"mtvscr $vB", LdStGeneral,
222
[(int_ppc_altivec_mtvscr VRRC:$vB)]>;
224
let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads.
225
def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src),
226
"lvebx $vD, $src", LdStGeneral,
227
[(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
228
def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src),
229
"lvehx $vD, $src", LdStGeneral,
230
[(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
231
def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src),
232
"lvewx $vD, $src", LdStGeneral,
233
[(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
234
def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src),
235
"lvx $vD, $src", LdStGeneral,
236
[(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
237
def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src),
238
"lvxl $vD, $src", LdStGeneral,
239
[(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
242
def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src),
243
"lvsl $vD, $src", LdStGeneral,
244
[(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
246
def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src),
247
"lvsr $vD, $src", LdStGeneral,
248
[(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
251
let PPC970_Unit = 2 in { // Stores.
252
def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst),
253
"stvebx $rS, $dst", LdStGeneral,
254
[(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
255
def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst),
256
"stvehx $rS, $dst", LdStGeneral,
257
[(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
258
def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst),
259
"stvewx $rS, $dst", LdStGeneral,
260
[(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
261
def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst),
262
"stvx $rS, $dst", LdStGeneral,
263
[(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
264
def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst),
265
"stvxl $rS, $dst", LdStGeneral,
266
[(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
269
let PPC970_Unit = 5 in { // VALU Operations.
270
// VA-Form instructions. 3-input AltiVec ops.
271
def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
272
"vmaddfp $vD, $vA, $vC, $vB", VecFP,
273
[(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
275
Requires<[FPContractions]>;
276
def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
277
"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
278
[(set VRRC:$vD, (fsub V_immneg0,
279
(fsub (fmul VRRC:$vA, VRRC:$vC),
281
Requires<[FPContractions]>;
283
def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
284
def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
285
def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>;
286
def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>;
287
def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
290
def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH),
291
"vsldoi $vD, $vA, $vB, $SH", VecFP,
293
(vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>;
295
// VX-Form instructions. AltiVec arithmetic ops.
296
def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
297
"vaddfp $vD, $vA, $vB", VecFP,
298
[(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
300
def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
301
"vaddubm $vD, $vA, $vB", VecGeneral,
302
[(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
303
def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
304
"vadduhm $vD, $vA, $vB", VecGeneral,
305
[(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
306
def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
307
"vadduwm $vD, $vA, $vB", VecGeneral,
308
[(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
310
def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
311
def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
312
def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
313
def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
314
def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
315
def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
316
def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
319
def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
320
"vand $vD, $vA, $vB", VecFP,
321
[(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
322
def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
323
"vandc $vD, $vA, $vB", VecFP,
324
[(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
326
def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
327
"vcfsx $vD, $vB, $UIMM", VecFP,
329
(int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
330
def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
331
"vcfux $vD, $vB, $UIMM", VecFP,
333
(int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
334
def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
335
"vctsxs $vD, $vB, $UIMM", VecFP,
337
(int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>;
338
def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
339
"vctuxs $vD, $vB, $UIMM", VecFP,
341
(int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>;
342
def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
343
def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>;
345
def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>;
346
def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>;
347
def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>;
348
def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>;
349
def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>;
350
def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>;
352
def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>;
353
def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>;
354
def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>;
355
def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>;
356
def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>;
357
def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>;
358
def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>;
359
def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>;
360
def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>;
361
def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>;
362
def VMINSW : VX1_Int< 898, "vminsw", int_ppc_altivec_vminsw>;
363
def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>;
364
def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>;
365
def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
367
def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
368
"vmrghb $vD, $vA, $vB", VecFP,
369
[(set VRRC:$vD, (vmrghb_shuffle VRRC:$vA, VRRC:$vB))]>;
370
def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
371
"vmrghh $vD, $vA, $vB", VecFP,
372
[(set VRRC:$vD, (vmrghh_shuffle VRRC:$vA, VRRC:$vB))]>;
373
def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
374
"vmrghw $vD, $vA, $vB", VecFP,
375
[(set VRRC:$vD, (vmrghw_shuffle VRRC:$vA, VRRC:$vB))]>;
376
def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
377
"vmrglb $vD, $vA, $vB", VecFP,
378
[(set VRRC:$vD, (vmrglb_shuffle VRRC:$vA, VRRC:$vB))]>;
379
def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
380
"vmrglh $vD, $vA, $vB", VecFP,
381
[(set VRRC:$vD, (vmrglh_shuffle VRRC:$vA, VRRC:$vB))]>;
382
def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
383
"vmrglw $vD, $vA, $vB", VecFP,
384
[(set VRRC:$vD, (vmrglw_shuffle VRRC:$vA, VRRC:$vB))]>;
386
def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
387
def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
388
def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
389
def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
390
def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
391
def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
393
def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
394
def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
395
def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
396
def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
397
def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
398
def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
399
def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>;
400
def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
402
def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>;
403
def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>;
404
def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>;
405
def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>;
406
def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>;
407
def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
409
def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
411
def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
412
"vsubfp $vD, $vA, $vB", VecGeneral,
413
[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
414
def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
415
"vsububm $vD, $vA, $vB", VecGeneral,
416
[(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
417
def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
418
"vsubuhm $vD, $vA, $vB", VecGeneral,
419
[(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
420
def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
421
"vsubuwm $vD, $vA, $vB", VecGeneral,
422
[(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
424
def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
425
def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
426
def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
427
def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
428
def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
429
def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
430
def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
431
def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
432
def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
433
def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
434
def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
436
def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
437
"vnor $vD, $vA, $vB", VecFP,
438
[(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
439
def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
440
"vor $vD, $vA, $vB", VecFP,
441
[(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
442
def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
443
"vxor $vD, $vA, $vB", VecFP,
444
[(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
446
def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>;
447
def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
448
def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
450
def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >;
451
def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
452
def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
453
def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
454
def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
456
def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
457
"vspltb $vD, $vB, $UIMM", VecPerm,
459
(vspltb_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
460
def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
461
"vsplth $vD, $vB, $UIMM", VecPerm,
463
(vsplth_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
464
def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
465
"vspltw $vD, $vB, $UIMM", VecPerm,
467
(vspltw_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
469
def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
470
def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
471
def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
472
def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
473
def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
474
def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
475
def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
476
def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
479
def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM),
480
"vspltisb $vD, $SIMM", VecPerm,
481
[(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>;
482
def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM),
483
"vspltish $vD, $SIMM", VecPerm,
484
[(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>;
485
def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM),
486
"vspltisw $vD, $SIMM", VecPerm,
487
[(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>;
490
def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
491
def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
492
def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
493
def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
494
def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
495
def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
496
"vpkuhum $vD, $vA, $vB", VecFP,
498
(vpkuhum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>;
499
def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
500
def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
501
"vpkuwum $vD, $vA, $vB", VecFP,
503
(vpkuwum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>;
504
def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
507
def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
508
def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
509
def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
510
def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
511
def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
512
def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
515
// Altivec Comparisons.
517
class VCMP<bits<10> xo, string asmstr, ValueType Ty>
518
: VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare,
519
[(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
520
class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
521
: VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare,
522
[(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> {
527
// f32 element comparisons.0
528
def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
529
def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
530
def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
531
def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
532
def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
533
def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
534
def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
535
def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
537
// i8 element comparisons.
538
def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
539
def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
540
def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
541
def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
542
def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
543
def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
545
// i16 element comparisons.
546
def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
547
def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
548
def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
549
def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
550
def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
551
def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
553
// i32 element comparisons.
554
def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
555
def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
556
def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
557
def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
558
def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
559
def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
561
def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins),
562
"vxor $vD, $vD, $vD", VecFP,
563
[(set VRRC:$vD, (v4i32 immAllZerosV))]>;
566
//===----------------------------------------------------------------------===//
567
// Additional Altivec Patterns
571
def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>;
572
def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
575
def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
576
(DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
577
def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
578
(DSTT 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
579
def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
580
(DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
581
def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
582
(DSTSTT 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
585
def : Pat<(int_ppc_altivec_dst G8RC:$rA, GPRC:$rB, imm:$STRM),
586
(DST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
587
def : Pat<(int_ppc_altivec_dstt G8RC:$rA, GPRC:$rB, imm:$STRM),
588
(DSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
589
def : Pat<(int_ppc_altivec_dstst G8RC:$rA, GPRC:$rB, imm:$STRM),
590
(DSTST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
591
def : Pat<(int_ppc_altivec_dststt G8RC:$rA, GPRC:$rB, imm:$STRM),
592
(DSTSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
595
def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
598
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
599
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
602
def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
603
def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
604
def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
606
def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
607
def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
608
def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
610
def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
611
def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
612
def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
614
def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
615
def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
616
def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
620
// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
621
def:Pat<(vsldoi_unary_shuffle:$in (v16i8 VRRC:$vA), undef),
622
(VSLDOI VRRC:$vA, VRRC:$vA, (VSLDOI_unary_get_imm VRRC:$in))>;
623
def:Pat<(vpkuwum_unary_shuffle (v16i8 VRRC:$vA), undef),
624
(VPKUWUM VRRC:$vA, VRRC:$vA)>;
625
def:Pat<(vpkuhum_unary_shuffle (v16i8 VRRC:$vA), undef),
626
(VPKUHUM VRRC:$vA, VRRC:$vA)>;
629
def:Pat<(vmrglb_unary_shuffle (v16i8 VRRC:$vA), undef),
630
(VMRGLB VRRC:$vA, VRRC:$vA)>;
631
def:Pat<(vmrglh_unary_shuffle (v16i8 VRRC:$vA), undef),
632
(VMRGLH VRRC:$vA, VRRC:$vA)>;
633
def:Pat<(vmrglw_unary_shuffle (v16i8 VRRC:$vA), undef),
634
(VMRGLW VRRC:$vA, VRRC:$vA)>;
635
def:Pat<(vmrghb_unary_shuffle (v16i8 VRRC:$vA), undef),
636
(VMRGHB VRRC:$vA, VRRC:$vA)>;
637
def:Pat<(vmrghh_unary_shuffle (v16i8 VRRC:$vA), undef),
638
(VMRGHH VRRC:$vA, VRRC:$vA)>;
639
def:Pat<(vmrghw_unary_shuffle (v16i8 VRRC:$vA), undef),
640
(VMRGHW VRRC:$vA, VRRC:$vA)>;
642
// Logical Operations
643
def : Pat<(v4i32 (vnot VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>;
644
def : Pat<(v4i32 (vnot_conv VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>;
646
def : Pat<(v4i32 (vnot_conv (or VRRC:$A, VRRC:$B))),
647
(VNOR VRRC:$A, VRRC:$B)>;
648
def : Pat<(v4i32 (and VRRC:$A, (vnot_conv VRRC:$B))),
649
(VANDC VRRC:$A, VRRC:$B)>;
651
def : Pat<(fmul VRRC:$vA, VRRC:$vB),
652
(VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>;
654
// Fused multiply add and multiply sub for packed float. These are represented
655
// separately from the real instructions above, for operations that must have
656
// the additional precision, such as Newton-Rhapson (used by divide, sqrt)
657
def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
658
(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
659
def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
660
(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
662
def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
663
(VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
664
def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
665
(VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
667
def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
668
(VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>;
671
def : Pat<(v16i8 (shl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))),
672
(v16i8 (VSLB VRRC:$vA, VRRC:$vB))>;
673
def : Pat<(v8i16 (shl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))),
674
(v8i16 (VSLH VRRC:$vA, VRRC:$vB))>;
675
def : Pat<(v4i32 (shl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))),
676
(v4i32 (VSLW VRRC:$vA, VRRC:$vB))>;
678
def : Pat<(v16i8 (srl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))),
679
(v16i8 (VSRB VRRC:$vA, VRRC:$vB))>;
680
def : Pat<(v8i16 (srl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))),
681
(v8i16 (VSRH VRRC:$vA, VRRC:$vB))>;
682
def : Pat<(v4i32 (srl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))),
683
(v4i32 (VSRW VRRC:$vA, VRRC:$vB))>;
685
def : Pat<(v16i8 (sra (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))),
686
(v16i8 (VSRAB VRRC:$vA, VRRC:$vB))>;
687
def : Pat<(v8i16 (sra (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))),
688
(v8i16 (VSRAH VRRC:$vA, VRRC:$vB))>;
689
def : Pat<(v4i32 (sra (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))),
690
(v4i32 (VSRAW VRRC:$vA, VRRC:$vB))>;
added
removed
libclamav/c++/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
