~louis/ubuntu/trusty/clamav/lp799623_fix

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//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//

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//

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// The LLVM Compiler Infrastructure

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//

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// This file is distributed under the University of Illinois Open Source

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// License. See LICENSE.TXT for details.

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//

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//===----------------------------------------------------------------------===//

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//

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// Pass to verify generated machine code. The following is checked:

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//

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// Operand counts: All explicit operands must be present.

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//

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// Register classes: All physical and virtual register operands must be

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// compatible with the register class required by the instruction descriptor.

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//

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// Register live intervals: Registers must be defined only once, and must be

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// defined before use.

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//

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// The machine code verifier is enabled from LLVMTargetMachine.cpp with the

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// command-line option -verify-machineinstrs, or by defining the environment

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// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive

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// the verifier errors.

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//===----------------------------------------------------------------------===//

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#include "llvm/Function.h"

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#include "llvm/CodeGen/LiveVariables.h"

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#include "llvm/CodeGen/MachineFunctionPass.h"

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#include "llvm/CodeGen/MachineFrameInfo.h"

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#include "llvm/CodeGen/MachineMemOperand.h"

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#include "llvm/CodeGen/MachineRegisterInfo.h"

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#include "llvm/CodeGen/Passes.h"

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#include "llvm/Target/TargetMachine.h"

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#include "llvm/Target/TargetRegisterInfo.h"

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#include "llvm/Target/TargetInstrInfo.h"

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#include "llvm/ADT/DenseSet.h"

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#include "llvm/ADT/SetOperations.h"

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#include "llvm/ADT/SmallVector.h"

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#include "llvm/Support/Debug.h"

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#include "llvm/Support/ErrorHandling.h"

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#include "llvm/Support/raw_ostream.h"

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using namespace llvm;

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namespace {

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struct MachineVerifier {

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MachineVerifier(Pass *pass, bool allowDoubleDefs) :

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PASS(pass),

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allowVirtDoubleDefs(allowDoubleDefs),

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allowPhysDoubleDefs(allowDoubleDefs),

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OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))

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{}

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bool runOnMachineFunction(MachineFunction &MF);

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Pass *const PASS;

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const bool allowVirtDoubleDefs;

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const bool allowPhysDoubleDefs;

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const char *const OutFileName;

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raw_ostream *OS;

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const MachineFunction *MF;

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const TargetMachine *TM;

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const TargetRegisterInfo *TRI;

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const MachineRegisterInfo *MRI;

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unsigned foundErrors;

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typedef SmallVector<unsigned, 16> RegVector;

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typedef DenseSet<unsigned> RegSet;

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typedef DenseMap<unsigned, const MachineInstr*> RegMap;

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BitVector regsReserved;

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RegSet regsLive;

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RegVector regsDefined, regsDead, regsKilled;

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RegSet regsLiveInButUnused;

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// Add Reg and any sub-registers to RV

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void addRegWithSubRegs(RegVector &RV, unsigned Reg) {

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RV.push_back(Reg);

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if (TargetRegisterInfo::isPhysicalRegister(Reg))

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for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)

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RV.push_back(*R);

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}

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struct BBInfo {

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// Is this MBB reachable from the MF entry point?

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bool reachable;

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// Vregs that must be live in because they are used without being

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// defined. Map value is the user.

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RegMap vregsLiveIn;

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// Vregs that must be dead in because they are defined without being

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// killed first. Map value is the defining instruction.

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RegMap vregsDeadIn;

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// Regs killed in MBB. They may be defined again, and will then be in both

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// regsKilled and regsLiveOut.

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RegSet regsKilled;

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// Regs defined in MBB and live out. Note that vregs passing through may

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// be live out without being mentioned here.

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RegSet regsLiveOut;

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// Vregs that pass through MBB untouched. This set is disjoint from

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// regsKilled and regsLiveOut.

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RegSet vregsPassed;

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// Vregs that must pass through MBB because they are needed by a successor

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// block. This set is disjoint from regsLiveOut.

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RegSet vregsRequired;

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BBInfo() : reachable(false) {}

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// Add register to vregsPassed if it belongs there. Return true if

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// anything changed.

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bool addPassed(unsigned Reg) {

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if (!TargetRegisterInfo::isVirtualRegister(Reg))

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return false;

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if (regsKilled.count(Reg) || regsLiveOut.count(Reg))

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return false;

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return vregsPassed.insert(Reg).second;

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}

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// Same for a full set.

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bool addPassed(const RegSet &RS) {

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bool changed = false;

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for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)

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if (addPassed(*I))

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changed = true;

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return changed;

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}

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// Add register to vregsRequired if it belongs there. Return true if

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// anything changed.

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bool addRequired(unsigned Reg) {

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if (!TargetRegisterInfo::isVirtualRegister(Reg))

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return false;

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if (regsLiveOut.count(Reg))

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return false;

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return vregsRequired.insert(Reg).second;

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}

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// Same for a full set.

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bool addRequired(const RegSet &RS) {

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bool changed = false;

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for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)

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if (addRequired(*I))

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changed = true;

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return changed;

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}

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// Same for a full map.

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bool addRequired(const RegMap &RM) {

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bool changed = false;

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for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)

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if (addRequired(I->first))

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changed = true;

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return changed;

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}

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// Live-out registers are either in regsLiveOut or vregsPassed.

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bool isLiveOut(unsigned Reg) const {

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return regsLiveOut.count(Reg) || vregsPassed.count(Reg);

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}

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};

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// Extra register info per MBB.

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DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;

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bool isReserved(unsigned Reg) {

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return Reg < regsReserved.size() && regsReserved.test(Reg);

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}

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// Analysis information if available

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LiveVariables *LiveVars;

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void visitMachineFunctionBefore();

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void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);

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void visitMachineInstrBefore(const MachineInstr *MI);

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void visitMachineOperand(const MachineOperand *MO, unsigned MONum);

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void visitMachineInstrAfter(const MachineInstr *MI);

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void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);

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void visitMachineFunctionAfter();

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void report(const char *msg, const MachineFunction *MF);

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void report(const char *msg, const MachineBasicBlock *MBB);

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void report(const char *msg, const MachineInstr *MI);

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void report(const char *msg, const MachineOperand *MO, unsigned MONum);

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void markReachable(const MachineBasicBlock *MBB);

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void calcRegsPassed();

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void checkPHIOps(const MachineBasicBlock *MBB);

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void calcRegsRequired();

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void verifyLiveVariables();

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};

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struct MachineVerifierPass : public MachineFunctionPass {

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static char ID; // Pass ID, replacement for typeid

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bool AllowDoubleDefs;

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explicit MachineVerifierPass(bool allowDoubleDefs = false)

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: MachineFunctionPass(&ID),

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AllowDoubleDefs(allowDoubleDefs) {}

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void getAnalysisUsage(AnalysisUsage &AU) const {

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AU.setPreservesAll();

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MachineFunctionPass::getAnalysisUsage(AU);

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}

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bool runOnMachineFunction(MachineFunction &MF) {

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MF.verify(this, AllowDoubleDefs);

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return false;

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}

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};

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}

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char MachineVerifierPass::ID = 0;

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static RegisterPass<MachineVerifierPass>

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MachineVer("machineverifier", "Verify generated machine code");

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static const PassInfo *const MachineVerifyID = &MachineVer;

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FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {

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return new MachineVerifierPass(allowPhysDoubleDefs);

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}

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void MachineFunction::verify(Pass *p, bool allowDoubleDefs) const {

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MachineVerifier(p, allowDoubleDefs)

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.runOnMachineFunction(const_cast<MachineFunction&>(*this));

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}

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bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {

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raw_ostream *OutFile = 0;

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if (OutFileName) {

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std::string ErrorInfo;

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OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,

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raw_fd_ostream::F_Append);

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if (!ErrorInfo.empty()) {

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errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';

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exit(1);

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}

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OS = OutFile;

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} else {

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OS = &errs();

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}

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foundErrors = 0;

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this->MF = &MF;

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TM = &MF.getTarget();

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TRI = TM->getRegisterInfo();

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MRI = &MF.getRegInfo();

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if (PASS) {

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LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();

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} else {

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LiveVars = NULL;

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}

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visitMachineFunctionBefore();

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for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();

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MFI!=MFE; ++MFI) {

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visitMachineBasicBlockBefore(MFI);

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for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),

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MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {

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visitMachineInstrBefore(MBBI);

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for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)

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visitMachineOperand(&MBBI->getOperand(I), I);

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visitMachineInstrAfter(MBBI);

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}

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visitMachineBasicBlockAfter(MFI);

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}

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visitMachineFunctionAfter();

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if (OutFile)

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delete OutFile;

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else if (foundErrors)

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llvm_report_error("Found "+Twine(foundErrors)+" machine code errors.");

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// Clean up.

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regsLive.clear();

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regsDefined.clear();

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regsDead.clear();

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regsKilled.clear();

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regsLiveInButUnused.clear();

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MBBInfoMap.clear();

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return false; // no changes

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}

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void MachineVerifier::report(const char *msg, const MachineFunction *MF) {

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assert(MF);

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*OS << '\n';

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if (!foundErrors++)

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MF->print(*OS);

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*OS << "*** Bad machine code: " << msg << " ***\n"

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<< "- function: " << MF->getFunction()->getNameStr() << "\n";

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}

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void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {

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assert(MBB);

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report(msg, MBB->getParent());

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*OS << "- basic block: " << MBB->getName()

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<< " " << (void*)MBB

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<< " (BB#" << MBB->getNumber() << ")\n";

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}

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void MachineVerifier::report(const char *msg, const MachineInstr *MI) {

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assert(MI);

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report(msg, MI->getParent());

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*OS << "- instruction: ";

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MI->print(*OS, TM);

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}

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void MachineVerifier::report(const char *msg,

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const MachineOperand *MO, unsigned MONum) {

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assert(MO);

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report(msg, MO->getParent());

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*OS << "- operand " << MONum << ": ";

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MO->print(*OS, TM);

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*OS << "\n";

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}

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void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {

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BBInfo &MInfo = MBBInfoMap[MBB];

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if (!MInfo.reachable) {

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MInfo.reachable = true;

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for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),

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SuE = MBB->succ_end(); SuI != SuE; ++SuI)

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markReachable(*SuI);

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}

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}

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void MachineVerifier::visitMachineFunctionBefore() {

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regsReserved = TRI->getReservedRegs(*MF);

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// A sub-register of a reserved register is also reserved

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for (int Reg = regsReserved.find_first(); Reg>=0;

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Reg = regsReserved.find_next(Reg)) {

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for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {

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// FIXME: This should probably be:

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// assert(regsReserved.test(*Sub) && "Non-reserved sub-register");

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regsReserved.set(*Sub);

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}

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}

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markReachable(&MF->front());

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}

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// Does iterator point to a and b as the first two elements?

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bool matchPair(MachineBasicBlock::const_succ_iterator i,

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const MachineBasicBlock *a, const MachineBasicBlock *b) {

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if (*i == a)

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return *++i == b;

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if (*i == b)

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return *++i == a;

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return false;

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}

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void

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MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {

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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();

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// Call AnalyzeBranch. If it succeeds, there several more conditions to check.

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MachineBasicBlock *TBB = 0, *FBB = 0;

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SmallVector<MachineOperand, 4> Cond;

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if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),

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TBB, FBB, Cond)) {

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// Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's

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// check whether its answers match up with reality.

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if (!TBB && !FBB) {

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// Block falls through to its successor.

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MachineFunction::const_iterator MBBI = MBB;

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++MBBI;

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if (MBBI == MF->end()) {

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// It's possible that the block legitimately ends with a noreturn

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// call or an unreachable, in which case it won't actually fall

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// out the bottom of the function.

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} else if (MBB->succ_empty()) {

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// It's possible that the block legitimately ends with a noreturn

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// call or an unreachable, in which case it won't actuall fall

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// out of the block.

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} else if (MBB->succ_size() != 1) {

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report("MBB exits via unconditional fall-through but doesn't have "

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"exactly one CFG successor!", MBB);

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} else if (MBB->succ_begin()[0] != MBBI) {

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report("MBB exits via unconditional fall-through but its successor "

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"differs from its CFG successor!", MBB);

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}

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if (!MBB->empty() && MBB->back().getDesc().isBarrier()) {

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report("MBB exits via unconditional fall-through but ends with a "

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"barrier instruction!", MBB);

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}

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if (!Cond.empty()) {

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report("MBB exits via unconditional fall-through but has a condition!",

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MBB);

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}

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} else if (TBB && !FBB && Cond.empty()) {

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// Block unconditionally branches somewhere.

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if (MBB->succ_size() != 1) {

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report("MBB exits via unconditional branch but doesn't have "

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"exactly one CFG successor!", MBB);

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} else if (MBB->succ_begin()[0] != TBB) {

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report("MBB exits via unconditional branch but the CFG "

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"successor doesn't match the actual successor!", MBB);

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}

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if (MBB->empty()) {

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report("MBB exits via unconditional branch but doesn't contain "

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"any instructions!", MBB);

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} else if (!MBB->back().getDesc().isBarrier()) {

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report("MBB exits via unconditional branch but doesn't end with a "

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"barrier instruction!", MBB);

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} else if (!MBB->back().getDesc().isTerminator()) {

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report("MBB exits via unconditional branch but the branch isn't a "

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"terminator instruction!", MBB);

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}

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} else if (TBB && !FBB && !Cond.empty()) {

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// Block conditionally branches somewhere, otherwise falls through.

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MachineFunction::const_iterator MBBI = MBB;

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++MBBI;

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if (MBBI == MF->end()) {

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report("MBB conditionally falls through out of function!", MBB);

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} if (MBB->succ_size() != 2) {

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report("MBB exits via conditional branch/fall-through but doesn't have "

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"exactly two CFG successors!", MBB);

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} else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {

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report("MBB exits via conditional branch/fall-through but the CFG "

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"successors don't match the actual successors!", MBB);

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}

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if (MBB->empty()) {

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report("MBB exits via conditional branch/fall-through but doesn't "

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"contain any instructions!", MBB);

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} else if (MBB->back().getDesc().isBarrier()) {

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report("MBB exits via conditional branch/fall-through but ends with a "

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"barrier instruction!", MBB);

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} else if (!MBB->back().getDesc().isTerminator()) {

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report("MBB exits via conditional branch/fall-through but the branch "

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"isn't a terminator instruction!", MBB);

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}

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} else if (TBB && FBB) {

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// Block conditionally branches somewhere, otherwise branches

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// somewhere else.

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if (MBB->succ_size() != 2) {

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report("MBB exits via conditional branch/branch but doesn't have "

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"exactly two CFG successors!", MBB);

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} else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {

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report("MBB exits via conditional branch/branch but the CFG "

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"successors don't match the actual successors!", MBB);

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}

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if (MBB->empty()) {

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report("MBB exits via conditional branch/branch but doesn't "

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"contain any instructions!", MBB);

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} else if (!MBB->back().getDesc().isBarrier()) {

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report("MBB exits via conditional branch/branch but doesn't end with a "

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"barrier instruction!", MBB);

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} else if (!MBB->back().getDesc().isTerminator()) {

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report("MBB exits via conditional branch/branch but the branch "

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"isn't a terminator instruction!", MBB);

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}

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if (Cond.empty()) {

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report("MBB exits via conditinal branch/branch but there's no "

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"condition!", MBB);

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}

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} else {

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report("AnalyzeBranch returned invalid data!", MBB);

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}

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}

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regsLive.clear();

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for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),

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E = MBB->livein_end(); I != E; ++I) {

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if (!TargetRegisterInfo::isPhysicalRegister(*I)) {

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report("MBB live-in list contains non-physical register", MBB);

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continue;

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}

479

regsLive.insert(*I);

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for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)

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regsLive.insert(*R);

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}

483

regsLiveInButUnused = regsLive;

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const MachineFrameInfo *MFI = MF->getFrameInfo();

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assert(MFI && "Function has no frame info");

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BitVector PR = MFI->getPristineRegs(MBB);

488

for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {

489

regsLive.insert(I);

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for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)

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regsLive.insert(*R);

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}

493

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regsKilled.clear();

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regsDefined.clear();

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}

497

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void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {

499

const TargetInstrDesc &TI = MI->getDesc();

500

if (MI->getNumOperands() < TI.getNumOperands()) {

501

report("Too few operands", MI);

502

*OS << TI.getNumOperands() << " operands expected, but "

503

<< MI->getNumExplicitOperands() << " given.\n";

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}

505

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// Check the MachineMemOperands for basic consistency.

507

for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),

508

E = MI->memoperands_end(); I != E; ++I) {

509

if ((*I)->isLoad() && !TI.mayLoad())

510

report("Missing mayLoad flag", MI);

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if ((*I)->isStore() && !TI.mayStore())

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report("Missing mayStore flag", MI);

513

}

514

}

515

516

void

517

MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {

518

const MachineInstr *MI = MO->getParent();

519

const TargetInstrDesc &TI = MI->getDesc();

520

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// The first TI.NumDefs operands must be explicit register defines

522

if (MONum < TI.getNumDefs()) {

523

if (!MO->isReg())

524

report("Explicit definition must be a register", MO, MONum);

525

else if (!MO->isDef())

526

report("Explicit definition marked as use", MO, MONum);

527

else if (MO->isImplicit())

528

report("Explicit definition marked as implicit", MO, MONum);

529

} else if (MONum < TI.getNumOperands()) {

530

if (MO->isReg()) {

531

if (MO->isDef())

532

report("Explicit operand marked as def", MO, MONum);

533

if (MO->isImplicit())

534

report("Explicit operand marked as implicit", MO, MONum);

535

}

536

} else {

537

// ARM adds %reg0 operands to indicate predicates. We'll allow that.

538

if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())

539

report("Extra explicit operand on non-variadic instruction", MO, MONum);

540

}

541

542

switch (MO->getType()) {

543

case MachineOperand::MO_Register: {

544

const unsigned Reg = MO->getReg();

545

if (!Reg)

546

return;

547

548

// Check Live Variables.

549

if (MO->isUndef()) {

550

// An <undef> doesn't refer to any register, so just skip it.

551

} else if (MO->isUse()) {

552

regsLiveInButUnused.erase(Reg);

553

554

bool isKill = false;

555

if (MO->isKill()) {

556

isKill = true;

557

// Tied operands on two-address instuctions MUST NOT have a <kill> flag.

558

if (MI->isRegTiedToDefOperand(MONum))

559

report("Illegal kill flag on two-address instruction operand",

560

MO, MONum);

561

} else {

562

// TwoAddress instr modifying a reg is treated as kill+def.

563

unsigned defIdx;

564

if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&

565

MI->getOperand(defIdx).getReg() == Reg)

566

isKill = true;

567

}

568

if (isKill) {

569

addRegWithSubRegs(regsKilled, Reg);

570

571

// Check that LiveVars knows this kill

572

if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) {

573

LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);

574

if (std::find(VI.Kills.begin(),

575

VI.Kills.end(), MI) == VI.Kills.end())

576

report("Kill missing from LiveVariables", MO, MONum);

577

}

578

}

579

580

// Use of a dead register.

581

if (!regsLive.count(Reg)) {

582

if (TargetRegisterInfo::isPhysicalRegister(Reg)) {

583

// Reserved registers may be used even when 'dead'.

584

if (!isReserved(Reg))

585

report("Using an undefined physical register", MO, MONum);

586

} else {

587

BBInfo &MInfo = MBBInfoMap[MI->getParent()];

588

// We don't know which virtual registers are live in, so only complain

589

// if vreg was killed in this MBB. Otherwise keep track of vregs that

590

// must be live in. PHI instructions are handled separately.

591

if (MInfo.regsKilled.count(Reg))

592

report("Using a killed virtual register", MO, MONum);

593

else if (!MI->isPHI())

594

MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));

595

}

596

}

597

} else {

598

assert(MO->isDef());

599

// Register defined.

600

// TODO: verify that earlyclobber ops are not used.

601

if (MO->isDead())

602

addRegWithSubRegs(regsDead, Reg);

603

else

604

addRegWithSubRegs(regsDefined, Reg);

605

}

606

607

// Check register classes.

608

if (MONum < TI.getNumOperands() && !MO->isImplicit()) {

609

const TargetOperandInfo &TOI = TI.OpInfo[MONum];

610

unsigned SubIdx = MO->getSubReg();

611

612

if (TargetRegisterInfo::isPhysicalRegister(Reg)) {

613

unsigned sr = Reg;

614

if (SubIdx) {

615

unsigned s = TRI->getSubReg(Reg, SubIdx);

616

if (!s) {

617

report("Invalid subregister index for physical register",

618

MO, MONum);

619

return;

620

}

621

sr = s;

622

}

623

if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {

624

if (!DRC->contains(sr)) {

625

report("Illegal physical register for instruction", MO, MONum);

626

*OS << TRI->getName(sr) << " is not a "

627

<< DRC->getName() << " register.\n";

628

}

629

}

630

} else {

631

// Virtual register.

632

const TargetRegisterClass *RC = MRI->getRegClass(Reg);

633

if (SubIdx) {

634

if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {

635

report("Invalid subregister index for virtual register", MO, MONum);

636

return;

637

}

638

RC = *(RC->subregclasses_begin()+SubIdx);

639

}

640

if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {

641

if (RC != DRC && !RC->hasSuperClass(DRC)) {

642

report("Illegal virtual register for instruction", MO, MONum);

643

*OS << "Expected a " << DRC->getName() << " register, but got a "

644

<< RC->getName() << " register\n";

645

}

646

}

647

}

648

}

649

break;

650

}

651

652

case MachineOperand::MO_MachineBasicBlock:

653

if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))

654

report("PHI operand is not in the CFG", MO, MONum);

655

break;

656

657

default:

658

break;

659

}

660

}

661

662

void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {

663

BBInfo &MInfo = MBBInfoMap[MI->getParent()];

664

set_union(MInfo.regsKilled, regsKilled);

665

set_subtract(regsLive, regsKilled);

666

regsKilled.clear();

667

668

// Verify that both <def> and <def,dead> operands refer to dead registers.

669

RegVector defs(regsDefined);

670

defs.append(regsDead.begin(), regsDead.end());

671

672

for (RegVector::const_iterator I = defs.begin(), E = defs.end();

673

I != E; ++I) {

674

if (regsLive.count(*I)) {

675

if (TargetRegisterInfo::isPhysicalRegister(*I)) {

676

if (!allowPhysDoubleDefs && !isReserved(*I) &&

677

!regsLiveInButUnused.count(*I)) {

678

report("Redefining a live physical register", MI);

679

*OS << "Register " << TRI->getName(*I)

680

<< " was defined but already live.\n";

681

}

682

} else {

683

if (!allowVirtDoubleDefs) {

684

report("Redefining a live virtual register", MI);

685

*OS << "Virtual register %reg" << *I

686

<< " was defined but already live.\n";

687

}

688

}

689

} else if (TargetRegisterInfo::isVirtualRegister(*I) &&

690

!MInfo.regsKilled.count(*I)) {

691

// Virtual register defined without being killed first must be dead on

692

// entry.

693

MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));

694

}

695

}

696

697

set_subtract(regsLive, regsDead); regsDead.clear();

698

set_union(regsLive, regsDefined); regsDefined.clear();

699

}

700

701

void

702

MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {

703

MBBInfoMap[MBB].regsLiveOut = regsLive;

704

regsLive.clear();

705

}

706

707

// Calculate the largest possible vregsPassed sets. These are the registers that

708

// can pass through an MBB live, but may not be live every time. It is assumed

709

// that all vregsPassed sets are empty before the call.

710

void MachineVerifier::calcRegsPassed() {

711

// First push live-out regs to successors' vregsPassed. Remember the MBBs that

712

// have any vregsPassed.

713

DenseSet<const MachineBasicBlock*> todo;

714

for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();

715

MFI != MFE; ++MFI) {

716

const MachineBasicBlock &MBB(*MFI);

717

BBInfo &MInfo = MBBInfoMap[&MBB];

718

if (!MInfo.reachable)

719

continue;

720

for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),

721

SuE = MBB.succ_end(); SuI != SuE; ++SuI) {

722

BBInfo &SInfo = MBBInfoMap[*SuI];

723

if (SInfo.addPassed(MInfo.regsLiveOut))

724

todo.insert(*SuI);

725

}

726

}

727

728

// Iteratively push vregsPassed to successors. This will converge to the same

729

// final state regardless of DenseSet iteration order.

730

while (!todo.empty()) {

731

const MachineBasicBlock *MBB = *todo.begin();

732

todo.erase(MBB);

733

BBInfo &MInfo = MBBInfoMap[MBB];

734

for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),

735

SuE = MBB->succ_end(); SuI != SuE; ++SuI) {

736

if (*SuI == MBB)

737

continue;

738

BBInfo &SInfo = MBBInfoMap[*SuI];

739

if (SInfo.addPassed(MInfo.vregsPassed))

740

todo.insert(*SuI);

741

}

742

}

743

}

744

745

// Calculate the set of virtual registers that must be passed through each basic

746

// block in order to satisfy the requirements of successor blocks. This is very

747

// similar to calcRegsPassed, only backwards.

748

void MachineVerifier::calcRegsRequired() {

749

// First push live-in regs to predecessors' vregsRequired.

750

DenseSet<const MachineBasicBlock*> todo;

751

for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();

752

MFI != MFE; ++MFI) {

753

const MachineBasicBlock &MBB(*MFI);

754

BBInfo &MInfo = MBBInfoMap[&MBB];

755

for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),

756

PrE = MBB.pred_end(); PrI != PrE; ++PrI) {

757

BBInfo &PInfo = MBBInfoMap[*PrI];

758

if (PInfo.addRequired(MInfo.vregsLiveIn))

759

todo.insert(*PrI);

760

}

761

}

762

763

// Iteratively push vregsRequired to predecessors. This will converge to the

764

// same final state regardless of DenseSet iteration order.

765

while (!todo.empty()) {

766

const MachineBasicBlock *MBB = *todo.begin();

767

todo.erase(MBB);

768

BBInfo &MInfo = MBBInfoMap[MBB];

769

for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),

770

PrE = MBB->pred_end(); PrI != PrE; ++PrI) {

771

if (*PrI == MBB)

772

continue;

773

BBInfo &SInfo = MBBInfoMap[*PrI];

774

if (SInfo.addRequired(MInfo.vregsRequired))

775

todo.insert(*PrI);

776

}

777

}

778

}

779

780

// Check PHI instructions at the beginning of MBB. It is assumed that

781

// calcRegsPassed has been run so BBInfo::isLiveOut is valid.

782

void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {

783

for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();

784

BBI != BBE && BBI->isPHI(); ++BBI) {

785

DenseSet<const MachineBasicBlock*> seen;

786

787

for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {

788

unsigned Reg = BBI->getOperand(i).getReg();

789

const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();

790

if (!Pre->isSuccessor(MBB))

791

continue;

792

seen.insert(Pre);

793

BBInfo &PrInfo = MBBInfoMap[Pre];

794

if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))

795

report("PHI operand is not live-out from predecessor",

796

&BBI->getOperand(i), i);

797

}

798

799

// Did we see all predecessors?

800

for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),

801

PrE = MBB->pred_end(); PrI != PrE; ++PrI) {

802

if (!seen.count(*PrI)) {

803

report("Missing PHI operand", BBI);

804

*OS << "BB#" << (*PrI)->getNumber()

805

<< " is a predecessor according to the CFG.\n";

806

}

807

}

808

}

809

}

810

811

void MachineVerifier::visitMachineFunctionAfter() {

812

calcRegsPassed();

813

814

for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();

815

MFI != MFE; ++MFI) {

816

BBInfo &MInfo = MBBInfoMap[MFI];

817

818

// Skip unreachable MBBs.

819

if (!MInfo.reachable)

820

continue;

821

822

checkPHIOps(MFI);

823

824

// Verify dead-in virtual registers.

825

if (!allowVirtDoubleDefs) {

826

for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),

827

PrE = MFI->pred_end(); PrI != PrE; ++PrI) {

828

BBInfo &PrInfo = MBBInfoMap[*PrI];

829

if (!PrInfo.reachable)

830

continue;

831

832

for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),

833

E = MInfo.vregsDeadIn.end(); I != E; ++I) {

834

// DeadIn register must be in neither regsLiveOut or vregsPassed of

835

// any predecessor.

836

if (PrInfo.isLiveOut(I->first)) {

837

report("Live-in virtual register redefined", I->second);

838

*OS << "Register %reg" << I->first

839

<< " was live-out from predecessor MBB #"

840

<< (*PrI)->getNumber() << ".\n";

841

}

842

}

843

}

844

}

845

}

846

847

// Now check LiveVariables info if available

848

if (LiveVars) {

849

calcRegsRequired();

850

verifyLiveVariables();

851

}

852

}

853

854

void MachineVerifier::verifyLiveVariables() {

855

assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");

856

for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,

857

RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {

858

LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);

859

for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();

860

MFI != MFE; ++MFI) {

861

BBInfo &MInfo = MBBInfoMap[MFI];

862

863

// Our vregsRequired should be identical to LiveVariables' AliveBlocks

864

if (MInfo.vregsRequired.count(Reg)) {

865

if (!VI.AliveBlocks.test(MFI->getNumber())) {

866

report("LiveVariables: Block missing from AliveBlocks", MFI);

867

*OS << "Virtual register %reg" << Reg

868

<< " must be live through the block.\n";

869

}

870

} else {

871

if (VI.AliveBlocks.test(MFI->getNumber())) {

872

report("LiveVariables: Block should not be in AliveBlocks", MFI);

873

*OS << "Virtual register %reg" << Reg

874

<< " is not needed live through the block.\n";

875

}

876

}

877

}

878

}

879

}

880

881

~louis/ubuntu/trusty/clamav/lp799623_fix_logrotate