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//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This implements routines for translating from LLVM IR into SelectionDAG IR.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "isel"
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#include "SelectionDAGBuilder.h"
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#include "FunctionLoweringInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/ConstantFolding.h"
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#include "llvm/Constants.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/InlineAsm.h"
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/IntrinsicInst.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/GCStrategy.h"
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#include "llvm/CodeGen/GCMetadata.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/DwarfWriter.h"
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#include "llvm/Analysis/DebugInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetIntrinsicInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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/// LimitFloatPrecision - Generate low-precision inline sequences for
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/// some float libcalls (6, 8 or 12 bits).
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static unsigned LimitFloatPrecision;
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static cl::opt<unsigned, true>
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LimitFPPrecision("limit-float-precision",
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cl::desc("Generate low-precision inline sequences "
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"for some float libcalls"),
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cl::location(LimitFloatPrecision),
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/// RegsForValue - This struct represents the registers (physical or virtual)
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/// that a particular set of values is assigned, and the type information
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/// about the value. The most common situation is to represent one value at a
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/// time, but struct or array values are handled element-wise as multiple
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/// values. The splitting of aggregates is performed recursively, so that we
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/// never have aggregate-typed registers. The values at this point do not
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/// necessarily have legal types, so each value may require one or more
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/// registers of some legal type.
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/// TLI - The TargetLowering object.
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const TargetLowering *TLI;
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/// ValueVTs - The value types of the values, which may not be legal, and
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/// may need be promoted or synthesized from one or more registers.
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SmallVector<EVT, 4> ValueVTs;
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/// RegVTs - The value types of the registers. This is the same size as
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/// ValueVTs and it records, for each value, what the type of the assigned
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/// register or registers are. (Individual values are never synthesized
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/// from more than one type of register.)
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/// With virtual registers, the contents of RegVTs is redundant with TLI's
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/// getRegisterType member function, however when with physical registers
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/// it is necessary to have a separate record of the types.
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SmallVector<EVT, 4> RegVTs;
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/// Regs - This list holds the registers assigned to the values.
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/// Each legal or promoted value requires one register, and each
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/// expanded value requires multiple registers.
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SmallVector<unsigned, 4> Regs;
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RegsForValue() : TLI(0) {}
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RegsForValue(const TargetLowering &tli,
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const SmallVector<unsigned, 4> ®s,
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EVT regvt, EVT valuevt)
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: TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
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RegsForValue(const TargetLowering &tli,
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const SmallVector<unsigned, 4> ®s,
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const SmallVector<EVT, 4> ®vts,
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const SmallVector<EVT, 4> &valuevts)
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: TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
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RegsForValue(LLVMContext &Context, const TargetLowering &tli,
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unsigned Reg, const Type *Ty) : TLI(&tli) {
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ComputeValueVTs(tli, Ty, ValueVTs);
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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EVT ValueVT = ValueVTs[Value];
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unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
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EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
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for (unsigned i = 0; i != NumRegs; ++i)
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Regs.push_back(Reg + i);
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RegVTs.push_back(RegisterVT);
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/// areValueTypesLegal - Return true if types of all the values are legal.
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bool areValueTypesLegal() {
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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EVT RegisterVT = RegVTs[Value];
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if (!TLI->isTypeLegal(RegisterVT))
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/// append - Add the specified values to this one.
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void append(const RegsForValue &RHS) {
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ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
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RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
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Regs.append(RHS.Regs.begin(), RHS.Regs.end());
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/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
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/// this value and returns the result as a ValueVTs value. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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/// If the Flag pointer is NULL, no flag is used.
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SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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SDValue &Chain, SDValue *Flag) const;
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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/// specified value into the registers specified by this object. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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/// If the Flag pointer is NULL, no flag is used.
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void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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SDValue &Chain, SDValue *Flag) const;
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/// AddInlineAsmOperands - Add this value to the specified inlineasm node
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/// operand list. This adds the code marker, matching input operand index
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/// (if applicable), and includes the number of values added into it.
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void AddInlineAsmOperands(unsigned Code,
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bool HasMatching, unsigned MatchingIdx,
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std::vector<SDValue> &Ops) const;
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/// getCopyFromParts - Create a value that contains the specified legal parts
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/// combined into the value they represent. If the parts combine to a type
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/// larger then ValueVT then AssertOp can be used to specify whether the extra
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/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
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/// (ISD::AssertSext).
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static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
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const SDValue *Parts,
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unsigned NumParts, EVT PartVT, EVT ValueVT,
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ISD::NodeType AssertOp = ISD::DELETED_NODE) {
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assert(NumParts > 0 && "No parts to assemble!");
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDValue Val = Parts[0];
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// Assemble the value from multiple parts.
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if (!ValueVT.isVector() && ValueVT.isInteger()) {
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unsigned PartBits = PartVT.getSizeInBits();
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unsigned ValueBits = ValueVT.getSizeInBits();
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// Assemble the power of 2 part.
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unsigned RoundParts = NumParts & (NumParts - 1) ?
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1 << Log2_32(NumParts) : NumParts;
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unsigned RoundBits = PartBits * RoundParts;
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EVT RoundVT = RoundBits == ValueBits ?
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ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
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EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
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if (RoundParts > 2) {
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Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2,
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Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2,
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RoundParts / 2, PartVT, HalfVT);
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Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
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Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
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if (TLI.isBigEndian())
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Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
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if (RoundParts < NumParts) {
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// Assemble the trailing non-power-of-2 part.
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unsigned OddParts = NumParts - RoundParts;
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EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
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Hi = getCopyFromParts(DAG, dl,
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Parts + RoundParts, OddParts, PartVT, OddVT);
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// Combine the round and odd parts.
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if (TLI.isBigEndian())
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EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
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Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
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Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
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DAG.getConstant(Lo.getValueType().getSizeInBits(),
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TLI.getPointerTy()));
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Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
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Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
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} else if (ValueVT.isVector()) {
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// Handle a multi-element vector.
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EVT IntermediateVT, RegisterVT;
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unsigned NumIntermediates;
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TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
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NumIntermediates, RegisterVT);
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assert(NumRegs == NumParts
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&& "Part count doesn't match vector breakdown!");
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NumParts = NumRegs; // Silence a compiler warning.
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assert(RegisterVT == PartVT
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&& "Part type doesn't match vector breakdown!");
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assert(RegisterVT == Parts[0].getValueType() &&
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"Part type doesn't match part!");
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// Assemble the parts into intermediate operands.
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SmallVector<SDValue, 8> Ops(NumIntermediates);
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if (NumIntermediates == NumParts) {
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// If the register was not expanded, truncate or copy the value,
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for (unsigned i = 0; i != NumParts; ++i)
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Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
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PartVT, IntermediateVT);
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} else if (NumParts > 0) {
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// If the intermediate type was expanded, build the intermediate
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// operands from the parts.
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assert(NumParts % NumIntermediates == 0 &&
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"Must expand into a divisible number of parts!");
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unsigned Factor = NumParts / NumIntermediates;
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for (unsigned i = 0; i != NumIntermediates; ++i)
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Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
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PartVT, IntermediateVT);
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// Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
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// intermediate operands.
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Val = DAG.getNode(IntermediateVT.isVector() ?
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ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
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ValueVT, &Ops[0], NumIntermediates);
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} else if (PartVT.isFloatingPoint()) {
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// FP split into multiple FP parts (for ppcf128)
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assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
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Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
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Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
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if (TLI.isBigEndian())
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Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
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// FP split into integer parts (soft fp)
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assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
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!PartVT.isVector() && "Unexpected split");
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EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
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Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
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// There is now one part, held in Val. Correct it to match ValueVT.
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PartVT = Val.getValueType();
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if (PartVT == ValueVT)
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if (PartVT.isVector()) {
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assert(ValueVT.isVector() && "Unknown vector conversion!");
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return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
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if (ValueVT.isVector()) {
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assert(ValueVT.getVectorElementType() == PartVT &&
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ValueVT.getVectorNumElements() == 1 &&
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"Only trivial scalar-to-vector conversions should get here!");
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return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
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if (PartVT.isInteger() &&
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ValueVT.isInteger()) {
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if (ValueVT.bitsLT(PartVT)) {
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// For a truncate, see if we have any information to
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// indicate whether the truncated bits will always be
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// zero or sign-extension.
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if (AssertOp != ISD::DELETED_NODE)
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Val = DAG.getNode(AssertOp, dl, PartVT, Val,
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DAG.getValueType(ValueVT));
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return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
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return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
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if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
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if (ValueVT.bitsLT(Val.getValueType())) {
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// FP_ROUND's are always exact here.
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return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
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DAG.getIntPtrConstant(1));
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return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
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if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
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return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
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llvm_unreachable("Unknown mismatch!");
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/// getCopyToParts - Create a series of nodes that contain the specified value
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/// split into legal parts. If the parts contain more bits than Val, then, for
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/// integers, ExtendKind can be used to specify how to generate the extra bits.
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static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl,
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SDValue Val, SDValue *Parts, unsigned NumParts,
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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EVT PtrVT = TLI.getPointerTy();
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EVT ValueVT = Val.getValueType();
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unsigned PartBits = PartVT.getSizeInBits();
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unsigned OrigNumParts = NumParts;
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assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
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if (!ValueVT.isVector()) {
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if (PartVT == ValueVT) {
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assert(NumParts == 1 && "No-op copy with multiple parts!");
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if (NumParts * PartBits > ValueVT.getSizeInBits()) {
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// If the parts cover more bits than the value has, promote the value.
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if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
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assert(NumParts == 1 && "Do not know what to promote to!");
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Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
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} else if (PartVT.isInteger() && ValueVT.isInteger()) {
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ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
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Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
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llvm_unreachable("Unknown mismatch!");
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} else if (PartBits == ValueVT.getSizeInBits()) {
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// Different types of the same size.
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assert(NumParts == 1 && PartVT != ValueVT);
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Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
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} else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
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// If the parts cover less bits than value has, truncate the value.
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if (PartVT.isInteger() && ValueVT.isInteger()) {
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ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
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Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
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llvm_unreachable("Unknown mismatch!");
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// The value may have changed - recompute ValueVT.
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ValueVT = Val.getValueType();
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assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
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"Failed to tile the value with PartVT!");
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assert(PartVT == ValueVT && "Type conversion failed!");
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// Expand the value into multiple parts.
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if (NumParts & (NumParts - 1)) {
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// The number of parts is not a power of 2. Split off and copy the tail.
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assert(PartVT.isInteger() && ValueVT.isInteger() &&
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"Do not know what to expand to!");
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unsigned RoundParts = 1 << Log2_32(NumParts);
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unsigned RoundBits = RoundParts * PartBits;
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unsigned OddParts = NumParts - RoundParts;
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SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
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DAG.getConstant(RoundBits,
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TLI.getPointerTy()));
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getCopyToParts(DAG, dl, OddVal, Parts + RoundParts,
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if (TLI.isBigEndian())
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// The odd parts were reversed by getCopyToParts - unreverse them.
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std::reverse(Parts + RoundParts, Parts + NumParts);
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NumParts = RoundParts;
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ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
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Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
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// The number of parts is a power of 2. Repeatedly bisect the value using
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Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
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EVT::getIntegerVT(*DAG.getContext(),
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ValueVT.getSizeInBits()),
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for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
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for (unsigned i = 0; i < NumParts; i += StepSize) {
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unsigned ThisBits = StepSize * PartBits / 2;
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EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
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SDValue &Part0 = Parts[i];
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SDValue &Part1 = Parts[i+StepSize/2];
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Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
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DAG.getConstant(1, PtrVT));
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Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
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DAG.getConstant(0, PtrVT));
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if (ThisBits == PartBits && ThisVT != PartVT) {
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Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
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Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
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if (TLI.isBigEndian())
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std::reverse(Parts, Parts + OrigNumParts);
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if (PartVT != ValueVT) {
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if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
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Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
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assert(ValueVT.getVectorElementType() == PartVT &&
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ValueVT.getVectorNumElements() == 1 &&
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"Only trivial vector-to-scalar conversions should get here!");
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Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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DAG.getConstant(0, PtrVT));
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// Handle a multi-element vector.
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EVT IntermediateVT, RegisterVT;
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unsigned NumIntermediates;
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unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
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IntermediateVT, NumIntermediates, RegisterVT);
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unsigned NumElements = ValueVT.getVectorNumElements();
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assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
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NumParts = NumRegs; // Silence a compiler warning.
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assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
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// Split the vector into intermediate operands.
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SmallVector<SDValue, 8> Ops(NumIntermediates);
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for (unsigned i = 0; i != NumIntermediates; ++i) {
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if (IntermediateVT.isVector())
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Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
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DAG.getConstant(i * (NumElements / NumIntermediates),
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Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
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DAG.getConstant(i, PtrVT));
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// Split the intermediate operands into legal parts.
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if (NumParts == NumIntermediates) {
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// If the register was not expanded, promote or copy the value,
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for (unsigned i = 0; i != NumParts; ++i)
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getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
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} else if (NumParts > 0) {
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// If the intermediate type was expanded, split each the value into
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assert(NumParts % NumIntermediates == 0 &&
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"Must expand into a divisible number of parts!");
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unsigned Factor = NumParts / NumIntermediates;
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for (unsigned i = 0; i != NumIntermediates; ++i)
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getCopyToParts(DAG, dl, Ops[i], &Parts[i*Factor], Factor, PartVT);
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void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
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TD = DAG.getTarget().getTargetData();
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/// clear - Clear out the curret SelectionDAG and the associated
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/// state and prepare this SelectionDAGBuilder object to be used
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/// for a new block. This doesn't clear out information about
539
/// additional blocks that are needed to complete switch lowering
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/// or PHI node updating; that information is cleared out as it is
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void SelectionDAGBuilder::clear() {
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PendingLoads.clear();
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PendingExports.clear();
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CurDebugLoc = DebugLoc::getUnknownLoc();
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/// getRoot - Return the current virtual root of the Selection DAG,
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/// flushing any PendingLoad items. This must be done before emitting
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/// a store or any other node that may need to be ordered after any
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/// prior load instructions.
557
SDValue SelectionDAGBuilder::getRoot() {
558
if (PendingLoads.empty())
559
return DAG.getRoot();
561
if (PendingLoads.size() == 1) {
562
SDValue Root = PendingLoads[0];
564
PendingLoads.clear();
568
// Otherwise, we have to make a token factor node.
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SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
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&PendingLoads[0], PendingLoads.size());
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PendingLoads.clear();
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/// getControlRoot - Similar to getRoot, but instead of flushing all the
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/// PendingLoad items, flush all the PendingExports items. It is necessary
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/// to do this before emitting a terminator instruction.
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SDValue SelectionDAGBuilder::getControlRoot() {
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SDValue Root = DAG.getRoot();
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if (PendingExports.empty())
586
// Turn all of the CopyToReg chains into one factored node.
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if (Root.getOpcode() != ISD::EntryToken) {
588
unsigned i = 0, e = PendingExports.size();
589
for (; i != e; ++i) {
590
assert(PendingExports[i].getNode()->getNumOperands() > 1);
591
if (PendingExports[i].getNode()->getOperand(0) == Root)
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break; // Don't add the root if we already indirectly depend on it.
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PendingExports.push_back(Root);
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Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
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PendingExports.size());
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PendingExports.clear();
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void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
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if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
609
DAG.AssignOrdering(Node, SDNodeOrder);
611
for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
612
AssignOrderingToNode(Node->getOperand(I).getNode());
615
void SelectionDAGBuilder::visit(Instruction &I) {
616
visit(I.getOpcode(), I);
619
void SelectionDAGBuilder::visit(unsigned Opcode, User &I) {
620
// Note: this doesn't use InstVisitor, because it has to work with
621
// ConstantExpr's in addition to instructions.
623
default: llvm_unreachable("Unknown instruction type encountered!");
624
// Build the switch statement using the Instruction.def file.
625
#define HANDLE_INST(NUM, OPCODE, CLASS) \
626
case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
627
#include "llvm/Instruction.def"
630
// Assign the ordering to the freshly created DAG nodes.
631
if (NodeMap.count(&I)) {
633
AssignOrderingToNode(getValue(&I).getNode());
637
SDValue SelectionDAGBuilder::getValue(const Value *V) {
638
SDValue &N = NodeMap[V];
639
if (N.getNode()) return N;
641
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
642
EVT VT = TLI.getValueType(V->getType(), true);
644
if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
645
return N = DAG.getConstant(*CI, VT);
647
if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
648
return N = DAG.getGlobalAddress(GV, VT);
650
if (isa<ConstantPointerNull>(C))
651
return N = DAG.getConstant(0, TLI.getPointerTy());
653
if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
654
return N = DAG.getConstantFP(*CFP, VT);
656
if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
657
return N = DAG.getUNDEF(VT);
659
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
660
visit(CE->getOpcode(), *CE);
661
SDValue N1 = NodeMap[V];
662
assert(N1.getNode() && "visit didn't populate the ValueMap!");
666
if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
667
SmallVector<SDValue, 4> Constants;
668
for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
670
SDNode *Val = getValue(*OI).getNode();
671
// If the operand is an empty aggregate, there are no values.
673
// Add each leaf value from the operand to the Constants list
674
// to form a flattened list of all the values.
675
for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
676
Constants.push_back(SDValue(Val, i));
679
return DAG.getMergeValues(&Constants[0], Constants.size(),
683
if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
684
assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
685
"Unknown struct or array constant!");
687
SmallVector<EVT, 4> ValueVTs;
688
ComputeValueVTs(TLI, C->getType(), ValueVTs);
689
unsigned NumElts = ValueVTs.size();
691
return SDValue(); // empty struct
692
SmallVector<SDValue, 4> Constants(NumElts);
693
for (unsigned i = 0; i != NumElts; ++i) {
694
EVT EltVT = ValueVTs[i];
695
if (isa<UndefValue>(C))
696
Constants[i] = DAG.getUNDEF(EltVT);
697
else if (EltVT.isFloatingPoint())
698
Constants[i] = DAG.getConstantFP(0, EltVT);
700
Constants[i] = DAG.getConstant(0, EltVT);
703
return DAG.getMergeValues(&Constants[0], NumElts,
707
if (BlockAddress *BA = dyn_cast<BlockAddress>(C))
708
return DAG.getBlockAddress(BA, VT);
710
const VectorType *VecTy = cast<VectorType>(V->getType());
711
unsigned NumElements = VecTy->getNumElements();
713
// Now that we know the number and type of the elements, get that number of
714
// elements into the Ops array based on what kind of constant it is.
715
SmallVector<SDValue, 16> Ops;
716
if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
717
for (unsigned i = 0; i != NumElements; ++i)
718
Ops.push_back(getValue(CP->getOperand(i)));
720
assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
721
EVT EltVT = TLI.getValueType(VecTy->getElementType());
724
if (EltVT.isFloatingPoint())
725
Op = DAG.getConstantFP(0, EltVT);
727
Op = DAG.getConstant(0, EltVT);
728
Ops.assign(NumElements, Op);
731
// Create a BUILD_VECTOR node.
732
return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
733
VT, &Ops[0], Ops.size());
736
// If this is a static alloca, generate it as the frameindex instead of
738
if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
739
DenseMap<const AllocaInst*, int>::iterator SI =
740
FuncInfo.StaticAllocaMap.find(AI);
741
if (SI != FuncInfo.StaticAllocaMap.end())
742
return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
745
unsigned InReg = FuncInfo.ValueMap[V];
746
assert(InReg && "Value not in map!");
748
RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
749
SDValue Chain = DAG.getEntryNode();
750
return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
753
/// Get the EVTs and ArgFlags collections that represent the legalized return
754
/// type of the given function. This does not require a DAG or a return value,
755
/// and is suitable for use before any DAGs for the function are constructed.
756
static void getReturnInfo(const Type* ReturnType,
757
Attributes attr, SmallVectorImpl<EVT> &OutVTs,
758
SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
760
SmallVectorImpl<uint64_t> *Offsets = 0) {
761
SmallVector<EVT, 4> ValueVTs;
762
ComputeValueVTs(TLI, ReturnType, ValueVTs);
763
unsigned NumValues = ValueVTs.size();
764
if (NumValues == 0) return;
767
for (unsigned j = 0, f = NumValues; j != f; ++j) {
768
EVT VT = ValueVTs[j];
769
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
771
if (attr & Attribute::SExt)
772
ExtendKind = ISD::SIGN_EXTEND;
773
else if (attr & Attribute::ZExt)
774
ExtendKind = ISD::ZERO_EXTEND;
776
// FIXME: C calling convention requires the return type to be promoted to
777
// at least 32-bit. But this is not necessary for non-C calling
778
// conventions. The frontend should mark functions whose return values
779
// require promoting with signext or zeroext attributes.
780
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
781
EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
782
if (VT.bitsLT(MinVT))
786
unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
787
EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
788
unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
789
PartVT.getTypeForEVT(ReturnType->getContext()));
791
// 'inreg' on function refers to return value
792
ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
793
if (attr & Attribute::InReg)
796
// Propagate extension type if any
797
if (attr & Attribute::SExt)
799
else if (attr & Attribute::ZExt)
802
for (unsigned i = 0; i < NumParts; ++i) {
803
OutVTs.push_back(PartVT);
804
OutFlags.push_back(Flags);
807
Offsets->push_back(Offset);
814
void SelectionDAGBuilder::visitRet(ReturnInst &I) {
815
SDValue Chain = getControlRoot();
816
SmallVector<ISD::OutputArg, 8> Outs;
817
FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
819
if (!FLI.CanLowerReturn) {
820
unsigned DemoteReg = FLI.DemoteRegister;
821
const Function *F = I.getParent()->getParent();
823
// Emit a store of the return value through the virtual register.
824
// Leave Outs empty so that LowerReturn won't try to load return
825
// registers the usual way.
826
SmallVector<EVT, 1> PtrValueVTs;
827
ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
830
SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
831
SDValue RetOp = getValue(I.getOperand(0));
833
SmallVector<EVT, 4> ValueVTs;
834
SmallVector<uint64_t, 4> Offsets;
835
ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
836
unsigned NumValues = ValueVTs.size();
838
SmallVector<SDValue, 4> Chains(NumValues);
839
EVT PtrVT = PtrValueVTs[0];
840
for (unsigned i = 0; i != NumValues; ++i) {
841
SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr,
842
DAG.getConstant(Offsets[i], PtrVT));
844
DAG.getStore(Chain, getCurDebugLoc(),
845
SDValue(RetOp.getNode(), RetOp.getResNo() + i),
846
Add, NULL, Offsets[i], false, false, 0);
849
Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
850
MVT::Other, &Chains[0], NumValues);
851
} else if (I.getNumOperands() != 0) {
852
SmallVector<EVT, 4> ValueVTs;
853
ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
854
unsigned NumValues = ValueVTs.size();
856
SDValue RetOp = getValue(I.getOperand(0));
857
for (unsigned j = 0, f = NumValues; j != f; ++j) {
858
EVT VT = ValueVTs[j];
860
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
862
const Function *F = I.getParent()->getParent();
863
if (F->paramHasAttr(0, Attribute::SExt))
864
ExtendKind = ISD::SIGN_EXTEND;
865
else if (F->paramHasAttr(0, Attribute::ZExt))
866
ExtendKind = ISD::ZERO_EXTEND;
868
// FIXME: C calling convention requires the return type to be promoted
869
// to at least 32-bit. But this is not necessary for non-C calling
870
// conventions. The frontend should mark functions whose return values
871
// require promoting with signext or zeroext attributes.
872
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
873
EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
874
if (VT.bitsLT(MinVT))
878
unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
879
EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
880
SmallVector<SDValue, 4> Parts(NumParts);
881
getCopyToParts(DAG, getCurDebugLoc(),
882
SDValue(RetOp.getNode(), RetOp.getResNo() + j),
883
&Parts[0], NumParts, PartVT, ExtendKind);
885
// 'inreg' on function refers to return value
886
ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
887
if (F->paramHasAttr(0, Attribute::InReg))
890
// Propagate extension type if any
891
if (F->paramHasAttr(0, Attribute::SExt))
893
else if (F->paramHasAttr(0, Attribute::ZExt))
896
for (unsigned i = 0; i < NumParts; ++i)
897
Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
902
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
903
CallingConv::ID CallConv =
904
DAG.getMachineFunction().getFunction()->getCallingConv();
905
Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
906
Outs, getCurDebugLoc(), DAG);
908
// Verify that the target's LowerReturn behaved as expected.
909
assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
910
"LowerReturn didn't return a valid chain!");
912
// Update the DAG with the new chain value resulting from return lowering.
916
/// CopyToExportRegsIfNeeded - If the given value has virtual registers
917
/// created for it, emit nodes to copy the value into the virtual
919
void SelectionDAGBuilder::CopyToExportRegsIfNeeded(Value *V) {
920
if (!V->use_empty()) {
921
DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
922
if (VMI != FuncInfo.ValueMap.end())
923
CopyValueToVirtualRegister(V, VMI->second);
927
/// ExportFromCurrentBlock - If this condition isn't known to be exported from
928
/// the current basic block, add it to ValueMap now so that we'll get a
930
void SelectionDAGBuilder::ExportFromCurrentBlock(Value *V) {
931
// No need to export constants.
932
if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
935
if (FuncInfo.isExportedInst(V)) return;
937
unsigned Reg = FuncInfo.InitializeRegForValue(V);
938
CopyValueToVirtualRegister(V, Reg);
941
bool SelectionDAGBuilder::isExportableFromCurrentBlock(Value *V,
942
const BasicBlock *FromBB) {
943
// The operands of the setcc have to be in this block. We don't know
944
// how to export them from some other block.
945
if (Instruction *VI = dyn_cast<Instruction>(V)) {
946
// Can export from current BB.
947
if (VI->getParent() == FromBB)
950
// Is already exported, noop.
951
return FuncInfo.isExportedInst(V);
954
// If this is an argument, we can export it if the BB is the entry block or
955
// if it is already exported.
956
if (isa<Argument>(V)) {
957
if (FromBB == &FromBB->getParent()->getEntryBlock())
960
// Otherwise, can only export this if it is already exported.
961
return FuncInfo.isExportedInst(V);
964
// Otherwise, constants can always be exported.
968
static bool InBlock(const Value *V, const BasicBlock *BB) {
969
if (const Instruction *I = dyn_cast<Instruction>(V))
970
return I->getParent() == BB;
974
/// getFCmpCondCode - Return the ISD condition code corresponding to
975
/// the given LLVM IR floating-point condition code. This includes
976
/// consideration of global floating-point math flags.
978
static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
979
ISD::CondCode FPC, FOC;
981
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
982
case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
983
case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
984
case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
985
case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
986
case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
987
case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
988
case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
989
case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
990
case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
991
case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
992
case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
993
case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
994
case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
995
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
996
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
998
llvm_unreachable("Invalid FCmp predicate opcode!");
999
FOC = FPC = ISD::SETFALSE;
1002
if (FiniteOnlyFPMath())
1008
/// getICmpCondCode - Return the ISD condition code corresponding to
1009
/// the given LLVM IR integer condition code.
1011
static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1013
case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1014
case ICmpInst::ICMP_NE: return ISD::SETNE;
1015
case ICmpInst::ICMP_SLE: return ISD::SETLE;
1016
case ICmpInst::ICMP_ULE: return ISD::SETULE;
1017
case ICmpInst::ICMP_SGE: return ISD::SETGE;
1018
case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1019
case ICmpInst::ICMP_SLT: return ISD::SETLT;
1020
case ICmpInst::ICMP_ULT: return ISD::SETULT;
1021
case ICmpInst::ICMP_SGT: return ISD::SETGT;
1022
case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1024
llvm_unreachable("Invalid ICmp predicate opcode!");
1029
/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1030
/// This function emits a branch and is used at the leaves of an OR or an
1031
/// AND operator tree.
1034
SelectionDAGBuilder::EmitBranchForMergedCondition(Value *Cond,
1035
MachineBasicBlock *TBB,
1036
MachineBasicBlock *FBB,
1037
MachineBasicBlock *CurBB) {
1038
const BasicBlock *BB = CurBB->getBasicBlock();
1040
// If the leaf of the tree is a comparison, merge the condition into
1042
if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1043
// The operands of the cmp have to be in this block. We don't know
1044
// how to export them from some other block. If this is the first block
1045
// of the sequence, no exporting is needed.
1046
if (CurBB == CurMBB ||
1047
(isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1048
isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1049
ISD::CondCode Condition;
1050
if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1051
Condition = getICmpCondCode(IC->getPredicate());
1052
} else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1053
Condition = getFCmpCondCode(FC->getPredicate());
1055
Condition = ISD::SETEQ; // silence warning.
1056
llvm_unreachable("Unknown compare instruction");
1059
CaseBlock CB(Condition, BOp->getOperand(0),
1060
BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1061
SwitchCases.push_back(CB);
1066
// Create a CaseBlock record representing this branch.
1067
CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1068
NULL, TBB, FBB, CurBB);
1069
SwitchCases.push_back(CB);
1072
/// FindMergedConditions - If Cond is an expression like
1073
void SelectionDAGBuilder::FindMergedConditions(Value *Cond,
1074
MachineBasicBlock *TBB,
1075
MachineBasicBlock *FBB,
1076
MachineBasicBlock *CurBB,
1078
// If this node is not part of the or/and tree, emit it as a branch.
1079
Instruction *BOp = dyn_cast<Instruction>(Cond);
1080
if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1081
(unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1082
BOp->getParent() != CurBB->getBasicBlock() ||
1083
!InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1084
!InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1085
EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1089
// Create TmpBB after CurBB.
1090
MachineFunction::iterator BBI = CurBB;
1091
MachineFunction &MF = DAG.getMachineFunction();
1092
MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1093
CurBB->getParent()->insert(++BBI, TmpBB);
1095
if (Opc == Instruction::Or) {
1096
// Codegen X | Y as:
1104
// Emit the LHS condition.
1105
FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1107
// Emit the RHS condition into TmpBB.
1108
FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1110
assert(Opc == Instruction::And && "Unknown merge op!");
1111
// Codegen X & Y as:
1118
// This requires creation of TmpBB after CurBB.
1120
// Emit the LHS condition.
1121
FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1123
// Emit the RHS condition into TmpBB.
1124
FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1128
/// If the set of cases should be emitted as a series of branches, return true.
1129
/// If we should emit this as a bunch of and/or'd together conditions, return
1132
SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1133
if (Cases.size() != 2) return true;
1135
// If this is two comparisons of the same values or'd or and'd together, they
1136
// will get folded into a single comparison, so don't emit two blocks.
1137
if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1138
Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1139
(Cases[0].CmpRHS == Cases[1].CmpLHS &&
1140
Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1144
// Handle: (X != null) | (Y != null) --> (X|Y) != 0
1145
// Handle: (X == null) & (Y == null) --> (X|Y) == 0
1146
if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1147
Cases[0].CC == Cases[1].CC &&
1148
isa<Constant>(Cases[0].CmpRHS) &&
1149
cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1150
if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1152
if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1159
void SelectionDAGBuilder::visitBr(BranchInst &I) {
1160
// Update machine-CFG edges.
1161
MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1163
// Figure out which block is immediately after the current one.
1164
MachineBasicBlock *NextBlock = 0;
1165
MachineFunction::iterator BBI = CurMBB;
1166
if (++BBI != FuncInfo.MF->end())
1169
if (I.isUnconditional()) {
1170
// Update machine-CFG edges.
1171
CurMBB->addSuccessor(Succ0MBB);
1173
// If this is not a fall-through branch, emit the branch.
1174
if (Succ0MBB != NextBlock)
1175
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1176
MVT::Other, getControlRoot(),
1177
DAG.getBasicBlock(Succ0MBB)));
1182
// If this condition is one of the special cases we handle, do special stuff
1184
Value *CondVal = I.getCondition();
1185
MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1187
// If this is a series of conditions that are or'd or and'd together, emit
1188
// this as a sequence of branches instead of setcc's with and/or operations.
1189
// For example, instead of something like:
1202
if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1203
if (BOp->hasOneUse() &&
1204
(BOp->getOpcode() == Instruction::And ||
1205
BOp->getOpcode() == Instruction::Or)) {
1206
FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1207
// If the compares in later blocks need to use values not currently
1208
// exported from this block, export them now. This block should always
1209
// be the first entry.
1210
assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1212
// Allow some cases to be rejected.
1213
if (ShouldEmitAsBranches(SwitchCases)) {
1214
for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1215
ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1216
ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1219
// Emit the branch for this block.
1220
visitSwitchCase(SwitchCases[0]);
1221
SwitchCases.erase(SwitchCases.begin());
1225
// Okay, we decided not to do this, remove any inserted MBB's and clear
1227
for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1228
FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1230
SwitchCases.clear();
1234
// Create a CaseBlock record representing this branch.
1235
CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1236
NULL, Succ0MBB, Succ1MBB, CurMBB);
1238
// Use visitSwitchCase to actually insert the fast branch sequence for this
1240
visitSwitchCase(CB);
1243
/// visitSwitchCase - Emits the necessary code to represent a single node in
1244
/// the binary search tree resulting from lowering a switch instruction.
1245
void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
1247
SDValue CondLHS = getValue(CB.CmpLHS);
1248
DebugLoc dl = getCurDebugLoc();
1250
// Build the setcc now.
1251
if (CB.CmpMHS == NULL) {
1252
// Fold "(X == true)" to X and "(X == false)" to !X to
1253
// handle common cases produced by branch lowering.
1254
if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1255
CB.CC == ISD::SETEQ)
1257
else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1258
CB.CC == ISD::SETEQ) {
1259
SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1260
Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1262
Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1264
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1266
const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1267
const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1269
SDValue CmpOp = getValue(CB.CmpMHS);
1270
EVT VT = CmpOp.getValueType();
1272
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1273
Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1276
SDValue SUB = DAG.getNode(ISD::SUB, dl,
1277
VT, CmpOp, DAG.getConstant(Low, VT));
1278
Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1279
DAG.getConstant(High-Low, VT), ISD::SETULE);
1283
// Update successor info
1284
CurMBB->addSuccessor(CB.TrueBB);
1285
CurMBB->addSuccessor(CB.FalseBB);
1287
// Set NextBlock to be the MBB immediately after the current one, if any.
1288
// This is used to avoid emitting unnecessary branches to the next block.
1289
MachineBasicBlock *NextBlock = 0;
1290
MachineFunction::iterator BBI = CurMBB;
1291
if (++BBI != FuncInfo.MF->end())
1294
// If the lhs block is the next block, invert the condition so that we can
1295
// fall through to the lhs instead of the rhs block.
1296
if (CB.TrueBB == NextBlock) {
1297
std::swap(CB.TrueBB, CB.FalseBB);
1298
SDValue True = DAG.getConstant(1, Cond.getValueType());
1299
Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1302
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1303
MVT::Other, getControlRoot(), Cond,
1304
DAG.getBasicBlock(CB.TrueBB));
1306
// If the branch was constant folded, fix up the CFG.
1307
if (BrCond.getOpcode() == ISD::BR) {
1308
CurMBB->removeSuccessor(CB.FalseBB);
1310
// Otherwise, go ahead and insert the false branch.
1311
if (BrCond == getControlRoot())
1312
CurMBB->removeSuccessor(CB.TrueBB);
1314
if (CB.FalseBB != NextBlock)
1315
BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1316
DAG.getBasicBlock(CB.FalseBB));
1319
DAG.setRoot(BrCond);
1322
/// visitJumpTable - Emit JumpTable node in the current MBB
1323
void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1324
// Emit the code for the jump table
1325
assert(JT.Reg != -1U && "Should lower JT Header first!");
1326
EVT PTy = TLI.getPointerTy();
1327
SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1329
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1330
SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1331
MVT::Other, Index.getValue(1),
1333
DAG.setRoot(BrJumpTable);
1336
/// visitJumpTableHeader - This function emits necessary code to produce index
1337
/// in the JumpTable from switch case.
1338
void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1339
JumpTableHeader &JTH) {
1340
// Subtract the lowest switch case value from the value being switched on and
1341
// conditional branch to default mbb if the result is greater than the
1342
// difference between smallest and largest cases.
1343
SDValue SwitchOp = getValue(JTH.SValue);
1344
EVT VT = SwitchOp.getValueType();
1345
SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1346
DAG.getConstant(JTH.First, VT));
1348
// The SDNode we just created, which holds the value being switched on minus
1349
// the smallest case value, needs to be copied to a virtual register so it
1350
// can be used as an index into the jump table in a subsequent basic block.
1351
// This value may be smaller or larger than the target's pointer type, and
1352
// therefore require extension or truncating.
1353
SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1355
unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1356
SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1357
JumpTableReg, SwitchOp);
1358
JT.Reg = JumpTableReg;
1360
// Emit the range check for the jump table, and branch to the default block
1361
// for the switch statement if the value being switched on exceeds the largest
1362
// case in the switch.
1363
SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1364
TLI.getSetCCResultType(Sub.getValueType()), Sub,
1365
DAG.getConstant(JTH.Last-JTH.First,VT),
1368
// Set NextBlock to be the MBB immediately after the current one, if any.
1369
// This is used to avoid emitting unnecessary branches to the next block.
1370
MachineBasicBlock *NextBlock = 0;
1371
MachineFunction::iterator BBI = CurMBB;
1373
if (++BBI != FuncInfo.MF->end())
1376
SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1377
MVT::Other, CopyTo, CMP,
1378
DAG.getBasicBlock(JT.Default));
1380
if (JT.MBB != NextBlock)
1381
BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1382
DAG.getBasicBlock(JT.MBB));
1384
DAG.setRoot(BrCond);
1387
/// visitBitTestHeader - This function emits necessary code to produce value
1388
/// suitable for "bit tests"
1389
void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
1390
// Subtract the minimum value
1391
SDValue SwitchOp = getValue(B.SValue);
1392
EVT VT = SwitchOp.getValueType();
1393
SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1394
DAG.getConstant(B.First, VT));
1397
SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1398
TLI.getSetCCResultType(Sub.getValueType()),
1399
Sub, DAG.getConstant(B.Range, VT),
1402
SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1403
TLI.getPointerTy());
1405
B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1406
SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1409
// Set NextBlock to be the MBB immediately after the current one, if any.
1410
// This is used to avoid emitting unnecessary branches to the next block.
1411
MachineBasicBlock *NextBlock = 0;
1412
MachineFunction::iterator BBI = CurMBB;
1413
if (++BBI != FuncInfo.MF->end())
1416
MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1418
CurMBB->addSuccessor(B.Default);
1419
CurMBB->addSuccessor(MBB);
1421
SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1422
MVT::Other, CopyTo, RangeCmp,
1423
DAG.getBasicBlock(B.Default));
1425
if (MBB != NextBlock)
1426
BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1427
DAG.getBasicBlock(MBB));
1429
DAG.setRoot(BrRange);
1432
/// visitBitTestCase - this function produces one "bit test"
1433
void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1436
// Make desired shift
1437
SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1438
TLI.getPointerTy());
1439
SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1441
DAG.getConstant(1, TLI.getPointerTy()),
1444
// Emit bit tests and jumps
1445
SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1446
TLI.getPointerTy(), SwitchVal,
1447
DAG.getConstant(B.Mask, TLI.getPointerTy()));
1448
SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1449
TLI.getSetCCResultType(AndOp.getValueType()),
1450
AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1453
CurMBB->addSuccessor(B.TargetBB);
1454
CurMBB->addSuccessor(NextMBB);
1456
SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1457
MVT::Other, getControlRoot(),
1458
AndCmp, DAG.getBasicBlock(B.TargetBB));
1460
// Set NextBlock to be the MBB immediately after the current one, if any.
1461
// This is used to avoid emitting unnecessary branches to the next block.
1462
MachineBasicBlock *NextBlock = 0;
1463
MachineFunction::iterator BBI = CurMBB;
1464
if (++BBI != FuncInfo.MF->end())
1467
if (NextMBB != NextBlock)
1468
BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1469
DAG.getBasicBlock(NextMBB));
1474
void SelectionDAGBuilder::visitInvoke(InvokeInst &I) {
1475
// Retrieve successors.
1476
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1477
MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1479
const Value *Callee(I.getCalledValue());
1480
if (isa<InlineAsm>(Callee))
1483
LowerCallTo(&I, getValue(Callee), false, LandingPad);
1485
// If the value of the invoke is used outside of its defining block, make it
1486
// available as a virtual register.
1487
CopyToExportRegsIfNeeded(&I);
1489
// Update successor info
1490
CurMBB->addSuccessor(Return);
1491
CurMBB->addSuccessor(LandingPad);
1493
// Drop into normal successor.
1494
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1495
MVT::Other, getControlRoot(),
1496
DAG.getBasicBlock(Return)));
1499
void SelectionDAGBuilder::visitUnwind(UnwindInst &I) {
1502
/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1503
/// small case ranges).
1504
bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1505
CaseRecVector& WorkList,
1507
MachineBasicBlock* Default) {
1508
Case& BackCase = *(CR.Range.second-1);
1510
// Size is the number of Cases represented by this range.
1511
size_t Size = CR.Range.second - CR.Range.first;
1515
// Get the MachineFunction which holds the current MBB. This is used when
1516
// inserting any additional MBBs necessary to represent the switch.
1517
MachineFunction *CurMF = FuncInfo.MF;
1519
// Figure out which block is immediately after the current one.
1520
MachineBasicBlock *NextBlock = 0;
1521
MachineFunction::iterator BBI = CR.CaseBB;
1523
if (++BBI != FuncInfo.MF->end())
1526
// TODO: If any two of the cases has the same destination, and if one value
1527
// is the same as the other, but has one bit unset that the other has set,
1528
// use bit manipulation to do two compares at once. For example:
1529
// "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1531
// Rearrange the case blocks so that the last one falls through if possible.
1532
if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1533
// The last case block won't fall through into 'NextBlock' if we emit the
1534
// branches in this order. See if rearranging a case value would help.
1535
for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1536
if (I->BB == NextBlock) {
1537
std::swap(*I, BackCase);
1543
// Create a CaseBlock record representing a conditional branch to
1544
// the Case's target mbb if the value being switched on SV is equal
1546
MachineBasicBlock *CurBlock = CR.CaseBB;
1547
for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1548
MachineBasicBlock *FallThrough;
1550
FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1551
CurMF->insert(BBI, FallThrough);
1553
// Put SV in a virtual register to make it available from the new blocks.
1554
ExportFromCurrentBlock(SV);
1556
// If the last case doesn't match, go to the default block.
1557
FallThrough = Default;
1560
Value *RHS, *LHS, *MHS;
1562
if (I->High == I->Low) {
1563
// This is just small small case range :) containing exactly 1 case
1565
LHS = SV; RHS = I->High; MHS = NULL;
1568
LHS = I->Low; MHS = SV; RHS = I->High;
1570
CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1572
// If emitting the first comparison, just call visitSwitchCase to emit the
1573
// code into the current block. Otherwise, push the CaseBlock onto the
1574
// vector to be later processed by SDISel, and insert the node's MBB
1575
// before the next MBB.
1576
if (CurBlock == CurMBB)
1577
visitSwitchCase(CB);
1579
SwitchCases.push_back(CB);
1581
CurBlock = FallThrough;
1587
static inline bool areJTsAllowed(const TargetLowering &TLI) {
1588
return !DisableJumpTables &&
1589
(TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1590
TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1593
static APInt ComputeRange(const APInt &First, const APInt &Last) {
1594
APInt LastExt(Last), FirstExt(First);
1595
uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1596
LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1597
return (LastExt - FirstExt + 1ULL);
1600
/// handleJTSwitchCase - Emit jumptable for current switch case range
1601
bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1602
CaseRecVector& WorkList,
1604
MachineBasicBlock* Default) {
1605
Case& FrontCase = *CR.Range.first;
1606
Case& BackCase = *(CR.Range.second-1);
1608
const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1609
const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1611
APInt TSize(First.getBitWidth(), 0);
1612
for (CaseItr I = CR.Range.first, E = CR.Range.second;
1616
if (!areJTsAllowed(TLI) || TSize.ult(APInt(First.getBitWidth(), 4)))
1619
APInt Range = ComputeRange(First, Last);
1620
double Density = TSize.roundToDouble() / Range.roundToDouble();
1624
DEBUG(dbgs() << "Lowering jump table\n"
1625
<< "First entry: " << First << ". Last entry: " << Last << '\n'
1626
<< "Range: " << Range
1627
<< "Size: " << TSize << ". Density: " << Density << "\n\n");
1629
// Get the MachineFunction which holds the current MBB. This is used when
1630
// inserting any additional MBBs necessary to represent the switch.
1631
MachineFunction *CurMF = FuncInfo.MF;
1633
// Figure out which block is immediately after the current one.
1634
MachineFunction::iterator BBI = CR.CaseBB;
1637
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1639
// Create a new basic block to hold the code for loading the address
1640
// of the jump table, and jumping to it. Update successor information;
1641
// we will either branch to the default case for the switch, or the jump
1643
MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1644
CurMF->insert(BBI, JumpTableBB);
1645
CR.CaseBB->addSuccessor(Default);
1646
CR.CaseBB->addSuccessor(JumpTableBB);
1648
// Build a vector of destination BBs, corresponding to each target
1649
// of the jump table. If the value of the jump table slot corresponds to
1650
// a case statement, push the case's BB onto the vector, otherwise, push
1652
std::vector<MachineBasicBlock*> DestBBs;
1654
for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1655
const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1656
const APInt &High = cast<ConstantInt>(I->High)->getValue();
1658
if (Low.sle(TEI) && TEI.sle(High)) {
1659
DestBBs.push_back(I->BB);
1663
DestBBs.push_back(Default);
1667
// Update successor info. Add one edge to each unique successor.
1668
BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1669
for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1670
E = DestBBs.end(); I != E; ++I) {
1671
if (!SuccsHandled[(*I)->getNumber()]) {
1672
SuccsHandled[(*I)->getNumber()] = true;
1673
JumpTableBB->addSuccessor(*I);
1677
// Create a jump table index for this jump table, or return an existing
1679
unsigned JTEncoding = TLI.getJumpTableEncoding();
1680
unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1681
->getJumpTableIndex(DestBBs);
1683
// Set the jump table information so that we can codegen it as a second
1684
// MachineBasicBlock
1685
JumpTable JT(-1U, JTI, JumpTableBB, Default);
1686
JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1687
if (CR.CaseBB == CurMBB)
1688
visitJumpTableHeader(JT, JTH);
1690
JTCases.push_back(JumpTableBlock(JTH, JT));
1695
/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1697
bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1698
CaseRecVector& WorkList,
1700
MachineBasicBlock* Default) {
1701
// Get the MachineFunction which holds the current MBB. This is used when
1702
// inserting any additional MBBs necessary to represent the switch.
1703
MachineFunction *CurMF = FuncInfo.MF;
1705
// Figure out which block is immediately after the current one.
1706
MachineFunction::iterator BBI = CR.CaseBB;
1709
Case& FrontCase = *CR.Range.first;
1710
Case& BackCase = *(CR.Range.second-1);
1711
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1713
// Size is the number of Cases represented by this range.
1714
unsigned Size = CR.Range.second - CR.Range.first;
1716
const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1717
const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1719
CaseItr Pivot = CR.Range.first + Size/2;
1721
// Select optimal pivot, maximizing sum density of LHS and RHS. This will
1722
// (heuristically) allow us to emit JumpTable's later.
1723
APInt TSize(First.getBitWidth(), 0);
1724
for (CaseItr I = CR.Range.first, E = CR.Range.second;
1728
APInt LSize = FrontCase.size();
1729
APInt RSize = TSize-LSize;
1730
DEBUG(dbgs() << "Selecting best pivot: \n"
1731
<< "First: " << First << ", Last: " << Last <<'\n'
1732
<< "LSize: " << LSize << ", RSize: " << RSize << '\n');
1733
for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1735
const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1736
const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1737
APInt Range = ComputeRange(LEnd, RBegin);
1738
assert((Range - 2ULL).isNonNegative() &&
1739
"Invalid case distance");
1740
double LDensity = (double)LSize.roundToDouble() /
1741
(LEnd - First + 1ULL).roundToDouble();
1742
double RDensity = (double)RSize.roundToDouble() /
1743
(Last - RBegin + 1ULL).roundToDouble();
1744
double Metric = Range.logBase2()*(LDensity+RDensity);
1745
// Should always split in some non-trivial place
1746
DEBUG(dbgs() <<"=>Step\n"
1747
<< "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1748
<< "LDensity: " << LDensity
1749
<< ", RDensity: " << RDensity << '\n'
1750
<< "Metric: " << Metric << '\n');
1751
if (FMetric < Metric) {
1754
DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1760
if (areJTsAllowed(TLI)) {
1761
// If our case is dense we *really* should handle it earlier!
1762
assert((FMetric > 0) && "Should handle dense range earlier!");
1764
Pivot = CR.Range.first + Size/2;
1767
CaseRange LHSR(CR.Range.first, Pivot);
1768
CaseRange RHSR(Pivot, CR.Range.second);
1769
Constant *C = Pivot->Low;
1770
MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1772
// We know that we branch to the LHS if the Value being switched on is
1773
// less than the Pivot value, C. We use this to optimize our binary
1774
// tree a bit, by recognizing that if SV is greater than or equal to the
1775
// LHS's Case Value, and that Case Value is exactly one less than the
1776
// Pivot's Value, then we can branch directly to the LHS's Target,
1777
// rather than creating a leaf node for it.
1778
if ((LHSR.second - LHSR.first) == 1 &&
1779
LHSR.first->High == CR.GE &&
1780
cast<ConstantInt>(C)->getValue() ==
1781
(cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1782
TrueBB = LHSR.first->BB;
1784
TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1785
CurMF->insert(BBI, TrueBB);
1786
WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1788
// Put SV in a virtual register to make it available from the new blocks.
1789
ExportFromCurrentBlock(SV);
1792
// Similar to the optimization above, if the Value being switched on is
1793
// known to be less than the Constant CR.LT, and the current Case Value
1794
// is CR.LT - 1, then we can branch directly to the target block for
1795
// the current Case Value, rather than emitting a RHS leaf node for it.
1796
if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1797
cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1798
(cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1799
FalseBB = RHSR.first->BB;
1801
FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1802
CurMF->insert(BBI, FalseBB);
1803
WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1805
// Put SV in a virtual register to make it available from the new blocks.
1806
ExportFromCurrentBlock(SV);
1809
// Create a CaseBlock record representing a conditional branch to
1810
// the LHS node if the value being switched on SV is less than C.
1811
// Otherwise, branch to LHS.
1812
CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1814
if (CR.CaseBB == CurMBB)
1815
visitSwitchCase(CB);
1817
SwitchCases.push_back(CB);
1822
/// handleBitTestsSwitchCase - if current case range has few destination and
1823
/// range span less, than machine word bitwidth, encode case range into series
1824
/// of masks and emit bit tests with these masks.
1825
bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
1826
CaseRecVector& WorkList,
1828
MachineBasicBlock* Default){
1829
EVT PTy = TLI.getPointerTy();
1830
unsigned IntPtrBits = PTy.getSizeInBits();
1832
Case& FrontCase = *CR.Range.first;
1833
Case& BackCase = *(CR.Range.second-1);
1835
// Get the MachineFunction which holds the current MBB. This is used when
1836
// inserting any additional MBBs necessary to represent the switch.
1837
MachineFunction *CurMF = FuncInfo.MF;
1839
// If target does not have legal shift left, do not emit bit tests at all.
1840
if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1844
for (CaseItr I = CR.Range.first, E = CR.Range.second;
1846
// Single case counts one, case range - two.
1847
numCmps += (I->Low == I->High ? 1 : 2);
1850
// Count unique destinations
1851
SmallSet<MachineBasicBlock*, 4> Dests;
1852
for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1853
Dests.insert(I->BB);
1854
if (Dests.size() > 3)
1855
// Don't bother the code below, if there are too much unique destinations
1858
DEBUG(dbgs() << "Total number of unique destinations: "
1859
<< Dests.size() << '\n'
1860
<< "Total number of comparisons: " << numCmps << '\n');
1862
// Compute span of values.
1863
const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1864
const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1865
APInt cmpRange = maxValue - minValue;
1867
DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
1868
<< "Low bound: " << minValue << '\n'
1869
<< "High bound: " << maxValue << '\n');
1871
if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1872
(!(Dests.size() == 1 && numCmps >= 3) &&
1873
!(Dests.size() == 2 && numCmps >= 5) &&
1874
!(Dests.size() >= 3 && numCmps >= 6)))
1877
DEBUG(dbgs() << "Emitting bit tests\n");
1878
APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1880
// Optimize the case where all the case values fit in a
1881
// word without having to subtract minValue. In this case,
1882
// we can optimize away the subtraction.
1883
if (minValue.isNonNegative() &&
1884
maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1885
cmpRange = maxValue;
1887
lowBound = minValue;
1890
CaseBitsVector CasesBits;
1891
unsigned i, count = 0;
1893
for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1894
MachineBasicBlock* Dest = I->BB;
1895
for (i = 0; i < count; ++i)
1896
if (Dest == CasesBits[i].BB)
1900
assert((count < 3) && "Too much destinations to test!");
1901
CasesBits.push_back(CaseBits(0, Dest, 0));
1905
const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1906
const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1908
uint64_t lo = (lowValue - lowBound).getZExtValue();
1909
uint64_t hi = (highValue - lowBound).getZExtValue();
1911
for (uint64_t j = lo; j <= hi; j++) {
1912
CasesBits[i].Mask |= 1ULL << j;
1913
CasesBits[i].Bits++;
1917
std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1921
// Figure out which block is immediately after the current one.
1922
MachineFunction::iterator BBI = CR.CaseBB;
1925
const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1927
DEBUG(dbgs() << "Cases:\n");
1928
for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1929
DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
1930
<< ", Bits: " << CasesBits[i].Bits
1931
<< ", BB: " << CasesBits[i].BB << '\n');
1933
MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1934
CurMF->insert(BBI, CaseBB);
1935
BTC.push_back(BitTestCase(CasesBits[i].Mask,
1939
// Put SV in a virtual register to make it available from the new blocks.
1940
ExportFromCurrentBlock(SV);
1943
BitTestBlock BTB(lowBound, cmpRange, SV,
1944
-1U, (CR.CaseBB == CurMBB),
1945
CR.CaseBB, Default, BTC);
1947
if (CR.CaseBB == CurMBB)
1948
visitBitTestHeader(BTB);
1950
BitTestCases.push_back(BTB);
1955
/// Clusterify - Transform simple list of Cases into list of CaseRange's
1956
size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
1957
const SwitchInst& SI) {
1960
// Start with "simple" cases
1961
for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
1962
MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1963
Cases.push_back(Case(SI.getSuccessorValue(i),
1964
SI.getSuccessorValue(i),
1967
std::sort(Cases.begin(), Cases.end(), CaseCmp());
1969
// Merge case into clusters
1970
if (Cases.size() >= 2)
1971
// Must recompute end() each iteration because it may be
1972
// invalidated by erase if we hold on to it
1973
for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
1974
const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
1975
const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
1976
MachineBasicBlock* nextBB = J->BB;
1977
MachineBasicBlock* currentBB = I->BB;
1979
// If the two neighboring cases go to the same destination, merge them
1980
// into a single case.
1981
if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
1989
for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1990
if (I->Low != I->High)
1991
// A range counts double, since it requires two compares.
1998
void SelectionDAGBuilder::visitSwitch(SwitchInst &SI) {
1999
// Figure out which block is immediately after the current one.
2000
MachineBasicBlock *NextBlock = 0;
2001
MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2003
// If there is only the default destination, branch to it if it is not the
2004
// next basic block. Otherwise, just fall through.
2005
if (SI.getNumOperands() == 2) {
2006
// Update machine-CFG edges.
2008
// If this is not a fall-through branch, emit the branch.
2009
CurMBB->addSuccessor(Default);
2010
if (Default != NextBlock)
2011
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2012
MVT::Other, getControlRoot(),
2013
DAG.getBasicBlock(Default)));
2018
// If there are any non-default case statements, create a vector of Cases
2019
// representing each one, and sort the vector so that we can efficiently
2020
// create a binary search tree from them.
2022
size_t numCmps = Clusterify(Cases, SI);
2023
DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2024
<< ". Total compares: " << numCmps << '\n');
2027
// Get the Value to be switched on and default basic blocks, which will be
2028
// inserted into CaseBlock records, representing basic blocks in the binary
2030
Value *SV = SI.getOperand(0);
2032
// Push the initial CaseRec onto the worklist
2033
CaseRecVector WorkList;
2034
WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2036
while (!WorkList.empty()) {
2037
// Grab a record representing a case range to process off the worklist
2038
CaseRec CR = WorkList.back();
2039
WorkList.pop_back();
2041
if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2044
// If the range has few cases (two or less) emit a series of specific
2046
if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2049
// If the switch has more than 5 blocks, and at least 40% dense, and the
2050
// target supports indirect branches, then emit a jump table rather than
2051
// lowering the switch to a binary tree of conditional branches.
2052
if (handleJTSwitchCase(CR, WorkList, SV, Default))
2055
// Emit binary tree. We need to pick a pivot, and push left and right ranges
2056
// onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2057
handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2061
void SelectionDAGBuilder::visitIndirectBr(IndirectBrInst &I) {
2062
// Update machine-CFG edges with unique successors.
2063
SmallVector<BasicBlock*, 32> succs;
2064
succs.reserve(I.getNumSuccessors());
2065
for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2066
succs.push_back(I.getSuccessor(i));
2067
array_pod_sort(succs.begin(), succs.end());
2068
succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2069
for (unsigned i = 0, e = succs.size(); i != e; ++i)
2070
CurMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2072
DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2073
MVT::Other, getControlRoot(),
2074
getValue(I.getAddress())));
2077
void SelectionDAGBuilder::visitFSub(User &I) {
2078
// -0.0 - X --> fneg
2079
const Type *Ty = I.getType();
2080
if (Ty->isVectorTy()) {
2081
if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2082
const VectorType *DestTy = cast<VectorType>(I.getType());
2083
const Type *ElTy = DestTy->getElementType();
2084
unsigned VL = DestTy->getNumElements();
2085
std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2086
Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2088
SDValue Op2 = getValue(I.getOperand(1));
2089
setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2090
Op2.getValueType(), Op2));
2096
if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2097
if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2098
SDValue Op2 = getValue(I.getOperand(1));
2099
setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2100
Op2.getValueType(), Op2));
2104
visitBinary(I, ISD::FSUB);
2107
void SelectionDAGBuilder::visitBinary(User &I, unsigned OpCode) {
2108
SDValue Op1 = getValue(I.getOperand(0));
2109
SDValue Op2 = getValue(I.getOperand(1));
2110
setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2111
Op1.getValueType(), Op1, Op2));
2114
void SelectionDAGBuilder::visitShift(User &I, unsigned Opcode) {
2115
SDValue Op1 = getValue(I.getOperand(0));
2116
SDValue Op2 = getValue(I.getOperand(1));
2117
if (!I.getType()->isVectorTy() &&
2118
Op2.getValueType() != TLI.getShiftAmountTy()) {
2119
// If the operand is smaller than the shift count type, promote it.
2120
EVT PTy = TLI.getPointerTy();
2121
EVT STy = TLI.getShiftAmountTy();
2122
if (STy.bitsGT(Op2.getValueType()))
2123
Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2124
TLI.getShiftAmountTy(), Op2);
2125
// If the operand is larger than the shift count type but the shift
2126
// count type has enough bits to represent any shift value, truncate
2127
// it now. This is a common case and it exposes the truncate to
2128
// optimization early.
2129
else if (STy.getSizeInBits() >=
2130
Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2131
Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2132
TLI.getShiftAmountTy(), Op2);
2133
// Otherwise we'll need to temporarily settle for some other
2134
// convenient type; type legalization will make adjustments as
2136
else if (PTy.bitsLT(Op2.getValueType()))
2137
Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2138
TLI.getPointerTy(), Op2);
2139
else if (PTy.bitsGT(Op2.getValueType()))
2140
Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2141
TLI.getPointerTy(), Op2);
2144
setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2145
Op1.getValueType(), Op1, Op2));
2148
void SelectionDAGBuilder::visitICmp(User &I) {
2149
ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2150
if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2151
predicate = IC->getPredicate();
2152
else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2153
predicate = ICmpInst::Predicate(IC->getPredicate());
2154
SDValue Op1 = getValue(I.getOperand(0));
2155
SDValue Op2 = getValue(I.getOperand(1));
2156
ISD::CondCode Opcode = getICmpCondCode(predicate);
2158
EVT DestVT = TLI.getValueType(I.getType());
2159
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2162
void SelectionDAGBuilder::visitFCmp(User &I) {
2163
FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2164
if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2165
predicate = FC->getPredicate();
2166
else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2167
predicate = FCmpInst::Predicate(FC->getPredicate());
2168
SDValue Op1 = getValue(I.getOperand(0));
2169
SDValue Op2 = getValue(I.getOperand(1));
2170
ISD::CondCode Condition = getFCmpCondCode(predicate);
2171
EVT DestVT = TLI.getValueType(I.getType());
2172
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2175
void SelectionDAGBuilder::visitSelect(User &I) {
2176
SmallVector<EVT, 4> ValueVTs;
2177
ComputeValueVTs(TLI, I.getType(), ValueVTs);
2178
unsigned NumValues = ValueVTs.size();
2179
if (NumValues == 0) return;
2181
SmallVector<SDValue, 4> Values(NumValues);
2182
SDValue Cond = getValue(I.getOperand(0));
2183
SDValue TrueVal = getValue(I.getOperand(1));
2184
SDValue FalseVal = getValue(I.getOperand(2));
2186
for (unsigned i = 0; i != NumValues; ++i)
2187
Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2188
TrueVal.getNode()->getValueType(i), Cond,
2189
SDValue(TrueVal.getNode(),
2190
TrueVal.getResNo() + i),
2191
SDValue(FalseVal.getNode(),
2192
FalseVal.getResNo() + i));
2194
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2195
DAG.getVTList(&ValueVTs[0], NumValues),
2196
&Values[0], NumValues));
2199
void SelectionDAGBuilder::visitTrunc(User &I) {
2200
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2201
SDValue N = getValue(I.getOperand(0));
2202
EVT DestVT = TLI.getValueType(I.getType());
2203
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2206
void SelectionDAGBuilder::visitZExt(User &I) {
2207
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2208
// ZExt also can't be a cast to bool for same reason. So, nothing much to do
2209
SDValue N = getValue(I.getOperand(0));
2210
EVT DestVT = TLI.getValueType(I.getType());
2211
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2214
void SelectionDAGBuilder::visitSExt(User &I) {
2215
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2216
// SExt also can't be a cast to bool for same reason. So, nothing much to do
2217
SDValue N = getValue(I.getOperand(0));
2218
EVT DestVT = TLI.getValueType(I.getType());
2219
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2222
void SelectionDAGBuilder::visitFPTrunc(User &I) {
2223
// FPTrunc is never a no-op cast, no need to check
2224
SDValue N = getValue(I.getOperand(0));
2225
EVT DestVT = TLI.getValueType(I.getType());
2226
setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2227
DestVT, N, DAG.getIntPtrConstant(0)));
2230
void SelectionDAGBuilder::visitFPExt(User &I){
2231
// FPTrunc is never a no-op cast, no need to check
2232
SDValue N = getValue(I.getOperand(0));
2233
EVT DestVT = TLI.getValueType(I.getType());
2234
setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2237
void SelectionDAGBuilder::visitFPToUI(User &I) {
2238
// FPToUI is never a no-op cast, no need to check
2239
SDValue N = getValue(I.getOperand(0));
2240
EVT DestVT = TLI.getValueType(I.getType());
2241
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2244
void SelectionDAGBuilder::visitFPToSI(User &I) {
2245
// FPToSI is never a no-op cast, no need to check
2246
SDValue N = getValue(I.getOperand(0));
2247
EVT DestVT = TLI.getValueType(I.getType());
2248
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2251
void SelectionDAGBuilder::visitUIToFP(User &I) {
2252
// UIToFP is never a no-op cast, no need to check
2253
SDValue N = getValue(I.getOperand(0));
2254
EVT DestVT = TLI.getValueType(I.getType());
2255
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2258
void SelectionDAGBuilder::visitSIToFP(User &I){
2259
// SIToFP is never a no-op cast, no need to check
2260
SDValue N = getValue(I.getOperand(0));
2261
EVT DestVT = TLI.getValueType(I.getType());
2262
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2265
void SelectionDAGBuilder::visitPtrToInt(User &I) {
2266
// What to do depends on the size of the integer and the size of the pointer.
2267
// We can either truncate, zero extend, or no-op, accordingly.
2268
SDValue N = getValue(I.getOperand(0));
2269
EVT SrcVT = N.getValueType();
2270
EVT DestVT = TLI.getValueType(I.getType());
2271
setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2274
void SelectionDAGBuilder::visitIntToPtr(User &I) {
2275
// What to do depends on the size of the integer and the size of the pointer.
2276
// We can either truncate, zero extend, or no-op, accordingly.
2277
SDValue N = getValue(I.getOperand(0));
2278
EVT SrcVT = N.getValueType();
2279
EVT DestVT = TLI.getValueType(I.getType());
2280
setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2283
void SelectionDAGBuilder::visitBitCast(User &I) {
2284
SDValue N = getValue(I.getOperand(0));
2285
EVT DestVT = TLI.getValueType(I.getType());
2287
// BitCast assures us that source and destination are the same size so this is
2288
// either a BIT_CONVERT or a no-op.
2289
if (DestVT != N.getValueType())
2290
setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2291
DestVT, N)); // convert types.
2293
setValue(&I, N); // noop cast.
2296
void SelectionDAGBuilder::visitInsertElement(User &I) {
2297
SDValue InVec = getValue(I.getOperand(0));
2298
SDValue InVal = getValue(I.getOperand(1));
2299
SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2301
getValue(I.getOperand(2)));
2302
setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2303
TLI.getValueType(I.getType()),
2304
InVec, InVal, InIdx));
2307
void SelectionDAGBuilder::visitExtractElement(User &I) {
2308
SDValue InVec = getValue(I.getOperand(0));
2309
SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2311
getValue(I.getOperand(1)));
2312
setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2313
TLI.getValueType(I.getType()), InVec, InIdx));
2316
// Utility for visitShuffleVector - Returns true if the mask is mask starting
2317
// from SIndx and increasing to the element length (undefs are allowed).
2318
static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2319
unsigned MaskNumElts = Mask.size();
2320
for (unsigned i = 0; i != MaskNumElts; ++i)
2321
if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2326
void SelectionDAGBuilder::visitShuffleVector(User &I) {
2327
SmallVector<int, 8> Mask;
2328
SDValue Src1 = getValue(I.getOperand(0));
2329
SDValue Src2 = getValue(I.getOperand(1));
2331
// Convert the ConstantVector mask operand into an array of ints, with -1
2332
// representing undef values.
2333
SmallVector<Constant*, 8> MaskElts;
2334
cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2335
unsigned MaskNumElts = MaskElts.size();
2336
for (unsigned i = 0; i != MaskNumElts; ++i) {
2337
if (isa<UndefValue>(MaskElts[i]))
2340
Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2343
EVT VT = TLI.getValueType(I.getType());
2344
EVT SrcVT = Src1.getValueType();
2345
unsigned SrcNumElts = SrcVT.getVectorNumElements();
2347
if (SrcNumElts == MaskNumElts) {
2348
setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2353
// Normalize the shuffle vector since mask and vector length don't match.
2354
if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2355
// Mask is longer than the source vectors and is a multiple of the source
2356
// vectors. We can use concatenate vector to make the mask and vectors
2358
if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2359
// The shuffle is concatenating two vectors together.
2360
setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2365
// Pad both vectors with undefs to make them the same length as the mask.
2366
unsigned NumConcat = MaskNumElts / SrcNumElts;
2367
bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2368
bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2369
SDValue UndefVal = DAG.getUNDEF(SrcVT);
2371
SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2372
SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2376
Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2377
getCurDebugLoc(), VT,
2378
&MOps1[0], NumConcat);
2379
Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2380
getCurDebugLoc(), VT,
2381
&MOps2[0], NumConcat);
2383
// Readjust mask for new input vector length.
2384
SmallVector<int, 8> MappedOps;
2385
for (unsigned i = 0; i != MaskNumElts; ++i) {
2387
if (Idx < (int)SrcNumElts)
2388
MappedOps.push_back(Idx);
2390
MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2393
setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2398
if (SrcNumElts > MaskNumElts) {
2399
// Analyze the access pattern of the vector to see if we can extract
2400
// two subvectors and do the shuffle. The analysis is done by calculating
2401
// the range of elements the mask access on both vectors.
2402
int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2403
int MaxRange[2] = {-1, -1};
2405
for (unsigned i = 0; i != MaskNumElts; ++i) {
2411
if (Idx >= (int)SrcNumElts) {
2415
if (Idx > MaxRange[Input])
2416
MaxRange[Input] = Idx;
2417
if (Idx < MinRange[Input])
2418
MinRange[Input] = Idx;
2421
// Check if the access is smaller than the vector size and can we find
2422
// a reasonable extract index.
2423
int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2425
int StartIdx[2]; // StartIdx to extract from
2426
for (int Input=0; Input < 2; ++Input) {
2427
if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2428
RangeUse[Input] = 0; // Unused
2429
StartIdx[Input] = 0;
2430
} else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2431
// Fits within range but we should see if we can find a good
2432
// start index that is a multiple of the mask length.
2433
if (MaxRange[Input] < (int)MaskNumElts) {
2434
RangeUse[Input] = 1; // Extract from beginning of the vector
2435
StartIdx[Input] = 0;
2437
StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2438
if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2439
StartIdx[Input] + MaskNumElts < SrcNumElts)
2440
RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2445
if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2446
setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2449
else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2450
// Extract appropriate subvector and generate a vector shuffle
2451
for (int Input=0; Input < 2; ++Input) {
2452
SDValue &Src = Input == 0 ? Src1 : Src2;
2453
if (RangeUse[Input] == 0)
2454
Src = DAG.getUNDEF(VT);
2456
Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2457
Src, DAG.getIntPtrConstant(StartIdx[Input]));
2460
// Calculate new mask.
2461
SmallVector<int, 8> MappedOps;
2462
for (unsigned i = 0; i != MaskNumElts; ++i) {
2465
MappedOps.push_back(Idx);
2466
else if (Idx < (int)SrcNumElts)
2467
MappedOps.push_back(Idx - StartIdx[0]);
2469
MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2472
setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2478
// We can't use either concat vectors or extract subvectors so fall back to
2479
// replacing the shuffle with extract and build vector.
2480
// to insert and build vector.
2481
EVT EltVT = VT.getVectorElementType();
2482
EVT PtrVT = TLI.getPointerTy();
2483
SmallVector<SDValue,8> Ops;
2484
for (unsigned i = 0; i != MaskNumElts; ++i) {
2486
Ops.push_back(DAG.getUNDEF(EltVT));
2491
if (Idx < (int)SrcNumElts)
2492
Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2493
EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2495
Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2497
DAG.getConstant(Idx - SrcNumElts, PtrVT));
2503
setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2504
VT, &Ops[0], Ops.size()));
2507
void SelectionDAGBuilder::visitInsertValue(InsertValueInst &I) {
2508
const Value *Op0 = I.getOperand(0);
2509
const Value *Op1 = I.getOperand(1);
2510
const Type *AggTy = I.getType();
2511
const Type *ValTy = Op1->getType();
2512
bool IntoUndef = isa<UndefValue>(Op0);
2513
bool FromUndef = isa<UndefValue>(Op1);
2515
unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2516
I.idx_begin(), I.idx_end());
2518
SmallVector<EVT, 4> AggValueVTs;
2519
ComputeValueVTs(TLI, AggTy, AggValueVTs);
2520
SmallVector<EVT, 4> ValValueVTs;
2521
ComputeValueVTs(TLI, ValTy, ValValueVTs);
2523
unsigned NumAggValues = AggValueVTs.size();
2524
unsigned NumValValues = ValValueVTs.size();
2525
SmallVector<SDValue, 4> Values(NumAggValues);
2527
SDValue Agg = getValue(Op0);
2528
SDValue Val = getValue(Op1);
2530
// Copy the beginning value(s) from the original aggregate.
2531
for (; i != LinearIndex; ++i)
2532
Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2533
SDValue(Agg.getNode(), Agg.getResNo() + i);
2534
// Copy values from the inserted value(s).
2535
for (; i != LinearIndex + NumValValues; ++i)
2536
Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2537
SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2538
// Copy remaining value(s) from the original aggregate.
2539
for (; i != NumAggValues; ++i)
2540
Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2541
SDValue(Agg.getNode(), Agg.getResNo() + i);
2543
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2544
DAG.getVTList(&AggValueVTs[0], NumAggValues),
2545
&Values[0], NumAggValues));
2548
void SelectionDAGBuilder::visitExtractValue(ExtractValueInst &I) {
2549
const Value *Op0 = I.getOperand(0);
2550
const Type *AggTy = Op0->getType();
2551
const Type *ValTy = I.getType();
2552
bool OutOfUndef = isa<UndefValue>(Op0);
2554
unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2555
I.idx_begin(), I.idx_end());
2557
SmallVector<EVT, 4> ValValueVTs;
2558
ComputeValueVTs(TLI, ValTy, ValValueVTs);
2560
unsigned NumValValues = ValValueVTs.size();
2561
SmallVector<SDValue, 4> Values(NumValValues);
2563
SDValue Agg = getValue(Op0);
2564
// Copy out the selected value(s).
2565
for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2566
Values[i - LinearIndex] =
2568
DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2569
SDValue(Agg.getNode(), Agg.getResNo() + i);
2571
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2572
DAG.getVTList(&ValValueVTs[0], NumValValues),
2573
&Values[0], NumValValues));
2576
void SelectionDAGBuilder::visitGetElementPtr(User &I) {
2577
SDValue N = getValue(I.getOperand(0));
2578
const Type *Ty = I.getOperand(0)->getType();
2580
for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2583
if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2584
unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2587
uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2588
N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2589
DAG.getIntPtrConstant(Offset));
2592
Ty = StTy->getElementType(Field);
2594
Ty = cast<SequentialType>(Ty)->getElementType();
2596
// If this is a constant subscript, handle it quickly.
2597
if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2598
if (CI->getZExtValue() == 0) continue;
2600
TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2602
EVT PTy = TLI.getPointerTy();
2603
unsigned PtrBits = PTy.getSizeInBits();
2605
OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2607
DAG.getConstant(Offs, MVT::i64));
2609
OffsVal = DAG.getIntPtrConstant(Offs);
2611
N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2616
// N = N + Idx * ElementSize;
2617
APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2618
TD->getTypeAllocSize(Ty));
2619
SDValue IdxN = getValue(Idx);
2621
// If the index is smaller or larger than intptr_t, truncate or extend
2623
IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2625
// If this is a multiply by a power of two, turn it into a shl
2626
// immediately. This is a very common case.
2627
if (ElementSize != 1) {
2628
if (ElementSize.isPowerOf2()) {
2629
unsigned Amt = ElementSize.logBase2();
2630
IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2631
N.getValueType(), IdxN,
2632
DAG.getConstant(Amt, TLI.getPointerTy()));
2634
SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2635
IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2636
N.getValueType(), IdxN, Scale);
2640
N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2641
N.getValueType(), N, IdxN);
2648
void SelectionDAGBuilder::visitAlloca(AllocaInst &I) {
2649
// If this is a fixed sized alloca in the entry block of the function,
2650
// allocate it statically on the stack.
2651
if (FuncInfo.StaticAllocaMap.count(&I))
2652
return; // getValue will auto-populate this.
2654
const Type *Ty = I.getAllocatedType();
2655
uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2657
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2660
SDValue AllocSize = getValue(I.getArraySize());
2662
AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2664
DAG.getConstant(TySize, AllocSize.getValueType()));
2666
EVT IntPtr = TLI.getPointerTy();
2667
AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2669
// Handle alignment. If the requested alignment is less than or equal to
2670
// the stack alignment, ignore it. If the size is greater than or equal to
2671
// the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2672
unsigned StackAlign =
2673
TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2674
if (Align <= StackAlign)
2677
// Round the size of the allocation up to the stack alignment size
2678
// by add SA-1 to the size.
2679
AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2680
AllocSize.getValueType(), AllocSize,
2681
DAG.getIntPtrConstant(StackAlign-1));
2683
// Mask out the low bits for alignment purposes.
2684
AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2685
AllocSize.getValueType(), AllocSize,
2686
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2688
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2689
SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2690
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2693
DAG.setRoot(DSA.getValue(1));
2695
// Inform the Frame Information that we have just allocated a variable-sized
2697
FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2700
void SelectionDAGBuilder::visitLoad(LoadInst &I) {
2701
const Value *SV = I.getOperand(0);
2702
SDValue Ptr = getValue(SV);
2704
const Type *Ty = I.getType();
2706
bool isVolatile = I.isVolatile();
2707
bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2708
unsigned Alignment = I.getAlignment();
2710
SmallVector<EVT, 4> ValueVTs;
2711
SmallVector<uint64_t, 4> Offsets;
2712
ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2713
unsigned NumValues = ValueVTs.size();
2718
bool ConstantMemory = false;
2720
// Serialize volatile loads with other side effects.
2722
else if (AA->pointsToConstantMemory(SV)) {
2723
// Do not serialize (non-volatile) loads of constant memory with anything.
2724
Root = DAG.getEntryNode();
2725
ConstantMemory = true;
2727
// Do not serialize non-volatile loads against each other.
2728
Root = DAG.getRoot();
2731
SmallVector<SDValue, 4> Values(NumValues);
2732
SmallVector<SDValue, 4> Chains(NumValues);
2733
EVT PtrVT = Ptr.getValueType();
2734
for (unsigned i = 0; i != NumValues; ++i) {
2735
SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2737
DAG.getConstant(Offsets[i], PtrVT));
2738
SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2739
A, SV, Offsets[i], isVolatile,
2740
isNonTemporal, Alignment);
2743
Chains[i] = L.getValue(1);
2746
if (!ConstantMemory) {
2747
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2748
MVT::Other, &Chains[0], NumValues);
2752
PendingLoads.push_back(Chain);
2755
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2756
DAG.getVTList(&ValueVTs[0], NumValues),
2757
&Values[0], NumValues));
2760
void SelectionDAGBuilder::visitStore(StoreInst &I) {
2761
Value *SrcV = I.getOperand(0);
2762
Value *PtrV = I.getOperand(1);
2764
SmallVector<EVT, 4> ValueVTs;
2765
SmallVector<uint64_t, 4> Offsets;
2766
ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2767
unsigned NumValues = ValueVTs.size();
2771
// Get the lowered operands. Note that we do this after
2772
// checking if NumResults is zero, because with zero results
2773
// the operands won't have values in the map.
2774
SDValue Src = getValue(SrcV);
2775
SDValue Ptr = getValue(PtrV);
2777
SDValue Root = getRoot();
2778
SmallVector<SDValue, 4> Chains(NumValues);
2779
EVT PtrVT = Ptr.getValueType();
2780
bool isVolatile = I.isVolatile();
2781
bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2782
unsigned Alignment = I.getAlignment();
2784
for (unsigned i = 0; i != NumValues; ++i) {
2785
SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
2786
DAG.getConstant(Offsets[i], PtrVT));
2787
Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2788
SDValue(Src.getNode(), Src.getResNo() + i),
2789
Add, PtrV, Offsets[i], isVolatile,
2790
isNonTemporal, Alignment);
2793
DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2794
MVT::Other, &Chains[0], NumValues));
2797
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2799
void SelectionDAGBuilder::visitTargetIntrinsic(CallInst &I,
2800
unsigned Intrinsic) {
2801
bool HasChain = !I.doesNotAccessMemory();
2802
bool OnlyLoad = HasChain && I.onlyReadsMemory();
2804
// Build the operand list.
2805
SmallVector<SDValue, 8> Ops;
2806
if (HasChain) { // If this intrinsic has side-effects, chainify it.
2808
// We don't need to serialize loads against other loads.
2809
Ops.push_back(DAG.getRoot());
2811
Ops.push_back(getRoot());
2815
// Info is set by getTgtMemInstrinsic
2816
TargetLowering::IntrinsicInfo Info;
2817
bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2819
// Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2820
if (!IsTgtIntrinsic)
2821
Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2823
// Add all operands of the call to the operand list.
2824
for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2825
SDValue Op = getValue(I.getOperand(i));
2826
assert(TLI.isTypeLegal(Op.getValueType()) &&
2827
"Intrinsic uses a non-legal type?");
2831
SmallVector<EVT, 4> ValueVTs;
2832
ComputeValueVTs(TLI, I.getType(), ValueVTs);
2834
for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2835
assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2836
"Intrinsic uses a non-legal type?");
2841
ValueVTs.push_back(MVT::Other);
2843
SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2847
if (IsTgtIntrinsic) {
2848
// This is target intrinsic that touches memory
2849
Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2850
VTs, &Ops[0], Ops.size(),
2851
Info.memVT, Info.ptrVal, Info.offset,
2852
Info.align, Info.vol,
2853
Info.readMem, Info.writeMem);
2854
} else if (!HasChain) {
2855
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2856
VTs, &Ops[0], Ops.size());
2857
} else if (!I.getType()->isVoidTy()) {
2858
Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2859
VTs, &Ops[0], Ops.size());
2861
Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2862
VTs, &Ops[0], Ops.size());
2866
SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2868
PendingLoads.push_back(Chain);
2873
if (!I.getType()->isVoidTy()) {
2874
if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2875
EVT VT = TLI.getValueType(PTy);
2876
Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2879
setValue(&I, Result);
2883
/// GetSignificand - Get the significand and build it into a floating-point
2884
/// number with exponent of 1:
2886
/// Op = (Op & 0x007fffff) | 0x3f800000;
2888
/// where Op is the hexidecimal representation of floating point value.
2890
GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
2891
SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2892
DAG.getConstant(0x007fffff, MVT::i32));
2893
SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
2894
DAG.getConstant(0x3f800000, MVT::i32));
2895
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
2898
/// GetExponent - Get the exponent:
2900
/// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
2902
/// where Op is the hexidecimal representation of floating point value.
2904
GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
2906
SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2907
DAG.getConstant(0x7f800000, MVT::i32));
2908
SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
2909
DAG.getConstant(23, TLI.getPointerTy()));
2910
SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
2911
DAG.getConstant(127, MVT::i32));
2912
return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
2915
/// getF32Constant - Get 32-bit floating point constant.
2917
getF32Constant(SelectionDAG &DAG, unsigned Flt) {
2918
return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
2921
/// Inlined utility function to implement binary input atomic intrinsics for
2922
/// visitIntrinsicCall: I is a call instruction
2923
/// Op is the associated NodeType for I
2925
SelectionDAGBuilder::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
2926
SDValue Root = getRoot();
2928
DAG.getAtomic(Op, getCurDebugLoc(),
2929
getValue(I.getOperand(2)).getValueType().getSimpleVT(),
2931
getValue(I.getOperand(1)),
2932
getValue(I.getOperand(2)),
2935
DAG.setRoot(L.getValue(1));
2939
// implVisitAluOverflow - Lower arithmetic overflow instrinsics.
2941
SelectionDAGBuilder::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
2942
SDValue Op1 = getValue(I.getOperand(1));
2943
SDValue Op2 = getValue(I.getOperand(2));
2945
SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
2946
setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
2950
/// visitExp - Lower an exp intrinsic. Handles the special sequences for
2951
/// limited-precision mode.
2953
SelectionDAGBuilder::visitExp(CallInst &I) {
2955
DebugLoc dl = getCurDebugLoc();
2957
if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2958
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2959
SDValue Op = getValue(I.getOperand(1));
2961
// Put the exponent in the right bit position for later addition to the
2964
// #define LOG2OFe 1.4426950f
2965
// IntegerPartOfX = ((int32_t)(X * LOG2OFe));
2966
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
2967
getF32Constant(DAG, 0x3fb8aa3b));
2968
SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
2970
// FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
2971
SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
2972
SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
2974
// IntegerPartOfX <<= 23;
2975
IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
2976
DAG.getConstant(23, TLI.getPointerTy()));
2978
if (LimitFloatPrecision <= 6) {
2979
// For floating-point precision of 6:
2981
// TwoToFractionalPartOfX =
2983
// (0.735607626f + 0.252464424f * x) * x;
2985
// error 0.0144103317, which is 6 bits
2986
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2987
getF32Constant(DAG, 0x3e814304));
2988
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2989
getF32Constant(DAG, 0x3f3c50c8));
2990
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
2991
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
2992
getF32Constant(DAG, 0x3f7f5e7e));
2993
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
2995
// Add the exponent into the result in integer domain.
2996
SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2997
TwoToFracPartOfX, IntegerPartOfX);
2999
result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3000
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3001
// For floating-point precision of 12:
3003
// TwoToFractionalPartOfX =
3006
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
3008
// 0.000107046256 error, which is 13 to 14 bits
3009
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3010
getF32Constant(DAG, 0x3da235e3));
3011
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3012
getF32Constant(DAG, 0x3e65b8f3));
3013
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3014
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3015
getF32Constant(DAG, 0x3f324b07));
3016
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3017
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3018
getF32Constant(DAG, 0x3f7ff8fd));
3019
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3021
// Add the exponent into the result in integer domain.
3022
SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3023
TwoToFracPartOfX, IntegerPartOfX);
3025
result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3026
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3027
// For floating-point precision of 18:
3029
// TwoToFractionalPartOfX =
3033
// (0.554906021e-1f +
3034
// (0.961591928e-2f +
3035
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3037
// error 2.47208000*10^(-7), which is better than 18 bits
3038
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3039
getF32Constant(DAG, 0x3924b03e));
3040
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3041
getF32Constant(DAG, 0x3ab24b87));
3042
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3043
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3044
getF32Constant(DAG, 0x3c1d8c17));
3045
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3046
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3047
getF32Constant(DAG, 0x3d634a1d));
3048
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3049
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3050
getF32Constant(DAG, 0x3e75fe14));
3051
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3052
SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3053
getF32Constant(DAG, 0x3f317234));
3054
SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3055
SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3056
getF32Constant(DAG, 0x3f800000));
3057
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3060
// Add the exponent into the result in integer domain.
3061
SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3062
TwoToFracPartOfX, IntegerPartOfX);
3064
result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3067
// No special expansion.
3068
result = DAG.getNode(ISD::FEXP, dl,
3069
getValue(I.getOperand(1)).getValueType(),
3070
getValue(I.getOperand(1)));
3073
setValue(&I, result);
3076
/// visitLog - Lower a log intrinsic. Handles the special sequences for
3077
/// limited-precision mode.
3079
SelectionDAGBuilder::visitLog(CallInst &I) {
3081
DebugLoc dl = getCurDebugLoc();
3083
if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3084
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3085
SDValue Op = getValue(I.getOperand(1));
3086
SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3088
// Scale the exponent by log(2) [0.69314718f].
3089
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3090
SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3091
getF32Constant(DAG, 0x3f317218));
3093
// Get the significand and build it into a floating-point number with
3095
SDValue X = GetSignificand(DAG, Op1, dl);
3097
if (LimitFloatPrecision <= 6) {
3098
// For floating-point precision of 6:
3102
// (1.4034025f - 0.23903021f * x) * x;
3104
// error 0.0034276066, which is better than 8 bits
3105
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3106
getF32Constant(DAG, 0xbe74c456));
3107
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3108
getF32Constant(DAG, 0x3fb3a2b1));
3109
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3110
SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3111
getF32Constant(DAG, 0x3f949a29));
3113
result = DAG.getNode(ISD::FADD, dl,
3114
MVT::f32, LogOfExponent, LogOfMantissa);
3115
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3116
// For floating-point precision of 12:
3122
// (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3124
// error 0.000061011436, which is 14 bits
3125
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3126
getF32Constant(DAG, 0xbd67b6d6));
3127
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3128
getF32Constant(DAG, 0x3ee4f4b8));
3129
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3130
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3131
getF32Constant(DAG, 0x3fbc278b));
3132
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3133
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3134
getF32Constant(DAG, 0x40348e95));
3135
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3136
SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3137
getF32Constant(DAG, 0x3fdef31a));
3139
result = DAG.getNode(ISD::FADD, dl,
3140
MVT::f32, LogOfExponent, LogOfMantissa);
3141
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3142
// For floating-point precision of 18:
3150
// (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3152
// error 0.0000023660568, which is better than 18 bits
3153
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3154
getF32Constant(DAG, 0xbc91e5ac));
3155
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3156
getF32Constant(DAG, 0x3e4350aa));
3157
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3158
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3159
getF32Constant(DAG, 0x3f60d3e3));
3160
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3161
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3162
getF32Constant(DAG, 0x4011cdf0));
3163
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3164
SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3165
getF32Constant(DAG, 0x406cfd1c));
3166
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3167
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3168
getF32Constant(DAG, 0x408797cb));
3169
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3170
SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3171
getF32Constant(DAG, 0x4006dcab));
3173
result = DAG.getNode(ISD::FADD, dl,
3174
MVT::f32, LogOfExponent, LogOfMantissa);
3177
// No special expansion.
3178
result = DAG.getNode(ISD::FLOG, dl,
3179
getValue(I.getOperand(1)).getValueType(),
3180
getValue(I.getOperand(1)));
3183
setValue(&I, result);
3186
/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3187
/// limited-precision mode.
3189
SelectionDAGBuilder::visitLog2(CallInst &I) {
3191
DebugLoc dl = getCurDebugLoc();
3193
if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3194
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3195
SDValue Op = getValue(I.getOperand(1));
3196
SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3198
// Get the exponent.
3199
SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3201
// Get the significand and build it into a floating-point number with
3203
SDValue X = GetSignificand(DAG, Op1, dl);
3205
// Different possible minimax approximations of significand in
3206
// floating-point for various degrees of accuracy over [1,2].
3207
if (LimitFloatPrecision <= 6) {
3208
// For floating-point precision of 6:
3210
// Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3212
// error 0.0049451742, which is more than 7 bits
3213
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3214
getF32Constant(DAG, 0xbeb08fe0));
3215
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3216
getF32Constant(DAG, 0x40019463));
3217
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3218
SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3219
getF32Constant(DAG, 0x3fd6633d));
3221
result = DAG.getNode(ISD::FADD, dl,
3222
MVT::f32, LogOfExponent, Log2ofMantissa);
3223
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3224
// For floating-point precision of 12:
3230
// (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3232
// error 0.0000876136000, which is better than 13 bits
3233
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3234
getF32Constant(DAG, 0xbda7262e));
3235
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3236
getF32Constant(DAG, 0x3f25280b));
3237
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3238
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3239
getF32Constant(DAG, 0x4007b923));
3240
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3241
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3242
getF32Constant(DAG, 0x40823e2f));
3243
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3244
SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3245
getF32Constant(DAG, 0x4020d29c));
3247
result = DAG.getNode(ISD::FADD, dl,
3248
MVT::f32, LogOfExponent, Log2ofMantissa);
3249
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3250
// For floating-point precision of 18:
3259
// 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3261
// error 0.0000018516, which is better than 18 bits
3262
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3263
getF32Constant(DAG, 0xbcd2769e));
3264
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3265
getF32Constant(DAG, 0x3e8ce0b9));
3266
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3267
SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3268
getF32Constant(DAG, 0x3fa22ae7));
3269
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3270
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3271
getF32Constant(DAG, 0x40525723));
3272
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3273
SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3274
getF32Constant(DAG, 0x40aaf200));
3275
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3276
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3277
getF32Constant(DAG, 0x40c39dad));
3278
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3279
SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3280
getF32Constant(DAG, 0x4042902c));
3282
result = DAG.getNode(ISD::FADD, dl,
3283
MVT::f32, LogOfExponent, Log2ofMantissa);
3286
// No special expansion.
3287
result = DAG.getNode(ISD::FLOG2, dl,
3288
getValue(I.getOperand(1)).getValueType(),
3289
getValue(I.getOperand(1)));
3292
setValue(&I, result);
3295
/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3296
/// limited-precision mode.
3298
SelectionDAGBuilder::visitLog10(CallInst &I) {
3300
DebugLoc dl = getCurDebugLoc();
3302
if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3303
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3304
SDValue Op = getValue(I.getOperand(1));
3305
SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3307
// Scale the exponent by log10(2) [0.30102999f].
3308
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3309
SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3310
getF32Constant(DAG, 0x3e9a209a));
3312
// Get the significand and build it into a floating-point number with
3314
SDValue X = GetSignificand(DAG, Op1, dl);
3316
if (LimitFloatPrecision <= 6) {
3317
// For floating-point precision of 6:
3319
// Log10ofMantissa =
3321
// (0.60948995f - 0.10380950f * x) * x;
3323
// error 0.0014886165, which is 6 bits
3324
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3325
getF32Constant(DAG, 0xbdd49a13));
3326
SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3327
getF32Constant(DAG, 0x3f1c0789));
3328
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3329
SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3330
getF32Constant(DAG, 0x3f011300));
3332
result = DAG.getNode(ISD::FADD, dl,
3333
MVT::f32, LogOfExponent, Log10ofMantissa);
3334
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3335
// For floating-point precision of 12:
3337
// Log10ofMantissa =
3340
// (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3342
// error 0.00019228036, which is better than 12 bits
3343
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3344
getF32Constant(DAG, 0x3d431f31));
3345
SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3346
getF32Constant(DAG, 0x3ea21fb2));
3347
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3348
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3349
getF32Constant(DAG, 0x3f6ae232));
3350
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3351
SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3352
getF32Constant(DAG, 0x3f25f7c3));
3354
result = DAG.getNode(ISD::FADD, dl,
3355
MVT::f32, LogOfExponent, Log10ofMantissa);
3356
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3357
// For floating-point precision of 18:
3359
// Log10ofMantissa =
3364
// (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3366
// error 0.0000037995730, which is better than 18 bits
3367
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3368
getF32Constant(DAG, 0x3c5d51ce));
3369
SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3370
getF32Constant(DAG, 0x3e00685a));
3371
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3372
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3373
getF32Constant(DAG, 0x3efb6798));
3374
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3375
SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3376
getF32Constant(DAG, 0x3f88d192));
3377
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3378
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3379
getF32Constant(DAG, 0x3fc4316c));
3380
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3381
SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3382
getF32Constant(DAG, 0x3f57ce70));
3384
result = DAG.getNode(ISD::FADD, dl,
3385
MVT::f32, LogOfExponent, Log10ofMantissa);
3388
// No special expansion.
3389
result = DAG.getNode(ISD::FLOG10, dl,
3390
getValue(I.getOperand(1)).getValueType(),
3391
getValue(I.getOperand(1)));
3394
setValue(&I, result);
3397
/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3398
/// limited-precision mode.
3400
SelectionDAGBuilder::visitExp2(CallInst &I) {
3402
DebugLoc dl = getCurDebugLoc();
3404
if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3405
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3406
SDValue Op = getValue(I.getOperand(1));
3408
SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3410
// FractionalPartOfX = x - (float)IntegerPartOfX;
3411
SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3412
SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3414
// IntegerPartOfX <<= 23;
3415
IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3416
DAG.getConstant(23, TLI.getPointerTy()));
3418
if (LimitFloatPrecision <= 6) {
3419
// For floating-point precision of 6:
3421
// TwoToFractionalPartOfX =
3423
// (0.735607626f + 0.252464424f * x) * x;
3425
// error 0.0144103317, which is 6 bits
3426
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3427
getF32Constant(DAG, 0x3e814304));
3428
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3429
getF32Constant(DAG, 0x3f3c50c8));
3430
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3431
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3432
getF32Constant(DAG, 0x3f7f5e7e));
3433
SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3434
SDValue TwoToFractionalPartOfX =
3435
DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3437
result = DAG.getNode(ISD::BIT_CONVERT, dl,
3438
MVT::f32, TwoToFractionalPartOfX);
3439
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3440
// For floating-point precision of 12:
3442
// TwoToFractionalPartOfX =
3445
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
3447
// error 0.000107046256, which is 13 to 14 bits
3448
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3449
getF32Constant(DAG, 0x3da235e3));
3450
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3451
getF32Constant(DAG, 0x3e65b8f3));
3452
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3453
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3454
getF32Constant(DAG, 0x3f324b07));
3455
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3456
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3457
getF32Constant(DAG, 0x3f7ff8fd));
3458
SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3459
SDValue TwoToFractionalPartOfX =
3460
DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3462
result = DAG.getNode(ISD::BIT_CONVERT, dl,
3463
MVT::f32, TwoToFractionalPartOfX);
3464
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3465
// For floating-point precision of 18:
3467
// TwoToFractionalPartOfX =
3471
// (0.554906021e-1f +
3472
// (0.961591928e-2f +
3473
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3474
// error 2.47208000*10^(-7), which is better than 18 bits
3475
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3476
getF32Constant(DAG, 0x3924b03e));
3477
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3478
getF32Constant(DAG, 0x3ab24b87));
3479
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3480
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3481
getF32Constant(DAG, 0x3c1d8c17));
3482
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3483
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3484
getF32Constant(DAG, 0x3d634a1d));
3485
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3486
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3487
getF32Constant(DAG, 0x3e75fe14));
3488
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3489
SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3490
getF32Constant(DAG, 0x3f317234));
3491
SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3492
SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3493
getF32Constant(DAG, 0x3f800000));
3494
SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3495
SDValue TwoToFractionalPartOfX =
3496
DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3498
result = DAG.getNode(ISD::BIT_CONVERT, dl,
3499
MVT::f32, TwoToFractionalPartOfX);
3502
// No special expansion.
3503
result = DAG.getNode(ISD::FEXP2, dl,
3504
getValue(I.getOperand(1)).getValueType(),
3505
getValue(I.getOperand(1)));
3508
setValue(&I, result);
3511
/// visitPow - Lower a pow intrinsic. Handles the special sequences for
3512
/// limited-precision mode with x == 10.0f.
3514
SelectionDAGBuilder::visitPow(CallInst &I) {
3516
Value *Val = I.getOperand(1);
3517
DebugLoc dl = getCurDebugLoc();
3518
bool IsExp10 = false;
3520
if (getValue(Val).getValueType() == MVT::f32 &&
3521
getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3522
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3523
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3524
if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3526
IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3531
if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3532
SDValue Op = getValue(I.getOperand(2));
3534
// Put the exponent in the right bit position for later addition to the
3537
// #define LOG2OF10 3.3219281f
3538
// IntegerPartOfX = (int32_t)(x * LOG2OF10);
3539
SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3540
getF32Constant(DAG, 0x40549a78));
3541
SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3543
// FractionalPartOfX = x - (float)IntegerPartOfX;
3544
SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3545
SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3547
// IntegerPartOfX <<= 23;
3548
IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3549
DAG.getConstant(23, TLI.getPointerTy()));
3551
if (LimitFloatPrecision <= 6) {
3552
// For floating-point precision of 6:
3554
// twoToFractionalPartOfX =
3556
// (0.735607626f + 0.252464424f * x) * x;
3558
// error 0.0144103317, which is 6 bits
3559
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3560
getF32Constant(DAG, 0x3e814304));
3561
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3562
getF32Constant(DAG, 0x3f3c50c8));
3563
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3564
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3565
getF32Constant(DAG, 0x3f7f5e7e));
3566
SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3567
SDValue TwoToFractionalPartOfX =
3568
DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3570
result = DAG.getNode(ISD::BIT_CONVERT, dl,
3571
MVT::f32, TwoToFractionalPartOfX);
3572
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3573
// For floating-point precision of 12:
3575
// TwoToFractionalPartOfX =
3578
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
3580
// error 0.000107046256, which is 13 to 14 bits
3581
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3582
getF32Constant(DAG, 0x3da235e3));
3583
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3584
getF32Constant(DAG, 0x3e65b8f3));
3585
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3586
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3587
getF32Constant(DAG, 0x3f324b07));
3588
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3589
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3590
getF32Constant(DAG, 0x3f7ff8fd));
3591
SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3592
SDValue TwoToFractionalPartOfX =
3593
DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3595
result = DAG.getNode(ISD::BIT_CONVERT, dl,
3596
MVT::f32, TwoToFractionalPartOfX);
3597
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3598
// For floating-point precision of 18:
3600
// TwoToFractionalPartOfX =
3604
// (0.554906021e-1f +
3605
// (0.961591928e-2f +
3606
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3607
// error 2.47208000*10^(-7), which is better than 18 bits
3608
SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3609
getF32Constant(DAG, 0x3924b03e));
3610
SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3611
getF32Constant(DAG, 0x3ab24b87));
3612
SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3613
SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3614
getF32Constant(DAG, 0x3c1d8c17));
3615
SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3616
SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3617
getF32Constant(DAG, 0x3d634a1d));
3618
SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3619
SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3620
getF32Constant(DAG, 0x3e75fe14));
3621
SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3622
SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3623
getF32Constant(DAG, 0x3f317234));
3624
SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3625
SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3626
getF32Constant(DAG, 0x3f800000));
3627
SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3628
SDValue TwoToFractionalPartOfX =
3629
DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3631
result = DAG.getNode(ISD::BIT_CONVERT, dl,
3632
MVT::f32, TwoToFractionalPartOfX);
3635
// No special expansion.
3636
result = DAG.getNode(ISD::FPOW, dl,
3637
getValue(I.getOperand(1)).getValueType(),
3638
getValue(I.getOperand(1)),
3639
getValue(I.getOperand(2)));
3642
setValue(&I, result);
3646
/// ExpandPowI - Expand a llvm.powi intrinsic.
3647
static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3648
SelectionDAG &DAG) {
3649
// If RHS is a constant, we can expand this out to a multiplication tree,
3650
// otherwise we end up lowering to a call to __powidf2 (for example). When
3651
// optimizing for size, we only want to do this if the expansion would produce
3652
// a small number of multiplies, otherwise we do the full expansion.
3653
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3654
// Get the exponent as a positive value.
3655
unsigned Val = RHSC->getSExtValue();
3656
if ((int)Val < 0) Val = -Val;
3658
// powi(x, 0) -> 1.0
3660
return DAG.getConstantFP(1.0, LHS.getValueType());
3662
Function *F = DAG.getMachineFunction().getFunction();
3663
if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3664
// If optimizing for size, don't insert too many multiplies. This
3665
// inserts up to 5 multiplies.
3666
CountPopulation_32(Val)+Log2_32(Val) < 7) {
3667
// We use the simple binary decomposition method to generate the multiply
3668
// sequence. There are more optimal ways to do this (for example,
3669
// powi(x,15) generates one more multiply than it should), but this has
3670
// the benefit of being both really simple and much better than a libcall.
3671
SDValue Res; // Logically starts equal to 1.0
3672
SDValue CurSquare = LHS;
3676
Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3678
Res = CurSquare; // 1.0*CurSquare.
3681
CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3682
CurSquare, CurSquare);
3686
// If the original was negative, invert the result, producing 1/(x*x*x).
3687
if (RHSC->getSExtValue() < 0)
3688
Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3689
DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3694
// Otherwise, expand to a libcall.
3695
return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3699
/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3700
/// we want to emit this as a call to a named external function, return the name
3701
/// otherwise lower it and return null.
3703
SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3704
DebugLoc dl = getCurDebugLoc();
3707
switch (Intrinsic) {
3709
// By default, turn this into a target intrinsic node.
3710
visitTargetIntrinsic(I, Intrinsic);
3712
case Intrinsic::vastart: visitVAStart(I); return 0;
3713
case Intrinsic::vaend: visitVAEnd(I); return 0;
3714
case Intrinsic::vacopy: visitVACopy(I); return 0;
3715
case Intrinsic::returnaddress:
3716
setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3717
getValue(I.getOperand(1))));
3719
case Intrinsic::frameaddress:
3720
setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3721
getValue(I.getOperand(1))));
3723
case Intrinsic::setjmp:
3724
return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3725
case Intrinsic::longjmp:
3726
return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3727
case Intrinsic::memcpy: {
3728
SDValue Op1 = getValue(I.getOperand(1));
3729
SDValue Op2 = getValue(I.getOperand(2));
3730
SDValue Op3 = getValue(I.getOperand(3));
3731
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3732
DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3733
I.getOperand(1), 0, I.getOperand(2), 0));
3736
case Intrinsic::memset: {
3737
SDValue Op1 = getValue(I.getOperand(1));
3738
SDValue Op2 = getValue(I.getOperand(2));
3739
SDValue Op3 = getValue(I.getOperand(3));
3740
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3741
DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3742
I.getOperand(1), 0));
3745
case Intrinsic::memmove: {
3746
SDValue Op1 = getValue(I.getOperand(1));
3747
SDValue Op2 = getValue(I.getOperand(2));
3748
SDValue Op3 = getValue(I.getOperand(3));
3749
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3751
// If the source and destination are known to not be aliases, we can
3752
// lower memmove as memcpy.
3753
uint64_t Size = -1ULL;
3754
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3755
Size = C->getZExtValue();
3756
if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3757
AliasAnalysis::NoAlias) {
3758
DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3759
I.getOperand(1), 0, I.getOperand(2), 0));
3763
DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3764
I.getOperand(1), 0, I.getOperand(2), 0));
3767
case Intrinsic::dbg_declare: {
3768
// FIXME: currently, we get here only if OptLevel != CodeGenOpt::None.
3769
// The real handling of this intrinsic is in FastISel.
3770
if (OptLevel != CodeGenOpt::None)
3771
// FIXME: Variable debug info is not supported here.
3773
DwarfWriter *DW = DAG.getDwarfWriter();
3776
DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3777
if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3780
MDNode *Variable = DI.getVariable();
3781
Value *Address = DI.getAddress();
3784
if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
3785
Address = BCI->getOperand(0);
3786
AllocaInst *AI = dyn_cast<AllocaInst>(Address);
3787
// Don't handle byval struct arguments or VLAs, for example.
3790
DenseMap<const AllocaInst*, int>::iterator SI =
3791
FuncInfo.StaticAllocaMap.find(AI);
3792
if (SI == FuncInfo.StaticAllocaMap.end())
3794
int FI = SI->second;
3796
if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo())
3797
if (MDNode *Dbg = DI.getMetadata("dbg"))
3798
MMI->setVariableDbgInfo(Variable, FI, Dbg);
3801
case Intrinsic::dbg_value: {
3802
// FIXME: currently, we get here only if OptLevel != CodeGenOpt::None.
3803
// The real handling of this intrinsic is in FastISel.
3804
if (OptLevel != CodeGenOpt::None)
3805
// FIXME: Variable debug info is not supported here.
3807
DwarfWriter *DW = DAG.getDwarfWriter();
3810
DbgValueInst &DI = cast<DbgValueInst>(I);
3811
if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3814
MDNode *Variable = DI.getVariable();
3815
Value *V = DI.getValue();
3818
if (BitCastInst *BCI = dyn_cast<BitCastInst>(V))
3819
V = BCI->getOperand(0);
3820
AllocaInst *AI = dyn_cast<AllocaInst>(V);
3821
// Don't handle byval struct arguments or VLAs, for example.
3824
DenseMap<const AllocaInst*, int>::iterator SI =
3825
FuncInfo.StaticAllocaMap.find(AI);
3826
if (SI == FuncInfo.StaticAllocaMap.end())
3828
int FI = SI->second;
3829
if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo())
3830
if (MDNode *Dbg = DI.getMetadata("dbg"))
3831
MMI->setVariableDbgInfo(Variable, FI, Dbg);
3834
case Intrinsic::eh_exception: {
3835
// Insert the EXCEPTIONADDR instruction.
3836
assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3837
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3839
Ops[0] = DAG.getRoot();
3840
SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3842
DAG.setRoot(Op.getValue(1));
3846
case Intrinsic::eh_selector: {
3847
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3849
if (CurMBB->isLandingPad())
3850
AddCatchInfo(I, MMI, CurMBB);
3853
FuncInfo.CatchInfoLost.insert(&I);
3855
// FIXME: Mark exception selector register as live in. Hack for PR1508.
3856
unsigned Reg = TLI.getExceptionSelectorRegister();
3857
if (Reg) CurMBB->addLiveIn(Reg);
3860
// Insert the EHSELECTION instruction.
3861
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3863
Ops[0] = getValue(I.getOperand(1));
3865
SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
3866
DAG.setRoot(Op.getValue(1));
3867
setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
3871
case Intrinsic::eh_typeid_for: {
3872
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3875
// Find the type id for the given typeinfo.
3876
GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3877
unsigned TypeID = MMI->getTypeIDFor(GV);
3878
Res = DAG.getConstant(TypeID, MVT::i32);
3880
// Return something different to eh_selector.
3881
Res = DAG.getConstant(1, MVT::i32);
3888
case Intrinsic::eh_return_i32:
3889
case Intrinsic::eh_return_i64:
3890
if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3891
MMI->setCallsEHReturn(true);
3892
DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
3895
getValue(I.getOperand(1)),
3896
getValue(I.getOperand(2))));
3898
setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3902
case Intrinsic::eh_unwind_init:
3903
if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3904
MMI->setCallsUnwindInit(true);
3907
case Intrinsic::eh_dwarf_cfa: {
3908
EVT VT = getValue(I.getOperand(1)).getValueType();
3909
SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl,
3910
TLI.getPointerTy());
3911
SDValue Offset = DAG.getNode(ISD::ADD, dl,
3913
DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
3914
TLI.getPointerTy()),
3916
SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
3918
DAG.getConstant(0, TLI.getPointerTy()));
3919
setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
3923
case Intrinsic::eh_sjlj_callsite: {
3924
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3925
ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
3926
assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
3927
assert(MMI->getCurrentCallSite() == 0 && "Overlapping call sites!");
3929
MMI->setCurrentCallSite(CI->getZExtValue());
3933
case Intrinsic::convertff:
3934
case Intrinsic::convertfsi:
3935
case Intrinsic::convertfui:
3936
case Intrinsic::convertsif:
3937
case Intrinsic::convertuif:
3938
case Intrinsic::convertss:
3939
case Intrinsic::convertsu:
3940
case Intrinsic::convertus:
3941
case Intrinsic::convertuu: {
3942
ISD::CvtCode Code = ISD::CVT_INVALID;
3943
switch (Intrinsic) {
3944
case Intrinsic::convertff: Code = ISD::CVT_FF; break;
3945
case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
3946
case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
3947
case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
3948
case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
3949
case Intrinsic::convertss: Code = ISD::CVT_SS; break;
3950
case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
3951
case Intrinsic::convertus: Code = ISD::CVT_US; break;
3952
case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
3954
EVT DestVT = TLI.getValueType(I.getType());
3955
Value *Op1 = I.getOperand(1);
3956
Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
3957
DAG.getValueType(DestVT),
3958
DAG.getValueType(getValue(Op1).getValueType()),
3959
getValue(I.getOperand(2)),
3960
getValue(I.getOperand(3)),
3965
case Intrinsic::sqrt:
3966
setValue(&I, DAG.getNode(ISD::FSQRT, dl,
3967
getValue(I.getOperand(1)).getValueType(),
3968
getValue(I.getOperand(1))));
3970
case Intrinsic::powi:
3971
setValue(&I, ExpandPowI(dl, getValue(I.getOperand(1)),
3972
getValue(I.getOperand(2)), DAG));
3974
case Intrinsic::sin:
3975
setValue(&I, DAG.getNode(ISD::FSIN, dl,
3976
getValue(I.getOperand(1)).getValueType(),
3977
getValue(I.getOperand(1))));
3979
case Intrinsic::cos:
3980
setValue(&I, DAG.getNode(ISD::FCOS, dl,
3981
getValue(I.getOperand(1)).getValueType(),
3982
getValue(I.getOperand(1))));
3984
case Intrinsic::log:
3987
case Intrinsic::log2:
3990
case Intrinsic::log10:
3993
case Intrinsic::exp:
3996
case Intrinsic::exp2:
3999
case Intrinsic::pow:
4002
case Intrinsic::pcmarker: {
4003
SDValue Tmp = getValue(I.getOperand(1));
4004
DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4007
case Intrinsic::readcyclecounter: {
4008
SDValue Op = getRoot();
4009
Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4010
DAG.getVTList(MVT::i64, MVT::Other),
4013
DAG.setRoot(Res.getValue(1));
4016
case Intrinsic::bswap:
4017
setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4018
getValue(I.getOperand(1)).getValueType(),
4019
getValue(I.getOperand(1))));
4021
case Intrinsic::cttz: {
4022
SDValue Arg = getValue(I.getOperand(1));
4023
EVT Ty = Arg.getValueType();
4024
setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4027
case Intrinsic::ctlz: {
4028
SDValue Arg = getValue(I.getOperand(1));
4029
EVT Ty = Arg.getValueType();
4030
setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4033
case Intrinsic::ctpop: {
4034
SDValue Arg = getValue(I.getOperand(1));
4035
EVT Ty = Arg.getValueType();
4036
setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4039
case Intrinsic::stacksave: {
4040
SDValue Op = getRoot();
4041
Res = DAG.getNode(ISD::STACKSAVE, dl,
4042
DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4044
DAG.setRoot(Res.getValue(1));
4047
case Intrinsic::stackrestore: {
4048
Res = getValue(I.getOperand(1));
4049
DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4052
case Intrinsic::stackprotector: {
4053
// Emit code into the DAG to store the stack guard onto the stack.
4054
MachineFunction &MF = DAG.getMachineFunction();
4055
MachineFrameInfo *MFI = MF.getFrameInfo();
4056
EVT PtrTy = TLI.getPointerTy();
4058
SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4059
AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4061
int FI = FuncInfo.StaticAllocaMap[Slot];
4062
MFI->setStackProtectorIndex(FI);
4064
SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4066
// Store the stack protector onto the stack.
4067
Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4068
PseudoSourceValue::getFixedStack(FI),
4074
case Intrinsic::objectsize: {
4075
// If we don't know by now, we're never going to know.
4076
ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
4078
assert(CI && "Non-constant type in __builtin_object_size?");
4080
SDValue Arg = getValue(I.getOperand(0));
4081
EVT Ty = Arg.getValueType();
4083
if (CI->getZExtValue() == 0)
4084
Res = DAG.getConstant(-1ULL, Ty);
4086
Res = DAG.getConstant(0, Ty);
4091
case Intrinsic::var_annotation:
4092
// Discard annotate attributes
4095
case Intrinsic::init_trampoline: {
4096
const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4100
Ops[1] = getValue(I.getOperand(1));
4101
Ops[2] = getValue(I.getOperand(2));
4102
Ops[3] = getValue(I.getOperand(3));
4103
Ops[4] = DAG.getSrcValue(I.getOperand(1));
4104
Ops[5] = DAG.getSrcValue(F);
4106
Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4107
DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4111
DAG.setRoot(Res.getValue(1));
4114
case Intrinsic::gcroot:
4116
Value *Alloca = I.getOperand(1);
4117
Constant *TypeMap = cast<Constant>(I.getOperand(2));
4119
FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4120
GFI->addStackRoot(FI->getIndex(), TypeMap);
4123
case Intrinsic::gcread:
4124
case Intrinsic::gcwrite:
4125
llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4127
case Intrinsic::flt_rounds:
4128
setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4130
case Intrinsic::trap:
4131
DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4133
case Intrinsic::uadd_with_overflow:
4134
return implVisitAluOverflow(I, ISD::UADDO);
4135
case Intrinsic::sadd_with_overflow:
4136
return implVisitAluOverflow(I, ISD::SADDO);
4137
case Intrinsic::usub_with_overflow:
4138
return implVisitAluOverflow(I, ISD::USUBO);
4139
case Intrinsic::ssub_with_overflow:
4140
return implVisitAluOverflow(I, ISD::SSUBO);
4141
case Intrinsic::umul_with_overflow:
4142
return implVisitAluOverflow(I, ISD::UMULO);
4143
case Intrinsic::smul_with_overflow:
4144
return implVisitAluOverflow(I, ISD::SMULO);
4146
case Intrinsic::prefetch: {
4149
Ops[1] = getValue(I.getOperand(1));
4150
Ops[2] = getValue(I.getOperand(2));
4151
Ops[3] = getValue(I.getOperand(3));
4152
DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4156
case Intrinsic::memory_barrier: {
4159
for (int x = 1; x < 6; ++x)
4160
Ops[x] = getValue(I.getOperand(x));
4162
DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4165
case Intrinsic::atomic_cmp_swap: {
4166
SDValue Root = getRoot();
4168
DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4169
getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4171
getValue(I.getOperand(1)),
4172
getValue(I.getOperand(2)),
4173
getValue(I.getOperand(3)),
4176
DAG.setRoot(L.getValue(1));
4179
case Intrinsic::atomic_load_add:
4180
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4181
case Intrinsic::atomic_load_sub:
4182
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4183
case Intrinsic::atomic_load_or:
4184
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4185
case Intrinsic::atomic_load_xor:
4186
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4187
case Intrinsic::atomic_load_and:
4188
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4189
case Intrinsic::atomic_load_nand:
4190
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4191
case Intrinsic::atomic_load_max:
4192
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4193
case Intrinsic::atomic_load_min:
4194
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4195
case Intrinsic::atomic_load_umin:
4196
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4197
case Intrinsic::atomic_load_umax:
4198
return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4199
case Intrinsic::atomic_swap:
4200
return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4202
case Intrinsic::invariant_start:
4203
case Intrinsic::lifetime_start:
4204
// Discard region information.
4205
setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4207
case Intrinsic::invariant_end:
4208
case Intrinsic::lifetime_end:
4209
// Discard region information.
4214
/// Test if the given instruction is in a position to be optimized
4215
/// with a tail-call. This roughly means that it's in a block with
4216
/// a return and there's nothing that needs to be scheduled
4217
/// between it and the return.
4219
/// This function only tests target-independent requirements.
4221
isInTailCallPosition(CallSite CS, Attributes CalleeRetAttr,
4222
const TargetLowering &TLI) {
4223
const Instruction *I = CS.getInstruction();
4224
const BasicBlock *ExitBB = I->getParent();
4225
const TerminatorInst *Term = ExitBB->getTerminator();
4226
const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
4227
const Function *F = ExitBB->getParent();
4229
// The block must end in a return statement or unreachable.
4231
// FIXME: Decline tailcall if it's not guaranteed and if the block ends in
4232
// an unreachable, for now. The way tailcall optimization is currently
4233
// implemented means it will add an epilogue followed by a jump. That is
4234
// not profitable. Also, if the callee is a special function (e.g.
4235
// longjmp on x86), it can end up causing miscompilation that has not
4236
// been fully understood.
4238
(!GuaranteedTailCallOpt || !isa<UnreachableInst>(Term))) return false;
4240
// If I will have a chain, make sure no other instruction that will have a
4241
// chain interposes between I and the return.
4242
if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
4243
!I->isSafeToSpeculativelyExecute())
4244
for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
4248
if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() ||
4249
!BBI->isSafeToSpeculativelyExecute())
4253
// If the block ends with a void return or unreachable, it doesn't matter
4254
// what the call's return type is.
4255
if (!Ret || Ret->getNumOperands() == 0) return true;
4257
// If the return value is undef, it doesn't matter what the call's
4259
if (isa<UndefValue>(Ret->getOperand(0))) return true;
4261
// Conservatively require the attributes of the call to match those of
4262
// the return. Ignore noalias because it doesn't affect the call sequence.
4263
unsigned CallerRetAttr = F->getAttributes().getRetAttributes();
4264
if ((CalleeRetAttr ^ CallerRetAttr) & ~Attribute::NoAlias)
4267
// It's not safe to eliminate the sign / zero extension of the return value.
4268
if ((CallerRetAttr & Attribute::ZExt) || (CallerRetAttr & Attribute::SExt))
4271
// Otherwise, make sure the unmodified return value of I is the return value.
4272
for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ;
4273
U = dyn_cast<Instruction>(U->getOperand(0))) {
4276
if (!U->hasOneUse())
4280
// Check for a truly no-op truncate.
4281
if (isa<TruncInst>(U) &&
4282
TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType()))
4284
// Check for a truly no-op bitcast.
4285
if (isa<BitCastInst>(U) &&
4286
(U->getOperand(0)->getType() == U->getType() ||
4287
(U->getOperand(0)->getType()->isPointerTy() &&
4288
U->getType()->isPointerTy())))
4290
// Otherwise it's not a true no-op.
4297
void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee,
4299
MachineBasicBlock *LandingPad) {
4300
const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4301
const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4302
const Type *RetTy = FTy->getReturnType();
4303
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4304
unsigned BeginLabel = 0, EndLabel = 0;
4306
TargetLowering::ArgListTy Args;
4307
TargetLowering::ArgListEntry Entry;
4308
Args.reserve(CS.arg_size());
4310
// Check whether the function can return without sret-demotion.
4311
SmallVector<EVT, 4> OutVTs;
4312
SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
4313
SmallVector<uint64_t, 4> Offsets;
4314
getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4315
OutVTs, OutsFlags, TLI, &Offsets);
4317
bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4318
FTy->isVarArg(), OutVTs, OutsFlags, DAG);
4320
SDValue DemoteStackSlot;
4322
if (!CanLowerReturn) {
4323
uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4324
FTy->getReturnType());
4325
unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4326
FTy->getReturnType());
4327
MachineFunction &MF = DAG.getMachineFunction();
4328
int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4329
const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4331
DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4332
Entry.Node = DemoteStackSlot;
4333
Entry.Ty = StackSlotPtrType;
4334
Entry.isSExt = false;
4335
Entry.isZExt = false;
4336
Entry.isInReg = false;
4337
Entry.isSRet = true;
4338
Entry.isNest = false;
4339
Entry.isByVal = false;
4340
Entry.Alignment = Align;
4341
Args.push_back(Entry);
4342
RetTy = Type::getVoidTy(FTy->getContext());
4345
for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4347
SDValue ArgNode = getValue(*i);
4348
Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4350
unsigned attrInd = i - CS.arg_begin() + 1;
4351
Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4352
Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4353
Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4354
Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4355
Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4356
Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4357
Entry.Alignment = CS.getParamAlignment(attrInd);
4358
Args.push_back(Entry);
4361
if (LandingPad && MMI) {
4362
// Insert a label before the invoke call to mark the try range. This can be
4363
// used to detect deletion of the invoke via the MachineModuleInfo.
4364
BeginLabel = MMI->NextLabelID();
4366
// For SjLj, keep track of which landing pads go with which invokes
4367
// so as to maintain the ordering of pads in the LSDA.
4368
unsigned CallSiteIndex = MMI->getCurrentCallSite();
4369
if (CallSiteIndex) {
4370
MMI->setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4371
// Now that the call site is handled, stop tracking it.
4372
MMI->setCurrentCallSite(0);
4375
// Both PendingLoads and PendingExports must be flushed here;
4376
// this call might not return.
4378
DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4379
getControlRoot(), BeginLabel));
4382
// Check if target-independent constraints permit a tail call here.
4383
// Target-dependent constraints are checked within TLI.LowerCallTo.
4385
!isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4388
std::pair<SDValue,SDValue> Result =
4389
TLI.LowerCallTo(getRoot(), RetTy,
4390
CS.paramHasAttr(0, Attribute::SExt),
4391
CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4392
CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4393
CS.getCallingConv(),
4395
!CS.getInstruction()->use_empty(),
4396
Callee, Args, DAG, getCurDebugLoc());
4397
assert((isTailCall || Result.second.getNode()) &&
4398
"Non-null chain expected with non-tail call!");
4399
assert((Result.second.getNode() || !Result.first.getNode()) &&
4400
"Null value expected with tail call!");
4401
if (Result.first.getNode()) {
4402
setValue(CS.getInstruction(), Result.first);
4403
} else if (!CanLowerReturn && Result.second.getNode()) {
4404
// The instruction result is the result of loading from the
4405
// hidden sret parameter.
4406
SmallVector<EVT, 1> PVTs;
4407
const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4409
ComputeValueVTs(TLI, PtrRetTy, PVTs);
4410
assert(PVTs.size() == 1 && "Pointers should fit in one register");
4411
EVT PtrVT = PVTs[0];
4412
unsigned NumValues = OutVTs.size();
4413
SmallVector<SDValue, 4> Values(NumValues);
4414
SmallVector<SDValue, 4> Chains(NumValues);
4416
for (unsigned i = 0; i < NumValues; ++i) {
4417
SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4419
DAG.getConstant(Offsets[i], PtrVT));
4420
SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
4421
Add, NULL, Offsets[i], false, false, 1);
4423
Chains[i] = L.getValue(1);
4426
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4427
MVT::Other, &Chains[0], NumValues);
4428
PendingLoads.push_back(Chain);
4430
// Collect the legal value parts into potentially illegal values
4431
// that correspond to the original function's return values.
4432
SmallVector<EVT, 4> RetTys;
4433
RetTy = FTy->getReturnType();
4434
ComputeValueVTs(TLI, RetTy, RetTys);
4435
ISD::NodeType AssertOp = ISD::DELETED_NODE;
4436
SmallVector<SDValue, 4> ReturnValues;
4437
unsigned CurReg = 0;
4438
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4440
EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4441
unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4443
SDValue ReturnValue =
4444
getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4445
RegisterVT, VT, AssertOp);
4446
ReturnValues.push_back(ReturnValue);
4450
setValue(CS.getInstruction(),
4451
DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4452
DAG.getVTList(&RetTys[0], RetTys.size()),
4453
&ReturnValues[0], ReturnValues.size()));
4457
// As a special case, a null chain means that a tail call has been emitted and
4458
// the DAG root is already updated.
4459
if (Result.second.getNode())
4460
DAG.setRoot(Result.second);
4464
if (LandingPad && MMI) {
4465
// Insert a label at the end of the invoke call to mark the try range. This
4466
// can be used to detect deletion of the invoke via the MachineModuleInfo.
4467
EndLabel = MMI->NextLabelID();
4468
DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4469
getRoot(), EndLabel));
4471
// Inform MachineModuleInfo of range.
4472
MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4476
/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4477
/// value is equal or not-equal to zero.
4478
static bool IsOnlyUsedInZeroEqualityComparison(Value *V) {
4479
for (Value::use_iterator UI = V->use_begin(), E = V->use_end();
4481
if (ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4482
if (IC->isEquality())
4483
if (Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4484
if (C->isNullValue())
4486
// Unknown instruction.
4492
static SDValue getMemCmpLoad(Value *PtrVal, MVT LoadVT, const Type *LoadTy,
4493
SelectionDAGBuilder &Builder) {
4495
// Check to see if this load can be trivially constant folded, e.g. if the
4496
// input is from a string literal.
4497
if (Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4498
// Cast pointer to the type we really want to load.
4499
LoadInput = ConstantExpr::getBitCast(LoadInput,
4500
PointerType::getUnqual(LoadTy));
4502
if (Constant *LoadCst = ConstantFoldLoadFromConstPtr(LoadInput, Builder.TD))
4503
return Builder.getValue(LoadCst);
4506
// Otherwise, we have to emit the load. If the pointer is to unfoldable but
4507
// still constant memory, the input chain can be the entry node.
4509
bool ConstantMemory = false;
4511
// Do not serialize (non-volatile) loads of constant memory with anything.
4512
if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4513
Root = Builder.DAG.getEntryNode();
4514
ConstantMemory = true;
4516
// Do not serialize non-volatile loads against each other.
4517
Root = Builder.DAG.getRoot();
4520
SDValue Ptr = Builder.getValue(PtrVal);
4521
SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4522
Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/,
4524
false /*nontemporal*/, 1 /* align=1 */);
4526
if (!ConstantMemory)
4527
Builder.PendingLoads.push_back(LoadVal.getValue(1));
4532
/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4533
/// If so, return true and lower it, otherwise return false and it will be
4534
/// lowered like a normal call.
4535
bool SelectionDAGBuilder::visitMemCmpCall(CallInst &I) {
4536
// Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4537
if (I.getNumOperands() != 4)
4540
Value *LHS = I.getOperand(1), *RHS = I.getOperand(2);
4541
if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
4542
!I.getOperand(3)->getType()->isIntegerTy() ||
4543
!I.getType()->isIntegerTy())
4546
ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3));
4548
// memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4549
// memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4550
if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4551
bool ActuallyDoIt = true;
4554
switch (Size->getZExtValue()) {
4556
LoadVT = MVT::Other;
4558
ActuallyDoIt = false;
4562
LoadTy = Type::getInt16Ty(Size->getContext());
4566
LoadTy = Type::getInt32Ty(Size->getContext());
4570
LoadTy = Type::getInt64Ty(Size->getContext());
4574
LoadVT = MVT::v4i32;
4575
LoadTy = Type::getInt32Ty(Size->getContext());
4576
LoadTy = VectorType::get(LoadTy, 4);
4581
// This turns into unaligned loads. We only do this if the target natively
4582
// supports the MVT we'll be loading or if it is small enough (<= 4) that
4583
// we'll only produce a small number of byte loads.
4585
// Require that we can find a legal MVT, and only do this if the target
4586
// supports unaligned loads of that type. Expanding into byte loads would
4588
if (ActuallyDoIt && Size->getZExtValue() > 4) {
4589
// TODO: Handle 5 byte compare as 4-byte + 1 byte.
4590
// TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
4591
if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
4592
ActuallyDoIt = false;
4596
SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
4597
SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
4599
SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
4601
EVT CallVT = TLI.getValueType(I.getType(), true);
4602
setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
4612
void SelectionDAGBuilder::visitCall(CallInst &I) {
4613
const char *RenameFn = 0;
4614
if (Function *F = I.getCalledFunction()) {
4615
if (F->isDeclaration()) {
4616
const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4618
if (unsigned IID = II->getIntrinsicID(F)) {
4619
RenameFn = visitIntrinsicCall(I, IID);
4624
if (unsigned IID = F->getIntrinsicID()) {
4625
RenameFn = visitIntrinsicCall(I, IID);
4631
// Check for well-known libc/libm calls. If the function is internal, it
4632
// can't be a library call.
4633
if (!F->hasLocalLinkage() && F->hasName()) {
4634
StringRef Name = F->getName();
4635
if (Name == "copysign" || Name == "copysignf") {
4636
if (I.getNumOperands() == 3 && // Basic sanity checks.
4637
I.getOperand(1)->getType()->isFloatingPointTy() &&
4638
I.getType() == I.getOperand(1)->getType() &&
4639
I.getType() == I.getOperand(2)->getType()) {
4640
SDValue LHS = getValue(I.getOperand(1));
4641
SDValue RHS = getValue(I.getOperand(2));
4642
setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4643
LHS.getValueType(), LHS, RHS));
4646
} else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4647
if (I.getNumOperands() == 2 && // Basic sanity checks.
4648
I.getOperand(1)->getType()->isFloatingPointTy() &&
4649
I.getType() == I.getOperand(1)->getType()) {
4650
SDValue Tmp = getValue(I.getOperand(1));
4651
setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4652
Tmp.getValueType(), Tmp));
4655
} else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4656
if (I.getNumOperands() == 2 && // Basic sanity checks.
4657
I.getOperand(1)->getType()->isFloatingPointTy() &&
4658
I.getType() == I.getOperand(1)->getType() &&
4659
I.onlyReadsMemory()) {
4660
SDValue Tmp = getValue(I.getOperand(1));
4661
setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4662
Tmp.getValueType(), Tmp));
4665
} else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4666
if (I.getNumOperands() == 2 && // Basic sanity checks.
4667
I.getOperand(1)->getType()->isFloatingPointTy() &&
4668
I.getType() == I.getOperand(1)->getType() &&
4669
I.onlyReadsMemory()) {
4670
SDValue Tmp = getValue(I.getOperand(1));
4671
setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4672
Tmp.getValueType(), Tmp));
4675
} else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
4676
if (I.getNumOperands() == 2 && // Basic sanity checks.
4677
I.getOperand(1)->getType()->isFloatingPointTy() &&
4678
I.getType() == I.getOperand(1)->getType() &&
4679
I.onlyReadsMemory()) {
4680
SDValue Tmp = getValue(I.getOperand(1));
4681
setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
4682
Tmp.getValueType(), Tmp));
4685
} else if (Name == "memcmp") {
4686
if (visitMemCmpCall(I))
4690
} else if (isa<InlineAsm>(I.getOperand(0))) {
4697
Callee = getValue(I.getOperand(0));
4699
Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4701
// Check if we can potentially perform a tail call. More detailed checking is
4702
// be done within LowerCallTo, after more information about the call is known.
4703
LowerCallTo(&I, Callee, I.isTailCall());
4706
/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4707
/// this value and returns the result as a ValueVT value. This uses
4708
/// Chain/Flag as the input and updates them for the output Chain/Flag.
4709
/// If the Flag pointer is NULL, no flag is used.
4710
SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4711
SDValue &Chain, SDValue *Flag) const {
4712
// Assemble the legal parts into the final values.
4713
SmallVector<SDValue, 4> Values(ValueVTs.size());
4714
SmallVector<SDValue, 8> Parts;
4715
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4716
// Copy the legal parts from the registers.
4717
EVT ValueVT = ValueVTs[Value];
4718
unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4719
EVT RegisterVT = RegVTs[Value];
4721
Parts.resize(NumRegs);
4722
for (unsigned i = 0; i != NumRegs; ++i) {
4725
P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4727
P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4728
*Flag = P.getValue(2);
4731
Chain = P.getValue(1);
4733
// If the source register was virtual and if we know something about it,
4734
// add an assert node.
4735
if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4736
RegisterVT.isInteger() && !RegisterVT.isVector()) {
4737
unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4738
FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4739
if (FLI.LiveOutRegInfo.size() > SlotNo) {
4740
FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4742
unsigned RegSize = RegisterVT.getSizeInBits();
4743
unsigned NumSignBits = LOI.NumSignBits;
4744
unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4746
// FIXME: We capture more information than the dag can represent. For
4747
// now, just use the tightest assertzext/assertsext possible.
4749
EVT FromVT(MVT::Other);
4750
if (NumSignBits == RegSize)
4751
isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4752
else if (NumZeroBits >= RegSize-1)
4753
isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4754
else if (NumSignBits > RegSize-8)
4755
isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4756
else if (NumZeroBits >= RegSize-8)
4757
isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4758
else if (NumSignBits > RegSize-16)
4759
isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4760
else if (NumZeroBits >= RegSize-16)
4761
isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4762
else if (NumSignBits > RegSize-32)
4763
isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4764
else if (NumZeroBits >= RegSize-32)
4765
isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4767
if (FromVT != MVT::Other)
4768
P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4769
RegisterVT, P, DAG.getValueType(FromVT));
4776
Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4777
NumRegs, RegisterVT, ValueVT);
4782
return DAG.getNode(ISD::MERGE_VALUES, dl,
4783
DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4784
&Values[0], ValueVTs.size());
4787
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4788
/// specified value into the registers specified by this object. This uses
4789
/// Chain/Flag as the input and updates them for the output Chain/Flag.
4790
/// If the Flag pointer is NULL, no flag is used.
4791
void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4792
SDValue &Chain, SDValue *Flag) const {
4793
// Get the list of the values's legal parts.
4794
unsigned NumRegs = Regs.size();
4795
SmallVector<SDValue, 8> Parts(NumRegs);
4796
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4797
EVT ValueVT = ValueVTs[Value];
4798
unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4799
EVT RegisterVT = RegVTs[Value];
4801
getCopyToParts(DAG, dl,
4802
Val.getValue(Val.getResNo() + Value),
4803
&Parts[Part], NumParts, RegisterVT);
4807
// Copy the parts into the registers.
4808
SmallVector<SDValue, 8> Chains(NumRegs);
4809
for (unsigned i = 0; i != NumRegs; ++i) {
4812
Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4814
Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4815
*Flag = Part.getValue(1);
4818
Chains[i] = Part.getValue(0);
4821
if (NumRegs == 1 || Flag)
4822
// If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4823
// flagged to it. That is the CopyToReg nodes and the user are considered
4824
// a single scheduling unit. If we create a TokenFactor and return it as
4825
// chain, then the TokenFactor is both a predecessor (operand) of the
4826
// user as well as a successor (the TF operands are flagged to the user).
4827
// c1, f1 = CopyToReg
4828
// c2, f2 = CopyToReg
4829
// c3 = TokenFactor c1, c2
4832
Chain = Chains[NumRegs-1];
4834
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4837
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
4838
/// operand list. This adds the code marker and includes the number of
4839
/// values added into it.
4840
void RegsForValue::AddInlineAsmOperands(unsigned Code,
4841
bool HasMatching,unsigned MatchingIdx,
4843
std::vector<SDValue> &Ops) const {
4844
assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4845
unsigned Flag = Code | (Regs.size() << 3);
4847
Flag |= 0x80000000 | (MatchingIdx << 16);
4848
SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
4851
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4852
unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
4853
EVT RegisterVT = RegVTs[Value];
4854
for (unsigned i = 0; i != NumRegs; ++i) {
4855
assert(Reg < Regs.size() && "Mismatch in # registers expected");
4856
Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4861
/// isAllocatableRegister - If the specified register is safe to allocate,
4862
/// i.e. it isn't a stack pointer or some other special register, return the
4863
/// register class for the register. Otherwise, return null.
4864
static const TargetRegisterClass *
4865
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4866
const TargetLowering &TLI,
4867
const TargetRegisterInfo *TRI) {
4868
EVT FoundVT = MVT::Other;
4869
const TargetRegisterClass *FoundRC = 0;
4870
for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4871
E = TRI->regclass_end(); RCI != E; ++RCI) {
4872
EVT ThisVT = MVT::Other;
4874
const TargetRegisterClass *RC = *RCI;
4875
// If none of the value types for this register class are valid, we
4876
// can't use it. For example, 64-bit reg classes on 32-bit targets.
4877
for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4879
if (TLI.isTypeLegal(*I)) {
4880
// If we have already found this register in a different register class,
4881
// choose the one with the largest VT specified. For example, on
4882
// PowerPC, we favor f64 register classes over f32.
4883
if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4890
if (ThisVT == MVT::Other) continue;
4892
// NOTE: This isn't ideal. In particular, this might allocate the
4893
// frame pointer in functions that need it (due to them not being taken
4894
// out of allocation, because a variable sized allocation hasn't been seen
4895
// yet). This is a slight code pessimization, but should still work.
4896
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4897
E = RC->allocation_order_end(MF); I != E; ++I)
4899
// We found a matching register class. Keep looking at others in case
4900
// we find one with larger registers that this physreg is also in.
4911
/// AsmOperandInfo - This contains information for each constraint that we are
4913
class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4914
public TargetLowering::AsmOperandInfo {
4916
/// CallOperand - If this is the result output operand or a clobber
4917
/// this is null, otherwise it is the incoming operand to the CallInst.
4918
/// This gets modified as the asm is processed.
4919
SDValue CallOperand;
4921
/// AssignedRegs - If this is a register or register class operand, this
4922
/// contains the set of register corresponding to the operand.
4923
RegsForValue AssignedRegs;
4925
explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4926
: TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4929
/// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4930
/// busy in OutputRegs/InputRegs.
4931
void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4932
std::set<unsigned> &OutputRegs,
4933
std::set<unsigned> &InputRegs,
4934
const TargetRegisterInfo &TRI) const {
4936
for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4937
MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4940
for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4941
MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4945
/// getCallOperandValEVT - Return the EVT of the Value* that this operand
4946
/// corresponds to. If there is no Value* for this operand, it returns
4948
EVT getCallOperandValEVT(LLVMContext &Context,
4949
const TargetLowering &TLI,
4950
const TargetData *TD) const {
4951
if (CallOperandVal == 0) return MVT::Other;
4953
if (isa<BasicBlock>(CallOperandVal))
4954
return TLI.getPointerTy();
4956
const llvm::Type *OpTy = CallOperandVal->getType();
4958
// If this is an indirect operand, the operand is a pointer to the
4961
const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
4963
llvm_report_error("Indirect operand for inline asm not a pointer!");
4964
OpTy = PtrTy->getElementType();
4967
// If OpTy is not a single value, it may be a struct/union that we
4968
// can tile with integers.
4969
if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4970
unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4979
OpTy = IntegerType::get(Context, BitSize);
4984
return TLI.getValueType(OpTy, true);
4988
/// MarkRegAndAliases - Mark the specified register and all aliases in the
4990
static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4991
const TargetRegisterInfo &TRI) {
4992
assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4994
if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4995
for (; *Aliases; ++Aliases)
4996
Regs.insert(*Aliases);
4999
} // end llvm namespace.
5002
/// GetRegistersForValue - Assign registers (virtual or physical) for the
5003
/// specified operand. We prefer to assign virtual registers, to allow the
5004
/// register allocator to handle the assignment process. However, if the asm
5005
/// uses features that we can't model on machineinstrs, we have SDISel do the
5006
/// allocation. This produces generally horrible, but correct, code.
5008
/// OpInfo describes the operand.
5009
/// Input and OutputRegs are the set of already allocated physical registers.
5011
void SelectionDAGBuilder::
5012
GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5013
std::set<unsigned> &OutputRegs,
5014
std::set<unsigned> &InputRegs) {
5015
LLVMContext &Context = FuncInfo.Fn->getContext();
5017
// Compute whether this value requires an input register, an output register,
5019
bool isOutReg = false;
5020
bool isInReg = false;
5021
switch (OpInfo.Type) {
5022
case InlineAsm::isOutput:
5025
// If there is an input constraint that matches this, we need to reserve
5026
// the input register so no other inputs allocate to it.
5027
isInReg = OpInfo.hasMatchingInput();
5029
case InlineAsm::isInput:
5033
case InlineAsm::isClobber:
5040
MachineFunction &MF = DAG.getMachineFunction();
5041
SmallVector<unsigned, 4> Regs;
5043
// If this is a constraint for a single physreg, or a constraint for a
5044
// register class, find it.
5045
std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5046
TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5047
OpInfo.ConstraintVT);
5049
unsigned NumRegs = 1;
5050
if (OpInfo.ConstraintVT != MVT::Other) {
5051
// If this is a FP input in an integer register (or visa versa) insert a bit
5052
// cast of the input value. More generally, handle any case where the input
5053
// value disagrees with the register class we plan to stick this in.
5054
if (OpInfo.Type == InlineAsm::isInput &&
5055
PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5056
// Try to convert to the first EVT that the reg class contains. If the
5057
// types are identical size, use a bitcast to convert (e.g. two differing
5059
EVT RegVT = *PhysReg.second->vt_begin();
5060
if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5061
OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5062
RegVT, OpInfo.CallOperand);
5063
OpInfo.ConstraintVT = RegVT;
5064
} else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5065
// If the input is a FP value and we want it in FP registers, do a
5066
// bitcast to the corresponding integer type. This turns an f64 value
5067
// into i64, which can be passed with two i32 values on a 32-bit
5069
RegVT = EVT::getIntegerVT(Context,
5070
OpInfo.ConstraintVT.getSizeInBits());
5071
OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5072
RegVT, OpInfo.CallOperand);
5073
OpInfo.ConstraintVT = RegVT;
5077
NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5081
EVT ValueVT = OpInfo.ConstraintVT;
5083
// If this is a constraint for a specific physical register, like {r17},
5085
if (unsigned AssignedReg = PhysReg.first) {
5086
const TargetRegisterClass *RC = PhysReg.second;
5087
if (OpInfo.ConstraintVT == MVT::Other)
5088
ValueVT = *RC->vt_begin();
5090
// Get the actual register value type. This is important, because the user
5091
// may have asked for (e.g.) the AX register in i32 type. We need to
5092
// remember that AX is actually i16 to get the right extension.
5093
RegVT = *RC->vt_begin();
5095
// This is a explicit reference to a physical register.
5096
Regs.push_back(AssignedReg);
5098
// If this is an expanded reference, add the rest of the regs to Regs.
5100
TargetRegisterClass::iterator I = RC->begin();
5101
for (; *I != AssignedReg; ++I)
5102
assert(I != RC->end() && "Didn't find reg!");
5104
// Already added the first reg.
5106
for (; NumRegs; --NumRegs, ++I) {
5107
assert(I != RC->end() && "Ran out of registers to allocate!");
5112
OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5113
const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5114
OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5118
// Otherwise, if this was a reference to an LLVM register class, create vregs
5119
// for this reference.
5120
if (const TargetRegisterClass *RC = PhysReg.second) {
5121
RegVT = *RC->vt_begin();
5122
if (OpInfo.ConstraintVT == MVT::Other)
5125
// Create the appropriate number of virtual registers.
5126
MachineRegisterInfo &RegInfo = MF.getRegInfo();
5127
for (; NumRegs; --NumRegs)
5128
Regs.push_back(RegInfo.createVirtualRegister(RC));
5130
OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5134
// This is a reference to a register class that doesn't directly correspond
5135
// to an LLVM register class. Allocate NumRegs consecutive, available,
5136
// registers from the class.
5137
std::vector<unsigned> RegClassRegs
5138
= TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5139
OpInfo.ConstraintVT);
5141
const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5142
unsigned NumAllocated = 0;
5143
for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5144
unsigned Reg = RegClassRegs[i];
5145
// See if this register is available.
5146
if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5147
(isInReg && InputRegs.count(Reg))) { // Already used.
5148
// Make sure we find consecutive registers.
5153
// Check to see if this register is allocatable (i.e. don't give out the
5155
const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5156
if (!RC) { // Couldn't allocate this register.
5157
// Reset NumAllocated to make sure we return consecutive registers.
5162
// Okay, this register is good, we can use it.
5165
// If we allocated enough consecutive registers, succeed.
5166
if (NumAllocated == NumRegs) {
5167
unsigned RegStart = (i-NumAllocated)+1;
5168
unsigned RegEnd = i+1;
5169
// Mark all of the allocated registers used.
5170
for (unsigned i = RegStart; i != RegEnd; ++i)
5171
Regs.push_back(RegClassRegs[i]);
5173
OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5174
OpInfo.ConstraintVT);
5175
OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5180
// Otherwise, we couldn't allocate enough registers for this.
5183
/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5184
/// processed uses a memory 'm' constraint.
5186
hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5187
const TargetLowering &TLI) {
5188
for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5189
InlineAsm::ConstraintInfo &CI = CInfos[i];
5190
for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5191
TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5192
if (CType == TargetLowering::C_Memory)
5196
// Indirect operand accesses access memory.
5204
/// visitInlineAsm - Handle a call to an InlineAsm object.
5206
void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
5207
InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5209
/// ConstraintOperands - Information about all of the constraints.
5210
std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5212
std::set<unsigned> OutputRegs, InputRegs;
5214
// Do a prepass over the constraints, canonicalizing them, and building up the
5215
// ConstraintOperands list.
5216
std::vector<InlineAsm::ConstraintInfo>
5217
ConstraintInfos = IA->ParseConstraints();
5219
bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5221
SDValue Chain, Flag;
5223
// We won't need to flush pending loads if this asm doesn't touch
5224
// memory and is nonvolatile.
5225
if (hasMemory || IA->hasSideEffects())
5228
Chain = DAG.getRoot();
5230
unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5231
unsigned ResNo = 0; // ResNo - The result number of the next output.
5232
for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5233
ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5234
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5236
EVT OpVT = MVT::Other;
5238
// Compute the value type for each operand.
5239
switch (OpInfo.Type) {
5240
case InlineAsm::isOutput:
5241
// Indirect outputs just consume an argument.
5242
if (OpInfo.isIndirect) {
5243
OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5247
// The return value of the call is this value. As such, there is no
5248
// corresponding argument.
5249
assert(!CS.getType()->isVoidTy() &&
5251
if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5252
OpVT = TLI.getValueType(STy->getElementType(ResNo));
5254
assert(ResNo == 0 && "Asm only has one result!");
5255
OpVT = TLI.getValueType(CS.getType());
5259
case InlineAsm::isInput:
5260
OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5262
case InlineAsm::isClobber:
5267
// If this is an input or an indirect output, process the call argument.
5268
// BasicBlocks are labels, currently appearing only in asm's.
5269
if (OpInfo.CallOperandVal) {
5270
// Strip bitcasts, if any. This mostly comes up for functions.
5271
OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5273
if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5274
OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5276
OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5279
OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5282
OpInfo.ConstraintVT = OpVT;
5285
// Second pass over the constraints: compute which constraint option to use
5286
// and assign registers to constraints that want a specific physreg.
5287
for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5288
SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5290
// If this is an output operand with a matching input operand, look up the
5291
// matching input. If their types mismatch, e.g. one is an integer, the
5292
// other is floating point, or their sizes are different, flag it as an
5294
if (OpInfo.hasMatchingInput()) {
5295
SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5296
if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5297
if ((OpInfo.ConstraintVT.isInteger() !=
5298
Input.ConstraintVT.isInteger()) ||
5299
(OpInfo.ConstraintVT.getSizeInBits() !=
5300
Input.ConstraintVT.getSizeInBits())) {
5301
llvm_report_error("Unsupported asm: input constraint"
5302
" with a matching output constraint of incompatible"
5305
Input.ConstraintVT = OpInfo.ConstraintVT;
5309
// Compute the constraint code and ConstraintType to use.
5310
TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5312
// If this is a memory input, and if the operand is not indirect, do what we
5313
// need to to provide an address for the memory input.
5314
if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5315
!OpInfo.isIndirect) {
5316
assert(OpInfo.Type == InlineAsm::isInput &&
5317
"Can only indirectify direct input operands!");
5319
// Memory operands really want the address of the value. If we don't have
5320
// an indirect input, put it in the constpool if we can, otherwise spill
5321
// it to a stack slot.
5323
// If the operand is a float, integer, or vector constant, spill to a
5324
// constant pool entry to get its address.
5325
Value *OpVal = OpInfo.CallOperandVal;
5326
if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5327
isa<ConstantVector>(OpVal)) {
5328
OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5329
TLI.getPointerTy());
5331
// Otherwise, create a stack slot and emit a store to it before the
5333
const Type *Ty = OpVal->getType();
5334
uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5335
unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5336
MachineFunction &MF = DAG.getMachineFunction();
5337
int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5338
SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5339
Chain = DAG.getStore(Chain, getCurDebugLoc(),
5340
OpInfo.CallOperand, StackSlot, NULL, 0,
5342
OpInfo.CallOperand = StackSlot;
5345
// There is no longer a Value* corresponding to this operand.
5346
OpInfo.CallOperandVal = 0;
5348
// It is now an indirect operand.
5349
OpInfo.isIndirect = true;
5352
// If this constraint is for a specific register, allocate it before
5354
if (OpInfo.ConstraintType == TargetLowering::C_Register)
5355
GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5358
ConstraintInfos.clear();
5360
// Second pass - Loop over all of the operands, assigning virtual or physregs
5361
// to register class operands.
5362
for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5363
SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5365
// C_Register operands have already been allocated, Other/Memory don't need
5367
if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5368
GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5371
// AsmNodeOperands - The operands for the ISD::INLINEASM node.
5372
std::vector<SDValue> AsmNodeOperands;
5373
AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5374
AsmNodeOperands.push_back(
5375
DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5376
TLI.getPointerTy()));
5379
// Loop over all of the inputs, copying the operand values into the
5380
// appropriate registers and processing the output regs.
5381
RegsForValue RetValRegs;
5383
// IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5384
std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5386
for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5387
SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5389
switch (OpInfo.Type) {
5390
case InlineAsm::isOutput: {
5391
if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5392
OpInfo.ConstraintType != TargetLowering::C_Register) {
5393
// Memory output, or 'other' output (e.g. 'X' constraint).
5394
assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5396
// Add information to the INLINEASM node to know about this output.
5397
unsigned ResOpType = 4/*MEM*/ | (1<<3);
5398
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5399
TLI.getPointerTy()));
5400
AsmNodeOperands.push_back(OpInfo.CallOperand);
5404
// Otherwise, this is a register or register class output.
5406
// Copy the output from the appropriate register. Find a register that
5408
if (OpInfo.AssignedRegs.Regs.empty()) {
5409
llvm_report_error("Couldn't allocate output reg for"
5410
" constraint '" + OpInfo.ConstraintCode + "'!");
5413
// If this is an indirect operand, store through the pointer after the
5415
if (OpInfo.isIndirect) {
5416
IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5417
OpInfo.CallOperandVal));
5419
// This is the result value of the call.
5420
assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5421
// Concatenate this output onto the outputs list.
5422
RetValRegs.append(OpInfo.AssignedRegs);
5425
// Add information to the INLINEASM node to know that this register is
5427
OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5428
6 /* EARLYCLOBBER REGDEF */ :
5436
case InlineAsm::isInput: {
5437
SDValue InOperandVal = OpInfo.CallOperand;
5439
if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5440
// If this is required to match an output register we have already set,
5441
// just use its register.
5442
unsigned OperandNo = OpInfo.getMatchedOperand();
5444
// Scan until we find the definition we already emitted of this operand.
5445
// When we find it, create a RegsForValue operand.
5446
unsigned CurOp = 2; // The first operand.
5447
for (; OperandNo; --OperandNo) {
5448
// Advance to the next operand.
5450
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5451
assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5452
(OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5453
(OpFlag & 7) == 4 /*MEM*/) &&
5454
"Skipped past definitions?");
5455
CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5459
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5460
if ((OpFlag & 7) == 2 /*REGDEF*/
5461
|| (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5462
// Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5463
if (OpInfo.isIndirect) {
5464
llvm_report_error("Don't know how to handle tied indirect "
5465
"register inputs yet!");
5467
RegsForValue MatchedRegs;
5468
MatchedRegs.TLI = &TLI;
5469
MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5470
EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5471
MatchedRegs.RegVTs.push_back(RegVT);
5472
MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5473
for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5475
MatchedRegs.Regs.push_back
5476
(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5478
// Use the produced MatchedRegs object to
5479
MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5481
MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5482
true, OpInfo.getMatchedOperand(),
5483
DAG, AsmNodeOperands);
5486
assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5487
assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5488
"Unexpected number of operands");
5489
// Add information to the INLINEASM node to know about this input.
5490
// See InlineAsm.h isUseOperandTiedToDef.
5491
OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5492
AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5493
TLI.getPointerTy()));
5494
AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5499
if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5500
assert(!OpInfo.isIndirect &&
5501
"Don't know how to handle indirect other inputs yet!");
5503
std::vector<SDValue> Ops;
5504
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5505
hasMemory, Ops, DAG);
5507
llvm_report_error("Invalid operand for inline asm"
5508
" constraint '" + OpInfo.ConstraintCode + "'!");
5511
// Add information to the INLINEASM node to know about this input.
5512
unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5513
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5514
TLI.getPointerTy()));
5515
AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5517
} else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5518
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5519
assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5520
"Memory operands expect pointer values");
5522
// Add information to the INLINEASM node to know about this input.
5523
unsigned ResOpType = 4/*MEM*/ | (1<<3);
5524
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5525
TLI.getPointerTy()));
5526
AsmNodeOperands.push_back(InOperandVal);
5530
assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5531
OpInfo.ConstraintType == TargetLowering::C_Register) &&
5532
"Unknown constraint type!");
5533
assert(!OpInfo.isIndirect &&
5534
"Don't know how to handle indirect register inputs yet!");
5536
// Copy the input into the appropriate registers.
5537
if (OpInfo.AssignedRegs.Regs.empty() ||
5538
!OpInfo.AssignedRegs.areValueTypesLegal()) {
5539
llvm_report_error("Couldn't allocate input reg for"
5540
" constraint '"+ OpInfo.ConstraintCode +"'!");
5543
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5546
OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5547
DAG, AsmNodeOperands);
5550
case InlineAsm::isClobber: {
5551
// Add the clobbered value to the operand list, so that the register
5552
// allocator is aware that the physreg got clobbered.
5553
if (!OpInfo.AssignedRegs.Regs.empty())
5554
OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5562
// Finish up input operands.
5563
AsmNodeOperands[0] = Chain;
5564
if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5566
Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5567
DAG.getVTList(MVT::Other, MVT::Flag),
5568
&AsmNodeOperands[0], AsmNodeOperands.size());
5569
Flag = Chain.getValue(1);
5571
// If this asm returns a register value, copy the result from that register
5572
// and set it as the value of the call.
5573
if (!RetValRegs.Regs.empty()) {
5574
SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5577
// FIXME: Why don't we do this for inline asms with MRVs?
5578
if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5579
EVT ResultType = TLI.getValueType(CS.getType());
5581
// If any of the results of the inline asm is a vector, it may have the
5582
// wrong width/num elts. This can happen for register classes that can
5583
// contain multiple different value types. The preg or vreg allocated may
5584
// not have the same VT as was expected. Convert it to the right type
5585
// with bit_convert.
5586
if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5587
Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5590
} else if (ResultType != Val.getValueType() &&
5591
ResultType.isInteger() && Val.getValueType().isInteger()) {
5592
// If a result value was tied to an input value, the computed result may
5593
// have a wider width than the expected result. Extract the relevant
5595
Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5598
assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5601
setValue(CS.getInstruction(), Val);
5602
// Don't need to use this as a chain in this case.
5603
if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5607
std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5609
// Process indirect outputs, first output all of the flagged copies out of
5611
for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5612
RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5613
Value *Ptr = IndirectStoresToEmit[i].second;
5614
SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5616
StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5620
// Emit the non-flagged stores from the physregs.
5621
SmallVector<SDValue, 8> OutChains;
5622
for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5623
SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5624
StoresToEmit[i].first,
5625
getValue(StoresToEmit[i].second),
5626
StoresToEmit[i].second, 0,
5628
OutChains.push_back(Val);
5631
if (!OutChains.empty())
5632
Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5633
&OutChains[0], OutChains.size());
5638
void SelectionDAGBuilder::visitVAStart(CallInst &I) {
5639
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5640
MVT::Other, getRoot(),
5641
getValue(I.getOperand(1)),
5642
DAG.getSrcValue(I.getOperand(1))));
5645
void SelectionDAGBuilder::visitVAArg(VAArgInst &I) {
5646
SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5647
getRoot(), getValue(I.getOperand(0)),
5648
DAG.getSrcValue(I.getOperand(0)));
5650
DAG.setRoot(V.getValue(1));
5653
void SelectionDAGBuilder::visitVAEnd(CallInst &I) {
5654
DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5655
MVT::Other, getRoot(),
5656
getValue(I.getOperand(1)),
5657
DAG.getSrcValue(I.getOperand(1))));
5660
void SelectionDAGBuilder::visitVACopy(CallInst &I) {
5661
DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5662
MVT::Other, getRoot(),
5663
getValue(I.getOperand(1)),
5664
getValue(I.getOperand(2)),
5665
DAG.getSrcValue(I.getOperand(1)),
5666
DAG.getSrcValue(I.getOperand(2))));
5669
/// TargetLowering::LowerCallTo - This is the default LowerCallTo
5670
/// implementation, which just calls LowerCall.
5671
/// FIXME: When all targets are
5672
/// migrated to using LowerCall, this hook should be integrated into SDISel.
5673
std::pair<SDValue, SDValue>
5674
TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5675
bool RetSExt, bool RetZExt, bool isVarArg,
5676
bool isInreg, unsigned NumFixedArgs,
5677
CallingConv::ID CallConv, bool isTailCall,
5678
bool isReturnValueUsed,
5680
ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5681
// Handle all of the outgoing arguments.
5682
SmallVector<ISD::OutputArg, 32> Outs;
5683
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5684
SmallVector<EVT, 4> ValueVTs;
5685
ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5686
for (unsigned Value = 0, NumValues = ValueVTs.size();
5687
Value != NumValues; ++Value) {
5688
EVT VT = ValueVTs[Value];
5689
const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5690
SDValue Op = SDValue(Args[i].Node.getNode(),
5691
Args[i].Node.getResNo() + Value);
5692
ISD::ArgFlagsTy Flags;
5693
unsigned OriginalAlignment =
5694
getTargetData()->getABITypeAlignment(ArgTy);
5700
if (Args[i].isInReg)
5704
if (Args[i].isByVal) {
5706
const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5707
const Type *ElementTy = Ty->getElementType();
5708
unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5709
unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5710
// For ByVal, alignment should come from FE. BE will guess if this
5711
// info is not there but there are cases it cannot get right.
5712
if (Args[i].Alignment)
5713
FrameAlign = Args[i].Alignment;
5714
Flags.setByValAlign(FrameAlign);
5715
Flags.setByValSize(FrameSize);
5719
Flags.setOrigAlign(OriginalAlignment);
5721
EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5722
unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5723
SmallVector<SDValue, 4> Parts(NumParts);
5724
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5727
ExtendKind = ISD::SIGN_EXTEND;
5728
else if (Args[i].isZExt)
5729
ExtendKind = ISD::ZERO_EXTEND;
5731
getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
5732
PartVT, ExtendKind);
5734
for (unsigned j = 0; j != NumParts; ++j) {
5735
// if it isn't first piece, alignment must be 1
5736
ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5737
if (NumParts > 1 && j == 0)
5738
MyFlags.Flags.setSplit();
5740
MyFlags.Flags.setOrigAlign(1);
5742
Outs.push_back(MyFlags);
5747
// Handle the incoming return values from the call.
5748
SmallVector<ISD::InputArg, 32> Ins;
5749
SmallVector<EVT, 4> RetTys;
5750
ComputeValueVTs(*this, RetTy, RetTys);
5751
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5753
EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5754
unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5755
for (unsigned i = 0; i != NumRegs; ++i) {
5756
ISD::InputArg MyFlags;
5757
MyFlags.VT = RegisterVT;
5758
MyFlags.Used = isReturnValueUsed;
5760
MyFlags.Flags.setSExt();
5762
MyFlags.Flags.setZExt();
5764
MyFlags.Flags.setInReg();
5765
Ins.push_back(MyFlags);
5769
SmallVector<SDValue, 4> InVals;
5770
Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5771
Outs, Ins, dl, DAG, InVals);
5773
// Verify that the target's LowerCall behaved as expected.
5774
assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5775
"LowerCall didn't return a valid chain!");
5776
assert((!isTailCall || InVals.empty()) &&
5777
"LowerCall emitted a return value for a tail call!");
5778
assert((isTailCall || InVals.size() == Ins.size()) &&
5779
"LowerCall didn't emit the correct number of values!");
5780
DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5781
assert(InVals[i].getNode() &&
5782
"LowerCall emitted a null value!");
5783
assert(Ins[i].VT == InVals[i].getValueType() &&
5784
"LowerCall emitted a value with the wrong type!");
5787
// For a tail call, the return value is merely live-out and there aren't
5788
// any nodes in the DAG representing it. Return a special value to
5789
// indicate that a tail call has been emitted and no more Instructions
5790
// should be processed in the current block.
5793
return std::make_pair(SDValue(), SDValue());
5796
// Collect the legal value parts into potentially illegal values
5797
// that correspond to the original function's return values.
5798
ISD::NodeType AssertOp = ISD::DELETED_NODE;
5800
AssertOp = ISD::AssertSext;
5802
AssertOp = ISD::AssertZext;
5803
SmallVector<SDValue, 4> ReturnValues;
5804
unsigned CurReg = 0;
5805
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5807
EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5808
unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5810
ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
5811
NumRegs, RegisterVT, VT,
5816
// For a function returning void, there is no return value. We can't create
5817
// such a node, so we just return a null return value in that case. In
5818
// that case, nothing will actualy look at the value.
5819
if (ReturnValues.empty())
5820
return std::make_pair(SDValue(), Chain);
5822
SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5823
DAG.getVTList(&RetTys[0], RetTys.size()),
5824
&ReturnValues[0], ReturnValues.size());
5825
return std::make_pair(Res, Chain);
5828
void TargetLowering::LowerOperationWrapper(SDNode *N,
5829
SmallVectorImpl<SDValue> &Results,
5830
SelectionDAG &DAG) {
5831
SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5833
Results.push_back(Res);
5836
SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5837
llvm_unreachable("LowerOperation not implemented for this target!");
5841
void SelectionDAGBuilder::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5842
SDValue Op = getValue(V);
5843
assert((Op.getOpcode() != ISD::CopyFromReg ||
5844
cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5845
"Copy from a reg to the same reg!");
5846
assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5848
RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5849
SDValue Chain = DAG.getEntryNode();
5850
RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5851
PendingExports.push_back(Chain);
5854
#include "llvm/CodeGen/SelectionDAGISel.h"
5856
void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
5857
// If this is the entry block, emit arguments.
5858
Function &F = *LLVMBB->getParent();
5859
SelectionDAG &DAG = SDB->DAG;
5860
SDValue OldRoot = DAG.getRoot();
5861
DebugLoc dl = SDB->getCurDebugLoc();
5862
const TargetData *TD = TLI.getTargetData();
5863
SmallVector<ISD::InputArg, 16> Ins;
5865
// Check whether the function can return without sret-demotion.
5866
SmallVector<EVT, 4> OutVTs;
5867
SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
5868
getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5869
OutVTs, OutsFlags, TLI);
5870
FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5872
FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(),
5873
OutVTs, OutsFlags, DAG);
5874
if (!FLI.CanLowerReturn) {
5875
// Put in an sret pointer parameter before all the other parameters.
5876
SmallVector<EVT, 1> ValueVTs;
5877
ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5879
// NOTE: Assuming that a pointer will never break down to more than one VT
5881
ISD::ArgFlagsTy Flags;
5883
EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), ValueVTs[0]);
5884
ISD::InputArg RetArg(Flags, RegisterVT, true);
5885
Ins.push_back(RetArg);
5888
// Set up the incoming argument description vector.
5890
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5891
I != E; ++I, ++Idx) {
5892
SmallVector<EVT, 4> ValueVTs;
5893
ComputeValueVTs(TLI, I->getType(), ValueVTs);
5894
bool isArgValueUsed = !I->use_empty();
5895
for (unsigned Value = 0, NumValues = ValueVTs.size();
5896
Value != NumValues; ++Value) {
5897
EVT VT = ValueVTs[Value];
5898
const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
5899
ISD::ArgFlagsTy Flags;
5900
unsigned OriginalAlignment =
5901
TD->getABITypeAlignment(ArgTy);
5903
if (F.paramHasAttr(Idx, Attribute::ZExt))
5905
if (F.paramHasAttr(Idx, Attribute::SExt))
5907
if (F.paramHasAttr(Idx, Attribute::InReg))
5909
if (F.paramHasAttr(Idx, Attribute::StructRet))
5911
if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5913
const PointerType *Ty = cast<PointerType>(I->getType());
5914
const Type *ElementTy = Ty->getElementType();
5915
unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5916
unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5917
// For ByVal, alignment should be passed from FE. BE will guess if
5918
// this info is not there but there are cases it cannot get right.
5919
if (F.getParamAlignment(Idx))
5920
FrameAlign = F.getParamAlignment(Idx);
5921
Flags.setByValAlign(FrameAlign);
5922
Flags.setByValSize(FrameSize);
5924
if (F.paramHasAttr(Idx, Attribute::Nest))
5926
Flags.setOrigAlign(OriginalAlignment);
5928
EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5929
unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5930
for (unsigned i = 0; i != NumRegs; ++i) {
5931
ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5932
if (NumRegs > 1 && i == 0)
5933
MyFlags.Flags.setSplit();
5934
// if it isn't first piece, alignment must be 1
5936
MyFlags.Flags.setOrigAlign(1);
5937
Ins.push_back(MyFlags);
5942
// Call the target to set up the argument values.
5943
SmallVector<SDValue, 8> InVals;
5944
SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5948
// Verify that the target's LowerFormalArguments behaved as expected.
5949
assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
5950
"LowerFormalArguments didn't return a valid chain!");
5951
assert(InVals.size() == Ins.size() &&
5952
"LowerFormalArguments didn't emit the correct number of values!");
5954
for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5955
assert(InVals[i].getNode() &&
5956
"LowerFormalArguments emitted a null value!");
5957
assert(Ins[i].VT == InVals[i].getValueType() &&
5958
"LowerFormalArguments emitted a value with the wrong type!");
5962
// Update the DAG with the new chain value resulting from argument lowering.
5963
DAG.setRoot(NewRoot);
5965
// Set up the argument values.
5968
if (!FLI.CanLowerReturn) {
5969
// Create a virtual register for the sret pointer, and put in a copy
5970
// from the sret argument into it.
5971
SmallVector<EVT, 1> ValueVTs;
5972
ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5973
EVT VT = ValueVTs[0];
5974
EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5975
ISD::NodeType AssertOp = ISD::DELETED_NODE;
5976
SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
5977
RegVT, VT, AssertOp);
5979
MachineFunction& MF = SDB->DAG.getMachineFunction();
5980
MachineRegisterInfo& RegInfo = MF.getRegInfo();
5981
unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
5982
FLI.DemoteRegister = SRetReg;
5983
NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
5985
DAG.setRoot(NewRoot);
5987
// i indexes lowered arguments. Bump it past the hidden sret argument.
5988
// Idx indexes LLVM arguments. Don't touch it.
5992
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5994
SmallVector<SDValue, 4> ArgValues;
5995
SmallVector<EVT, 4> ValueVTs;
5996
ComputeValueVTs(TLI, I->getType(), ValueVTs);
5997
unsigned NumValues = ValueVTs.size();
5998
for (unsigned Value = 0; Value != NumValues; ++Value) {
5999
EVT VT = ValueVTs[Value];
6000
EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6001
unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6003
if (!I->use_empty()) {
6004
ISD::NodeType AssertOp = ISD::DELETED_NODE;
6005
if (F.paramHasAttr(Idx, Attribute::SExt))
6006
AssertOp = ISD::AssertSext;
6007
else if (F.paramHasAttr(Idx, Attribute::ZExt))
6008
AssertOp = ISD::AssertZext;
6010
ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6011
NumParts, PartVT, VT,
6018
if (!I->use_empty()) {
6019
SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6020
SDB->getCurDebugLoc());
6021
SDB->setValue(I, Res);
6023
// If this argument is live outside of the entry block, insert a copy from
6024
// whereever we got it to the vreg that other BB's will reference it as.
6025
SDB->CopyToExportRegsIfNeeded(I);
6029
assert(i == InVals.size() && "Argument register count mismatch!");
6031
// Finally, if the target has anything special to do, allow it to do so.
6032
// FIXME: this should insert code into the DAG!
6033
EmitFunctionEntryCode(F, SDB->DAG.getMachineFunction());
6036
/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6037
/// ensure constants are generated when needed. Remember the virtual registers
6038
/// that need to be added to the Machine PHI nodes as input. We cannot just
6039
/// directly add them, because expansion might result in multiple MBB's for one
6040
/// BB. As such, the start of the BB might correspond to a different MBB than
6044
SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
6045
TerminatorInst *TI = LLVMBB->getTerminator();
6047
SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6049
// Check successor nodes' PHI nodes that expect a constant to be available
6051
for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6052
BasicBlock *SuccBB = TI->getSuccessor(succ);
6053
if (!isa<PHINode>(SuccBB->begin())) continue;
6054
MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6056
// If this terminator has multiple identical successors (common for
6057
// switches), only handle each succ once.
6058
if (!SuccsHandled.insert(SuccMBB)) continue;
6060
MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6063
// At this point we know that there is a 1-1 correspondence between LLVM PHI
6064
// nodes and Machine PHI nodes, but the incoming operands have not been
6066
for (BasicBlock::iterator I = SuccBB->begin();
6067
(PN = dyn_cast<PHINode>(I)); ++I) {
6068
// Ignore dead phi's.
6069
if (PN->use_empty()) continue;
6072
Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6074
if (Constant *C = dyn_cast<Constant>(PHIOp)) {
6075
unsigned &RegOut = SDB->ConstantsOut[C];
6077
RegOut = FuncInfo->CreateRegForValue(C);
6078
SDB->CopyValueToVirtualRegister(C, RegOut);
6082
Reg = FuncInfo->ValueMap[PHIOp];
6084
assert(isa<AllocaInst>(PHIOp) &&
6085
FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6086
"Didn't codegen value into a register!??");
6087
Reg = FuncInfo->CreateRegForValue(PHIOp);
6088
SDB->CopyValueToVirtualRegister(PHIOp, Reg);
6092
// Remember that this register needs to added to the machine PHI node as
6093
// the input for this MBB.
6094
SmallVector<EVT, 4> ValueVTs;
6095
ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6096
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6097
EVT VT = ValueVTs[vti];
6098
unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6099
for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6100
SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6101
Reg += NumRegisters;
6105
SDB->ConstantsOut.clear();
6108
/// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6109
/// supports legal types, and it emits MachineInstrs directly instead of
6110
/// creating SelectionDAG nodes.
6113
SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6115
TerminatorInst *TI = LLVMBB->getTerminator();
6117
SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6118
unsigned OrigNumPHINodesToUpdate = SDB->PHINodesToUpdate.size();
6120
// Check successor nodes' PHI nodes that expect a constant to be available
6122
for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6123
BasicBlock *SuccBB = TI->getSuccessor(succ);
6124
if (!isa<PHINode>(SuccBB->begin())) continue;
6125
MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6127
// If this terminator has multiple identical successors (common for
6128
// switches), only handle each succ once.
6129
if (!SuccsHandled.insert(SuccMBB)) continue;
6131
MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6134
// At this point we know that there is a 1-1 correspondence between LLVM PHI
6135
// nodes and Machine PHI nodes, but the incoming operands have not been
6137
for (BasicBlock::iterator I = SuccBB->begin();
6138
(PN = dyn_cast<PHINode>(I)); ++I) {
6139
// Ignore dead phi's.
6140
if (PN->use_empty()) continue;
6142
// Only handle legal types. Two interesting things to note here. First,
6143
// by bailing out early, we may leave behind some dead instructions,
6144
// since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6145
// own moves. Second, this check is necessary becuase FastISel doesn't
6146
// use CreateRegForValue to create registers, so it always creates
6147
// exactly one register for each non-void instruction.
6148
EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6149
if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6152
VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
6154
SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6159
Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6161
unsigned Reg = F->getRegForValue(PHIOp);
6163
SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6166
SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
added
removed
libclamav/c++/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
