1
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false -post-RA-scheduler=true | FileCheck %s
13
; BranchFolding should tail-merge the stores since they all precede
14
; direct branches to the same place.
16
; CHECK: tail_merge_me:
18
; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: movl $1, HABC(%rip)
22
define void @tail_merge_me() nounwind {
25
br i1 %a, label %A, label %next
28
br i1 %b, label %B, label %C
32
store i32 0, i32* @GHJK
37
store i32 0, i32* @GHJK
42
store i32 0, i32* @GHJK
46
store i32 1, i32* @HABC
48
br i1 %c, label %return, label %altret
51
call void @ear(i32 1000)
54
call void @far(i32 1001)
58
declare i8* @choose(i8*, i8*)
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; BranchFolding should tail-duplicate the indirect jump to avoid
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; redundant branching.
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; CHECK: tail_duplicate_me:
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: jmpq *%rbx
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: jmpq *%rbx
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; CHECK: movl $0, GHJK(%rip)
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; CHECK-NEXT: jmpq *%rbx
71
define void @tail_duplicate_me() nounwind {
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%c = call i8* @choose(i8* blockaddress(@tail_duplicate_me, %return),
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i8* blockaddress(@tail_duplicate_me, %altret))
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br i1 %a, label %A, label %next
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br i1 %b, label %B, label %C
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store i32 0, i32* @GHJK
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store i32 0, i32* @GHJK
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store i32 0, i32* @GHJK
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indirectbr i8* %c, [label %return, label %altret]
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call void @ear(i32 1000)
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call void @far(i32 1001)
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; BranchFolding shouldn't try to merge the tails of two blocks
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; with only a branch in common, regardless of the fallthrough situation.
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; CHECK: dont_merge_oddly:
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; CHECK: ucomiss %xmm1, %xmm2
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; CHECK-NEXT: jbe .LBB3_3
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; CHECK-NEXT: ucomiss %xmm0, %xmm1
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; CHECK-NEXT: ja .LBB3_4
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; CHECK-NEXT: .LBB3_2:
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; CHECK-NEXT: movb $1, %al
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; CHECK-NEXT: .LBB3_3:
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; CHECK-NEXT: ucomiss %xmm0, %xmm2
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; CHECK-NEXT: jbe .LBB3_2
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; CHECK-NEXT: .LBB3_4:
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; CHECK-NEXT: xorb %al, %al
126
define i1 @dont_merge_oddly(float* %result) nounwind {
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%tmp4 = getelementptr float* %result, i32 2
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%tmp5 = load float* %tmp4, align 4
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%tmp7 = getelementptr float* %result, i32 4
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%tmp8 = load float* %tmp7, align 4
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%tmp10 = getelementptr float* %result, i32 6
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%tmp11 = load float* %tmp10, align 4
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%tmp12 = fcmp olt float %tmp8, %tmp11
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br i1 %tmp12, label %bb, label %bb21
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%tmp23469 = fcmp olt float %tmp5, %tmp8
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br i1 %tmp23469, label %bb26, label %bb30
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%tmp23 = fcmp olt float %tmp5, %tmp11
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br i1 %tmp23, label %bb26, label %bb30
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; Do any-size tail-merging when two candidate blocks will both require
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; an unconditional jump to complete a two-way conditional branch.
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; CHECK: c_expand_expr_stmt:
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; CHECK-NEXT: .LBB4_12:
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; CHECK-NEXT: movq 8(%rax), %rax
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; CHECK-NEXT: movb 16(%rax), %al
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; CHECK-NEXT: cmpb $16, %al
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; CHECK-NEXT: je .LBB4_6
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; CHECK-NEXT: cmpb $23, %al
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; CHECK-NEXT: je .LBB4_6
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; CHECK-NEXT: jmp .LBB4_15
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; CHECK-NEXT: .LBB4_14:
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; CHECK-NEXT: cmpb $23, %bl
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; CHECK-NEXT: jne .LBB4_15
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; CHECK-NEXT: .LBB4_15:
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%0 = type { %struct.rtx_def* }
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%struct.lang_decl = type opaque
172
%struct.rtx_def = type { i16, i8, i8, [1 x %union.rtunion] }
173
%struct.tree_decl = type { [24 x i8], i8*, i32, %union.tree_node*, i32, i8, i8, i8, i8, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %union..2anon, %0, %union.tree_node*, %struct.lang_decl* }
174
%union..2anon = type { i32 }
175
%union.rtunion = type { i8* }
176
%union.tree_node = type { %struct.tree_decl }
178
define fastcc void @c_expand_expr_stmt(%union.tree_node* %expr) nounwind {
180
%tmp4 = load i8* null, align 8 ; <i8> [#uses=3]
181
switch i8 %tmp4, label %bb3 [
186
switch i32 undef, label %bb1 [
192
switch i32 undef, label %bb1 [
193
i32 0, label %lvalue_p.exit
199
lvalue_p.exit: ; preds = %bb.i
200
%tmp21 = load %union.tree_node** null, align 8 ; <%union.tree_node*> [#uses=3]
201
%tmp22 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 0 ; <i8*> [#uses=1]
202
%tmp23 = load i8* %tmp22, align 8 ; <i8> [#uses=1]
203
%tmp24 = zext i8 %tmp23 to i32 ; <i32> [#uses=1]
204
switch i32 %tmp24, label %lvalue_p.exit4 [
209
bb.i1: ; preds = %lvalue_p.exit
210
%tmp25 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 2 ; <i32*> [#uses=1]
211
%tmp26 = bitcast i32* %tmp25 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
212
%tmp27 = load %union.tree_node** %tmp26, align 8 ; <%union.tree_node*> [#uses=2]
213
%tmp28 = getelementptr inbounds %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
214
%tmp29 = load i8* %tmp28, align 8 ; <i8> [#uses=1]
215
%tmp30 = zext i8 %tmp29 to i32 ; <i32> [#uses=1]
216
switch i32 %tmp30, label %lvalue_p.exit4 [
217
i32 0, label %bb2.i.i2
221
bb.i.i: ; preds = %bb.i1
222
%tmp34 = tail call fastcc i32 @lvalue_p(%union.tree_node* null) nounwind ; <i32> [#uses=1]
223
%phitmp = icmp ne i32 %tmp34, 0 ; <i1> [#uses=1]
224
br label %lvalue_p.exit4
226
bb2.i.i2: ; preds = %bb.i1
227
%tmp35 = getelementptr inbounds %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
228
%tmp36 = bitcast i8* %tmp35 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
229
%tmp37 = load %union.tree_node** %tmp36, align 8 ; <%union.tree_node*> [#uses=1]
230
%tmp38 = getelementptr inbounds %union.tree_node* %tmp37, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
231
%tmp39 = load i8* %tmp38, align 8 ; <i8> [#uses=1]
232
switch i8 %tmp39, label %bb2 [
233
i8 16, label %lvalue_p.exit4
234
i8 23, label %lvalue_p.exit4
237
bb2.i3: ; preds = %lvalue_p.exit
238
%tmp40 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
239
%tmp41 = bitcast i8* %tmp40 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
240
%tmp42 = load %union.tree_node** %tmp41, align 8 ; <%union.tree_node*> [#uses=1]
241
%tmp43 = getelementptr inbounds %union.tree_node* %tmp42, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
242
%tmp44 = load i8* %tmp43, align 8 ; <i8> [#uses=1]
243
switch i8 %tmp44, label %bb2 [
244
i8 16, label %lvalue_p.exit4
245
i8 23, label %lvalue_p.exit4
248
lvalue_p.exit4: ; preds = %bb2.i3, %bb2.i3, %bb2.i.i2, %bb2.i.i2, %bb.i.i, %bb.i1, %lvalue_p.exit
249
%tmp45 = phi i1 [ %phitmp, %bb.i.i ], [ false, %bb2.i.i2 ], [ false, %bb2.i.i2 ], [ false, %bb.i1 ], [ false, %bb2.i3 ], [ false, %bb2.i3 ], [ false, %lvalue_p.exit ] ; <i1> [#uses=1]
250
%tmp46 = icmp eq i8 %tmp4, 0 ; <i1> [#uses=1]
251
%or.cond = or i1 %tmp45, %tmp46 ; <i1> [#uses=1]
252
br i1 %or.cond, label %bb2, label %bb3
254
bb1: ; preds = %bb2.i.i, %bb.i, %bb
255
%.old = icmp eq i8 %tmp4, 23 ; <i1> [#uses=1]
256
br i1 %.old, label %bb2, label %bb3
258
bb2: ; preds = %bb1, %lvalue_p.exit4, %bb2.i3, %bb2.i.i2
261
bb3: ; preds = %bb2, %bb1, %lvalue_p.exit4, %bb2.i, %entry
262
%expr_addr.0 = phi %union.tree_node* [ null, %bb2 ], [ %expr, %bb2.i ], [ %expr, %entry ], [ %expr, %bb1 ], [ %expr, %lvalue_p.exit4 ] ; <%union.tree_node*> [#uses=0]
266
declare fastcc i32 @lvalue_p(%union.tree_node* nocapture) nounwind readonly
268
declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind
271
; If one tail merging candidate falls through into the other,
272
; tail merging is likely profitable regardless of how few
273
; instructions are involved. This function should have only
274
; one ret instruction.
278
; CHECK-NEXT: .LBB5_2:
279
; CHECK-NEXT: addq $8, %rsp
282
define void @foo(i1* %V) nounwind {
284
%t0 = icmp eq i1* %V, null
285
br i1 %t0, label %return, label %bb
297
; one - One instruction may be tail-duplicated even with optsize.
300
; CHECK: movl $0, XYZ(%rip)
301
; CHECK: movl $0, XYZ(%rip)
303
@XYZ = external global i32
305
define void @one() nounwind optsize {
307
%0 = icmp eq i32 undef, 0
308
br i1 %0, label %bbx, label %bby
311
switch i32 undef, label %bb7 [
312
i32 16, label %return
316
volatile store i32 0, i32* @XYZ
320
switch i32 undef, label %bb12 [
321
i32 128, label %return
325
volatile store i32 0, i32* @XYZ
332
; two - Same as one, but with two instructions in the common
333
; tail instead of one. This is too much to be merged, given
334
; the optsize attribute.
338
; CHECK: movl $0, XYZ(%rip)
339
; CHECK: movl $1, XYZ(%rip)
343
define void @two() nounwind optsize {
345
%0 = icmp eq i32 undef, 0
346
br i1 %0, label %bbx, label %bby
349
switch i32 undef, label %bb7 [
350
i32 16, label %return
354
volatile store i32 0, i32* @XYZ
355
volatile store i32 1, i32* @XYZ
359
switch i32 undef, label %bb12 [
360
i32 128, label %return
364
volatile store i32 0, i32* @XYZ
365
volatile store i32 1, i32* @XYZ
372
; two_nosize - Same as two, but without the optsize attribute.
373
; Now two instructions are enough to be tail-duplicated.
376
; CHECK: movl $0, XYZ(%rip)
377
; CHECK: movl $1, XYZ(%rip)
378
; CHECK: movl $0, XYZ(%rip)
379
; CHECK: movl $1, XYZ(%rip)
381
define void @two_nosize() nounwind {
383
%0 = icmp eq i32 undef, 0
384
br i1 %0, label %bbx, label %bby
387
switch i32 undef, label %bb7 [
388
i32 16, label %return
392
volatile store i32 0, i32* @XYZ
393
volatile store i32 1, i32* @XYZ
397
switch i32 undef, label %bb12 [
398
i32 128, label %return
402
volatile store i32 0, i32* @XYZ
403
volatile store i32 1, i32* @XYZ