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  • Committer: Bazaar Package Importer
  • Author(s): Scott Kitterman
  • Date: 2010-03-12 11:30:04 UTC
  • mfrom: (0.41.1 upstream)
  • Revision ID: james.westby@ubuntu.com-20100312113004-b0fop4bkycszdd0z
Tags: 0.96~rc1+dfsg-0ubuntu1
https://launchpad.net/bugs/537636
* New upstream RC - FFE (LP: #537636):
  - Add OfficialDatabaseOnly option to clamav-base.postinst.in
  - Add LocalSocketGroup option to clamav-base.postinst.in
  - Add LocalSocketMode option to clamav-base.postinst.in
  - Add CrossFilesystems option to clamav-base.postinst.in
  - Add ClamukoScannerCount option to clamav-base.postinst.in
  - Add BytecodeSecurity opiton to clamav-base.postinst.in
  - Add DetectionStatsHostID option to clamav-freshclam.postinst.in
  - Add Bytecode option to clamav-freshclam.postinst.in
  - Add MilterSocketGroup option to clamav-milter.postinst.in
  - Add MilterSocketMode option to clamav-milter.postinst.in
  - Add ReportHostname option to clamav-milter.postinst.in
  - Bump libclamav SO version to 6.1.0 in libclamav6.install
  - Drop clamdmon from clamav.examples (no longer shipped by upstream)
  - Drop libclamav.a from libclamav-dev.install (not built by upstream)
  - Update SO version for lintian override for libclamav6
  - Add new Bytecode Testing Tool, usr/bin/clambc, to clamav.install
  - Add build-depends on python and python-setuptools for new test suite
  - Update debian/copyright for the embedded copy of llvm (using the system
    llvm is not currently feasible)

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libclamav/c++/llvm/lib/Target/X86/X86.td
 
1
//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
 
2
// 
 
3
//                     The LLVM Compiler Infrastructure
 
4
//
 
5
// This file is distributed under the University of Illinois Open Source
 
6
// License. See LICENSE.TXT for details.
 
7
// 
 
8
//===----------------------------------------------------------------------===//
 
9
//
 
10
// This is a target description file for the Intel i386 architecture, refered to
 
11
// here as the "X86" architecture.
 
12
//
 
13
//===----------------------------------------------------------------------===//
 
14
 
 
15
// Get the target-independent interfaces which we are implementing...
 
16
//
 
17
include "llvm/Target/Target.td"
 
18
 
 
19
//===----------------------------------------------------------------------===//
 
20
// X86 Subtarget features.
 
21
//===----------------------------------------------------------------------===//
 
22
 
 
23
def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
 
24
                                      "Enable conditional move instructions">;
 
25
 
 
26
 
 
27
def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
 
28
                                      "Enable MMX instructions">;
 
29
def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
 
30
                                      "Enable SSE instructions",
 
31
                                      // SSE codegen depends on cmovs, and all
 
32
                                      // SSE1+ processors support them. 
 
33
                                      [FeatureMMX, FeatureCMOV]>;
 
34
def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
 
35
                                      "Enable SSE2 instructions",
 
36
                                      [FeatureSSE1]>;
 
37
def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
 
38
                                      "Enable SSE3 instructions",
 
39
                                      [FeatureSSE2]>;
 
40
def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
 
41
                                      "Enable SSSE3 instructions",
 
42
                                      [FeatureSSE3]>;
 
43
def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
 
44
                                      "Enable SSE 4.1 instructions",
 
45
                                      [FeatureSSSE3]>;
 
46
def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
 
47
                                      "Enable SSE 4.2 instructions",
 
48
                                      [FeatureSSE41]>;
 
49
def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
 
50
                                      "Enable 3DNow! instructions">;
 
51
def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
 
52
                                      "Enable 3DNow! Athlon instructions",
 
53
                                      [Feature3DNow]>;
 
54
// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
 
55
// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
 
56
// without disabling 64-bit mode.
 
57
def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
 
58
                                      "Support 64-bit instructions">;
 
59
def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
 
60
                                       "Bit testing of memory is slow">;
 
61
def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 
62
                                      "Support SSE 4a instructions">;
 
63
 
 
64
def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
 
65
                                      "Enable AVX instructions">;
 
66
def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
 
67
                                     "Enable three-operand fused multiple-add">;
 
68
def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 
69
                                      "Enable four-operand fused multiple-add">;
 
70
def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
 
71
                                          "HasVectorUAMem", "true",
 
72
                 "Allow unaligned memory operands on vector/SIMD instructions">;
 
73
 
 
74
//===----------------------------------------------------------------------===//
 
75
// X86 processors supported.
 
76
//===----------------------------------------------------------------------===//
 
77
 
 
78
class Proc<string Name, list<SubtargetFeature> Features>
 
79
 : Processor<Name, NoItineraries, Features>;
 
80
 
 
81
def : Proc<"generic",         []>;
 
82
def : Proc<"i386",            []>;
 
83
def : Proc<"i486",            []>;
 
84
def : Proc<"i586",            []>;
 
85
def : Proc<"pentium",         []>;
 
86
def : Proc<"pentium-mmx",     [FeatureMMX]>;
 
87
def : Proc<"i686",            []>;
 
88
def : Proc<"pentiumpro",      [FeatureCMOV]>;
 
89
def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 
90
def : Proc<"pentium3",        [FeatureSSE1]>;
 
91
def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 
92
def : Proc<"pentium4",        [FeatureSSE2]>;
 
93
def : Proc<"x86-64",          [FeatureSSE2,   Feature64Bit, FeatureSlowBTMem]>;
 
94
def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
 
95
def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
 
96
def : Proc<"nocona",          [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
 
97
def : Proc<"core2",           [FeatureSSSE3,  Feature64Bit, FeatureSlowBTMem]>;
 
98
def : Proc<"penryn",          [FeatureSSE41,  Feature64Bit, FeatureSlowBTMem]>;
 
99
def : Proc<"atom",            [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
 
100
def : Proc<"corei7",          [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem]>;
 
101
def : Proc<"nehalem",         [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem]>;
 
102
// Sandy Bridge does not have FMA
 
103
def : Proc<"sandybridge",     [FeatureSSE42,  FeatureAVX,   Feature64Bit]>;
 
104
 
 
105
def : Proc<"k6",              [FeatureMMX]>;
 
106
def : Proc<"k6-2",            [FeatureMMX,    Feature3DNow]>;
 
107
def : Proc<"k6-3",            [FeatureMMX,    Feature3DNow]>;
 
108
def : Proc<"athlon",          [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
 
109
def : Proc<"athlon-tbird",    [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
 
110
def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 
111
def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 
112
def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 
113
def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 
114
                               FeatureSlowBTMem]>;
 
115
def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 
116
                               FeatureSlowBTMem]>;
 
117
def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 
118
                               FeatureSlowBTMem]>;
 
119
def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 
120
                               FeatureSlowBTMem]>;
 
121
def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 
122
                               FeatureSlowBTMem]>;
 
123
def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 
124
                               FeatureSlowBTMem]>;
 
125
def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, Feature64Bit,
 
126
                               FeatureSlowBTMem]>;
 
127
def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
 
128
                               Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
 
129
def : Proc<"barcelona",       [FeatureSSE3,   FeatureSSE4A,
 
130
                               Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
 
131
def : Proc<"istanbul",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
 
132
                               Feature3DNowA]>;
 
133
def : Proc<"shanghai",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
 
134
                               Feature3DNowA]>;
 
135
 
 
136
def : Proc<"winchip-c6",      [FeatureMMX]>;
 
137
def : Proc<"winchip2",        [FeatureMMX, Feature3DNow]>;
 
138
def : Proc<"c3",              [FeatureMMX, Feature3DNow]>;
 
139
def : Proc<"c3-2",            [FeatureSSE1]>;
 
140
 
 
141
//===----------------------------------------------------------------------===//
 
142
// Register File Description
 
143
//===----------------------------------------------------------------------===//
 
144
 
 
145
include "X86RegisterInfo.td"
 
146
 
 
147
//===----------------------------------------------------------------------===//
 
148
// Instruction Descriptions
 
149
//===----------------------------------------------------------------------===//
 
150
 
 
151
include "X86InstrInfo.td"
 
152
 
 
153
def X86InstrInfo : InstrInfo {
 
154
 
 
155
  // Define how we want to layout our TargetSpecific information field... This
 
156
  // should be kept up-to-date with the fields in the X86InstrInfo.h file.
 
157
  let TSFlagsFields = ["FormBits",
 
158
                       "hasOpSizePrefix",
 
159
                       "hasAdSizePrefix",
 
160
                       "Prefix",
 
161
                       "hasREX_WPrefix",
 
162
                       "ImmTypeBits",
 
163
                       "FPFormBits",
 
164
                       "hasLockPrefix",
 
165
                       "SegOvrBits",
 
166
                       "Opcode"];
 
167
  let TSFlagsShifts = [0,
 
168
                       6,
 
169
                       7,
 
170
                       8,
 
171
                       12,
 
172
                       13,
 
173
                       16,
 
174
                       19,
 
175
                       20,
 
176
                       24];
 
177
}
 
178
 
 
179
//===----------------------------------------------------------------------===//
 
180
// Calling Conventions
 
181
//===----------------------------------------------------------------------===//
 
182
 
 
183
include "X86CallingConv.td"
 
184
 
 
185
 
 
186
//===----------------------------------------------------------------------===//
 
187
// Assembly Printers
 
188
//===----------------------------------------------------------------------===//
 
189
 
 
190
// Currently the X86 assembly parser only supports ATT syntax.
 
191
def ATTAsmParser : AsmParser {
 
192
  string AsmParserClassName  = "ATTAsmParser";
 
193
  int Variant = 0;
 
194
 
 
195
  // Discard comments in assembly strings.
 
196
  string CommentDelimiter = "#";
 
197
 
 
198
  // Recognize hard coded registers.
 
199
  string RegisterPrefix = "%";
 
200
}
 
201
 
 
202
// The X86 target supports two different syntaxes for emitting machine code.
 
203
// This is controlled by the -x86-asm-syntax={att|intel}
 
204
def ATTAsmWriter : AsmWriter {
 
205
  string AsmWriterClassName  = "ATTInstPrinter";
 
206
  int Variant = 0;
 
207
}
 
208
def IntelAsmWriter : AsmWriter {
 
209
  string AsmWriterClassName  = "IntelInstPrinter";
 
210
  int Variant = 1;
 
211
}
 
212
 
 
213
def X86 : Target {
 
214
  // Information about the instructions...
 
215
  let InstructionSet = X86InstrInfo;
 
216
 
 
217
  let AssemblyParsers = [ATTAsmParser];
 
218
 
 
219
  let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 
220
}