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//====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file describes the X86-64 instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand Definitions.
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// 64-bits but only 32 bits are significant.
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def i64i32imm : Operand<i64>;
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// 64-bits but only 32 bits are significant, and those bits are treated as being
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def i64i32imm_pcrel : Operand<i64> {
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let PrintMethod = "print_pcrel_imm";
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// 64-bits but only 8 bits are significant.
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def i64i8imm : Operand<i64> {
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let ParserMatchClass = ImmSExt8AsmOperand;
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def lea64mem : Operand<i64> {
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let PrintMethod = "printlea64mem";
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let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
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let ParserMatchClass = X86MemAsmOperand;
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def lea64_32mem : Operand<i32> {
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let PrintMethod = "printlea64_32mem";
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let AsmOperandLowerMethod = "lower_lea64_32mem";
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let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
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let ParserMatchClass = X86MemAsmOperand;
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//===----------------------------------------------------------------------===//
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// Complex Pattern Definitions.
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def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
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[add, sub, mul, X86mul_imm, shl, or, frameindex,
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def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
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[tglobaltlsaddr], []>;
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//===----------------------------------------------------------------------===//
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def i64immSExt8 : PatLeaf<(i64 immSext8)>;
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def GetLo32XForm : SDNodeXForm<imm, [{
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// Transformation function: get the low 32 bits.
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return getI32Imm((unsigned)N->getZExtValue());
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def i64immSExt32 : PatLeaf<(i64 imm), [{
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// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// sign extended field.
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return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
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def i64immZExt32 : PatLeaf<(i64 imm), [{
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// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// unsignedsign extended field.
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return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
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def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
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def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
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def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
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def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
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def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
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def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
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def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
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def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
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def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
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def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
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def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
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//===----------------------------------------------------------------------===//
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// Instruction list...
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// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber EFLAGS.
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let Defs = [RSP, EFLAGS], Uses = [RSP] in {
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def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
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[(X86callseq_start timm:$amt)]>,
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Requires<[In64BitMode]>;
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def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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[(X86callseq_end timm:$amt1, timm:$amt2)]>,
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Requires<[In64BitMode]>;
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// Interrupt Instructions
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def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>;
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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// All calls clobber the non-callee saved registers. RSP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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// NOTE: this pattern doesn't match "X86call imm", because we do not know
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// that the offset between an arbitrary immediate and the call will fit in
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// the 32-bit pcrel field that we have.
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def CALL64pcrel32 : Ii32<0xE8, RawFrm,
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(outs), (ins i64i32imm_pcrel:$dst, variable_ops),
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"call{q}\t$dst", []>,
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Requires<[In64BitMode, NotWin64]>;
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def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
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"call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
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Requires<[NotWin64]>;
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def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
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"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
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Requires<[NotWin64]>;
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def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
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"lcall{q}\t{*}$dst", []>;
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// FIXME: We need to teach codegen about single list of call-clobbered
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// All calls clobber the non-callee saved registers. RSP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
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def WINCALL64pcrel32 : I<0xE8, RawFrm,
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(outs), (ins i64i32imm_pcrel:$dst, variable_ops),
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def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
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[(X86call GR64:$dst)]>, Requires<[IsWin64]>;
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def WINCALL64m : I<0xFF, MRM2m, (outs),
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(ins i64mem:$dst, variable_ops), "call\t{*}$dst",
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[(X86call (loadi64 addr:$dst))]>,
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
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"#TC_RETURN $dst $offset",
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
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"#TC_RETURN $dst $offset",
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst, variable_ops),
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"jmp{q}\t{*}$dst # TAILCALL",
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
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def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
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[(brind GR64:$dst)]>;
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def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
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[(brind (loadi64 addr:$dst))]>;
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def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
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"ljmp{q}\t{*}$dst", []>;
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//===----------------------------------------------------------------------===//
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// EH Pseudo Instructions
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let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1, isCodeGenOnly = 1 in {
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def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
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"ret\t#eh_return, addr: $addr",
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[(X86ehret GR64:$addr)]>;
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions...
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def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
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def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
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let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
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def LEAVE64 : I<0xC9, RawFrm,
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(outs), (ins), "leave", []>;
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let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
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def POP64r : I<0x58, AddRegFrm,
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(outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
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def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
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def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
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let mayStore = 1 in {
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def PUSH64r : I<0x50, AddRegFrm,
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(outs), (ins GR64:$reg), "push{q}\t$reg", []>;
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def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
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def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
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let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
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def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
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"push{q}\t$imm", []>;
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def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
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"push{q}\t$imm", []>;
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def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
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"push{q}\t$imm", []>;
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let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
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def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf{q}", []>, REX_W;
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let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
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def PUSHFQ64 : I<0x9C, RawFrm, (outs), (ins), "pushf{q}", []>;
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def LEA64_32r : I<0x8D, MRMSrcMem,
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(outs GR32:$dst), (ins lea64_32mem:$src),
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"lea{l}\t{$src|$dst}, {$dst|$src}",
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[(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
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let isReMaterializable = 1 in
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def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
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"lea{q}\t{$src|$dst}, {$dst|$src}",
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[(set GR64:$dst, lea64addr:$src)]>;
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let isTwoAddress = 1 in
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def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
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[(set GR64:$dst, (bswap GR64:$src))]>, TB;
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// Bit scan instructions.
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let Defs = [EFLAGS] in {
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def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"bsf{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
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def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"bsf{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
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(implicit EFLAGS)]>, TB;
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def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"bsr{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
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def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"bsr{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
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(implicit EFLAGS)]>, TB;
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let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
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def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
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[(X86rep_movs i64)]>, REP;
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let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
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def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
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[(X86rep_stos i64)]>, REP;
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def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
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def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
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// Fast system-call instructions
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def SYSEXIT64 : RI<0x35, RawFrm,
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(outs), (ins), "sysexit", []>, TB;
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//===----------------------------------------------------------------------===//
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// Move Instructions...
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let neverHasSideEffects = 1 in
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def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
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"movabs{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, imm:$src)]>;
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def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, i64immSExt32:$src)]>;
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def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (load addr:$src))]>;
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def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(store GR64:$src, addr:$dst)]>;
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def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
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"mov{q}\t{$src, $dst|$dst, $src}",
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[(store i64immSExt32:$src, addr:$dst)]>;
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def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
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"mov{q}\t{$src, %rax|%rax, $src}", []>;
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def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
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"mov{q}\t{$src, %rax|%rax, $src}", []>;
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def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
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"mov{q}\t{%rax, $dst|$dst, %rax}", []>;
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def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
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"mov{q}\t{%rax, $dst|$dst, %rax}", []>;
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// Moves to and from segment registers
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def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>;
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// Moves to and from debug registers
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def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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// Moves to and from control registers
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def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG_64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_64:$dst), (ins GR64:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
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// Sign/Zero extenders
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// MOVSX64rr8 always has a REX prefix and it has an 8-bit register
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// operand, which makes it a rare instruction with an 8-bit register
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// operand that can never access an h register. If support for h registers
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// were generalized, this would require a special register class.
379
def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
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"movs{bq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sext GR8:$src))]>, TB;
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def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
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"movs{bq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
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def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
386
"movs{wq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sext GR16:$src))]>, TB;
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def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"movs{wq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
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def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sext GR32:$src))]>;
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def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
395
"movs{lq|xd}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
398
// movzbq and movzwq encodings for the disassembler
399
def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
400
"movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
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"movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
404
"movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
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def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
406
"movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
408
// Use movzbl instead of movzbq when the destination is a register; it's
409
// equivalent due to implicit zero-extending, and it has a smaller encoding.
410
def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
411
"", [(set GR64:$dst, (zext GR8:$src))]>, TB;
412
def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
413
"", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
414
// Use movzwl instead of movzwq when the destination is a register; it's
415
// equivalent due to implicit zero-extending, and it has a smaller encoding.
416
def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
417
"", [(set GR64:$dst, (zext GR16:$src))]>, TB;
418
def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
419
"", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
421
// There's no movzlq instruction, but movl can be used for this purpose, using
422
// implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
423
// extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
424
// zero-extension, however this isn't possible when the 32-bit value is
425
// defined by a truncate or is copied from something where the high bits aren't
426
// necessarily all zero. In such cases, we fall back to these explicit zext
428
def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
429
"", [(set GR64:$dst, (zext GR32:$src))]>;
430
def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
431
"", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
433
// Any instruction that defines a 32-bit result leaves the high half of the
434
// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
435
// be copying from a truncate. And x86's cmov doesn't do anything if the
436
// condition is false. But any other 32-bit operation will zero-extend
438
def def32 : PatLeaf<(i32 GR32:$src), [{
439
return N->getOpcode() != ISD::TRUNCATE &&
440
N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
441
N->getOpcode() != ISD::CopyFromReg &&
442
N->getOpcode() != X86ISD::CMOV;
445
// In the case of a 32-bit def that is known to implicitly zero-extend,
446
// we can use a SUBREG_TO_REG.
447
def : Pat<(i64 (zext def32:$src)),
448
(SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
450
let neverHasSideEffects = 1 in {
451
let Defs = [RAX], Uses = [EAX] in
452
def CDQE : RI<0x98, RawFrm, (outs), (ins),
453
"{cltq|cdqe}", []>; // RAX = signext(EAX)
455
let Defs = [RAX,RDX], Uses = [RAX] in
456
def CQO : RI<0x99, RawFrm, (outs), (ins),
457
"{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
460
//===----------------------------------------------------------------------===//
461
// Arithmetic Instructions...
464
let Defs = [EFLAGS] in {
466
def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
467
"add{q}\t{$src, %rax|%rax, $src}", []>;
469
let isTwoAddress = 1 in {
470
let isConvertibleToThreeAddress = 1 in {
471
let isCommutable = 1 in
472
// Register-Register Addition
473
def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
474
(ins GR64:$src1, GR64:$src2),
475
"add{q}\t{$src2, $dst|$dst, $src2}",
476
[(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
479
// Register-Integer Addition
480
def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
481
(ins GR64:$src1, i64i8imm:$src2),
482
"add{q}\t{$src2, $dst|$dst, $src2}",
483
[(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
485
def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
486
(ins GR64:$src1, i64i32imm:$src2),
487
"add{q}\t{$src2, $dst|$dst, $src2}",
488
[(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
490
} // isConvertibleToThreeAddress
492
// Register-Memory Addition
493
def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
494
(ins GR64:$src1, i64mem:$src2),
495
"add{q}\t{$src2, $dst|$dst, $src2}",
496
[(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
499
// Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
500
// differently encoded.
501
def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst),
502
(ins GR64:$src1, GR64:$src2),
503
"add{l}\t{$src2, $dst|$dst, $src2}", []>;
507
// Memory-Register Addition
508
def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
509
"add{q}\t{$src2, $dst|$dst, $src2}",
510
[(store (add (load addr:$dst), GR64:$src2), addr:$dst),
512
def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
513
"add{q}\t{$src2, $dst|$dst, $src2}",
514
[(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
516
def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
517
"add{q}\t{$src2, $dst|$dst, $src2}",
518
[(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
521
let Uses = [EFLAGS] in {
523
def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
524
"adc{q}\t{$src, %rax|%rax, $src}", []>;
526
let isTwoAddress = 1 in {
527
let isCommutable = 1 in
528
def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
529
(ins GR64:$src1, GR64:$src2),
530
"adc{q}\t{$src2, $dst|$dst, $src2}",
531
[(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
533
def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
534
(ins GR64:$src1, GR64:$src2),
535
"adc{q}\t{$src2, $dst|$dst, $src2}", []>;
537
def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
538
(ins GR64:$src1, i64mem:$src2),
539
"adc{q}\t{$src2, $dst|$dst, $src2}",
540
[(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
542
def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
543
(ins GR64:$src1, i64i8imm:$src2),
544
"adc{q}\t{$src2, $dst|$dst, $src2}",
545
[(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
546
def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
547
(ins GR64:$src1, i64i32imm:$src2),
548
"adc{q}\t{$src2, $dst|$dst, $src2}",
549
[(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
552
def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
553
"adc{q}\t{$src2, $dst|$dst, $src2}",
554
[(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
555
def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
556
"adc{q}\t{$src2, $dst|$dst, $src2}",
557
[(store (adde (load addr:$dst), i64immSExt8:$src2),
559
def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
560
"adc{q}\t{$src2, $dst|$dst, $src2}",
561
[(store (adde (load addr:$dst), i64immSExt32:$src2),
565
let isTwoAddress = 1 in {
566
// Register-Register Subtraction
567
def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
568
(ins GR64:$src1, GR64:$src2),
569
"sub{q}\t{$src2, $dst|$dst, $src2}",
570
[(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
573
def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
574
(ins GR64:$src1, GR64:$src2),
575
"sub{q}\t{$src2, $dst|$dst, $src2}", []>;
577
// Register-Memory Subtraction
578
def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
579
(ins GR64:$src1, i64mem:$src2),
580
"sub{q}\t{$src2, $dst|$dst, $src2}",
581
[(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
584
// Register-Integer Subtraction
585
def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
586
(ins GR64:$src1, i64i8imm:$src2),
587
"sub{q}\t{$src2, $dst|$dst, $src2}",
588
[(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
590
def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
591
(ins GR64:$src1, i64i32imm:$src2),
592
"sub{q}\t{$src2, $dst|$dst, $src2}",
593
[(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
597
def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
598
"sub{q}\t{$src, %rax|%rax, $src}", []>;
600
// Memory-Register Subtraction
601
def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
602
"sub{q}\t{$src2, $dst|$dst, $src2}",
603
[(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
606
// Memory-Integer Subtraction
607
def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
608
"sub{q}\t{$src2, $dst|$dst, $src2}",
609
[(store (sub (load addr:$dst), i64immSExt8:$src2),
612
def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
613
"sub{q}\t{$src2, $dst|$dst, $src2}",
614
[(store (sub (load addr:$dst), i64immSExt32:$src2),
618
let Uses = [EFLAGS] in {
619
let isTwoAddress = 1 in {
620
def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
621
(ins GR64:$src1, GR64:$src2),
622
"sbb{q}\t{$src2, $dst|$dst, $src2}",
623
[(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
625
def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
626
(ins GR64:$src1, GR64:$src2),
627
"sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
629
def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
630
(ins GR64:$src1, i64mem:$src2),
631
"sbb{q}\t{$src2, $dst|$dst, $src2}",
632
[(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
634
def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
635
(ins GR64:$src1, i64i8imm:$src2),
636
"sbb{q}\t{$src2, $dst|$dst, $src2}",
637
[(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
638
def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
639
(ins GR64:$src1, i64i32imm:$src2),
640
"sbb{q}\t{$src2, $dst|$dst, $src2}",
641
[(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
644
def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
645
"sbb{q}\t{$src, %rax|%rax, $src}", []>;
647
def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
648
"sbb{q}\t{$src2, $dst|$dst, $src2}",
649
[(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
650
def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
651
"sbb{q}\t{$src2, $dst|$dst, $src2}",
652
[(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
653
def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
654
"sbb{q}\t{$src2, $dst|$dst, $src2}",
655
[(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
659
// Unsigned multiplication
660
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
661
def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
662
"mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
664
def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
665
"mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
667
// Signed multiplication
668
def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
669
"imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
671
def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
672
"imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
675
let Defs = [EFLAGS] in {
676
let isTwoAddress = 1 in {
677
let isCommutable = 1 in
678
// Register-Register Signed Integer Multiplication
679
def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
680
(ins GR64:$src1, GR64:$src2),
681
"imul{q}\t{$src2, $dst|$dst, $src2}",
682
[(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
683
(implicit EFLAGS)]>, TB;
685
// Register-Memory Signed Integer Multiplication
686
def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
687
(ins GR64:$src1, i64mem:$src2),
688
"imul{q}\t{$src2, $dst|$dst, $src2}",
689
[(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
690
(implicit EFLAGS)]>, TB;
693
// Suprisingly enough, these are not two address instructions!
695
// Register-Integer Signed Integer Multiplication
696
def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
697
(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
698
"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
699
[(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
701
def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
702
(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
703
"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
704
[(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
707
// Memory-Integer Signed Integer Multiplication
708
def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
709
(outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
710
"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
711
[(set GR64:$dst, (mul (load addr:$src1),
714
def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
715
(outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
716
"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
717
[(set GR64:$dst, (mul (load addr:$src1),
718
i64immSExt32:$src2)),
722
// Unsigned division / remainder
723
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
724
// RDX:RAX/r64 = RAX,RDX
725
def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
727
// Signed division / remainder
728
// RDX:RAX/r64 = RAX,RDX
729
def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
730
"idiv{q}\t$src", []>;
732
// RDX:RAX/[mem64] = RAX,RDX
733
def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
735
// RDX:RAX/[mem64] = RAX,RDX
736
def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
737
"idiv{q}\t$src", []>;
741
// Unary instructions
742
let Defs = [EFLAGS], CodeSize = 2 in {
743
let isTwoAddress = 1 in
744
def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
745
[(set GR64:$dst, (ineg GR64:$src)),
747
def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
748
[(store (ineg (loadi64 addr:$dst)), addr:$dst),
751
let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
752
def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
753
[(set GR64:$dst, (add GR64:$src, 1)),
755
def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
756
[(store (add (loadi64 addr:$dst), 1), addr:$dst),
759
let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
760
def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
761
[(set GR64:$dst, (add GR64:$src, -1)),
763
def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
764
[(store (add (loadi64 addr:$dst), -1), addr:$dst),
767
// In 64-bit mode, single byte INC and DEC cannot be encoded.
768
let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
769
// Can transform into LEA.
770
def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
772
[(set GR16:$dst, (add GR16:$src, 1)),
774
OpSize, Requires<[In64BitMode]>;
775
def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
777
[(set GR32:$dst, (add GR32:$src, 1)),
779
Requires<[In64BitMode]>;
780
def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
782
[(set GR16:$dst, (add GR16:$src, -1)),
784
OpSize, Requires<[In64BitMode]>;
785
def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
787
[(set GR32:$dst, (add GR32:$src, -1)),
789
Requires<[In64BitMode]>;
790
} // isConvertibleToThreeAddress
792
// These are duplicates of their 32-bit counterparts. Only needed so X86 knows
793
// how to unfold them.
794
let isTwoAddress = 0, CodeSize = 2 in {
795
def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
796
[(store (add (loadi16 addr:$dst), 1), addr:$dst),
798
OpSize, Requires<[In64BitMode]>;
799
def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
800
[(store (add (loadi32 addr:$dst), 1), addr:$dst),
802
Requires<[In64BitMode]>;
803
def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
804
[(store (add (loadi16 addr:$dst), -1), addr:$dst),
806
OpSize, Requires<[In64BitMode]>;
807
def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
808
[(store (add (loadi32 addr:$dst), -1), addr:$dst),
810
Requires<[In64BitMode]>;
812
} // Defs = [EFLAGS], CodeSize
815
let Defs = [EFLAGS] in {
816
// Shift instructions
817
let isTwoAddress = 1 in {
819
def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
820
"shl{q}\t{%cl, $dst|$dst, %CL}",
821
[(set GR64:$dst, (shl GR64:$src, CL))]>;
822
let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
823
def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
824
(ins GR64:$src1, i8imm:$src2),
825
"shl{q}\t{$src2, $dst|$dst, $src2}",
826
[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
827
// NOTE: We don't include patterns for shifts of a register by one, because
828
// 'add reg,reg' is cheaper.
829
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
834
def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
835
"shl{q}\t{%cl, $dst|$dst, %CL}",
836
[(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
837
def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
838
"shl{q}\t{$src, $dst|$dst, $src}",
839
[(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
840
def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
842
[(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
844
let isTwoAddress = 1 in {
846
def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
847
"shr{q}\t{%cl, $dst|$dst, %CL}",
848
[(set GR64:$dst, (srl GR64:$src, CL))]>;
849
def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
850
"shr{q}\t{$src2, $dst|$dst, $src2}",
851
[(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
852
def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
854
[(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
858
def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
859
"shr{q}\t{%cl, $dst|$dst, %CL}",
860
[(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
861
def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
862
"shr{q}\t{$src, $dst|$dst, $src}",
863
[(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
864
def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
866
[(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
868
let isTwoAddress = 1 in {
870
def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
871
"sar{q}\t{%cl, $dst|$dst, %CL}",
872
[(set GR64:$dst, (sra GR64:$src, CL))]>;
873
def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
874
(ins GR64:$src1, i8imm:$src2),
875
"sar{q}\t{$src2, $dst|$dst, $src2}",
876
[(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
877
def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
879
[(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
883
def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
884
"sar{q}\t{%cl, $dst|$dst, %CL}",
885
[(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
886
def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
887
"sar{q}\t{$src, $dst|$dst, $src}",
888
[(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
889
def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
891
[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
893
// Rotate instructions
895
let isTwoAddress = 1 in {
896
def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
897
"rcl{q}\t{1, $dst|$dst, 1}", []>;
898
def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
899
"rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
901
def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
902
"rcr{q}\t{1, $dst|$dst, 1}", []>;
903
def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
904
"rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
907
def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
908
"rcl{q}\t{%cl, $dst|$dst, CL}", []>;
909
def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
910
"rcr{q}\t{%cl, $dst|$dst, CL}", []>;
914
let isTwoAddress = 0 in {
915
def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
916
"rcl{q}\t{1, $dst|$dst, 1}", []>;
917
def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
918
"rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
919
def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
920
"rcr{q}\t{1, $dst|$dst, 1}", []>;
921
def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
922
"rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
925
def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
926
"rcl{q}\t{%cl, $dst|$dst, CL}", []>;
927
def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
928
"rcr{q}\t{%cl, $dst|$dst, CL}", []>;
932
let isTwoAddress = 1 in {
934
def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
935
"rol{q}\t{%cl, $dst|$dst, %CL}",
936
[(set GR64:$dst, (rotl GR64:$src, CL))]>;
937
def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
938
(ins GR64:$src1, i8imm:$src2),
939
"rol{q}\t{$src2, $dst|$dst, $src2}",
940
[(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
941
def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
943
[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
947
def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
948
"rol{q}\t{%cl, $dst|$dst, %CL}",
949
[(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
950
def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
951
"rol{q}\t{$src, $dst|$dst, $src}",
952
[(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
953
def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
955
[(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
957
let isTwoAddress = 1 in {
959
def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
960
"ror{q}\t{%cl, $dst|$dst, %CL}",
961
[(set GR64:$dst, (rotr GR64:$src, CL))]>;
962
def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
963
(ins GR64:$src1, i8imm:$src2),
964
"ror{q}\t{$src2, $dst|$dst, $src2}",
965
[(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
966
def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
968
[(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
972
def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
973
"ror{q}\t{%cl, $dst|$dst, %CL}",
974
[(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
975
def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
976
"ror{q}\t{$src, $dst|$dst, $src}",
977
[(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
978
def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
980
[(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
982
// Double shift instructions (generalizations of rotate)
983
let isTwoAddress = 1 in {
985
def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
986
(ins GR64:$src1, GR64:$src2),
987
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
988
[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
990
def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
991
(ins GR64:$src1, GR64:$src2),
992
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
993
[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
997
let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
998
def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
1000
(ins GR64:$src1, GR64:$src2, i8imm:$src3),
1001
"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1002
[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
1005
def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
1007
(ins GR64:$src1, GR64:$src2, i8imm:$src3),
1008
"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1009
[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
1015
let Uses = [CL] in {
1016
def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1017
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1018
[(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
1020
def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1021
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1022
[(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
1025
def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
1026
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1027
"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1028
[(store (X86shld (loadi64 addr:$dst), GR64:$src2,
1029
(i8 imm:$src3)), addr:$dst)]>,
1031
def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
1032
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1033
"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1034
[(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
1035
(i8 imm:$src3)), addr:$dst)]>,
1037
} // Defs = [EFLAGS]
1039
//===----------------------------------------------------------------------===//
1040
// Logical Instructions...
1043
let isTwoAddress = 1 , AddedComplexity = 15 in
1044
def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
1045
[(set GR64:$dst, (not GR64:$src))]>;
1046
def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
1047
[(store (not (loadi64 addr:$dst)), addr:$dst)]>;
1049
let Defs = [EFLAGS] in {
1050
def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
1051
"and{q}\t{$src, %rax|%rax, $src}", []>;
1053
let isTwoAddress = 1 in {
1054
let isCommutable = 1 in
1055
def AND64rr : RI<0x21, MRMDestReg,
1056
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1057
"and{q}\t{$src2, $dst|$dst, $src2}",
1058
[(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
1059
(implicit EFLAGS)]>;
1060
def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
1061
(ins GR64:$src1, GR64:$src2),
1062
"and{q}\t{$src2, $dst|$dst, $src2}", []>;
1063
def AND64rm : RI<0x23, MRMSrcMem,
1064
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1065
"and{q}\t{$src2, $dst|$dst, $src2}",
1066
[(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
1067
(implicit EFLAGS)]>;
1068
def AND64ri8 : RIi8<0x83, MRM4r,
1069
(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1070
"and{q}\t{$src2, $dst|$dst, $src2}",
1071
[(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
1072
(implicit EFLAGS)]>;
1073
def AND64ri32 : RIi32<0x81, MRM4r,
1074
(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1075
"and{q}\t{$src2, $dst|$dst, $src2}",
1076
[(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
1077
(implicit EFLAGS)]>;
1080
def AND64mr : RI<0x21, MRMDestMem,
1081
(outs), (ins i64mem:$dst, GR64:$src),
1082
"and{q}\t{$src, $dst|$dst, $src}",
1083
[(store (and (load addr:$dst), GR64:$src), addr:$dst),
1084
(implicit EFLAGS)]>;
1085
def AND64mi8 : RIi8<0x83, MRM4m,
1086
(outs), (ins i64mem:$dst, i64i8imm :$src),
1087
"and{q}\t{$src, $dst|$dst, $src}",
1088
[(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
1089
(implicit EFLAGS)]>;
1090
def AND64mi32 : RIi32<0x81, MRM4m,
1091
(outs), (ins i64mem:$dst, i64i32imm:$src),
1092
"and{q}\t{$src, $dst|$dst, $src}",
1093
[(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1094
(implicit EFLAGS)]>;
1096
let isTwoAddress = 1 in {
1097
let isCommutable = 1 in
1098
def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
1099
(ins GR64:$src1, GR64:$src2),
1100
"or{q}\t{$src2, $dst|$dst, $src2}",
1101
[(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
1102
(implicit EFLAGS)]>;
1103
def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
1104
(ins GR64:$src1, GR64:$src2),
1105
"or{q}\t{$src2, $dst|$dst, $src2}", []>;
1106
def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
1107
(ins GR64:$src1, i64mem:$src2),
1108
"or{q}\t{$src2, $dst|$dst, $src2}",
1109
[(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
1110
(implicit EFLAGS)]>;
1111
def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
1112
(ins GR64:$src1, i64i8imm:$src2),
1113
"or{q}\t{$src2, $dst|$dst, $src2}",
1114
[(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
1115
(implicit EFLAGS)]>;
1116
def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
1117
(ins GR64:$src1, i64i32imm:$src2),
1118
"or{q}\t{$src2, $dst|$dst, $src2}",
1119
[(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
1120
(implicit EFLAGS)]>;
1123
def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1124
"or{q}\t{$src, $dst|$dst, $src}",
1125
[(store (or (load addr:$dst), GR64:$src), addr:$dst),
1126
(implicit EFLAGS)]>;
1127
def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
1128
"or{q}\t{$src, $dst|$dst, $src}",
1129
[(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1130
(implicit EFLAGS)]>;
1131
def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1132
"or{q}\t{$src, $dst|$dst, $src}",
1133
[(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1134
(implicit EFLAGS)]>;
1136
def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
1137
"or{q}\t{$src, %rax|%rax, $src}", []>;
1139
let isTwoAddress = 1 in {
1140
let isCommutable = 1 in
1141
def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
1142
(ins GR64:$src1, GR64:$src2),
1143
"xor{q}\t{$src2, $dst|$dst, $src2}",
1144
[(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
1145
(implicit EFLAGS)]>;
1146
def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
1147
(ins GR64:$src1, GR64:$src2),
1148
"xor{q}\t{$src2, $dst|$dst, $src2}", []>;
1149
def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
1150
(ins GR64:$src1, i64mem:$src2),
1151
"xor{q}\t{$src2, $dst|$dst, $src2}",
1152
[(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
1153
(implicit EFLAGS)]>;
1154
def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1155
(ins GR64:$src1, i64i8imm:$src2),
1156
"xor{q}\t{$src2, $dst|$dst, $src2}",
1157
[(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1158
(implicit EFLAGS)]>;
1159
def XOR64ri32 : RIi32<0x81, MRM6r,
1160
(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1161
"xor{q}\t{$src2, $dst|$dst, $src2}",
1162
[(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1163
(implicit EFLAGS)]>;
1166
def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1167
"xor{q}\t{$src, $dst|$dst, $src}",
1168
[(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1169
(implicit EFLAGS)]>;
1170
def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1171
"xor{q}\t{$src, $dst|$dst, $src}",
1172
[(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1173
(implicit EFLAGS)]>;
1174
def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1175
"xor{q}\t{$src, $dst|$dst, $src}",
1176
[(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1177
(implicit EFLAGS)]>;
1179
def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1180
"xor{q}\t{$src, %rax|%rax, $src}", []>;
1182
} // Defs = [EFLAGS]
1184
//===----------------------------------------------------------------------===//
1185
// Comparison Instructions...
1188
// Integer comparison
1189
let Defs = [EFLAGS] in {
1190
def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1191
"test{q}\t{$src, %rax|%rax, $src}", []>;
1192
let isCommutable = 1 in
1193
def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1194
"test{q}\t{$src2, $src1|$src1, $src2}",
1195
[(X86cmp (and GR64:$src1, GR64:$src2), 0),
1196
(implicit EFLAGS)]>;
1197
def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1198
"test{q}\t{$src2, $src1|$src1, $src2}",
1199
[(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1200
(implicit EFLAGS)]>;
1201
def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1202
(ins GR64:$src1, i64i32imm:$src2),
1203
"test{q}\t{$src2, $src1|$src1, $src2}",
1204
[(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1205
(implicit EFLAGS)]>;
1206
def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1207
(ins i64mem:$src1, i64i32imm:$src2),
1208
"test{q}\t{$src2, $src1|$src1, $src2}",
1209
[(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1210
(implicit EFLAGS)]>;
1213
def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1214
"cmp{q}\t{$src, %rax|%rax, $src}", []>;
1215
def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1216
"cmp{q}\t{$src2, $src1|$src1, $src2}",
1217
[(X86cmp GR64:$src1, GR64:$src2),
1218
(implicit EFLAGS)]>;
1219
def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1220
"cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1221
def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1222
"cmp{q}\t{$src2, $src1|$src1, $src2}",
1223
[(X86cmp (loadi64 addr:$src1), GR64:$src2),
1224
(implicit EFLAGS)]>;
1225
def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1226
"cmp{q}\t{$src2, $src1|$src1, $src2}",
1227
[(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1228
(implicit EFLAGS)]>;
1229
def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1230
"cmp{q}\t{$src2, $src1|$src1, $src2}",
1231
[(X86cmp GR64:$src1, i64immSExt8:$src2),
1232
(implicit EFLAGS)]>;
1233
def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1234
"cmp{q}\t{$src2, $src1|$src1, $src2}",
1235
[(X86cmp GR64:$src1, i64immSExt32:$src2),
1236
(implicit EFLAGS)]>;
1237
def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1238
"cmp{q}\t{$src2, $src1|$src1, $src2}",
1239
[(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1240
(implicit EFLAGS)]>;
1241
def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1242
(ins i64mem:$src1, i64i32imm:$src2),
1243
"cmp{q}\t{$src2, $src1|$src1, $src2}",
1244
[(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1245
(implicit EFLAGS)]>;
1246
} // Defs = [EFLAGS]
1249
// TODO: BTC, BTR, and BTS
1250
let Defs = [EFLAGS] in {
1251
def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1252
"bt{q}\t{$src2, $src1|$src1, $src2}",
1253
[(X86bt GR64:$src1, GR64:$src2),
1254
(implicit EFLAGS)]>, TB;
1256
// Unlike with the register+register form, the memory+register form of the
1257
// bt instruction does not ignore the high bits of the index. From ISel's
1258
// perspective, this is pretty bizarre. Disable these instructions for now.
1259
def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1260
"bt{q}\t{$src2, $src1|$src1, $src2}",
1261
// [(X86bt (loadi64 addr:$src1), GR64:$src2),
1262
// (implicit EFLAGS)]
1266
def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1267
"bt{q}\t{$src2, $src1|$src1, $src2}",
1268
[(X86bt GR64:$src1, i64immSExt8:$src2),
1269
(implicit EFLAGS)]>, TB;
1270
// Note that these instructions don't need FastBTMem because that
1271
// only applies when the other operand is in a register. When it's
1272
// an immediate, bt is still fast.
1273
def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1274
"bt{q}\t{$src2, $src1|$src1, $src2}",
1275
[(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1276
(implicit EFLAGS)]>, TB;
1278
def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1279
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1280
def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1281
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1282
def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1283
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1284
def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1285
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1287
def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1288
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1289
def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1290
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1291
def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1292
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1293
def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1294
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1296
def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1297
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1298
def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1299
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1300
def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1301
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1302
def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1303
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1304
} // Defs = [EFLAGS]
1306
// Conditional moves
1307
let Uses = [EFLAGS], isTwoAddress = 1 in {
1308
let isCommutable = 1 in {
1309
def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1310
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1311
"cmovb{q}\t{$src2, $dst|$dst, $src2}",
1312
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1313
X86_COND_B, EFLAGS))]>, TB;
1314
def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1315
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1316
"cmovae{q}\t{$src2, $dst|$dst, $src2}",
1317
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1318
X86_COND_AE, EFLAGS))]>, TB;
1319
def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1320
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1321
"cmove{q}\t{$src2, $dst|$dst, $src2}",
1322
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1323
X86_COND_E, EFLAGS))]>, TB;
1324
def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1325
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1326
"cmovne{q}\t{$src2, $dst|$dst, $src2}",
1327
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1328
X86_COND_NE, EFLAGS))]>, TB;
1329
def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1330
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1331
"cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1332
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1333
X86_COND_BE, EFLAGS))]>, TB;
1334
def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1335
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1336
"cmova{q}\t{$src2, $dst|$dst, $src2}",
1337
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1338
X86_COND_A, EFLAGS))]>, TB;
1339
def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1340
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1341
"cmovl{q}\t{$src2, $dst|$dst, $src2}",
1342
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1343
X86_COND_L, EFLAGS))]>, TB;
1344
def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1345
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1346
"cmovge{q}\t{$src2, $dst|$dst, $src2}",
1347
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1348
X86_COND_GE, EFLAGS))]>, TB;
1349
def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1350
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1351
"cmovle{q}\t{$src2, $dst|$dst, $src2}",
1352
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1353
X86_COND_LE, EFLAGS))]>, TB;
1354
def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1355
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1356
"cmovg{q}\t{$src2, $dst|$dst, $src2}",
1357
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1358
X86_COND_G, EFLAGS))]>, TB;
1359
def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1360
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1361
"cmovs{q}\t{$src2, $dst|$dst, $src2}",
1362
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1363
X86_COND_S, EFLAGS))]>, TB;
1364
def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1365
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1366
"cmovns{q}\t{$src2, $dst|$dst, $src2}",
1367
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1368
X86_COND_NS, EFLAGS))]>, TB;
1369
def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1370
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1371
"cmovp{q}\t{$src2, $dst|$dst, $src2}",
1372
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1373
X86_COND_P, EFLAGS))]>, TB;
1374
def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1375
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1376
"cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1377
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1378
X86_COND_NP, EFLAGS))]>, TB;
1379
def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1380
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1381
"cmovo{q}\t{$src2, $dst|$dst, $src2}",
1382
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1383
X86_COND_O, EFLAGS))]>, TB;
1384
def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1385
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1386
"cmovno{q}\t{$src2, $dst|$dst, $src2}",
1387
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1388
X86_COND_NO, EFLAGS))]>, TB;
1389
} // isCommutable = 1
1391
def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1392
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1393
"cmovb{q}\t{$src2, $dst|$dst, $src2}",
1394
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1395
X86_COND_B, EFLAGS))]>, TB;
1396
def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1397
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1398
"cmovae{q}\t{$src2, $dst|$dst, $src2}",
1399
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1400
X86_COND_AE, EFLAGS))]>, TB;
1401
def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1402
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1403
"cmove{q}\t{$src2, $dst|$dst, $src2}",
1404
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1405
X86_COND_E, EFLAGS))]>, TB;
1406
def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1407
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1408
"cmovne{q}\t{$src2, $dst|$dst, $src2}",
1409
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1410
X86_COND_NE, EFLAGS))]>, TB;
1411
def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1412
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1413
"cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1414
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1415
X86_COND_BE, EFLAGS))]>, TB;
1416
def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1417
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1418
"cmova{q}\t{$src2, $dst|$dst, $src2}",
1419
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1420
X86_COND_A, EFLAGS))]>, TB;
1421
def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1422
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1423
"cmovl{q}\t{$src2, $dst|$dst, $src2}",
1424
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1425
X86_COND_L, EFLAGS))]>, TB;
1426
def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1427
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1428
"cmovge{q}\t{$src2, $dst|$dst, $src2}",
1429
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1430
X86_COND_GE, EFLAGS))]>, TB;
1431
def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1432
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1433
"cmovle{q}\t{$src2, $dst|$dst, $src2}",
1434
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1435
X86_COND_LE, EFLAGS))]>, TB;
1436
def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1437
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1438
"cmovg{q}\t{$src2, $dst|$dst, $src2}",
1439
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1440
X86_COND_G, EFLAGS))]>, TB;
1441
def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1442
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1443
"cmovs{q}\t{$src2, $dst|$dst, $src2}",
1444
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1445
X86_COND_S, EFLAGS))]>, TB;
1446
def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1447
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1448
"cmovns{q}\t{$src2, $dst|$dst, $src2}",
1449
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1450
X86_COND_NS, EFLAGS))]>, TB;
1451
def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1452
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1453
"cmovp{q}\t{$src2, $dst|$dst, $src2}",
1454
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1455
X86_COND_P, EFLAGS))]>, TB;
1456
def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1457
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1458
"cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1459
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1460
X86_COND_NP, EFLAGS))]>, TB;
1461
def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1462
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1463
"cmovo{q}\t{$src2, $dst|$dst, $src2}",
1464
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1465
X86_COND_O, EFLAGS))]>, TB;
1466
def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1467
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1468
"cmovno{q}\t{$src2, $dst|$dst, $src2}",
1469
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1470
X86_COND_NO, EFLAGS))]>, TB;
1473
// Use sbb to materialize carry flag into a GPR.
1474
// FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
1475
// However, Pat<> can't replicate the destination reg into the inputs of the
1477
// FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
1479
let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
1480
def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
1481
[(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
1483
def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1486
//===----------------------------------------------------------------------===//
1487
// Conversion Instructions...
1490
// f64 -> signed i64
1491
def CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1492
"cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1493
def CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1494
"cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1495
def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1496
"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1498
(int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1499
def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst),
1501
"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1502
[(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1503
(load addr:$src)))]>;
1504
def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1505
"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1506
[(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1507
def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1508
"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1509
[(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1510
def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1511
"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1513
(int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1514
def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst),
1516
"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1518
(int_x86_sse2_cvttsd2si64
1519
(load addr:$src)))]>;
1521
// Signed i64 -> f64
1522
def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1523
"cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1524
[(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1525
def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1526
"cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1527
[(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1529
let isTwoAddress = 1 in {
1530
def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1531
(outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1532
"cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1534
(int_x86_sse2_cvtsi642sd VR128:$src1,
1536
def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1537
(outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1538
"cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1540
(int_x86_sse2_cvtsi642sd VR128:$src1,
1541
(loadi64 addr:$src2)))]>;
1544
// Signed i64 -> f32
1545
def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1546
"cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1547
[(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1548
def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1549
"cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1550
[(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1552
let isTwoAddress = 1 in {
1553
def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1554
(outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1555
"cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1557
(int_x86_sse_cvtsi642ss VR128:$src1,
1559
def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1561
(ins VR128:$src1, i64mem:$src2),
1562
"cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1564
(int_x86_sse_cvtsi642ss VR128:$src1,
1565
(loadi64 addr:$src2)))]>;
1568
// f32 -> signed i64
1569
def CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1570
"cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1571
def CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1572
"cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1573
def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1574
"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1576
(int_x86_sse_cvtss2si64 VR128:$src))]>;
1577
def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1578
"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1579
[(set GR64:$dst, (int_x86_sse_cvtss2si64
1580
(load addr:$src)))]>;
1581
def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1582
"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1583
[(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1584
def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1585
"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1586
[(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1587
def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1588
"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1590
(int_x86_sse_cvttss2si64 VR128:$src))]>;
1591
def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst),
1593
"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1595
(int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1597
// Descriptor-table support instructions
1599
// LLDT is not interpreted specially in 64-bit mode because there is no sign
1601
def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
1602
"sldt{q}\t$dst", []>, TB;
1603
def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
1604
"sldt{q}\t$dst", []>, TB;
1606
//===----------------------------------------------------------------------===//
1607
// Alias Instructions
1608
//===----------------------------------------------------------------------===//
1610
// We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
1611
// smaller encoding, but doing so at isel time interferes with rematerialization
1612
// in the current register allocator. For now, this is rewritten when the
1613
// instruction is lowered to an MCInst.
1614
// FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1615
// when we have a better way to specify isel priority.
1616
let Defs = [EFLAGS],
1617
AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1618
def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
1619
[(set GR64:$dst, 0)]>;
1621
// Materialize i64 constant where top 32-bits are zero. This could theoretically
1622
// use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
1623
// that would make it more difficult to rematerialize.
1624
let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1625
def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1626
"", [(set GR64:$dst, i64immZExt32:$src)]>;
1628
//===----------------------------------------------------------------------===//
1629
// Thread Local Storage Instructions
1630
//===----------------------------------------------------------------------===//
1632
// All calls clobber the non-callee saved registers. RSP is marked as
1633
// a use to prevent stack-pointer assignments that appear immediately
1634
// before calls from potentially appearing dead.
1635
let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1636
FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1637
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1638
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1639
XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1641
def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1643
"leaq\t$sym(%rip), %rdi; "
1646
"call\t__tls_get_addr@PLT",
1647
[(X86tlsaddr tls64addr:$sym)]>,
1648
Requires<[In64BitMode]>;
1650
let AddedComplexity = 5, isCodeGenOnly = 1 in
1651
def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1652
"movq\t%gs:$src, $dst",
1653
[(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1655
let AddedComplexity = 5, isCodeGenOnly = 1 in
1656
def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1657
"movq\t%fs:$src, $dst",
1658
[(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1660
//===----------------------------------------------------------------------===//
1661
// Atomic Instructions
1662
//===----------------------------------------------------------------------===//
1664
let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1665
def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1667
"cmpxchgq\t$swap,$ptr",
1668
[(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1671
let Constraints = "$val = $dst" in {
1672
let Defs = [EFLAGS] in
1673
def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
1676
[(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1679
def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
1680
(ins GR64:$val,i64mem:$ptr),
1681
"xchg{q}\t{$val, $ptr|$ptr, $val}",
1682
[(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1684
def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1685
"xchg{q}\t{$val, $src|$src, $val}", []>;
1688
def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1689
"xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1690
def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1691
"xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1693
def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1694
"cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1695
def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1696
"cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1698
let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1699
def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1700
"cmpxchg16b\t$dst", []>, TB;
1702
def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1703
"xchg{q}\t{$src, %rax|%rax, $src}", []>;
1705
// Optimized codegen when the non-memory output is not used.
1706
let Defs = [EFLAGS] in {
1707
// FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1708
def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1710
"add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1711
def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1712
(ins i64mem:$dst, i64i8imm :$src2),
1714
"add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1715
def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1716
(ins i64mem:$dst, i64i32imm :$src2),
1718
"add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1719
def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1721
"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1722
def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1723
(ins i64mem:$dst, i64i8imm :$src2),
1725
"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1726
def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1727
(ins i64mem:$dst, i64i32imm:$src2),
1729
"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1730
def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1732
"inc{q}\t$dst", []>, LOCK;
1733
def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1735
"dec{q}\t$dst", []>, LOCK;
1737
// Atomic exchange, and, or, xor
1738
let Constraints = "$val = $dst", Defs = [EFLAGS],
1739
usesCustomInserter = 1 in {
1740
def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1741
"#ATOMAND64 PSEUDO!",
1742
[(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1743
def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1744
"#ATOMOR64 PSEUDO!",
1745
[(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1746
def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1747
"#ATOMXOR64 PSEUDO!",
1748
[(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1749
def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1750
"#ATOMNAND64 PSEUDO!",
1751
[(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1752
def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1753
"#ATOMMIN64 PSEUDO!",
1754
[(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1755
def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1756
"#ATOMMAX64 PSEUDO!",
1757
[(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1758
def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1759
"#ATOMUMIN64 PSEUDO!",
1760
[(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1761
def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1762
"#ATOMUMAX64 PSEUDO!",
1763
[(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1766
// Segmentation support instructions
1768
// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1769
def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1770
"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1771
def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1772
"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1774
def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1775
"lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1776
def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1777
"lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1779
def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
1781
def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
1782
"push{q}\t%fs", []>, TB;
1783
def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
1784
"push{q}\t%gs", []>, TB;
1786
def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
1787
"pop{q}\t%fs", []>, TB;
1788
def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
1789
"pop{q}\t%gs", []>, TB;
1791
def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1792
"lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
1793
def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1794
"lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1795
def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1796
"lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1798
// Specialized register support
1800
// no m form encodable; use SMSW16m
1801
def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
1802
"smsw{q}\t$dst", []>, TB;
1804
// String manipulation instructions
1806
def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1808
//===----------------------------------------------------------------------===//
1809
// Non-Instruction Patterns
1810
//===----------------------------------------------------------------------===//
1812
// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1813
// code model mode, should use 'movabs'. FIXME: This is really a hack, the
1814
// 'movabs' predicate should handle this sort of thing.
1815
def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1816
(MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1817
def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1818
(MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1819
def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1820
(MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1821
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1822
(MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1823
def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1824
(MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
1826
// In static codegen with small code model, we can get the address of a label
1827
// into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1828
// the MOV64ri64i32 should accept these.
1829
def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1830
(MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1831
def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1832
(MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1833
def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1834
(MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1835
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1836
(MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1837
def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1838
(MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
1840
// In kernel code model, we can get the address of a label
1841
// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1842
// the MOV64ri32 should accept these.
1843
def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1844
(MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1845
def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1846
(MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1847
def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1848
(MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1849
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1850
(MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1851
def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1852
(MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1854
// If we have small model and -static mode, it is safe to store global addresses
1855
// directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1856
// for MOV64mi32 should handle this sort of thing.
1857
def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1858
(MOV64mi32 addr:$dst, tconstpool:$src)>,
1859
Requires<[NearData, IsStatic]>;
1860
def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1861
(MOV64mi32 addr:$dst, tjumptable:$src)>,
1862
Requires<[NearData, IsStatic]>;
1863
def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1864
(MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1865
Requires<[NearData, IsStatic]>;
1866
def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1867
(MOV64mi32 addr:$dst, texternalsym:$src)>,
1868
Requires<[NearData, IsStatic]>;
1869
def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1870
(MOV64mi32 addr:$dst, tblockaddress:$src)>,
1871
Requires<[NearData, IsStatic]>;
1874
// Direct PC relative function call for small code model. 32-bit displacement
1875
// sign extended to 64-bit.
1876
def : Pat<(X86call (i64 tglobaladdr:$dst)),
1877
(CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1878
def : Pat<(X86call (i64 texternalsym:$dst)),
1879
(CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1881
def : Pat<(X86call (i64 tglobaladdr:$dst)),
1882
(WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1883
def : Pat<(X86call (i64 texternalsym:$dst)),
1884
(WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1887
def : Pat<(X86tcret GR64:$dst, imm:$off),
1888
(TCRETURNri64 GR64:$dst, imm:$off)>;
1890
def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1891
(TCRETURNdi64 tglobaladdr:$dst, imm:$off)>;
1893
def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1894
(TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1898
// TEST R,R is smaller than CMP R,0
1899
def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1900
(TEST64rr GR64:$src1, GR64:$src1)>;
1902
// Conditional moves with folded loads with operands swapped and conditions
1904
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1905
(CMOVAE64rm GR64:$src2, addr:$src1)>;
1906
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1907
(CMOVB64rm GR64:$src2, addr:$src1)>;
1908
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1909
(CMOVNE64rm GR64:$src2, addr:$src1)>;
1910
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1911
(CMOVE64rm GR64:$src2, addr:$src1)>;
1912
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1913
(CMOVA64rm GR64:$src2, addr:$src1)>;
1914
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1915
(CMOVBE64rm GR64:$src2, addr:$src1)>;
1916
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1917
(CMOVGE64rm GR64:$src2, addr:$src1)>;
1918
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1919
(CMOVL64rm GR64:$src2, addr:$src1)>;
1920
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1921
(CMOVG64rm GR64:$src2, addr:$src1)>;
1922
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1923
(CMOVLE64rm GR64:$src2, addr:$src1)>;
1924
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1925
(CMOVNP64rm GR64:$src2, addr:$src1)>;
1926
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1927
(CMOVP64rm GR64:$src2, addr:$src1)>;
1928
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1929
(CMOVNS64rm GR64:$src2, addr:$src1)>;
1930
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1931
(CMOVS64rm GR64:$src2, addr:$src1)>;
1932
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1933
(CMOVNO64rm GR64:$src2, addr:$src1)>;
1934
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1935
(CMOVO64rm GR64:$src2, addr:$src1)>;
1937
// zextload bool -> zextload byte
1938
def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1941
// When extloading from 16-bit and smaller memory locations into 64-bit
1942
// registers, use zero-extending loads so that the entire 64-bit register is
1943
// defined, avoiding partial-register updates.
1944
def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1945
def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1946
def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1947
// For other extloads, use subregs, since the high contents of the register are
1948
// defined after an extload.
1949
def : Pat<(extloadi64i32 addr:$src),
1950
(SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1953
// anyext. Define these to do an explicit zero-extend to
1954
// avoid partial-register updates.
1955
def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1956
def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1957
def : Pat<(i64 (anyext GR32:$src)),
1958
(SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1960
//===----------------------------------------------------------------------===//
1962
//===----------------------------------------------------------------------===//
1964
// Odd encoding trick: -128 fits into an 8-bit immediate field while
1965
// +128 doesn't, so in this special case use a sub instead of an add.
1966
def : Pat<(add GR64:$src1, 128),
1967
(SUB64ri8 GR64:$src1, -128)>;
1968
def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1969
(SUB64mi8 addr:$dst, -128)>;
1971
// The same trick applies for 32-bit immediate fields in 64-bit
1973
def : Pat<(add GR64:$src1, 0x0000000080000000),
1974
(SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1975
def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1976
(SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1978
// Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
1979
// has an immediate with at least 32 bits of leading zeros, to avoid needing to
1980
// materialize that immediate in a register first.
1981
def : Pat<(and GR64:$src, i64immZExt32:$imm),
1985
(EXTRACT_SUBREG GR64:$src, x86_subreg_32bit),
1986
(i32 (GetLo32XForm imm:$imm))),
1989
// r & (2^32-1) ==> movz
1990
def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1991
(MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1992
// r & (2^16-1) ==> movz
1993
def : Pat<(and GR64:$src, 0xffff),
1994
(MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1995
// r & (2^8-1) ==> movz
1996
def : Pat<(and GR64:$src, 0xff),
1997
(MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1998
// r & (2^8-1) ==> movz
1999
def : Pat<(and GR32:$src1, 0xff),
2000
(MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
2001
Requires<[In64BitMode]>;
2002
// r & (2^8-1) ==> movz
2003
def : Pat<(and GR16:$src1, 0xff),
2004
(MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
2005
Requires<[In64BitMode]>;
2007
// sext_inreg patterns
2008
def : Pat<(sext_inreg GR64:$src, i32),
2009
(MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
2010
def : Pat<(sext_inreg GR64:$src, i16),
2011
(MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2012
def : Pat<(sext_inreg GR64:$src, i8),
2013
(MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
2014
def : Pat<(sext_inreg GR32:$src, i8),
2015
(MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
2016
Requires<[In64BitMode]>;
2017
def : Pat<(sext_inreg GR16:$src, i8),
2018
(MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
2019
Requires<[In64BitMode]>;
2022
def : Pat<(i32 (trunc GR64:$src)),
2023
(EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
2024
def : Pat<(i16 (trunc GR64:$src)),
2025
(EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
2026
def : Pat<(i8 (trunc GR64:$src)),
2027
(EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
2028
def : Pat<(i8 (trunc GR32:$src)),
2029
(EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
2030
Requires<[In64BitMode]>;
2031
def : Pat<(i8 (trunc GR16:$src)),
2032
(EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
2033
Requires<[In64BitMode]>;
2035
// h-register tricks.
2036
// For now, be conservative on x86-64 and use an h-register extract only if the
2037
// value is immediately zero-extended or stored, which are somewhat common
2038
// cases. This uses a bunch of code to prevent a register requiring a REX prefix
2039
// from being allocated in the same instruction as the h register, as there's
2040
// currently no way to describe this requirement to the register allocator.
2042
// h-register extract and zero-extend.
2043
def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
2047
(EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2048
x86_subreg_8bit_hi)),
2050
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
2052
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2053
x86_subreg_8bit_hi))>,
2054
Requires<[In64BitMode]>;
2055
def : Pat<(srl GR16:$src, (i8 8)),
2058
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2059
x86_subreg_8bit_hi)),
2061
Requires<[In64BitMode]>;
2062
def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
2064
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2065
x86_subreg_8bit_hi))>,
2066
Requires<[In64BitMode]>;
2067
def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
2069
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2070
x86_subreg_8bit_hi))>,
2071
Requires<[In64BitMode]>;
2072
def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
2076
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2077
x86_subreg_8bit_hi)),
2079
def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
2083
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2084
x86_subreg_8bit_hi)),
2087
// h-register extract and store.
2088
def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
2091
(EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2092
x86_subreg_8bit_hi))>;
2093
def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
2096
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2097
x86_subreg_8bit_hi))>,
2098
Requires<[In64BitMode]>;
2099
def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
2102
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2103
x86_subreg_8bit_hi))>,
2104
Requires<[In64BitMode]>;
2106
// (shl x, 1) ==> (add x, x)
2107
def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
2109
// (shl x (and y, 63)) ==> (shl x, y)
2110
def : Pat<(shl GR64:$src1, (and CL, 63)),
2111
(SHL64rCL GR64:$src1)>;
2112
def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2113
(SHL64mCL addr:$dst)>;
2115
def : Pat<(srl GR64:$src1, (and CL, 63)),
2116
(SHR64rCL GR64:$src1)>;
2117
def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2118
(SHR64mCL addr:$dst)>;
2120
def : Pat<(sra GR64:$src1, (and CL, 63)),
2121
(SAR64rCL GR64:$src1)>;
2122
def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2123
(SAR64mCL addr:$dst)>;
2125
// Double shift patterns
2126
def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm)),
2127
(SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
2129
def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
2130
GR64:$src2, (i8 imm)), addr:$dst),
2131
(SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
2133
def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm)),
2134
(SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
2136
def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
2137
GR64:$src2, (i8 imm)), addr:$dst),
2138
(SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
2140
// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
2141
let AddedComplexity = 5 in { // Try this before the selecting to OR
2142
def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt8:$src2),
2144
(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2145
def : Pat<(parallel (or_is_add GR64:$src1, i64immSExt32:$src2),
2147
(ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2148
def : Pat<(parallel (or_is_add GR64:$src1, GR64:$src2),
2150
(ADD64rr GR64:$src1, GR64:$src2)>;
2151
} // AddedComplexity
2153
// X86 specific add which produces a flag.
2154
def : Pat<(addc GR64:$src1, GR64:$src2),
2155
(ADD64rr GR64:$src1, GR64:$src2)>;
2156
def : Pat<(addc GR64:$src1, (load addr:$src2)),
2157
(ADD64rm GR64:$src1, addr:$src2)>;
2158
def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
2159
(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2160
def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
2161
(ADD64ri32 GR64:$src1, imm:$src2)>;
2163
def : Pat<(subc GR64:$src1, GR64:$src2),
2164
(SUB64rr GR64:$src1, GR64:$src2)>;
2165
def : Pat<(subc GR64:$src1, (load addr:$src2)),
2166
(SUB64rm GR64:$src1, addr:$src2)>;
2167
def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
2168
(SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2169
def : Pat<(subc GR64:$src1, imm:$src2),
2170
(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2172
//===----------------------------------------------------------------------===//
2173
// EFLAGS-defining Patterns
2174
//===----------------------------------------------------------------------===//
2176
// Register-Register Addition with EFLAGS result
2177
def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
2179
(ADD64rr GR64:$src1, GR64:$src2)>;
2181
// Register-Integer Addition with EFLAGS result
2182
def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
2184
(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2185
def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
2187
(ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2189
// Register-Memory Addition with EFLAGS result
2190
def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
2192
(ADD64rm GR64:$src1, addr:$src2)>;
2194
// Memory-Register Addition with EFLAGS result
2195
def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
2198
(ADD64mr addr:$dst, GR64:$src2)>;
2199
def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2202
(ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
2203
def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst),
2204
i64immSExt32:$src2),
2207
(ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
2209
// Register-Register Subtraction with EFLAGS result
2210
def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
2212
(SUB64rr GR64:$src1, GR64:$src2)>;
2214
// Register-Memory Subtraction with EFLAGS result
2215
def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
2217
(SUB64rm GR64:$src1, addr:$src2)>;
2219
// Register-Integer Subtraction with EFLAGS result
2220
def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
2222
(SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2223
def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
2225
(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2227
// Memory-Register Subtraction with EFLAGS result
2228
def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
2231
(SUB64mr addr:$dst, GR64:$src2)>;
2233
// Memory-Integer Subtraction with EFLAGS result
2234
def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2238
(SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
2239
def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2240
i64immSExt32:$src2),
2243
(SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
2245
// Register-Register Signed Integer Multiplication with EFLAGS result
2246
def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
2248
(IMUL64rr GR64:$src1, GR64:$src2)>;
2250
// Register-Memory Signed Integer Multiplication with EFLAGS result
2251
def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
2253
(IMUL64rm GR64:$src1, addr:$src2)>;
2255
// Register-Integer Signed Integer Multiplication with EFLAGS result
2256
def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
2258
(IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2259
def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
2261
(IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2263
// Memory-Integer Signed Integer Multiplication with EFLAGS result
2264
def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
2266
(IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2267
def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
2269
(IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2271
// INC and DEC with EFLAGS result. Note that these do not set CF.
2272
def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
2273
(INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2274
def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
2276
(INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2277
def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
2278
(DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2279
def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
2281
(DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2283
def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
2284
(INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2285
def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
2287
(INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2288
def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2289
(DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2290
def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2292
(DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2294
def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2295
(INC64r GR64:$src)>;
2296
def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2298
(INC64m addr:$dst)>;
2299
def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2300
(DEC64r GR64:$src)>;
2301
def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2303
(DEC64m addr:$dst)>;
2305
// Register-Register Logical Or with EFLAGS result
2306
def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
2308
(OR64rr GR64:$src1, GR64:$src2)>;
2310
// Register-Integer Logical Or with EFLAGS result
2311
def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
2313
(OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2314
def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
2316
(OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2318
// Register-Memory Logical Or with EFLAGS result
2319
def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
2321
(OR64rm GR64:$src1, addr:$src2)>;
2323
// Memory-Register Logical Or with EFLAGS result
2324
def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
2327
(OR64mr addr:$dst, GR64:$src2)>;
2328
def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2331
(OR64mi8 addr:$dst, i64immSExt8:$src2)>;
2332
def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2335
(OR64mi32 addr:$dst, i64immSExt32:$src2)>;
2337
// Register-Register Logical XOr with EFLAGS result
2338
def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
2340
(XOR64rr GR64:$src1, GR64:$src2)>;
2342
// Register-Integer Logical XOr with EFLAGS result
2343
def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
2345
(XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2346
def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
2348
(XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2350
// Register-Memory Logical XOr with EFLAGS result
2351
def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
2353
(XOR64rm GR64:$src1, addr:$src2)>;
2355
// Memory-Register Logical XOr with EFLAGS result
2356
def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
2359
(XOR64mr addr:$dst, GR64:$src2)>;
2360
def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2363
(XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
2364
def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst),
2365
i64immSExt32:$src2),
2368
(XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
2370
// Register-Register Logical And with EFLAGS result
2371
def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
2373
(AND64rr GR64:$src1, GR64:$src2)>;
2375
// Register-Integer Logical And with EFLAGS result
2376
def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
2378
(AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2379
def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
2381
(AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2383
// Register-Memory Logical And with EFLAGS result
2384
def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
2386
(AND64rm GR64:$src1, addr:$src2)>;
2388
// Memory-Register Logical And with EFLAGS result
2389
def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
2392
(AND64mr addr:$dst, GR64:$src2)>;
2393
def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2396
(AND64mi8 addr:$dst, i64immSExt8:$src2)>;
2397
def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst),
2398
i64immSExt32:$src2),
2401
(AND64mi32 addr:$dst, i64immSExt32:$src2)>;
2403
//===----------------------------------------------------------------------===//
2404
// X86-64 SSE Instructions
2405
//===----------------------------------------------------------------------===//
2407
// Move instructions...
2409
def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2410
"mov{d|q}\t{$src, $dst|$dst, $src}",
2412
(v2i64 (scalar_to_vector GR64:$src)))]>;
2413
def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2414
"mov{d|q}\t{$src, $dst|$dst, $src}",
2415
[(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2418
def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2419
"mov{d|q}\t{$src, $dst|$dst, $src}",
2420
[(set FR64:$dst, (bitconvert GR64:$src))]>;
2421
def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2422
"movq\t{$src, $dst|$dst, $src}",
2423
[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2425
def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2426
"mov{d|q}\t{$src, $dst|$dst, $src}",
2427
[(set GR64:$dst, (bitconvert FR64:$src))]>;
2428
def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2429
"movq\t{$src, $dst|$dst, $src}",
2430
[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2432
//===----------------------------------------------------------------------===//
2433
// X86-64 SSE4.1 Instructions
2434
//===----------------------------------------------------------------------===//
2436
/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2437
multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2438
def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2439
(ins VR128:$src1, i32i8imm:$src2),
2440
!strconcat(OpcodeStr,
2441
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2443
(extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2444
def mr : SS4AIi8<opc, MRMDestMem, (outs),
2445
(ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2446
!strconcat(OpcodeStr,
2447
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2448
[(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2449
addr:$dst)]>, OpSize, REX_W;
2452
defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2454
let isTwoAddress = 1 in {
2455
multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2456
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2457
(ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2458
!strconcat(OpcodeStr,
2459
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2461
(v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2463
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2464
(ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2465
!strconcat(OpcodeStr,
2466
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2468
(v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2469
imm:$src3)))]>, OpSize, REX_W;
2473
defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2475
// -disable-16bit support.
2476
def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2477
(MOV16mi addr:$dst, imm:$src)>;
2478
def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2479
(MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2480
def : Pat<(i64 (sextloadi16 addr:$dst)),
2481
(MOVSX64rm16 addr:$dst)>;
2482
def : Pat<(i64 (zextloadi16 addr:$dst)),
2483
(MOVZX64rm16 addr:$dst)>;
2484
def : Pat<(i64 (extloadi16 addr:$dst)),
2485
(MOVZX64rm16 addr:$dst)>;
added
removed
libclamav/c++/llvm/lib/Target/X86/X86Instr64bit.td
