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//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file describes the PowerPC 64-bit instructions. These patterns are used
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// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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def s16imm64 : Operand<i64> {
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let PrintMethod = "printS16ImmOperand";
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def u16imm64 : Operand<i64> {
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let PrintMethod = "printU16ImmOperand";
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def symbolHi64 : Operand<i64> {
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let PrintMethod = "printSymbolHi";
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def symbolLo64 : Operand<i64> {
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let PrintMethod = "printSymbolLo";
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//===----------------------------------------------------------------------===//
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// 64-bit transformation functions.
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def SHL64 : SDNodeXForm<imm, [{
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// Transformation function: 63 - imm
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return getI32Imm(63 - N->getZExtValue());
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def SRL64 : SDNodeXForm<imm, [{
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// Transformation function: 64 - imm
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return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
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def HI32_48 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
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def HI48_64 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
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//===----------------------------------------------------------------------===//
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def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
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let isCall = 1, PPC970_Unit = 7,
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// All calls clobber the PPC64 non-callee saved registers.
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Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
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F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
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V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
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CR0,CR1,CR5,CR6,CR7,CARRY] in {
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// Convenient aliases for call instructions
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def BL8_Darwin : IForm<18, 0, 1,
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(outs), (ins calltarget:$func, variable_ops),
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"bl $func", BrB, []>; // See Pat patterns below.
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def BLA8_Darwin : IForm<18, 1, 1,
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(outs), (ins aaddr:$func, variable_ops),
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"bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>;
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let Uses = [CTR8, RM] in {
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def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
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(outs), (ins variable_ops),
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[(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>;
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// ELF 64 ABI Calls = Darwin ABI Calls
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// Used to define BL8_ELF and BLA8_ELF
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let isCall = 1, PPC970_Unit = 7,
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// All calls clobber the PPC64 non-callee saved registers.
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Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
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F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
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V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
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CR0,CR1,CR5,CR6,CR7,CARRY] in {
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// Convenient aliases for call instructions
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def BL8_ELF : IForm<18, 0, 1,
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(outs), (ins calltarget:$func, variable_ops),
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"bl $func", BrB, []>; // See Pat patterns below.
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def BLA8_ELF : IForm<18, 1, 1,
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(outs), (ins aaddr:$func, variable_ops),
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"bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>;
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let Uses = [CTR8, RM] in {
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def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
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(outs), (ins variable_ops),
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[(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>;
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def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)),
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(BL8_Darwin tglobaladdr:$dst)>;
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def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)),
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(BL8_Darwin texternalsym:$dst)>;
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def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)),
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(BL8_ELF tglobaladdr:$dst)>;
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def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)),
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(BL8_ELF texternalsym:$dst)>;
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let usesCustomInserter = 1 in {
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let Uses = [CR0] in {
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def ATOMIC_LOAD_ADD_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
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"${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!",
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[(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_LOAD_SUB_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
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"${:comment} ATOMIC_LOAD_SUB_I64 PSEUDO!",
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[(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_LOAD_OR_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
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"${:comment} ATOMIC_LOAD_OR_I64 PSEUDO!",
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[(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_LOAD_XOR_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
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"${:comment} ATOMIC_LOAD_XOR_I64 PSEUDO!",
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[(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_LOAD_AND_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
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"${:comment} ATOMIC_LOAD_AND_I64 PSEUDO!",
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[(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_LOAD_NAND_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
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"${:comment} ATOMIC_LOAD_NAND_I64 PSEUDO!",
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[(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_CMP_SWAP_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new),
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"${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!",
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(atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
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def ATOMIC_SWAP_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
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"${:comment} ATOMIC_SWAP_I64 PSEUDO!",
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[(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
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// Instructions to support atomic operations
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def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
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"ldarx $rD, $ptr", LdStLDARX,
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[(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
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def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
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"stdcx. $rS, $dst", LdStSTDCX,
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[(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
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def TCRETURNdi8 :Pseudo< (outs),
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(ins calltarget:$dst, i32imm:$offset, variable_ops),
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"#TC_RETURNd8 $dst $offset",
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
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def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
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"#TC_RETURNa8 $func $offset",
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[(PPCtc_return (i64 imm:$func), imm:$offset)]>;
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
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def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops),
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"#TC_RETURNr8 $dst $offset",
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let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
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isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
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def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
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Requires<[In64BitMode]>;
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
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isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
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def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
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isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
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def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
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def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
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(TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
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def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
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(TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
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def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
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(TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
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//===----------------------------------------------------------------------===//
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// 64-bit SPR manipulation instrs.
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let Uses = [CTR8] in {
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def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
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"mfctr $rT", SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in {
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def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
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"mtctr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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let Defs = [X1], Uses = [X1] in
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def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),
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"${:comment} DYNALLOC8 $result, $negsize, $fpsi",
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(PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
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let Defs = [LR8] in {
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def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
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"mtlr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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let Uses = [LR8] in {
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def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
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"mflr $rT", SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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//===----------------------------------------------------------------------===//
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// Fixed point instructions.
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let PPC970_Unit = 1 in { // FXU Operations.
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// Copies, extends, truncates.
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def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
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"li $rD, $imm", IntGeneral,
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[(set G8RC:$rD, immSExt16:$imm)]>;
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def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
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"lis $rD, $imm", IntGeneral,
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[(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
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def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"nand $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
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def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"and $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
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def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"andc $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
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def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
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def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"nor $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
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def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"orc $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
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def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"eqv $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
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def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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"xor $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
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// Logical ops with immediate.
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def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
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def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"andis. $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
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def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
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def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
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def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
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def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2", IntGeneral,
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[(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
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def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"add $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
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let Defs = [CARRY] in {
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def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"addc $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
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PPC970_DGroup_Cracked;
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def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
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"addic $rD, $rA, $imm", IntGeneral,
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[(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>;
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def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
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"addi $rD, $rA, $imm", IntGeneral,
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[(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
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def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
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"addis $rD, $rA, $imm", IntGeneral,
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[(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
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let Defs = [CARRY] in {
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def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
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"subfic $rD, $rA, $imm", IntGeneral,
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[(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
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def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"subfc $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
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PPC970_DGroup_Cracked;
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def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"subf $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
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def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
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"neg $rT, $rA", IntGeneral,
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[(set G8RC:$rT, (ineg G8RC:$rA))]>;
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let Uses = [CARRY], Defs = [CARRY] in {
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def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"adde $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
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def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
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"addme $rT, $rA", IntGeneral,
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[(set G8RC:$rT, (adde G8RC:$rA, -1))]>;
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def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
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"addze $rT, $rA", IntGeneral,
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[(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
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def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"subfe $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
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def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
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"subfme $rT, $rA", IntGeneral,
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[(set G8RC:$rT, (sube -1, G8RC:$rA))]>;
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def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
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"subfze $rT, $rA", IntGeneral,
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[(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
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def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"mulhd $rT, $rA, $rB", IntMulHW,
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[(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
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def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"mulhdu $rT, $rA, $rB", IntMulHWU,
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[(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
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def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
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"cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
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def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
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"cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
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def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
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"cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
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def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
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"cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
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def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
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"sld $rA, $rS, $rB", IntRotateD,
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[(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
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def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
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"srd $rA, $rS, $rB", IntRotateD,
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[(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
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let Defs = [CARRY] in {
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def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
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"srad $rA, $rS, $rB", IntRotateD,
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[(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
413
def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
414
"extsb $rA, $rS", IntGeneral,
415
[(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
416
def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
417
"extsh $rA, $rS", IntGeneral,
418
[(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
420
def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
421
"extsw $rA, $rS", IntGeneral,
422
[(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
423
/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
424
def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
425
"extsw $rA, $rS", IntGeneral,
426
[(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
427
def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
428
"extsw $rA, $rS", IntGeneral,
429
[(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
431
let Defs = [CARRY] in {
432
def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
433
"sradi $rA, $rS, $SH", IntRotateD,
434
[(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
436
def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
437
"cntlzd $rA, $rS", IntGeneral,
438
[(set G8RC:$rA, (ctlz G8RC:$rS))]>;
440
def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
441
"divd $rT, $rA, $rB", IntDivD,
442
[(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
443
PPC970_DGroup_First, PPC970_DGroup_Cracked;
444
def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
445
"divdu $rT, $rA, $rB", IntDivD,
446
[(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
447
PPC970_DGroup_First, PPC970_DGroup_Cracked;
448
def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
449
"mulld $rT, $rA, $rB", IntMulHD,
450
[(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
453
let isCommutable = 1 in {
454
def RLDIMI : MDForm_1<30, 3,
455
(outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
456
"rldimi $rA, $rS, $SH, $MB", IntRotateD,
457
[]>, isPPC64, RegConstraint<"$rSi = $rA">,
461
// Rotate instructions.
462
def RLDCL : MDForm_1<30, 0,
463
(outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB),
464
"rldcl $rA, $rS, $rB, $MB", IntRotateD,
466
def RLDICL : MDForm_1<30, 0,
467
(outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
468
"rldicl $rA, $rS, $SH, $MB", IntRotateD,
470
def RLDICR : MDForm_1<30, 1,
471
(outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
472
"rldicr $rA, $rS, $SH, $ME", IntRotateD,
474
} // End FXU Operations.
477
//===----------------------------------------------------------------------===//
478
// Load/Store instructions.
482
// Sign extending loads.
483
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
484
def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
485
"lha $rD, $src", LdStLHA,
486
[(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
487
PPC970_DGroup_Cracked;
488
def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
489
"lwa $rD, $src", LdStLWA,
490
[(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
491
PPC970_DGroup_Cracked;
492
def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
493
"lhax $rD, $src", LdStLHA,
494
[(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
495
PPC970_DGroup_Cracked;
496
def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
497
"lwax $rD, $src", LdStLHA,
498
[(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
499
PPC970_DGroup_Cracked;
503
def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
505
"lhau $rD, $disp($rA)", LdStGeneral,
506
[]>, RegConstraint<"$rA = $ea_result">,
507
NoEncode<"$ea_result">;
512
// Zero extending loads.
513
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
514
def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
515
"lbz $rD, $src", LdStGeneral,
516
[(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
517
def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
518
"lhz $rD, $src", LdStGeneral,
519
[(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
520
def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
521
"lwz $rD, $src", LdStGeneral,
522
[(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
524
def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
525
"lbzx $rD, $src", LdStGeneral,
526
[(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
527
def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
528
"lhzx $rD, $src", LdStGeneral,
529
[(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
530
def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
531
"lwzx $rD, $src", LdStGeneral,
532
[(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
537
def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
538
"lbzu $rD, $addr", LdStGeneral,
539
[]>, RegConstraint<"$addr.reg = $ea_result">,
540
NoEncode<"$ea_result">;
541
def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
542
"lhzu $rD, $addr", LdStGeneral,
543
[]>, RegConstraint<"$addr.reg = $ea_result">,
544
NoEncode<"$ea_result">;
545
def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
546
"lwzu $rD, $addr", LdStGeneral,
547
[]>, RegConstraint<"$addr.reg = $ea_result">,
548
NoEncode<"$ea_result">;
553
// Full 8-byte loads.
554
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
555
def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
556
"ld $rD, $src", LdStLD,
557
[(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
558
def LDtoc: DSForm_1<58, 0, (outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
559
"ld $rD, $disp($reg)", LdStLD,
561
(PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
562
let RST = 2, DS = 8 in
563
def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg),
564
"ld 2, 8($reg)", LdStLD,
565
[(PPCload_toc G8RC:$reg)]>, isPPC64;
566
let RST = 2, DS = 40, RA = 1 in
567
def LDtoc_restore : DSForm_1<58, 0, (outs), (ins),
568
"ld 2, 40(1)", LdStLD,
570
def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
571
"ldx $rD, $src", LdStLD,
572
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
575
def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
576
"ldu $rD, $addr", LdStLD,
577
[]>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
578
NoEncode<"$ea_result">;
582
def : Pat<(PPCtoc_restore),
584
def : Pat<(PPCload ixaddr:$src),
586
def : Pat<(PPCload xaddr:$src),
589
let PPC970_Unit = 2 in {
590
// Truncating stores.
591
def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
592
"stb $rS, $src", LdStGeneral,
593
[(truncstorei8 G8RC:$rS, iaddr:$src)]>;
594
def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
595
"sth $rS, $src", LdStGeneral,
596
[(truncstorei16 G8RC:$rS, iaddr:$src)]>;
597
def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
598
"stw $rS, $src", LdStGeneral,
599
[(truncstorei32 G8RC:$rS, iaddr:$src)]>;
600
def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
601
"stbx $rS, $dst", LdStGeneral,
602
[(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
603
PPC970_DGroup_Cracked;
604
def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
605
"sthx $rS, $dst", LdStGeneral,
606
[(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
607
PPC970_DGroup_Cracked;
608
def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
609
"stwx $rS, $dst", LdStGeneral,
610
[(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
611
PPC970_DGroup_Cracked;
612
// Normal 8-byte stores.
613
def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
614
"std $rS, $dst", LdStSTD,
615
[(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
616
def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
617
"stdx $rS, $dst", LdStSTD,
618
[(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
619
PPC970_DGroup_Cracked;
622
let PPC970_Unit = 2 in {
624
def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
625
symbolLo:$ptroff, ptr_rc:$ptrreg),
626
"stbu $rS, $ptroff($ptrreg)", LdStGeneral,
627
[(set ptr_rc:$ea_res,
628
(pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
629
iaddroff:$ptroff))]>,
630
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
631
def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
632
symbolLo:$ptroff, ptr_rc:$ptrreg),
633
"sthu $rS, $ptroff($ptrreg)", LdStGeneral,
634
[(set ptr_rc:$ea_res,
635
(pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
636
iaddroff:$ptroff))]>,
637
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
639
def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
640
s16immX4:$ptroff, ptr_rc:$ptrreg),
641
"stdu $rS, $ptroff($ptrreg)", LdStSTD,
642
[(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
643
iaddroff:$ptroff))]>,
644
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
648
def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
649
"stdux $rS, $dst", LdStSTD,
652
// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
653
def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
654
"std $rT, $dst", LdStSTD,
655
[(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
656
def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
657
"stdx $rT, $dst", LdStSTD,
658
[(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
659
PPC970_DGroup_Cracked;
664
//===----------------------------------------------------------------------===//
665
// Floating point instructions.
669
let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
670
def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
671
"fcfid $frD, $frB", FPGeneral,
672
[(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
673
def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
674
"fctidz $frD, $frB", FPGeneral,
675
[(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
679
//===----------------------------------------------------------------------===//
680
// Instruction Patterns
683
// Extensions and truncates to/from 32-bit regs.
684
def : Pat<(i64 (zext GPRC:$in)),
685
(RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
686
def : Pat<(i64 (anyext GPRC:$in)),
687
(OR4To8 GPRC:$in, GPRC:$in)>;
688
def : Pat<(i32 (trunc G8RC:$in)),
689
(OR8To4 G8RC:$in, G8RC:$in)>;
691
// Extending loads with i64 targets.
692
def : Pat<(zextloadi1 iaddr:$src),
694
def : Pat<(zextloadi1 xaddr:$src),
696
def : Pat<(extloadi1 iaddr:$src),
698
def : Pat<(extloadi1 xaddr:$src),
700
def : Pat<(extloadi8 iaddr:$src),
702
def : Pat<(extloadi8 xaddr:$src),
704
def : Pat<(extloadi16 iaddr:$src),
706
def : Pat<(extloadi16 xaddr:$src),
708
def : Pat<(extloadi32 iaddr:$src),
710
def : Pat<(extloadi32 xaddr:$src),
713
// Standard shifts. These are represented separately from the real shifts above
714
// so that we can distinguish between shifts that allow 6-bit and 7-bit shift
716
def : Pat<(sra G8RC:$rS, GPRC:$rB),
717
(SRAD G8RC:$rS, GPRC:$rB)>;
718
def : Pat<(srl G8RC:$rS, GPRC:$rB),
719
(SRD G8RC:$rS, GPRC:$rB)>;
720
def : Pat<(shl G8RC:$rS, GPRC:$rB),
721
(SLD G8RC:$rS, GPRC:$rB)>;
724
def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
725
(RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
726
def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
727
(RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
730
def : Pat<(rotl G8RC:$in, GPRC:$sh),
731
(RLDCL G8RC:$in, GPRC:$sh, 0)>;
732
def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
733
(RLDICL G8RC:$in, imm:$imm, 0)>;
735
// Hi and Lo for Darwin Global Addresses.
736
def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
737
def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
738
def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
739
def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
740
def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
741
def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
742
def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
743
def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
744
def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
745
(ADDIS8 G8RC:$in, tglobaladdr:$g)>;
746
def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
747
(ADDIS8 G8RC:$in, tconstpool:$g)>;
748
def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
749
(ADDIS8 G8RC:$in, tjumptable:$g)>;
750
def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
751
(ADDIS8 G8RC:$in, tblockaddress:$g)>;
added
removed
libclamav/c++/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
