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//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file implements the SelectionDAG::Legalize method.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/DwarfWriter.h"
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#include "llvm/Analysis/DebugInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetSubtarget.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/LLVMContext.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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//===----------------------------------------------------------------------===//
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/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
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/// hacks on it until the target machine can handle it. This involves
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/// eliminating value sizes the machine cannot handle (promoting small sizes to
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/// large sizes or splitting up large values into small values) as well as
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/// eliminating operations the machine cannot handle.
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/// This code also does a small amount of optimization and recognition of idioms
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/// as part of its processing. For example, if a target does not support a
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/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
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/// will attempt merge setcc and brc instructions into brcc's.
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class SelectionDAGLegalize {
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CodeGenOpt::Level OptLevel;
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// Libcall insertion helpers.
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/// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
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/// legalized. We use this to ensure that calls are properly serialized
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/// against each other, including inserted libcalls.
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SDValue LastCALLSEQ_END;
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/// IsLegalizingCall - This member is used *only* for purposes of providing
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/// helpful assertions that a libcall isn't created while another call is
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/// being legalized (which could lead to non-serialized call sequences).
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bool IsLegalizingCall;
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Legal, // The target natively supports this operation.
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Promote, // This operation should be executed in a larger type.
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Expand // Try to expand this to other ops, otherwise use a libcall.
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/// ValueTypeActions - This is a bitvector that contains two bits for each
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/// value type, where the two bits correspond to the LegalizeAction enum.
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/// This can be queried with "getTypeAction(VT)".
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TargetLowering::ValueTypeActionImpl ValueTypeActions;
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/// LegalizedNodes - For nodes that are of legal width, and that have more
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/// than one use, this map indicates what regularized operand to use. This
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/// allows us to avoid legalizing the same thing more than once.
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DenseMap<SDValue, SDValue> LegalizedNodes;
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void AddLegalizedOperand(SDValue From, SDValue To) {
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LegalizedNodes.insert(std::make_pair(From, To));
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// If someone requests legalization of the new node, return itself.
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LegalizedNodes.insert(std::make_pair(To, To));
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SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
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/// getTypeAction - Return how we should legalize values of this type, either
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/// it is already legal or we need to expand it into multiple registers of
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/// smaller integer type, or we need to promote it to a larger type.
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LegalizeAction getTypeAction(EVT VT) const {
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(LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT);
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/// isTypeLegal - Return true if this type is legal on this target.
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bool isTypeLegal(EVT VT) const {
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return getTypeAction(VT) == Legal;
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/// LegalizeOp - We know that the specified value has a legal type.
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/// Recursively ensure that the operands have legal types, then return the
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SDValue LegalizeOp(SDValue O);
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SDValue OptimizeFloatStore(StoreSDNode *ST);
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/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
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/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
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/// is necessary to spill the vector being inserted into to memory, perform
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/// the insert there, and then read the result back.
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SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
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SDValue Idx, DebugLoc dl);
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SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
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SDValue Idx, DebugLoc dl);
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/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
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/// performs the same shuffe in terms of order or result bytes, but on a type
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/// whose vector element type is narrower than the original shuffle type.
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/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
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SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
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SDValue N1, SDValue N2,
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SmallVectorImpl<int> &Mask) const;
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bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
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SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
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void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
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SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
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SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
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RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
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RTLIB::Libcall Call_PPCF128);
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SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
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RTLIB::Libcall Call_I8,
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RTLIB::Libcall Call_I16,
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RTLIB::Libcall Call_I32,
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RTLIB::Libcall Call_I64,
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RTLIB::Libcall Call_I128);
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SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
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SDValue ExpandBUILD_VECTOR(SDNode *Node);
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SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
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void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
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SmallVectorImpl<SDValue> &Results);
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SDValue ExpandFCOPYSIGN(SDNode *Node);
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SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
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SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
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SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
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SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
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SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
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SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
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SDValue ExpandVectorBuildThroughStack(SDNode* Node);
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void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
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void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
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/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
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/// performs the same shuffe in terms of order or result bytes, but on a type
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/// whose vector element type is narrower than the original shuffle type.
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/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
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SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
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SDValue N1, SDValue N2,
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SmallVectorImpl<int> &Mask) const {
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unsigned NumMaskElts = VT.getVectorNumElements();
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unsigned NumDestElts = NVT.getVectorNumElements();
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unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
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assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
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if (NumEltsGrowth == 1)
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return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
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SmallVector<int, 8> NewMask;
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for (unsigned i = 0; i != NumMaskElts; ++i) {
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for (unsigned j = 0; j != NumEltsGrowth; ++j) {
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NewMask.push_back(-1);
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NewMask.push_back(Idx * NumEltsGrowth + j);
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assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
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assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
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return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
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SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
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CodeGenOpt::Level ol)
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: TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
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ValueTypeActions(TLI.getValueTypeActions()) {
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assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
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"Too many value types for ValueTypeActions to hold!");
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void SelectionDAGLegalize::LegalizeDAG() {
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LastCALLSEQ_END = DAG.getEntryNode();
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IsLegalizingCall = false;
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// The legalize process is inherently a bottom-up recursive process (users
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// legalize their uses before themselves). Given infinite stack space, we
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// could just start legalizing on the root and traverse the whole graph. In
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// practice however, this causes us to run out of stack space on large basic
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// blocks. To avoid this problem, compute an ordering of the nodes where each
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// node is only legalized after all of its operands are legalized.
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DAG.AssignTopologicalOrder();
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for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
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E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
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LegalizeOp(SDValue(I, 0));
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// Finally, it's possible the root changed. Get the new root.
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SDValue OldRoot = DAG.getRoot();
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assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
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DAG.setRoot(LegalizedNodes[OldRoot]);
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LegalizedNodes.clear();
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// Remove dead nodes now.
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DAG.RemoveDeadNodes();
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/// FindCallEndFromCallStart - Given a chained node that is part of a call
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/// sequence, find the CALLSEQ_END node that terminates the call sequence.
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static SDNode *FindCallEndFromCallStart(SDNode *Node) {
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if (Node->getOpcode() == ISD::CALLSEQ_END)
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if (Node->use_empty())
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return 0; // No CallSeqEnd
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// The chain is usually at the end.
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SDValue TheChain(Node, Node->getNumValues()-1);
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if (TheChain.getValueType() != MVT::Other) {
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// Sometimes it's at the beginning.
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TheChain = SDValue(Node, 0);
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if (TheChain.getValueType() != MVT::Other) {
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// Otherwise, hunt for it.
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for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
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if (Node->getValueType(i) == MVT::Other) {
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TheChain = SDValue(Node, i);
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// Otherwise, we walked into a node without a chain.
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if (TheChain.getValueType() != MVT::Other)
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for (SDNode::use_iterator UI = Node->use_begin(),
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E = Node->use_end(); UI != E; ++UI) {
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// Make sure to only follow users of our token chain.
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for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
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if (User->getOperand(i) == TheChain)
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if (SDNode *Result = FindCallEndFromCallStart(User))
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/// FindCallStartFromCallEnd - Given a chained node that is part of a call
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/// sequence, find the CALLSEQ_START node that initiates the call sequence.
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static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
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assert(Node && "Didn't find callseq_start for a call??");
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if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
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assert(Node->getOperand(0).getValueType() == MVT::Other &&
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"Node doesn't have a token chain argument!");
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return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
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/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
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/// see if any uses can reach Dest. If no dest operands can get to dest,
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/// legalize them, legalize ourself, and return false, otherwise, return true.
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/// Keep track of the nodes we fine that actually do lead to Dest in
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/// NodesLeadingTo. This avoids retraversing them exponential number of times.
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bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
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SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
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if (N == Dest) return true; // N certainly leads to Dest :)
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// If we've already processed this node and it does lead to Dest, there is no
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// need to reprocess it.
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if (NodesLeadingTo.count(N)) return true;
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// If the first result of this node has been already legalized, then it cannot
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if (LegalizedNodes.count(SDValue(N, 0))) return false;
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// Okay, this node has not already been legalized. Check and legalize all
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// operands. If none lead to Dest, then we can legalize this node.
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bool OperandsLeadToDest = false;
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
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OperandsLeadToDest |= // If an operand leads to Dest, so do we.
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LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
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if (OperandsLeadToDest) {
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NodesLeadingTo.insert(N);
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// Okay, this node looks safe, legalize it and return false.
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LegalizeOp(SDValue(N, 0));
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/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
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/// a load from the constant pool.
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static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
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SelectionDAG &DAG, const TargetLowering &TLI) {
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DebugLoc dl = CFP->getDebugLoc();
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// If a FP immediate is precise when represented as a float and if the
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// target can do an extending load from float to double, we put it into
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// the constant pool as a float, even if it's is statically typed as a
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// double. This shrinks FP constants and canonicalizes them for targets where
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// an FP extending load is the same cost as a normal load (such as on the x87
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// fp stack or PPC FP unit).
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EVT VT = CFP->getValueType(0);
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ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
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assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
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return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
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(VT == MVT::f64) ? MVT::i64 : MVT::i32);
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while (SVT != MVT::f32) {
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SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
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if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
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// Only do this if the target has a native EXTLOAD instruction from
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TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
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TLI.ShouldShrinkFPConstant(OrigVT)) {
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const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
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LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
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SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
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unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
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return DAG.getExtLoad(ISD::EXTLOAD, dl,
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OrigVT, DAG.getEntryNode(),
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CPIdx, PseudoSourceValue::getConstantPool(),
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0, VT, false, false, Alignment);
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return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
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PseudoSourceValue::getConstantPool(), 0, false, false,
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/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
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SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
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const TargetLowering &TLI) {
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SDValue Chain = ST->getChain();
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SDValue Ptr = ST->getBasePtr();
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SDValue Val = ST->getValue();
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EVT VT = Val.getValueType();
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int Alignment = ST->getAlignment();
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int SVOffset = ST->getSrcValueOffset();
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DebugLoc dl = ST->getDebugLoc();
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if (ST->getMemoryVT().isFloatingPoint() ||
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ST->getMemoryVT().isVector()) {
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EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
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if (TLI.isTypeLegal(intVT)) {
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// Expand to a bitconvert of the value to the integer type of the
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// same size, then a (misaligned) int store.
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// FIXME: Does not handle truncating floating point stores!
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SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
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return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
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SVOffset, ST->isVolatile(), ST->isNonTemporal(),
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// Do a (aligned) store to a stack slot, then copy from the stack slot
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// to the final destination using (unaligned) integer loads and stores.
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EVT StoredVT = ST->getMemoryVT();
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TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits()));
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unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
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unsigned RegBytes = RegVT.getSizeInBits() / 8;
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unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
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// Make sure the stack slot is also aligned for the register type.
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SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
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// Perform the original store, only redirected to the stack slot.
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SDValue Store = DAG.getTruncStore(Chain, dl,
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Val, StackPtr, NULL, 0, StoredVT,
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SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
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SmallVector<SDValue, 8> Stores;
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// Do all but one copies using the full register width.
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for (unsigned i = 1; i < NumRegs; i++) {
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// Load one integer register's worth from the stack slot.
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SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0,
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// Store it to the final location. Remember the store.
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Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
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ST->getSrcValue(), SVOffset + Offset,
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ST->isVolatile(), ST->isNonTemporal(),
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MinAlign(ST->getAlignment(), Offset)));
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// Increment the pointers.
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StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
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// The last store may be partial. Do a truncating store. On big-endian
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// machines this requires an extending load from the stack slot to ensure
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// that the bits are in the right place.
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EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset));
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// Load from the stack slot.
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SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
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NULL, 0, MemVT, false, false, 0);
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Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
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ST->getSrcValue(), SVOffset + Offset,
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MemVT, ST->isVolatile(),
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MinAlign(ST->getAlignment(), Offset)));
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// The order of the stores doesn't matter - say it with a TokenFactor.
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return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
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assert(ST->getMemoryVT().isInteger() &&
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!ST->getMemoryVT().isVector() &&
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"Unaligned store of unknown type.");
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// Get the half-size VT
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EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
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int NumBits = NewStoredVT.getSizeInBits();
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int IncrementSize = NumBits / 8;
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// Divide the stored value in two parts.
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SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
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SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
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// Store the two parts
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SDValue Store1, Store2;
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Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
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ST->getSrcValue(), SVOffset, NewStoredVT,
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ST->isVolatile(), ST->isNonTemporal(), Alignment);
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, TLI.getPointerTy()));
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Alignment = MinAlign(Alignment, IncrementSize);
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Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
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ST->getSrcValue(), SVOffset + IncrementSize,
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NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
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return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
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/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
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SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
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const TargetLowering &TLI) {
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int SVOffset = LD->getSrcValueOffset();
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SDValue Chain = LD->getChain();
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SDValue Ptr = LD->getBasePtr();
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EVT VT = LD->getValueType(0);
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EVT LoadedVT = LD->getMemoryVT();
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DebugLoc dl = LD->getDebugLoc();
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if (VT.isFloatingPoint() || VT.isVector()) {
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EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
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if (TLI.isTypeLegal(intVT)) {
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// Expand to a (misaligned) integer load of the same size,
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// then bitconvert to floating point or vector.
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SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
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SVOffset, LD->isVolatile(),
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LD->isNonTemporal(), LD->getAlignment());
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SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
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if (VT.isFloatingPoint() && LoadedVT != VT)
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Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
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SDValue Ops[] = { Result, Chain };
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return DAG.getMergeValues(Ops, 2, dl);
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// Copy the value to a (aligned) stack slot using (unaligned) integer
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// loads and stores, then do a (aligned) load from the stack slot.
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EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
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unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
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unsigned RegBytes = RegVT.getSizeInBits() / 8;
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unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
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// Make sure the stack slot is also aligned for the register type.
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SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
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SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
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SmallVector<SDValue, 8> Stores;
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SDValue StackPtr = StackBase;
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// Do all but one copies using the full register width.
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for (unsigned i = 1; i < NumRegs; i++) {
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// Load one integer register's worth from the original location.
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SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
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SVOffset + Offset, LD->isVolatile(),
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MinAlign(LD->getAlignment(), Offset));
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// Follow the load with a store to the stack slot. Remember the store.
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Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
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NULL, 0, false, false, 0));
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// Increment the pointers.
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
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StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
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// The last copy may be partial. Do an extending load.
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EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset));
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SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
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LD->getSrcValue(), SVOffset + Offset,
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MemVT, LD->isVolatile(),
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MinAlign(LD->getAlignment(), Offset));
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// Follow the load with a store to the stack slot. Remember the store.
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// On big-endian machines this requires a truncating store to ensure
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// that the bits end up in the right place.
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Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
562
NULL, 0, MemVT, false, false, 0));
564
// The order of the stores doesn't matter - say it with a TokenFactor.
565
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
568
// Finally, perform the original load only redirected to the stack slot.
569
Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
570
NULL, 0, LoadedVT, false, false, 0);
572
// Callers expect a MERGE_VALUES node.
573
SDValue Ops[] = { Load, TF };
574
return DAG.getMergeValues(Ops, 2, dl);
577
assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
578
"Unaligned load of unsupported type.");
580
// Compute the new VT that is half the size of the old one. This is an
582
unsigned NumBits = LoadedVT.getSizeInBits();
584
NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
587
unsigned Alignment = LD->getAlignment();
588
unsigned IncrementSize = NumBits / 8;
589
ISD::LoadExtType HiExtType = LD->getExtensionType();
591
// If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
592
if (HiExtType == ISD::NON_EXTLOAD)
593
HiExtType = ISD::ZEXTLOAD;
595
// Load the value in two parts
597
if (TLI.isLittleEndian()) {
598
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
599
SVOffset, NewLoadedVT, LD->isVolatile(),
600
LD->isNonTemporal(), Alignment);
601
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
602
DAG.getConstant(IncrementSize, TLI.getPointerTy()));
603
Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
604
SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
605
LD->isNonTemporal(), MinAlign(Alignment, IncrementSize));
607
Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
608
SVOffset, NewLoadedVT, LD->isVolatile(),
609
LD->isNonTemporal(), Alignment);
610
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
611
DAG.getConstant(IncrementSize, TLI.getPointerTy()));
612
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
613
SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
614
LD->isNonTemporal(), MinAlign(Alignment, IncrementSize));
617
// aggregate the two parts
618
SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
619
SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
620
Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
622
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
625
SDValue Ops[] = { Result, TF };
626
return DAG.getMergeValues(Ops, 2, dl);
629
/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
630
/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
631
/// is necessary to spill the vector being inserted into to memory, perform
632
/// the insert there, and then read the result back.
633
SDValue SelectionDAGLegalize::
634
PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
640
// If the target doesn't support this, we have to spill the input vector
641
// to a temporary stack slot, update the element, then reload it. This is
642
// badness. We could also load the value into a vector register (either
643
// with a "move to register" or "extload into register" instruction, then
644
// permute it into place, if the idx is a constant and if the idx is
645
// supported by the target.
646
EVT VT = Tmp1.getValueType();
647
EVT EltVT = VT.getVectorElementType();
648
EVT IdxVT = Tmp3.getValueType();
649
EVT PtrVT = TLI.getPointerTy();
650
SDValue StackPtr = DAG.CreateStackTemporary(VT);
652
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
655
SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
656
PseudoSourceValue::getFixedStack(SPFI), 0,
659
// Truncate or zero extend offset to target pointer type.
660
unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
661
Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
662
// Add the offset to the index.
663
unsigned EltSize = EltVT.getSizeInBits()/8;
664
Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
665
SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
666
// Store the scalar value.
667
Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
668
PseudoSourceValue::getFixedStack(SPFI), 0, EltVT,
670
// Load the updated vector.
671
return DAG.getLoad(VT, dl, Ch, StackPtr,
672
PseudoSourceValue::getFixedStack(SPFI), 0,
677
SDValue SelectionDAGLegalize::
678
ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
679
if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
680
// SCALAR_TO_VECTOR requires that the type of the value being inserted
681
// match the element type of the vector being created, except for
682
// integers in which case the inserted value can be over width.
683
EVT EltVT = Vec.getValueType().getVectorElementType();
684
if (Val.getValueType() == EltVT ||
685
(EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
686
SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
687
Vec.getValueType(), Val);
689
unsigned NumElts = Vec.getValueType().getVectorNumElements();
690
// We generate a shuffle of InVec and ScVec, so the shuffle mask
691
// should be 0,1,2,3,4,5... with the appropriate element replaced with
693
SmallVector<int, 8> ShufOps;
694
for (unsigned i = 0; i != NumElts; ++i)
695
ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
697
return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
701
return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
704
SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
705
// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
706
// FIXME: We shouldn't do this for TargetConstantFP's.
707
// FIXME: move this to the DAG Combiner! Note that we can't regress due
708
// to phase ordering between legalized code and the dag combiner. This
709
// probably means that we need to integrate dag combiner and legalizer
711
// We generally can't do this one for long doubles.
712
SDValue Tmp1 = ST->getChain();
713
SDValue Tmp2 = ST->getBasePtr();
715
int SVOffset = ST->getSrcValueOffset();
716
unsigned Alignment = ST->getAlignment();
717
bool isVolatile = ST->isVolatile();
718
bool isNonTemporal = ST->isNonTemporal();
719
DebugLoc dl = ST->getDebugLoc();
720
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
721
if (CFP->getValueType(0) == MVT::f32 &&
722
getTypeAction(MVT::i32) == Legal) {
723
Tmp3 = DAG.getConstant(CFP->getValueAPF().
724
bitcastToAPInt().zextOrTrunc(32),
726
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
727
SVOffset, isVolatile, isNonTemporal, Alignment);
728
} else if (CFP->getValueType(0) == MVT::f64) {
729
// If this target supports 64-bit registers, do a single 64-bit store.
730
if (getTypeAction(MVT::i64) == Legal) {
731
Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
732
zextOrTrunc(64), MVT::i64);
733
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
734
SVOffset, isVolatile, isNonTemporal, Alignment);
735
} else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
736
// Otherwise, if the target supports 32-bit registers, use 2 32-bit
737
// stores. If the target supports neither 32- nor 64-bits, this
738
// xform is certainly not worth it.
739
const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
740
SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
741
SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
742
if (TLI.isBigEndian()) std::swap(Lo, Hi);
744
Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
745
SVOffset, isVolatile, isNonTemporal, Alignment);
746
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
747
DAG.getIntPtrConstant(4));
748
Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
749
isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
751
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
758
/// LegalizeOp - We know that the specified value has a legal type, and
759
/// that its operands are legal. Now ensure that the operation itself
760
/// is legal, recursively ensuring that the operands' operations remain
762
SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
763
if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
766
SDNode *Node = Op.getNode();
767
DebugLoc dl = Node->getDebugLoc();
769
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
770
assert(getTypeAction(Node->getValueType(i)) == Legal &&
771
"Unexpected illegal type!");
773
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
774
assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
775
Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
776
"Unexpected illegal type!");
778
// Note that LegalizeOp may be reentered even from single-use nodes, which
779
// means that we always must cache transformed nodes.
780
DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
781
if (I != LegalizedNodes.end()) return I->second;
783
SDValue Tmp1, Tmp2, Tmp3, Tmp4;
785
bool isCustom = false;
787
// Figure out the correct action; the way to query this varies by opcode
788
TargetLowering::LegalizeAction Action;
789
bool SimpleFinishLegalizing = true;
790
switch (Node->getOpcode()) {
791
case ISD::INTRINSIC_W_CHAIN:
792
case ISD::INTRINSIC_WO_CHAIN:
793
case ISD::INTRINSIC_VOID:
796
Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
798
case ISD::SINT_TO_FP:
799
case ISD::UINT_TO_FP:
800
case ISD::EXTRACT_VECTOR_ELT:
801
Action = TLI.getOperationAction(Node->getOpcode(),
802
Node->getOperand(0).getValueType());
804
case ISD::FP_ROUND_INREG:
805
case ISD::SIGN_EXTEND_INREG: {
806
EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
807
Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
813
unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
814
Node->getOpcode() == ISD::SETCC ? 2 : 1;
815
unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
816
EVT OpVT = Node->getOperand(CompareOperand).getValueType();
817
ISD::CondCode CCCode =
818
cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
819
Action = TLI.getCondCodeAction(CCCode, OpVT);
820
if (Action == TargetLowering::Legal) {
821
if (Node->getOpcode() == ISD::SELECT_CC)
822
Action = TLI.getOperationAction(Node->getOpcode(),
823
Node->getValueType(0));
825
Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
831
// FIXME: Model these properly. LOAD and STORE are complicated, and
832
// STORE expects the unlegalized operand in some cases.
833
SimpleFinishLegalizing = false;
835
case ISD::CALLSEQ_START:
836
case ISD::CALLSEQ_END:
837
// FIXME: This shouldn't be necessary. These nodes have special properties
838
// dealing with the recursive nature of legalization. Removing this
839
// special case should be done as part of making LegalizeDAG non-recursive.
840
SimpleFinishLegalizing = false;
842
case ISD::EXTRACT_ELEMENT:
843
case ISD::FLT_ROUNDS_:
851
case ISD::MERGE_VALUES:
853
case ISD::FRAME_TO_ARGS_OFFSET:
854
// These operations lie about being legal: when they claim to be legal,
855
// they should actually be expanded.
856
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
857
if (Action == TargetLowering::Legal)
858
Action = TargetLowering::Expand;
860
case ISD::TRAMPOLINE:
862
case ISD::RETURNADDR:
863
// These operations lie about being legal: when they claim to be legal,
864
// they should actually be custom-lowered.
865
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
866
if (Action == TargetLowering::Legal)
867
Action = TargetLowering::Custom;
869
case ISD::BUILD_VECTOR:
870
// A weird case: legalization for BUILD_VECTOR never legalizes the
872
// FIXME: This really sucks... changing it isn't semantically incorrect,
873
// but it massively pessimizes the code for floating-point BUILD_VECTORs
874
// because ConstantFP operands get legalized into constant pool loads
875
// before the BUILD_VECTOR code can see them. It doesn't usually bite,
876
// though, because BUILD_VECTORS usually get lowered into other nodes
877
// which get legalized properly.
878
SimpleFinishLegalizing = false;
881
if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
882
Action = TargetLowering::Legal;
884
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
889
if (SimpleFinishLegalizing) {
890
SmallVector<SDValue, 8> Ops, ResultVals;
891
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
892
Ops.push_back(LegalizeOp(Node->getOperand(i)));
893
switch (Node->getOpcode()) {
900
// Branches tweak the chain to include LastCALLSEQ_END
901
Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
903
Ops[0] = LegalizeOp(Ops[0]);
904
LastCALLSEQ_END = DAG.getEntryNode();
911
// Legalizing shifts/rotates requires adjusting the shift amount
912
// to the appropriate width.
913
if (!Ops[1].getValueType().isVector())
914
Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
919
// Legalizing shifts/rotates requires adjusting the shift amount
920
// to the appropriate width.
921
if (!Ops[2].getValueType().isVector())
922
Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
926
Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
929
case TargetLowering::Legal:
930
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
931
ResultVals.push_back(Result.getValue(i));
933
case TargetLowering::Custom:
934
// FIXME: The handling for custom lowering with multiple results is
936
Tmp1 = TLI.LowerOperation(Result, DAG);
937
if (Tmp1.getNode()) {
938
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
940
ResultVals.push_back(Tmp1);
942
ResultVals.push_back(Tmp1.getValue(i));
948
case TargetLowering::Expand:
949
ExpandNode(Result.getNode(), ResultVals);
951
case TargetLowering::Promote:
952
PromoteNode(Result.getNode(), ResultVals);
955
if (!ResultVals.empty()) {
956
for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
957
if (ResultVals[i] != SDValue(Node, i))
958
ResultVals[i] = LegalizeOp(ResultVals[i]);
959
AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
961
return ResultVals[Op.getResNo()];
965
switch (Node->getOpcode()) {
972
llvm_unreachable("Do not know how to legalize this operator!");
974
case ISD::BUILD_VECTOR:
975
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
976
default: llvm_unreachable("This action is not supported yet!");
977
case TargetLowering::Custom:
978
Tmp3 = TLI.LowerOperation(Result, DAG);
979
if (Tmp3.getNode()) {
984
case TargetLowering::Expand:
985
Result = ExpandBUILD_VECTOR(Result.getNode());
989
case ISD::CALLSEQ_START: {
990
SDNode *CallEnd = FindCallEndFromCallStart(Node);
992
// Recursively Legalize all of the inputs of the call end that do not lead
993
// to this call start. This ensures that any libcalls that need be inserted
994
// are inserted *before* the CALLSEQ_START.
995
{SmallPtrSet<SDNode*, 32> NodesLeadingTo;
996
for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
997
LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1001
// Now that we legalized all of the inputs (which may have inserted
1002
// libcalls) create the new CALLSEQ_START node.
1003
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1005
// Merge in the last call, to ensure that this call start after the last
1007
if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1008
Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1009
Tmp1, LastCALLSEQ_END);
1010
Tmp1 = LegalizeOp(Tmp1);
1013
// Do not try to legalize the target-specific arguments (#1+).
1014
if (Tmp1 != Node->getOperand(0)) {
1015
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1017
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1020
// Remember that the CALLSEQ_START is legalized.
1021
AddLegalizedOperand(Op.getValue(0), Result);
1022
if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1023
AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1025
// Now that the callseq_start and all of the non-call nodes above this call
1026
// sequence have been legalized, legalize the call itself. During this
1027
// process, no libcalls can/will be inserted, guaranteeing that no calls
1029
assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1030
// Note that we are selecting this call!
1031
LastCALLSEQ_END = SDValue(CallEnd, 0);
1032
IsLegalizingCall = true;
1034
// Legalize the call, starting from the CALLSEQ_END.
1035
LegalizeOp(LastCALLSEQ_END);
1036
assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1039
case ISD::CALLSEQ_END:
1040
// If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1041
// will cause this node to be legalized as well as handling libcalls right.
1042
if (LastCALLSEQ_END.getNode() != Node) {
1043
LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1044
DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1045
assert(I != LegalizedNodes.end() &&
1046
"Legalizing the call start should have legalized this node!");
1050
// Otherwise, the call start has been legalized and everything is going
1051
// according to plan. Just legalize ourselves normally here.
1052
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1053
// Do not try to legalize the target-specific arguments (#1+), except for
1054
// an optional flag input.
1055
if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1056
if (Tmp1 != Node->getOperand(0)) {
1057
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1059
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1062
Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1063
if (Tmp1 != Node->getOperand(0) ||
1064
Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1065
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1068
Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1071
assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1072
// This finishes up call legalization.
1073
IsLegalizingCall = false;
1075
// If the CALLSEQ_END node has a flag, remember that we legalized it.
1076
AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1077
if (Node->getNumValues() == 2)
1078
AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1079
return Result.getValue(Op.getResNo());
1081
LoadSDNode *LD = cast<LoadSDNode>(Node);
1082
Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1083
Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1085
ISD::LoadExtType ExtType = LD->getExtensionType();
1086
if (ExtType == ISD::NON_EXTLOAD) {
1087
EVT VT = Node->getValueType(0);
1088
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1089
Tmp3 = Result.getValue(0);
1090
Tmp4 = Result.getValue(1);
1092
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1093
default: llvm_unreachable("This action is not supported yet!");
1094
case TargetLowering::Legal:
1095
// If this is an unaligned load and the target doesn't support it,
1097
if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1098
const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1099
unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1100
if (LD->getAlignment() < ABIAlignment){
1101
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1103
Tmp3 = Result.getOperand(0);
1104
Tmp4 = Result.getOperand(1);
1105
Tmp3 = LegalizeOp(Tmp3);
1106
Tmp4 = LegalizeOp(Tmp4);
1110
case TargetLowering::Custom:
1111
Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1112
if (Tmp1.getNode()) {
1113
Tmp3 = LegalizeOp(Tmp1);
1114
Tmp4 = LegalizeOp(Tmp1.getValue(1));
1117
case TargetLowering::Promote: {
1118
// Only promote a load of vector type to another.
1119
assert(VT.isVector() && "Cannot promote this load!");
1120
// Change base type to a different vector type.
1121
EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1123
Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1124
LD->getSrcValueOffset(),
1125
LD->isVolatile(), LD->isNonTemporal(),
1126
LD->getAlignment());
1127
Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1128
Tmp4 = LegalizeOp(Tmp1.getValue(1));
1132
// Since loads produce two values, make sure to remember that we
1133
// legalized both of them.
1134
AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1135
AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1136
return Op.getResNo() ? Tmp4 : Tmp3;
1138
EVT SrcVT = LD->getMemoryVT();
1139
unsigned SrcWidth = SrcVT.getSizeInBits();
1140
int SVOffset = LD->getSrcValueOffset();
1141
unsigned Alignment = LD->getAlignment();
1142
bool isVolatile = LD->isVolatile();
1143
bool isNonTemporal = LD->isNonTemporal();
1145
if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1146
// Some targets pretend to have an i1 loading operation, and actually
1147
// load an i8. This trick is correct for ZEXTLOAD because the top 7
1148
// bits are guaranteed to be zero; it helps the optimizers understand
1149
// that these bits are zero. It is also useful for EXTLOAD, since it
1150
// tells the optimizers that those bits are undefined. It would be
1151
// nice to have an effective generic way of getting these benefits...
1152
// Until such a way is found, don't insist on promoting i1 here.
1153
(SrcVT != MVT::i1 ||
1154
TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1155
// Promote to a byte-sized load if not loading an integral number of
1156
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1157
unsigned NewWidth = SrcVT.getStoreSizeInBits();
1158
EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1161
// The extra bits are guaranteed to be zero, since we stored them that
1162
// way. A zext load from NVT thus automatically gives zext from SrcVT.
1164
ISD::LoadExtType NewExtType =
1165
ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1167
Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1168
Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1169
NVT, isVolatile, isNonTemporal, Alignment);
1171
Ch = Result.getValue(1); // The chain.
1173
if (ExtType == ISD::SEXTLOAD)
1174
// Having the top bits zero doesn't help when sign extending.
1175
Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1176
Result.getValueType(),
1177
Result, DAG.getValueType(SrcVT));
1178
else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1179
// All the top bits are guaranteed to be zero - inform the optimizers.
1180
Result = DAG.getNode(ISD::AssertZext, dl,
1181
Result.getValueType(), Result,
1182
DAG.getValueType(SrcVT));
1184
Tmp1 = LegalizeOp(Result);
1185
Tmp2 = LegalizeOp(Ch);
1186
} else if (SrcWidth & (SrcWidth - 1)) {
1187
// If not loading a power-of-2 number of bits, expand as two loads.
1188
assert(!SrcVT.isVector() && "Unsupported extload!");
1189
unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1190
assert(RoundWidth < SrcWidth);
1191
unsigned ExtraWidth = SrcWidth - RoundWidth;
1192
assert(ExtraWidth < RoundWidth);
1193
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1194
"Load size not an integral number of bytes!");
1195
EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1196
EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1198
unsigned IncrementSize;
1200
if (TLI.isLittleEndian()) {
1201
// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1202
// Load the bottom RoundWidth bits.
1203
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1204
Node->getValueType(0), Tmp1, Tmp2,
1205
LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1206
isNonTemporal, Alignment);
1208
// Load the remaining ExtraWidth bits.
1209
IncrementSize = RoundWidth / 8;
1210
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1211
DAG.getIntPtrConstant(IncrementSize));
1212
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1213
LD->getSrcValue(), SVOffset + IncrementSize,
1214
ExtraVT, isVolatile, isNonTemporal,
1215
MinAlign(Alignment, IncrementSize));
1217
// Build a factor node to remember that this load is independent of the
1219
Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1222
// Move the top bits to the right place.
1223
Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1224
DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1226
// Join the hi and lo parts.
1227
Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1229
// Big endian - avoid unaligned loads.
1230
// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1231
// Load the top RoundWidth bits.
1232
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1233
LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1234
isNonTemporal, Alignment);
1236
// Load the remaining ExtraWidth bits.
1237
IncrementSize = RoundWidth / 8;
1238
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1239
DAG.getIntPtrConstant(IncrementSize));
1240
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1241
Node->getValueType(0), Tmp1, Tmp2,
1242
LD->getSrcValue(), SVOffset + IncrementSize,
1243
ExtraVT, isVolatile, isNonTemporal,
1244
MinAlign(Alignment, IncrementSize));
1246
// Build a factor node to remember that this load is independent of the
1248
Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1251
// Move the top bits to the right place.
1252
Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1253
DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1255
// Join the hi and lo parts.
1256
Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1259
Tmp1 = LegalizeOp(Result);
1260
Tmp2 = LegalizeOp(Ch);
1262
switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1263
default: llvm_unreachable("This action is not supported yet!");
1264
case TargetLowering::Custom:
1267
case TargetLowering::Legal:
1268
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1269
Tmp1 = Result.getValue(0);
1270
Tmp2 = Result.getValue(1);
1273
Tmp3 = TLI.LowerOperation(Result, DAG);
1274
if (Tmp3.getNode()) {
1275
Tmp1 = LegalizeOp(Tmp3);
1276
Tmp2 = LegalizeOp(Tmp3.getValue(1));
1279
// If this is an unaligned load and the target doesn't support it,
1281
if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1282
const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1283
unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1284
if (LD->getAlignment() < ABIAlignment){
1285
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1287
Tmp1 = Result.getOperand(0);
1288
Tmp2 = Result.getOperand(1);
1289
Tmp1 = LegalizeOp(Tmp1);
1290
Tmp2 = LegalizeOp(Tmp2);
1295
case TargetLowering::Expand:
1296
// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1297
// f128 = EXTLOAD {f32,f64} too
1298
if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 ||
1299
Node->getValueType(0) == MVT::f128)) ||
1300
(SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) {
1301
SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1302
LD->getSrcValueOffset(),
1303
LD->isVolatile(), LD->isNonTemporal(),
1304
LD->getAlignment());
1305
Result = DAG.getNode(ISD::FP_EXTEND, dl,
1306
Node->getValueType(0), Load);
1307
Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1308
Tmp2 = LegalizeOp(Load.getValue(1));
1311
assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1312
// Turn the unsupported load into an EXTLOAD followed by an explicit
1313
// zero/sign extend inreg.
1314
Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1315
Tmp1, Tmp2, LD->getSrcValue(),
1316
LD->getSrcValueOffset(), SrcVT,
1317
LD->isVolatile(), LD->isNonTemporal(),
1318
LD->getAlignment());
1320
if (ExtType == ISD::SEXTLOAD)
1321
ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1322
Result.getValueType(),
1323
Result, DAG.getValueType(SrcVT));
1325
ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1326
Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1327
Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1332
// Since loads produce two values, make sure to remember that we legalized
1334
AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1335
AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1336
return Op.getResNo() ? Tmp2 : Tmp1;
1340
StoreSDNode *ST = cast<StoreSDNode>(Node);
1341
Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1342
Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1343
int SVOffset = ST->getSrcValueOffset();
1344
unsigned Alignment = ST->getAlignment();
1345
bool isVolatile = ST->isVolatile();
1346
bool isNonTemporal = ST->isNonTemporal();
1348
if (!ST->isTruncatingStore()) {
1349
if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1350
Result = SDValue(OptStore, 0);
1355
Tmp3 = LegalizeOp(ST->getValue());
1356
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1359
EVT VT = Tmp3.getValueType();
1360
switch (TLI.getOperationAction(ISD::STORE, VT)) {
1361
default: llvm_unreachable("This action is not supported yet!");
1362
case TargetLowering::Legal:
1363
// If this is an unaligned store and the target doesn't support it,
1365
if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1366
const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1367
unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1368
if (ST->getAlignment() < ABIAlignment)
1369
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1373
case TargetLowering::Custom:
1374
Tmp1 = TLI.LowerOperation(Result, DAG);
1375
if (Tmp1.getNode()) Result = Tmp1;
1377
case TargetLowering::Promote:
1378
assert(VT.isVector() && "Unknown legal promote case!");
1379
Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1380
TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1381
Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1382
ST->getSrcValue(), SVOffset, isVolatile,
1383
isNonTemporal, Alignment);
1389
Tmp3 = LegalizeOp(ST->getValue());
1391
EVT StVT = ST->getMemoryVT();
1392
unsigned StWidth = StVT.getSizeInBits();
1394
if (StWidth != StVT.getStoreSizeInBits()) {
1395
// Promote to a byte-sized store with upper bits zero if not
1396
// storing an integral number of bytes. For example, promote
1397
// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1398
EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits());
1399
Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1400
Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1401
SVOffset, NVT, isVolatile, isNonTemporal,
1403
} else if (StWidth & (StWidth - 1)) {
1404
// If not storing a power-of-2 number of bits, expand as two stores.
1405
assert(!StVT.isVector() && "Unsupported truncstore!");
1406
unsigned RoundWidth = 1 << Log2_32(StWidth);
1407
assert(RoundWidth < StWidth);
1408
unsigned ExtraWidth = StWidth - RoundWidth;
1409
assert(ExtraWidth < RoundWidth);
1410
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1411
"Store size not an integral number of bytes!");
1412
EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1413
EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1415
unsigned IncrementSize;
1417
if (TLI.isLittleEndian()) {
1418
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1419
// Store the bottom RoundWidth bits.
1420
Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1422
isVolatile, isNonTemporal, Alignment);
1424
// Store the remaining ExtraWidth bits.
1425
IncrementSize = RoundWidth / 8;
1426
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1427
DAG.getIntPtrConstant(IncrementSize));
1428
Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1429
DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1430
Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1431
SVOffset + IncrementSize, ExtraVT, isVolatile,
1433
MinAlign(Alignment, IncrementSize));
1435
// Big endian - avoid unaligned stores.
1436
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1437
// Store the top RoundWidth bits.
1438
Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1439
DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1440
Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1441
SVOffset, RoundVT, isVolatile, isNonTemporal,
1444
// Store the remaining ExtraWidth bits.
1445
IncrementSize = RoundWidth / 8;
1446
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1447
DAG.getIntPtrConstant(IncrementSize));
1448
Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1449
SVOffset + IncrementSize, ExtraVT, isVolatile,
1451
MinAlign(Alignment, IncrementSize));
1454
// The order of the stores doesn't matter.
1455
Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1457
if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1458
Tmp2 != ST->getBasePtr())
1459
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1462
switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1463
default: llvm_unreachable("This action is not supported yet!");
1464
case TargetLowering::Legal:
1465
// If this is an unaligned store and the target doesn't support it,
1467
if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1468
const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1469
unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1470
if (ST->getAlignment() < ABIAlignment)
1471
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1475
case TargetLowering::Custom:
1476
Result = TLI.LowerOperation(Result, DAG);
1479
// TRUNCSTORE:i16 i32 -> STORE i16
1480
assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1481
Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1482
Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1483
SVOffset, isVolatile, isNonTemporal,
1492
assert(Result.getValueType() == Op.getValueType() &&
1493
"Bad legalization!");
1495
// Make sure that the generated code is itself legal.
1497
Result = LegalizeOp(Result);
1499
// Note that LegalizeOp may be reentered even from single-use nodes, which
1500
// means that we always must cache transformed nodes.
1501
AddLegalizedOperand(Op, Result);
1505
SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1506
SDValue Vec = Op.getOperand(0);
1507
SDValue Idx = Op.getOperand(1);
1508
DebugLoc dl = Op.getDebugLoc();
1509
// Store the value to a temporary stack slot, then LOAD the returned part.
1510
SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1511
SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0,
1514
// Add the offset to the index.
1516
Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1517
Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1518
DAG.getConstant(EltSize, Idx.getValueType()));
1520
if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1521
Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1523
Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1525
StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1527
if (Op.getValueType().isVector())
1528
return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0,
1531
return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1532
NULL, 0, Vec.getValueType().getVectorElementType(),
1536
SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1537
// We can't handle this case efficiently. Allocate a sufficiently
1538
// aligned object on the stack, store each element into it, then load
1539
// the result as a vector.
1540
// Create the stack frame object.
1541
EVT VT = Node->getValueType(0);
1542
EVT EltVT = VT.getVectorElementType();
1543
DebugLoc dl = Node->getDebugLoc();
1544
SDValue FIPtr = DAG.CreateStackTemporary(VT);
1545
int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1546
const Value *SV = PseudoSourceValue::getFixedStack(FI);
1548
// Emit a store of each element to the stack slot.
1549
SmallVector<SDValue, 8> Stores;
1550
unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1551
// Store (in the right endianness) the elements to memory.
1552
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1553
// Ignore undef elements.
1554
if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1556
unsigned Offset = TypeByteSize*i;
1558
SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1559
Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1561
// If the destination vector element type is narrower than the source
1562
// element type, only store the bits necessary.
1563
if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1564
Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1565
Node->getOperand(i), Idx, SV, Offset,
1566
EltVT, false, false, 0));
1568
Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1569
Node->getOperand(i), Idx, SV, Offset,
1574
if (!Stores.empty()) // Not all undef elements?
1575
StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1576
&Stores[0], Stores.size());
1578
StoreChain = DAG.getEntryNode();
1580
// Result is a load from the stack slot.
1581
return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0);
1584
SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1585
DebugLoc dl = Node->getDebugLoc();
1586
SDValue Tmp1 = Node->getOperand(0);
1587
SDValue Tmp2 = Node->getOperand(1);
1588
assert((Tmp2.getValueType() == MVT::f32 ||
1589
Tmp2.getValueType() == MVT::f64) &&
1590
"Ugly special-cased code!");
1591
// Get the sign bit of the RHS.
1593
EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
1594
if (isTypeLegal(IVT)) {
1595
SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1597
assert(isTypeLegal(TLI.getPointerTy()) &&
1598
(TLI.getPointerTy() == MVT::i32 ||
1599
TLI.getPointerTy() == MVT::i64) &&
1600
"Legal type for load?!");
1601
SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
1602
SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
1604
DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0,
1606
if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
1607
LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
1608
LoadPtr, DAG.getIntPtrConstant(4));
1609
SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
1610
Ch, LoadPtr, NULL, 0, MVT::i32,
1614
DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1615
SignBit, DAG.getConstant(0, SignBit.getValueType()),
1617
// Get the absolute value of the result.
1618
SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1619
// Select between the nabs and abs value based on the sign bit of
1621
return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1622
DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1626
void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1627
SmallVectorImpl<SDValue> &Results) {
1628
unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1629
assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1630
" not tell us which reg is the stack pointer!");
1631
DebugLoc dl = Node->getDebugLoc();
1632
EVT VT = Node->getValueType(0);
1633
SDValue Tmp1 = SDValue(Node, 0);
1634
SDValue Tmp2 = SDValue(Node, 1);
1635
SDValue Tmp3 = Node->getOperand(2);
1636
SDValue Chain = Tmp1.getOperand(0);
1638
// Chain the dynamic stack allocation so that it doesn't modify the stack
1639
// pointer when other instructions are using the stack.
1640
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1642
SDValue Size = Tmp2.getOperand(1);
1643
SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1644
Chain = SP.getValue(1);
1645
unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1646
unsigned StackAlign =
1647
TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1648
if (Align > StackAlign)
1649
SP = DAG.getNode(ISD::AND, dl, VT, SP,
1650
DAG.getConstant(-(uint64_t)Align, VT));
1651
Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1652
Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1654
Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1655
DAG.getIntPtrConstant(0, true), SDValue());
1657
Results.push_back(Tmp1);
1658
Results.push_back(Tmp2);
1661
/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1662
/// condition code CC on the current target. This routine expands SETCC with
1663
/// illegal condition code into AND / OR of multiple SETCC values.
1664
void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1665
SDValue &LHS, SDValue &RHS,
1668
EVT OpVT = LHS.getValueType();
1669
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1670
switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1671
default: llvm_unreachable("Unknown condition code action!");
1672
case TargetLowering::Legal:
1675
case TargetLowering::Expand: {
1676
ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1679
default: llvm_unreachable("Don't know how to expand this condition!");
1680
case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1681
case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1682
case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1683
case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1684
case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1685
case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1686
case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1687
case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1688
case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1689
case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1690
case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1691
case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1692
// FIXME: Implement more expansions.
1695
SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1696
SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1697
LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1705
/// EmitStackConvert - Emit a store/load combination to the stack. This stores
1706
/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1707
/// a load from the stack slot to DestVT, extending it if needed.
1708
/// The resultant code need not be legal.
1709
SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1713
// Create the stack frame object.
1715
TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1716
getTypeForEVT(*DAG.getContext()));
1717
SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1719
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1720
int SPFI = StackPtrFI->getIndex();
1721
const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1723
unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1724
unsigned SlotSize = SlotVT.getSizeInBits();
1725
unsigned DestSize = DestVT.getSizeInBits();
1726
unsigned DestAlign =
1727
TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext()));
1729
// Emit a store to the stack slot. Use a truncstore if the input value is
1730
// later than DestVT.
1733
if (SrcSize > SlotSize)
1734
Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1735
SV, 0, SlotVT, false, false, SrcAlign);
1737
assert(SrcSize == SlotSize && "Invalid store");
1738
Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1739
SV, 0, false, false, SrcAlign);
1742
// Result is a load from the stack slot.
1743
if (SlotSize == DestSize)
1744
return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false,
1747
assert(SlotSize < DestSize && "Unknown extension!");
1748
return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
1749
false, false, DestAlign);
1752
SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1753
DebugLoc dl = Node->getDebugLoc();
1754
// Create a vector sized/aligned stack slot, store the value to element #0,
1755
// then load the whole vector back out.
1756
SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1758
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1759
int SPFI = StackPtrFI->getIndex();
1761
SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1763
PseudoSourceValue::getFixedStack(SPFI), 0,
1764
Node->getValueType(0).getVectorElementType(),
1766
return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1767
PseudoSourceValue::getFixedStack(SPFI), 0,
1772
/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1773
/// support the operation, but do support the resultant vector type.
1774
SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1775
unsigned NumElems = Node->getNumOperands();
1776
SDValue Value1, Value2;
1777
DebugLoc dl = Node->getDebugLoc();
1778
EVT VT = Node->getValueType(0);
1779
EVT OpVT = Node->getOperand(0).getValueType();
1780
EVT EltVT = VT.getVectorElementType();
1782
// If the only non-undef value is the low element, turn this into a
1783
// SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1784
bool isOnlyLowElement = true;
1785
bool MoreThanTwoValues = false;
1786
bool isConstant = true;
1787
for (unsigned i = 0; i < NumElems; ++i) {
1788
SDValue V = Node->getOperand(i);
1789
if (V.getOpcode() == ISD::UNDEF)
1792
isOnlyLowElement = false;
1793
if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1796
if (!Value1.getNode()) {
1798
} else if (!Value2.getNode()) {
1801
} else if (V != Value1 && V != Value2) {
1802
MoreThanTwoValues = true;
1806
if (!Value1.getNode())
1807
return DAG.getUNDEF(VT);
1809
if (isOnlyLowElement)
1810
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1812
// If all elements are constants, create a load from the constant pool.
1814
std::vector<Constant*> CV;
1815
for (unsigned i = 0, e = NumElems; i != e; ++i) {
1816
if (ConstantFPSDNode *V =
1817
dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1818
CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1819
} else if (ConstantSDNode *V =
1820
dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1822
CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1824
// If OpVT and EltVT don't match, EltVT is not legal and the
1825
// element values have been promoted/truncated earlier. Undo this;
1826
// we don't want a v16i8 to become a v16i32 for example.
1827
const ConstantInt *CI = V->getConstantIntValue();
1828
CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1829
CI->getZExtValue()));
1832
assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1833
const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1834
CV.push_back(UndefValue::get(OpNTy));
1837
Constant *CP = ConstantVector::get(CV);
1838
SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1839
unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1840
return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1841
PseudoSourceValue::getConstantPool(), 0,
1842
false, false, Alignment);
1845
if (!MoreThanTwoValues) {
1846
SmallVector<int, 8> ShuffleVec(NumElems, -1);
1847
for (unsigned i = 0; i < NumElems; ++i) {
1848
SDValue V = Node->getOperand(i);
1849
if (V.getOpcode() == ISD::UNDEF)
1851
ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1853
if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1854
// Get the splatted value into the low element of a vector register.
1855
SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1857
if (Value2.getNode())
1858
Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1860
Vec2 = DAG.getUNDEF(VT);
1862
// Return shuffle(LowValVec, undef, <0,0,0,0>)
1863
return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1867
// Otherwise, we can't handle this case efficiently.
1868
return ExpandVectorBuildThroughStack(Node);
1871
// ExpandLibCall - Expand a node into a call to a libcall. If the result value
1872
// does not fit into a register, return the lo part and set the hi part to the
1873
// by-reg argument. If it does fit into a single register, return the result
1874
// and leave the Hi part unset.
1875
SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1877
assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1878
// The input chain to this libcall is the entry node of the function.
1879
// Legalizing the call will automatically add the previous call to the
1881
SDValue InChain = DAG.getEntryNode();
1883
TargetLowering::ArgListTy Args;
1884
TargetLowering::ArgListEntry Entry;
1885
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1886
EVT ArgVT = Node->getOperand(i).getValueType();
1887
const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1888
Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1889
Entry.isSExt = isSigned;
1890
Entry.isZExt = !isSigned;
1891
Args.push_back(Entry);
1893
SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1894
TLI.getPointerTy());
1896
// Splice the libcall in wherever FindInputOutputChains tells us to.
1897
const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1898
std::pair<SDValue, SDValue> CallInfo =
1899
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1900
0, TLI.getLibcallCallingConv(LC), false,
1901
/*isReturnValueUsed=*/true,
1902
Callee, Args, DAG, Node->getDebugLoc());
1904
// Legalize the call sequence, starting with the chain. This will advance
1905
// the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1906
// was added by LowerCallTo (guaranteeing proper serialization of calls).
1907
LegalizeOp(CallInfo.second);
1908
return CallInfo.first;
1911
SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1912
RTLIB::Libcall Call_F32,
1913
RTLIB::Libcall Call_F64,
1914
RTLIB::Libcall Call_F80,
1915
RTLIB::Libcall Call_PPCF128) {
1917
switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1918
default: llvm_unreachable("Unexpected request for libcall!");
1919
case MVT::f32: LC = Call_F32; break;
1920
case MVT::f64: LC = Call_F64; break;
1921
case MVT::f80: LC = Call_F80; break;
1922
case MVT::ppcf128: LC = Call_PPCF128; break;
1924
return ExpandLibCall(LC, Node, false);
1927
SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1928
RTLIB::Libcall Call_I8,
1929
RTLIB::Libcall Call_I16,
1930
RTLIB::Libcall Call_I32,
1931
RTLIB::Libcall Call_I64,
1932
RTLIB::Libcall Call_I128) {
1934
switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1935
default: llvm_unreachable("Unexpected request for libcall!");
1936
case MVT::i8: LC = Call_I8; break;
1937
case MVT::i16: LC = Call_I16; break;
1938
case MVT::i32: LC = Call_I32; break;
1939
case MVT::i64: LC = Call_I64; break;
1940
case MVT::i128: LC = Call_I128; break;
1942
return ExpandLibCall(LC, Node, isSigned);
1945
/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
1946
/// INT_TO_FP operation of the specified operand when the target requests that
1947
/// we expand it. At this point, we know that the result and operand types are
1948
/// legal for the target.
1949
SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
1953
if (Op0.getValueType() == MVT::i32) {
1954
// simple 32-bit [signed|unsigned] integer to float/double expansion
1956
// Get the stack frame index of a 8 byte buffer.
1957
SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
1959
// word offset constant for Hi/Lo address computation
1960
SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
1961
// set up Hi and Lo (into buffer) address based on endian
1962
SDValue Hi = StackSlot;
1963
SDValue Lo = DAG.getNode(ISD::ADD, dl,
1964
TLI.getPointerTy(), StackSlot, WordOff);
1965
if (TLI.isLittleEndian())
1968
// if signed map to unsigned space
1971
// constant used to invert sign bit (signed to unsigned mapping)
1972
SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
1973
Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
1977
// store the lo of the constructed double - based on integer input
1978
SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
1979
Op0Mapped, Lo, NULL, 0,
1981
// initial hi portion of constructed double
1982
SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
1983
// store the hi of the constructed double - biased exponent
1984
SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0,
1986
// load the constructed double
1987
SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0,
1989
// FP constant to bias correct the final result
1990
SDValue Bias = DAG.getConstantFP(isSigned ?
1991
BitsToDouble(0x4330000080000000ULL) :
1992
BitsToDouble(0x4330000000000000ULL),
1994
// subtract the bias
1995
SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
1998
// handle final rounding
1999
if (DestVT == MVT::f64) {
2002
} else if (DestVT.bitsLT(MVT::f64)) {
2003
Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2004
DAG.getIntPtrConstant(0));
2005
} else if (DestVT.bitsGT(MVT::f64)) {
2006
Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2010
assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2012
// Implementation of unsigned i64 to f64 following the algorithm in
2013
// __floatundidf in compiler_rt. This implementation has the advantage
2014
// of performing rounding correctly, both in the default rounding mode
2015
// and in all alternate rounding modes.
2016
// TODO: Generalize this for use with other types.
2017
if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2019
DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2020
SDValue TwoP84PlusTwoP52 =
2021
DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2023
DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2025
SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2026
SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2027
DAG.getConstant(32, MVT::i64));
2028
SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2029
SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2030
SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr);
2031
SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr);
2032
SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52);
2033
return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2036
SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2038
SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2039
Op0, DAG.getConstant(0, Op0.getValueType()),
2041
SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2042
SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2043
SignSet, Four, Zero);
2045
// If the sign bit of the integer is set, the large number will be treated
2046
// as a negative number. To counteract this, the dynamic code adds an
2047
// offset depending on the data type.
2049
switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2050
default: llvm_unreachable("Unsupported integer type!");
2051
case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2052
case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2053
case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2054
case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2056
if (TLI.isLittleEndian()) FF <<= 32;
2057
Constant *FudgeFactor = ConstantInt::get(
2058
Type::getInt64Ty(*DAG.getContext()), FF);
2060
SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2061
unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2062
CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2063
Alignment = std::min(Alignment, 4u);
2065
if (DestVT == MVT::f32)
2066
FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2067
PseudoSourceValue::getConstantPool(), 0,
2068
false, false, Alignment);
2071
LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2072
DAG.getEntryNode(), CPIdx,
2073
PseudoSourceValue::getConstantPool(), 0,
2074
MVT::f32, false, false, Alignment));
2077
return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2080
/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2081
/// *INT_TO_FP operation of the specified operand when the target requests that
2082
/// we promote it. At this point, we know that the result and operand types are
2083
/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2084
/// operation that takes a larger input.
2085
SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2089
// First step, figure out the appropriate *INT_TO_FP operation to use.
2090
EVT NewInTy = LegalOp.getValueType();
2092
unsigned OpToUse = 0;
2094
// Scan for the appropriate larger type to use.
2096
NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2097
assert(NewInTy.isInteger() && "Ran out of possibilities!");
2099
// If the target supports SINT_TO_FP of this type, use it.
2100
if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2101
OpToUse = ISD::SINT_TO_FP;
2104
if (isSigned) continue;
2106
// If the target supports UINT_TO_FP of this type, use it.
2107
if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2108
OpToUse = ISD::UINT_TO_FP;
2112
// Otherwise, try a larger type.
2115
// Okay, we found the operation and type to use. Zero extend our input to the
2116
// desired type then run the operation on it.
2117
return DAG.getNode(OpToUse, dl, DestVT,
2118
DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2119
dl, NewInTy, LegalOp));
2122
/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2123
/// FP_TO_*INT operation of the specified operand when the target requests that
2124
/// we promote it. At this point, we know that the result and operand types are
2125
/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2126
/// operation that returns a larger result.
2127
SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2131
// First step, figure out the appropriate FP_TO*INT operation to use.
2132
EVT NewOutTy = DestVT;
2134
unsigned OpToUse = 0;
2136
// Scan for the appropriate larger type to use.
2138
NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2139
assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2141
if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2142
OpToUse = ISD::FP_TO_SINT;
2146
if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2147
OpToUse = ISD::FP_TO_UINT;
2151
// Otherwise, try a larger type.
2155
// Okay, we found the operation and type to use.
2156
SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2158
// Truncate the result of the extended FP_TO_*INT operation to the desired
2160
return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2163
/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2165
SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2166
EVT VT = Op.getValueType();
2167
EVT SHVT = TLI.getShiftAmountTy();
2168
SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2169
switch (VT.getSimpleVT().SimpleTy) {
2170
default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2172
Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2173
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2174
return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2176
Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2177
Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2178
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2179
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2180
Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2181
Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2182
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2183
Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2184
return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2186
Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2187
Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2188
Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2189
Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2190
Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2191
Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2192
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2193
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2194
Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2195
Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2196
Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2197
Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2198
Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2199
Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2200
Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2201
Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2202
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2203
Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2204
Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2205
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2206
return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2210
/// ExpandBitCount - Expand the specified bitcount instruction into operations.
2212
SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2215
default: llvm_unreachable("Cannot expand this yet!");
2217
static const uint64_t mask[6] = {
2218
0x5555555555555555ULL, 0x3333333333333333ULL,
2219
0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2220
0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2222
EVT VT = Op.getValueType();
2223
EVT ShVT = TLI.getShiftAmountTy();
2224
unsigned len = VT.getSizeInBits();
2225
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2226
//x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2227
unsigned EltSize = VT.isVector() ?
2228
VT.getVectorElementType().getSizeInBits() : len;
2229
SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2230
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2231
Op = DAG.getNode(ISD::ADD, dl, VT,
2232
DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2233
DAG.getNode(ISD::AND, dl, VT,
2234
DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2240
// for now, we do this:
2241
// x = x | (x >> 1);
2242
// x = x | (x >> 2);
2244
// x = x | (x >>16);
2245
// x = x | (x >>32); // for 64-bit input
2246
// return popcount(~x);
2248
// but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2249
EVT VT = Op.getValueType();
2250
EVT ShVT = TLI.getShiftAmountTy();
2251
unsigned len = VT.getSizeInBits();
2252
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2253
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2254
Op = DAG.getNode(ISD::OR, dl, VT, Op,
2255
DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2257
Op = DAG.getNOT(dl, Op, VT);
2258
return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2261
// for now, we use: { return popcount(~x & (x - 1)); }
2262
// unless the target has ctlz but not ctpop, in which case we use:
2263
// { return 32 - nlz(~x & (x-1)); }
2264
// see also http://www.hackersdelight.org/HDcode/ntz.cc
2265
EVT VT = Op.getValueType();
2266
SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2267
DAG.getNOT(dl, Op, VT),
2268
DAG.getNode(ISD::SUB, dl, VT, Op,
2269
DAG.getConstant(1, VT)));
2270
// If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2271
if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2272
TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2273
return DAG.getNode(ISD::SUB, dl, VT,
2274
DAG.getConstant(VT.getSizeInBits(), VT),
2275
DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2276
return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2281
void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2282
SmallVectorImpl<SDValue> &Results) {
2283
DebugLoc dl = Node->getDebugLoc();
2284
SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2285
switch (Node->getOpcode()) {
2289
Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2290
Results.push_back(Tmp1);
2293
Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2295
case ISD::FRAMEADDR:
2296
case ISD::RETURNADDR:
2297
case ISD::FRAME_TO_ARGS_OFFSET:
2298
Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2300
case ISD::FLT_ROUNDS_:
2301
Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2303
case ISD::EH_RETURN:
2306
case ISD::MEMBARRIER:
2308
Results.push_back(Node->getOperand(0));
2310
case ISD::DYNAMIC_STACKALLOC:
2311
ExpandDYNAMIC_STACKALLOC(Node, Results);
2313
case ISD::MERGE_VALUES:
2314
for (unsigned i = 0; i < Node->getNumValues(); i++)
2315
Results.push_back(Node->getOperand(i));
2318
EVT VT = Node->getValueType(0);
2320
Results.push_back(DAG.getConstant(0, VT));
2321
else if (VT.isFloatingPoint())
2322
Results.push_back(DAG.getConstantFP(0, VT));
2324
llvm_unreachable("Unknown value type!");
2328
// If this operation is not supported, lower it to 'abort()' call
2329
TargetLowering::ArgListTy Args;
2330
std::pair<SDValue, SDValue> CallResult =
2331
TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2332
false, false, false, false, 0, CallingConv::C, false,
2333
/*isReturnValueUsed=*/true,
2334
DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2336
Results.push_back(CallResult.second);
2340
case ISD::BIT_CONVERT:
2341
Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2342
Node->getValueType(0), dl);
2343
Results.push_back(Tmp1);
2345
case ISD::FP_EXTEND:
2346
Tmp1 = EmitStackConvert(Node->getOperand(0),
2347
Node->getOperand(0).getValueType(),
2348
Node->getValueType(0), dl);
2349
Results.push_back(Tmp1);
2351
case ISD::SIGN_EXTEND_INREG: {
2352
// NOTE: we could fall back on load/store here too for targets without
2353
// SAR. However, it is doubtful that any exist.
2354
EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2355
EVT VT = Node->getValueType(0);
2356
EVT ShiftAmountTy = TLI.getShiftAmountTy();
2359
unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2360
ExtraVT.getScalarType().getSizeInBits();
2361
SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2362
Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2363
Node->getOperand(0), ShiftCst);
2364
Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2365
Results.push_back(Tmp1);
2368
case ISD::FP_ROUND_INREG: {
2369
// The only way we can lower this is to turn it into a TRUNCSTORE,
2370
// EXTLOAD pair, targetting a temporary location (a stack slot).
2372
// NOTE: there is a choice here between constantly creating new stack
2373
// slots and always reusing the same one. We currently always create
2374
// new ones, as reuse may inhibit scheduling.
2375
EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2376
Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2377
Node->getValueType(0), dl);
2378
Results.push_back(Tmp1);
2381
case ISD::SINT_TO_FP:
2382
case ISD::UINT_TO_FP:
2383
Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2384
Node->getOperand(0), Node->getValueType(0), dl);
2385
Results.push_back(Tmp1);
2387
case ISD::FP_TO_UINT: {
2388
SDValue True, False;
2389
EVT VT = Node->getOperand(0).getValueType();
2390
EVT NVT = Node->getValueType(0);
2391
const uint64_t zero[] = {0, 0};
2392
APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2393
APInt x = APInt::getSignBit(NVT.getSizeInBits());
2394
(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2395
Tmp1 = DAG.getConstantFP(apf, VT);
2396
Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2397
Node->getOperand(0),
2399
True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2400
False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2401
DAG.getNode(ISD::FSUB, dl, VT,
2402
Node->getOperand(0), Tmp1));
2403
False = DAG.getNode(ISD::XOR, dl, NVT, False,
2404
DAG.getConstant(x, NVT));
2405
Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2406
Results.push_back(Tmp1);
2410
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2411
EVT VT = Node->getValueType(0);
2412
Tmp1 = Node->getOperand(0);
2413
Tmp2 = Node->getOperand(1);
2414
SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0,
2416
// Increment the pointer, VAList, to the next vaarg
2417
Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2418
DAG.getConstant(TLI.getTargetData()->
2419
getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2420
TLI.getPointerTy()));
2421
// Store the incremented VAList to the legalized pointer
2422
Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0,
2424
// Load the actual argument out of the pointer VAList
2425
Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0,
2427
Results.push_back(Results[0].getValue(1));
2431
// This defaults to loading a pointer from the input and storing it to the
2432
// output, returning the chain.
2433
const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2434
const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2435
Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2436
Node->getOperand(2), VS, 0, false, false, 0);
2437
Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0,
2439
Results.push_back(Tmp1);
2442
case ISD::EXTRACT_VECTOR_ELT:
2443
if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2444
// This must be an access of the only element. Return it.
2445
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2446
Node->getOperand(0));
2448
Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2449
Results.push_back(Tmp1);
2451
case ISD::EXTRACT_SUBVECTOR:
2452
Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2454
case ISD::CONCAT_VECTORS: {
2455
Results.push_back(ExpandVectorBuildThroughStack(Node));
2458
case ISD::SCALAR_TO_VECTOR:
2459
Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2461
case ISD::INSERT_VECTOR_ELT:
2462
Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2463
Node->getOperand(1),
2464
Node->getOperand(2), dl));
2466
case ISD::VECTOR_SHUFFLE: {
2467
SmallVector<int, 8> Mask;
2468
cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2470
EVT VT = Node->getValueType(0);
2471
EVT EltVT = VT.getVectorElementType();
2472
unsigned NumElems = VT.getVectorNumElements();
2473
SmallVector<SDValue, 8> Ops;
2474
for (unsigned i = 0; i != NumElems; ++i) {
2476
Ops.push_back(DAG.getUNDEF(EltVT));
2479
unsigned Idx = Mask[i];
2481
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2482
Node->getOperand(0),
2483
DAG.getIntPtrConstant(Idx)));
2485
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2486
Node->getOperand(1),
2487
DAG.getIntPtrConstant(Idx - NumElems)));
2489
Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2490
Results.push_back(Tmp1);
2493
case ISD::EXTRACT_ELEMENT: {
2494
EVT OpTy = Node->getOperand(0).getValueType();
2495
if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2497
Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2498
DAG.getConstant(OpTy.getSizeInBits()/2,
2499
TLI.getShiftAmountTy()));
2500
Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2503
Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2504
Node->getOperand(0));
2506
Results.push_back(Tmp1);
2509
case ISD::STACKSAVE:
2510
// Expand to CopyFromReg if the target set
2511
// StackPointerRegisterToSaveRestore.
2512
if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2513
Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2514
Node->getValueType(0)));
2515
Results.push_back(Results[0].getValue(1));
2517
Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2518
Results.push_back(Node->getOperand(0));
2521
case ISD::STACKRESTORE:
2522
// Expand to CopyToReg if the target set
2523
// StackPointerRegisterToSaveRestore.
2524
if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2525
Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2526
Node->getOperand(1)));
2528
Results.push_back(Node->getOperand(0));
2531
case ISD::FCOPYSIGN:
2532
Results.push_back(ExpandFCOPYSIGN(Node));
2535
// Expand Y = FNEG(X) -> Y = SUB -0.0, X
2536
Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2537
Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2538
Node->getOperand(0));
2539
Results.push_back(Tmp1);
2542
// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2543
EVT VT = Node->getValueType(0);
2544
Tmp1 = Node->getOperand(0);
2545
Tmp2 = DAG.getConstantFP(0.0, VT);
2546
Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2547
Tmp1, Tmp2, ISD::SETUGT);
2548
Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2549
Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2550
Results.push_back(Tmp1);
2554
Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2555
RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2558
Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2559
RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2562
Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2563
RTLIB::COS_F80, RTLIB::COS_PPCF128));
2566
Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2567
RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2570
Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2571
RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2574
Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2575
RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2578
Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2579
RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2582
Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2583
RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2586
Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2587
RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2590
Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2591
RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2594
Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2595
RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2598
Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2599
RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2601
case ISD::FNEARBYINT:
2602
Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2603
RTLIB::NEARBYINT_F64,
2604
RTLIB::NEARBYINT_F80,
2605
RTLIB::NEARBYINT_PPCF128));
2608
Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2609
RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2612
Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2613
RTLIB::POW_F80, RTLIB::POW_PPCF128));
2616
Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2617
RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2620
Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2621
RTLIB::REM_F80, RTLIB::REM_PPCF128));
2623
case ISD::ConstantFP: {
2624
ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2625
// Check to see if this FP immediate is already legal.
2626
// If this is a legal constant, turn it into a TargetConstantFP node.
2627
if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
2628
Results.push_back(SDValue(Node, 0));
2630
Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2633
case ISD::EHSELECTION: {
2634
unsigned Reg = TLI.getExceptionSelectorRegister();
2635
assert(Reg && "Can't expand to unknown register!");
2636
Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2637
Node->getValueType(0)));
2638
Results.push_back(Results[0].getValue(1));
2641
case ISD::EXCEPTIONADDR: {
2642
unsigned Reg = TLI.getExceptionAddressRegister();
2643
assert(Reg && "Can't expand to unknown register!");
2644
Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2645
Node->getValueType(0)));
2646
Results.push_back(Results[0].getValue(1));
2650
EVT VT = Node->getValueType(0);
2651
assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2652
TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2653
"Don't know how to expand this subtraction!");
2654
Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2655
DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2656
Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2657
Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2662
EVT VT = Node->getValueType(0);
2663
SDVTList VTs = DAG.getVTList(VT, VT);
2664
bool isSigned = Node->getOpcode() == ISD::SREM;
2665
unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2666
unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2667
Tmp2 = Node->getOperand(0);
2668
Tmp3 = Node->getOperand(1);
2669
if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2670
Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2671
} else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2673
Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2674
Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2675
Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2676
} else if (isSigned) {
2677
Tmp1 = ExpandIntLibCall(Node, true,
2679
RTLIB::SREM_I16, RTLIB::SREM_I32,
2680
RTLIB::SREM_I64, RTLIB::SREM_I128);
2682
Tmp1 = ExpandIntLibCall(Node, false,
2684
RTLIB::UREM_I16, RTLIB::UREM_I32,
2685
RTLIB::UREM_I64, RTLIB::UREM_I128);
2687
Results.push_back(Tmp1);
2692
bool isSigned = Node->getOpcode() == ISD::SDIV;
2693
unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2694
EVT VT = Node->getValueType(0);
2695
SDVTList VTs = DAG.getVTList(VT, VT);
2696
if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2697
Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2698
Node->getOperand(1));
2700
Tmp1 = ExpandIntLibCall(Node, true,
2702
RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2703
RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2705
Tmp1 = ExpandIntLibCall(Node, false,
2707
RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2708
RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2709
Results.push_back(Tmp1);
2714
unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2716
EVT VT = Node->getValueType(0);
2717
SDVTList VTs = DAG.getVTList(VT, VT);
2718
assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2719
"If this wasn't legal, it shouldn't have been created!");
2720
Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2721
Node->getOperand(1));
2722
Results.push_back(Tmp1.getValue(1));
2726
EVT VT = Node->getValueType(0);
2727
SDVTList VTs = DAG.getVTList(VT, VT);
2728
// See if multiply or divide can be lowered using two-result operations.
2729
// We just need the low half of the multiply; try both the signed
2730
// and unsigned forms. If the target supports both SMUL_LOHI and
2731
// UMUL_LOHI, form a preference by checking which forms of plain
2732
// MULH it supports.
2733
bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
2734
bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
2735
bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
2736
bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
2737
unsigned OpToUse = 0;
2738
if (HasSMUL_LOHI && !HasMULHS) {
2739
OpToUse = ISD::SMUL_LOHI;
2740
} else if (HasUMUL_LOHI && !HasMULHU) {
2741
OpToUse = ISD::UMUL_LOHI;
2742
} else if (HasSMUL_LOHI) {
2743
OpToUse = ISD::SMUL_LOHI;
2744
} else if (HasUMUL_LOHI) {
2745
OpToUse = ISD::UMUL_LOHI;
2748
Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
2749
Node->getOperand(1)));
2752
Tmp1 = ExpandIntLibCall(Node, false,
2754
RTLIB::MUL_I16, RTLIB::MUL_I32,
2755
RTLIB::MUL_I64, RTLIB::MUL_I128);
2756
Results.push_back(Tmp1);
2761
SDValue LHS = Node->getOperand(0);
2762
SDValue RHS = Node->getOperand(1);
2763
SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2764
ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2766
Results.push_back(Sum);
2767
EVT OType = Node->getValueType(1);
2769
SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2771
// LHSSign -> LHS >= 0
2772
// RHSSign -> RHS >= 0
2773
// SumSign -> Sum >= 0
2776
// Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2778
// Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2780
SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2781
SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2782
SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2783
Node->getOpcode() == ISD::SADDO ?
2784
ISD::SETEQ : ISD::SETNE);
2786
SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2787
SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2789
SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2790
Results.push_back(Cmp);
2795
SDValue LHS = Node->getOperand(0);
2796
SDValue RHS = Node->getOperand(1);
2797
SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
2798
ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2800
Results.push_back(Sum);
2801
Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
2802
Node->getOpcode () == ISD::UADDO ?
2803
ISD::SETULT : ISD::SETUGT));
2808
EVT VT = Node->getValueType(0);
2809
SDValue LHS = Node->getOperand(0);
2810
SDValue RHS = Node->getOperand(1);
2813
static const unsigned Ops[2][3] =
2814
{ { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
2815
{ ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
2816
bool isSigned = Node->getOpcode() == ISD::SMULO;
2817
if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
2818
BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
2819
TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
2820
} else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
2821
BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
2823
TopHalf = BottomHalf.getValue(1);
2824
} else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) {
2825
EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
2826
LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
2827
RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
2828
Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
2829
BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2830
DAG.getIntPtrConstant(0));
2831
TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2832
DAG.getIntPtrConstant(1));
2834
// FIXME: We should be able to fall back to a libcall with an illegal
2835
// type in some cases.
2836
// Also, we can fall back to a division in some cases, but that's a big
2837
// performance hit in the general case.
2838
llvm_unreachable("Don't know how to expand this operation yet!");
2841
Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
2842
Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
2843
TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
2846
TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
2847
DAG.getConstant(0, VT), ISD::SETNE);
2849
Results.push_back(BottomHalf);
2850
Results.push_back(TopHalf);
2853
case ISD::BUILD_PAIR: {
2854
EVT PairTy = Node->getValueType(0);
2855
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
2856
Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
2857
Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
2858
DAG.getConstant(PairTy.getSizeInBits()/2,
2859
TLI.getShiftAmountTy()));
2860
Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
2864
Tmp1 = Node->getOperand(0);
2865
Tmp2 = Node->getOperand(1);
2866
Tmp3 = Node->getOperand(2);
2867
if (Tmp1.getOpcode() == ISD::SETCC) {
2868
Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2870
cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2872
Tmp1 = DAG.getSelectCC(dl, Tmp1,
2873
DAG.getConstant(0, Tmp1.getValueType()),
2874
Tmp2, Tmp3, ISD::SETNE);
2876
Results.push_back(Tmp1);
2879
SDValue Chain = Node->getOperand(0);
2880
SDValue Table = Node->getOperand(1);
2881
SDValue Index = Node->getOperand(2);
2883
EVT PTy = TLI.getPointerTy();
2885
const TargetData &TD = *TLI.getTargetData();
2886
unsigned EntrySize =
2887
DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
2889
Index = DAG.getNode(ISD::MUL, dl, PTy,
2890
Index, DAG.getConstant(EntrySize, PTy));
2891
SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2893
EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
2894
SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2895
PseudoSourceValue::getJumpTable(), 0, MemVT,
2898
if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2899
// For PIC, the sequence is:
2900
// BRIND(load(Jumptable + index) + RelocBase)
2901
// RelocBase can be JumpTable, GOT or some sort of global base.
2902
Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2903
TLI.getPICJumpTableRelocBase(Table, DAG));
2905
Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2906
Results.push_back(Tmp1);
2910
// Expand brcond's setcc into its constituent parts and create a BR_CC
2912
Tmp1 = Node->getOperand(0);
2913
Tmp2 = Node->getOperand(1);
2914
if (Tmp2.getOpcode() == ISD::SETCC) {
2915
Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2916
Tmp1, Tmp2.getOperand(2),
2917
Tmp2.getOperand(0), Tmp2.getOperand(1),
2918
Node->getOperand(2));
2920
Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2921
DAG.getCondCode(ISD::SETNE), Tmp2,
2922
DAG.getConstant(0, Tmp2.getValueType()),
2923
Node->getOperand(2));
2925
Results.push_back(Tmp1);
2928
Tmp1 = Node->getOperand(0);
2929
Tmp2 = Node->getOperand(1);
2930
Tmp3 = Node->getOperand(2);
2931
LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
2933
// If we expanded the SETCC into an AND/OR, return the new node
2934
if (Tmp2.getNode() == 0) {
2935
Results.push_back(Tmp1);
2939
// Otherwise, SETCC for the given comparison type must be completely
2940
// illegal; expand it into a SELECT_CC.
2941
EVT VT = Node->getValueType(0);
2942
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
2943
DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
2944
Results.push_back(Tmp1);
2947
case ISD::SELECT_CC: {
2948
Tmp1 = Node->getOperand(0); // LHS
2949
Tmp2 = Node->getOperand(1); // RHS
2950
Tmp3 = Node->getOperand(2); // True
2951
Tmp4 = Node->getOperand(3); // False
2952
SDValue CC = Node->getOperand(4);
2954
LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
2955
Tmp1, Tmp2, CC, dl);
2957
assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
2958
Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2959
CC = DAG.getCondCode(ISD::SETNE);
2960
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
2962
Results.push_back(Tmp1);
2966
Tmp1 = Node->getOperand(0); // Chain
2967
Tmp2 = Node->getOperand(2); // LHS
2968
Tmp3 = Node->getOperand(3); // RHS
2969
Tmp4 = Node->getOperand(1); // CC
2971
LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
2972
Tmp2, Tmp3, Tmp4, dl);
2973
LastCALLSEQ_END = DAG.getEntryNode();
2975
assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
2976
Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2977
Tmp4 = DAG.getCondCode(ISD::SETNE);
2978
Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
2979
Tmp3, Node->getOperand(4));
2980
Results.push_back(Tmp1);
2983
case ISD::GLOBAL_OFFSET_TABLE:
2984
case ISD::GlobalAddress:
2985
case ISD::GlobalTLSAddress:
2986
case ISD::ExternalSymbol:
2987
case ISD::ConstantPool:
2988
case ISD::JumpTable:
2989
case ISD::INTRINSIC_W_CHAIN:
2990
case ISD::INTRINSIC_WO_CHAIN:
2991
case ISD::INTRINSIC_VOID:
2992
// FIXME: Custom lowering for these operations shouldn't return null!
2993
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2994
Results.push_back(SDValue(Node, i));
2998
void SelectionDAGLegalize::PromoteNode(SDNode *Node,
2999
SmallVectorImpl<SDValue> &Results) {
3000
EVT OVT = Node->getValueType(0);
3001
if (Node->getOpcode() == ISD::UINT_TO_FP ||
3002
Node->getOpcode() == ISD::SINT_TO_FP ||
3003
Node->getOpcode() == ISD::SETCC) {
3004
OVT = Node->getOperand(0).getValueType();
3006
EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3007
DebugLoc dl = Node->getDebugLoc();
3008
SDValue Tmp1, Tmp2, Tmp3;
3009
switch (Node->getOpcode()) {
3013
// Zero extend the argument.
3014
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3015
// Perform the larger operation.
3016
Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3017
if (Node->getOpcode() == ISD::CTTZ) {
3018
//if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3019
Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3020
Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3022
Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3023
DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3024
} else if (Node->getOpcode() == ISD::CTLZ) {
3025
// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3026
Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3027
DAG.getConstant(NVT.getSizeInBits() -
3028
OVT.getSizeInBits(), NVT));
3030
Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3033
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3034
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3035
Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3036
Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3037
DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3038
Results.push_back(Tmp1);
3041
case ISD::FP_TO_UINT:
3042
case ISD::FP_TO_SINT:
3043
Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3044
Node->getOpcode() == ISD::FP_TO_SINT, dl);
3045
Results.push_back(Tmp1);
3047
case ISD::UINT_TO_FP:
3048
case ISD::SINT_TO_FP:
3049
Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3050
Node->getOpcode() == ISD::SINT_TO_FP, dl);
3051
Results.push_back(Tmp1);
3056
unsigned ExtOp, TruncOp;
3057
if (OVT.isVector()) {
3058
ExtOp = ISD::BIT_CONVERT;
3059
TruncOp = ISD::BIT_CONVERT;
3060
} else if (OVT.isInteger()) {
3061
ExtOp = ISD::ANY_EXTEND;
3062
TruncOp = ISD::TRUNCATE;
3064
llvm_report_error("Cannot promote logic operation");
3066
// Promote each of the values to the new type.
3067
Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3068
Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3069
// Perform the larger operation, then convert back
3070
Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3071
Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3075
unsigned ExtOp, TruncOp;
3076
if (Node->getValueType(0).isVector()) {
3077
ExtOp = ISD::BIT_CONVERT;
3078
TruncOp = ISD::BIT_CONVERT;
3079
} else if (Node->getValueType(0).isInteger()) {
3080
ExtOp = ISD::ANY_EXTEND;
3081
TruncOp = ISD::TRUNCATE;
3083
ExtOp = ISD::FP_EXTEND;
3084
TruncOp = ISD::FP_ROUND;
3086
Tmp1 = Node->getOperand(0);
3087
// Promote each of the values to the new type.
3088
Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3089
Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3090
// Perform the larger operation, then round down.
3091
Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3092
if (TruncOp != ISD::FP_ROUND)
3093
Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3095
Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3096
DAG.getIntPtrConstant(0));
3097
Results.push_back(Tmp1);
3100
case ISD::VECTOR_SHUFFLE: {
3101
SmallVector<int, 8> Mask;
3102
cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3104
// Cast the two input vectors.
3105
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3106
Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3108
// Convert the shuffle mask to the right # elements.
3109
Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3110
Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3111
Results.push_back(Tmp1);
3115
unsigned ExtOp = ISD::FP_EXTEND;
3116
if (NVT.isInteger()) {
3117
ISD::CondCode CCCode =
3118
cast<CondCodeSDNode>(Node->getOperand(2))->get();
3119
ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3121
Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3122
Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3123
Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3124
Tmp1, Tmp2, Node->getOperand(2)));
3130
// SelectionDAG::Legalize - This is the entry point for the file.
3132
void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3133
/// run - This is the main entry point to this class.
3135
SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();
added
removed
libclamav/c++/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
