1
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
2
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
4
define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
8
; CHECK-NEXT: movl $12, %eax
9
; CHECK-NEXT: cmovael (%rcx), %eax
12
%0 = lshr i32 %x, %n ; <i32> [#uses=1]
13
%1 = and i32 %0, 1 ; <i32> [#uses=1]
14
%toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
16
%.0 = select i1 %toBool, i32 %v, i32 12 ; <i32> [#uses=1]
19
define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
23
; CHECK-NEXT: movl $12, %eax
24
; CHECK-NEXT: cmovbl (%rcx), %eax
27
%0 = lshr i32 %x, %n ; <i32> [#uses=1]
28
%1 = and i32 %0, 1 ; <i32> [#uses=1]
29
%toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
31
%.0 = select i1 %toBool, i32 12, i32 %v ; <i32> [#uses=1]
36
; x86's 32-bit cmov doesn't clobber the high 32 bits of the destination
37
; if the condition is false. An explicit zero-extend (movl) is needed
40
declare void @bar(i64) nounwind
42
define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
44
; CHECK: cmovnel %edi, %esi
45
; CHECK-NEXT: movl %esi, %edi
47
%c = trunc i64 %a to i32
48
%d = trunc i64 %b to i32
49
%e = select i1 %p, i32 %c, i32 %d
50
%f = zext i32 %e to i64
51
call void @bar(i64 %f)
57
; CodeGen shouldn't try to do a setne after an expanded 8-bit conditional
58
; move without recomputing EFLAGS, because the expansion of the conditional
59
; move with control flow may clobber EFLAGS (e.g., with xor, to set the
62
; The test is a little awkward; the important part is that there's a test before the
67
@g_3 = external global i8 ; <i8*> [#uses=1]
68
@g_96 = external global i8 ; <i8*> [#uses=2]
69
@g_100 = external global i8 ; <i8*> [#uses=2]
70
@_2E_str = external constant [15 x i8], align 1 ; <[15 x i8]*> [#uses=1]
72
define i32 @test4() nounwind {
74
%0 = load i8* @g_3, align 1 ; <i8> [#uses=2]
75
%1 = sext i8 %0 to i32 ; <i32> [#uses=1]
76
%.lobit.i = lshr i8 %0, 7 ; <i8> [#uses=1]
77
%tmp.i = zext i8 %.lobit.i to i32 ; <i32> [#uses=1]
78
%tmp.not.i = xor i32 %tmp.i, 1 ; <i32> [#uses=1]
79
%iftmp.17.0.i.i = ashr i32 %1, %tmp.not.i ; <i32> [#uses=1]
80
%retval56.i.i = trunc i32 %iftmp.17.0.i.i to i8 ; <i8> [#uses=1]
81
%2 = icmp eq i8 %retval56.i.i, 0 ; <i1> [#uses=2]
82
%g_96.promoted.i = load i8* @g_96 ; <i8> [#uses=3]
83
%3 = icmp eq i8 %g_96.promoted.i, 0 ; <i1> [#uses=2]
84
br i1 %3, label %func_4.exit.i, label %bb.i.i.i
86
bb.i.i.i: ; preds = %entry
87
%4 = volatile load i8* @g_100, align 1 ; <i8> [#uses=0]
88
br label %func_4.exit.i
93
; CHECK: testb %al, %al
94
; CHECK-NEXT: setne %al
97
func_4.exit.i: ; preds = %bb.i.i.i, %entry
98
%.not.i = xor i1 %2, true ; <i1> [#uses=1]
99
%brmerge.i = or i1 %3, %.not.i ; <i1> [#uses=1]
100
%.mux.i = select i1 %2, i8 %g_96.promoted.i, i8 0 ; <i8> [#uses=1]
101
br i1 %brmerge.i, label %func_1.exit, label %bb.i.i
103
bb.i.i: ; preds = %func_4.exit.i
104
%5 = volatile load i8* @g_100, align 1 ; <i8> [#uses=0]
105
br label %func_1.exit
107
func_1.exit: ; preds = %bb.i.i, %func_4.exit.i
108
%g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ] ; <i8> [#uses=2]
109
store i8 %g_96.tmp.0.i, i8* @g_96
110
%6 = zext i8 %g_96.tmp.0.i to i32 ; <i32> [#uses=1]
111
%7 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind ; <i32> [#uses=0]
115
declare i32 @printf(i8* nocapture, ...) nounwind
118
; Should compile to setcc | -2.
120
define i32 @test5(i32* nocapture %P) nounwind readonly {
124
; CHECK: movzbl %al, %eax
125
; CHECK: orl $-2, %eax
128
%0 = load i32* %P, align 4 ; <i32> [#uses=1]
129
%1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1]
130
%iftmp.0.0 = select i1 %1, i32 -1, i32 -2 ; <i32> [#uses=1]
134
define i32 @test6(i32* nocapture %P) nounwind readonly {
138
; CHECK: movzbl %al, %eax
139
; CHECK: leal 4(%rax,%rax,8), %eax
141
%0 = load i32* %P, align 4 ; <i32> [#uses=1]
142
%1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1]
143
%iftmp.0.0 = select i1 %1, i32 4, i32 13 ; <i32> [#uses=1]
148
; Don't try to use a 16-bit conditional move to do an 8-bit select,
149
; because it isn't worth it. Just use a branch instead.
150
define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
152
; CHECK: testb $1, %dil
153
; CHECK-NEXT: jne LBB
155
%d = select i1 %c, i8 %a, i8 %b