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//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file contains the entry points for global functions defined in the LLVM
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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class ARMBaseTargetMachine;
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class formatted_raw_ostream;
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// Enums corresponding to ARM condition codes
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// The CondCodes constants map directly to the 4-bit encoding of the
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// condition field for predicated instructions.
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inline static CondCodes getOppositeCondition(CondCodes CC){
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default: llvm_unreachable("Unknown condition code");
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inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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default: llvm_unreachable("Unknown condition code");
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case ARMCC::EQ: return "eq";
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case ARMCC::NE: return "ne";
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case ARMCC::HS: return "hs";
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case ARMCC::LO: return "lo";
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case ARMCC::MI: return "mi";
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case ARMCC::PL: return "pl";
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case ARMCC::VS: return "vs";
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case ARMCC::VC: return "vc";
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case ARMCC::HI: return "hi";
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case ARMCC::LS: return "ls";
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case ARMCC::GE: return "ge";
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case ARMCC::LT: return "lt";
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case ARMCC::GT: return "gt";
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case ARMCC::LE: return "le";
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case ARMCC::AL: return "al";
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FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
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FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
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FunctionPass *createARMExpandPseudoPass();
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FunctionPass *createARMConstantIslandPass();
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FunctionPass *createNEONPreAllocPass();
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FunctionPass *createNEONMoveFixPass();
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FunctionPass *createThumb2ITBlockPass();
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FunctionPass *createThumb2SizeReductionPass();
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extern Target TheARMTarget, TheThumbTarget;
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} // end namespace llvm;
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// Defines symbolic names for ARM registers. This defines a mapping from
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// register name to register number.
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#include "ARMGenRegisterNames.inc"
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// Defines symbolic names for the ARM instructions.
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#include "ARMGenInstrNames.inc"