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//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file defines the TargetMachine and LLVMTargetMachine classes.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETMACHINE_H
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#define LLVM_TARGET_TARGETMACHINE_H
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#include "llvm/Target/TargetInstrItineraries.h"
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class TargetSubtarget;
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class TargetInstrInfo;
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class TargetIntrinsicInfo;
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class TargetFrameInfo;
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class TargetRegisterInfo;
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class PassManagerBase;
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class TargetELFWriterInfo;
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class formatted_raw_ostream;
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// Relocation model types.
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PIC_, // Cannot be named PIC due to collision with -DPIC
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// Code generation optimization level.
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namespace CodeGenOpt {
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//===----------------------------------------------------------------------===//
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/// TargetMachine - Primary interface to the complete machine description for
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/// the target machine. All target-specific information should be accessible
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/// through this interface.
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TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
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void operator=(const TargetMachine &); // DO NOT IMPLEMENT
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protected: // Can only create subclasses.
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TargetMachine(const Target &);
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/// getSubtargetImpl - virtual method implemented by subclasses that returns
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/// a reference to that target's TargetSubtarget-derived member variable.
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virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
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/// TheTarget - The Target that this machine was created for.
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const Target &TheTarget;
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/// AsmInfo - Contains target specific asm information.
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const MCAsmInfo *AsmInfo;
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virtual ~TargetMachine();
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const Target &getTarget() const { return TheTarget; }
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// Interfaces to the major aspects of target machine information:
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// -- Instruction opcode and operand information
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// -- Pipelines and scheduling information
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// -- Stack frame information
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// -- Selection DAG lowering information
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virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
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virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
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virtual TargetLowering *getTargetLowering() const { return 0; }
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virtual const TargetData *getTargetData() const { return 0; }
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/// getMCAsmInfo - Return target specific asm information.
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const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
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/// getSubtarget - This method returns a pointer to the specified type of
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/// TargetSubtarget. In debug builds, it verifies that the object being
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/// returned is of the correct type.
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template<typename STC> const STC &getSubtarget() const {
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return *static_cast<const STC*>(getSubtargetImpl());
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/// getRegisterInfo - If register information is available, return it. If
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/// not, return null. This is kept separate from RegInfo until RegInfo has
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/// details of graph coloring register allocation removed from it.
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virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
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/// getIntrinsicInfo - If intrinsic information is available, return it. If
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/// not, return null.
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virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
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/// getJITInfo - If this target supports a JIT, return information for it,
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/// otherwise return null.
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virtual TargetJITInfo *getJITInfo() { return 0; }
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/// getInstrItineraryData - Returns instruction itinerary data for the target
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/// or specific subtarget.
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virtual const InstrItineraryData getInstrItineraryData() const {
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return InstrItineraryData();
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/// getELFWriterInfo - If this target supports an ELF writer, return
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/// information for it, otherwise return null.
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virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
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/// getRelocationModel - Returns the code generation relocation model. The
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/// choices are static, PIC, and dynamic-no-pic, and target default.
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static Reloc::Model getRelocationModel();
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/// setRelocationModel - Sets the code generation relocation model.
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static void setRelocationModel(Reloc::Model Model);
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/// getCodeModel - Returns the code model. The choices are small, kernel,
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/// medium, large, and target default.
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static CodeModel::Model getCodeModel();
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/// setCodeModel - Sets the code model.
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static void setCodeModel(CodeModel::Model Model);
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/// getAsmVerbosityDefault - Returns the default value of asm verbosity.
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static bool getAsmVerbosityDefault();
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/// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
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static void setAsmVerbosityDefault(bool);
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/// CodeGenFileType - These enums are meant to be passed into
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/// addPassesToEmitFile to indicate what type of file to emit, and returned by
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/// it to indicate what type of file could actually be made.
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enum CodeGenFileType {
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CGFT_Null // Do not emit any output.
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/// getEnableTailMergeDefault - the default setting for -enable-tail-merge
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/// on this target. User flag overrides.
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virtual bool getEnableTailMergeDefault() const { return true; }
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/// addPassesToEmitFile - Add passes to the specified pass manager to get the
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/// specified file emitted. Typically this will involve several steps of code
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/// generation. This method should return true if emission of this file type
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/// is not supported, or false on success.
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virtual bool addPassesToEmitFile(PassManagerBase &,
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formatted_raw_ostream &,
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bool DisableVerify = true) {
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
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/// get machine code emitted. This uses a JITCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method returns true if machine code emission is
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virtual bool addPassesToEmitMachineCode(PassManagerBase &,
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bool DisableVerify = true) {
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/// addPassesToEmitWholeFile - This method can be implemented by targets that
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/// require having the entire module at once. This is not recommended, do not
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virtual bool WantsWholeFile() const { return false; }
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virtual bool addPassesToEmitWholeFile(PassManager &, formatted_raw_ostream &,
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bool DisableVerify = true) {
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/// LLVMTargetMachine - This class describes a target machine that is
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/// implemented with the LLVM target-independent code generator.
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class LLVMTargetMachine : public TargetMachine {
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protected: // Can only create subclasses.
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LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
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/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
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/// both emitting to assembly files or machine code output.
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bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
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virtual void setCodeModelForJIT();
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virtual void setCodeModelForStatic();
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/// addPassesToEmitFile - Add passes to the specified pass manager to get the
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/// specified file emitted. Typically this will involve several steps of code
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/// generation. If OptLevel is None, the code generator should emit code as
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/// fast as possible, though the generated code may be less efficient.
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virtual bool addPassesToEmitFile(PassManagerBase &PM,
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formatted_raw_ostream &Out,
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CodeGenFileType FileType,
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bool DisableVerify = true);
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
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/// get machine code emitted. This uses a JITCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method returns true if machine code emission is
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virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
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bool DisableVerify = true);
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/// Target-Independent Code Generator Pass Configuration Options.
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/// addInstSelector - This method should add any "last minute" LLVM->LLVM
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/// passes, then install an instruction selector pass, which converts from
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/// LLVM code to machine instructions.
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virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
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/// addPreRegAlloc - This method may be implemented by targets that want to
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/// run passes immediately before register allocation. This should return
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/// true if -print-machineinstrs should print after these passes.
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virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
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/// addPostRegAlloc - This method may be implemented by targets that want
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/// to run passes after register allocation but before prolog-epilog
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/// insertion. This should return true if -print-machineinstrs should print
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/// after these passes.
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virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
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/// addPreSched2 - This method may be implemented by targets that want to
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/// run passes after prolog-epilog insertion and before the second instruction
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/// scheduling pass. This should return true if -print-machineinstrs should
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/// print after these passes.
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virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
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/// addPreEmitPass - This pass may be implemented by targets that want to run
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/// passes immediately before machine code is emitted. This should return
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/// true if -print-machineinstrs should print out the code after the passes.
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virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
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/// addCodeEmitter - This pass should be overridden by the target to add a
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/// code emitter, if supported. If this is not supported, 'true' should be
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virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
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/// getEnableTailMergeDefault - the default setting for -enable-tail-merge
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/// on this target. User flag overrides.
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virtual bool getEnableTailMergeDefault() const { return true; }
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} // End llvm namespace