~louis/ubuntu/trusty/clamav/lp799623_fix

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//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//

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//

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// The LLVM Compiler Infrastructure

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//

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// This file is distributed under the University of Illinois Open Source

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// License. See LICENSE.TXT for details.

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//

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//===----------------------------------------------------------------------===//

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//

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// This file is part of the X86 Disassembler Emitter.

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// It contains the implementation of a single recognizable instruction.

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// Documentation for the disassembler emitter in general can be found in

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// X86DisasemblerEmitter.h.

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//

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//===----------------------------------------------------------------------===//

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#include "X86DisassemblerShared.h"

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#include "X86RecognizableInstr.h"

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#include "X86ModRMFilters.h"

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#include "llvm/Support/ErrorHandling.h"

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#include <string>

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using namespace llvm;

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#define MRM_MAPPING \

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MAP(C1, 33) \

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MAP(C2, 34) \

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MAP(C3, 35) \

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MAP(C4, 36) \

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MAP(C8, 37) \

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MAP(C9, 38) \

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MAP(E8, 39) \

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MAP(F0, 40) \

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MAP(F8, 41) \

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MAP(F9, 42)

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// A clone of X86 since we can't depend on something that is generated.

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namespace X86Local {

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enum {

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Pseudo = 0,

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RawFrm = 1,

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AddRegFrm = 2,

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MRMDestReg = 3,

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MRMDestMem = 4,

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MRMSrcReg = 5,

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MRMSrcMem = 6,

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MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,

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MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,

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MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,

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MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,

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MRMInitReg = 32,

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#define MAP(from, to) MRM_##from = to,

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MRM_MAPPING

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#undef MAP

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lastMRM

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};

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enum {

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TB = 1,

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REP = 2,

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D8 = 3, D9 = 4, DA = 5, DB = 6,

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DC = 7, DD = 8, DE = 9, DF = 10,

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XD = 11, XS = 12,

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T8 = 13, P_TA = 14,

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P_0F_AE = 16, P_0F_01 = 17

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};

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}

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// If rows are added to the opcode extension tables, then corresponding entries

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// must be added here.

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//

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// If the row corresponds to a single byte (i.e., 8f), then add an entry for

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// that byte to ONE_BYTE_EXTENSION_TABLES.

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//

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// If the row corresponds to two bytes where the first is 0f, add an entry for

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// the second byte to TWO_BYTE_EXTENSION_TABLES.

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//

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// If the row corresponds to some other set of bytes, you will need to modify

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// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes

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// to the X86 TD files, except in two cases: if the first two bytes of such a

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// new combination are 0f 38 or 0f 3a, you just have to add maps called

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// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a

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// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line

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// in RecognizableInstr::emitDecodePath().

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#define ONE_BYTE_EXTENSION_TABLES \

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EXTENSION_TABLE(80) \

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EXTENSION_TABLE(81) \

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EXTENSION_TABLE(82) \

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EXTENSION_TABLE(83) \

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EXTENSION_TABLE(8f) \

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EXTENSION_TABLE(c0) \

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EXTENSION_TABLE(c1) \

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EXTENSION_TABLE(c6) \

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EXTENSION_TABLE(c7) \

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EXTENSION_TABLE(d0) \

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EXTENSION_TABLE(d1) \

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EXTENSION_TABLE(d2) \

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EXTENSION_TABLE(d3) \

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EXTENSION_TABLE(f6) \

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EXTENSION_TABLE(f7) \

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EXTENSION_TABLE(fe) \

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EXTENSION_TABLE(ff)

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#define TWO_BYTE_EXTENSION_TABLES \

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EXTENSION_TABLE(00) \

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EXTENSION_TABLE(01) \

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EXTENSION_TABLE(18) \

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EXTENSION_TABLE(71) \

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EXTENSION_TABLE(72) \

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EXTENSION_TABLE(73) \

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EXTENSION_TABLE(ae) \

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EXTENSION_TABLE(b9) \

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EXTENSION_TABLE(ba) \

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EXTENSION_TABLE(c7)

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using namespace X86Disassembler;

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/// needsModRMForDecode - Indicates whether a particular instruction requires a

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/// ModR/M byte for the instruction to be properly decoded. For example, a

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/// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to

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/// 0b11.

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///

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/// @param form - The form of the instruction.

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/// @return - true if the form implies that a ModR/M byte is required, false

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/// otherwise.

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static bool needsModRMForDecode(uint8_t form) {

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if (form == X86Local::MRMDestReg ||

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form == X86Local::MRMDestMem ||

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form == X86Local::MRMSrcReg ||

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form == X86Local::MRMSrcMem ||

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(form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||

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(form >= X86Local::MRM0m && form <= X86Local::MRM7m))

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return true;

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else

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return false;

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}

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/// isRegFormat - Indicates whether a particular form requires the Mod field of

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/// the ModR/M byte to be 0b11.

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///

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/// @param form - The form of the instruction.

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/// @return - true if the form implies that Mod must be 0b11, false

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/// otherwise.

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static bool isRegFormat(uint8_t form) {

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if (form == X86Local::MRMDestReg ||

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form == X86Local::MRMSrcReg ||

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(form >= X86Local::MRM0r && form <= X86Local::MRM7r))

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return true;

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else

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return false;

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}

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/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.

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/// Useful for switch statements and the like.

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///

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/// @param init - A reference to the BitsInit to be decoded.

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/// @return - The field, with the first bit in the BitsInit as the lowest

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/// order bit.

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static uint8_t byteFromBitsInit(BitsInit &init) {

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int width = init.getNumBits();

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assert(width <= 8 && "Field is too large for uint8_t!");

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int index;

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uint8_t mask = 0x01;

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uint8_t ret = 0;

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for (index = 0; index < width; index++) {

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if (static_cast<BitInit*>(init.getBit(index))->getValue())

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ret |= mask;

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mask <<= 1;

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}

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return ret;

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}

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/// byteFromRec - Extract a value at most 8 bits in with from a Record given the

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/// name of the field.

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///

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/// @param rec - The record from which to extract the value.

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/// @param name - The name of the field in the record.

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/// @return - The field, as translated by byteFromBitsInit().

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static uint8_t byteFromRec(const Record* rec, const std::string &name) {

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BitsInit* bits = rec->getValueAsBitsInit(name);

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return byteFromBitsInit(*bits);

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}

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RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,

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const CodeGenInstruction &insn,

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InstrUID uid) {

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UID = uid;

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Rec = insn.TheDef;

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Name = Rec->getName();

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Spec = &tables.specForUID(UID);

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if (!Rec->isSubClassOf("X86Inst")) {

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ShouldBeEmitted = false;

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return;

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}

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Prefix = byteFromRec(Rec, "Prefix");

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Opcode = byteFromRec(Rec, "Opcode");

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Form = byteFromRec(Rec, "FormBits");

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SegOvr = byteFromRec(Rec, "SegOvrBits");

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HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");

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HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");

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HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");

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IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");

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Name = Rec->getName();

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AsmString = Rec->getValueAsString("AsmString");

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Operands = &insn.OperandList;

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IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos);

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HasFROperands = false;

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ShouldBeEmitted = true;

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}

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void RecognizableInstr::processInstr(DisassemblerTables &tables,

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const CodeGenInstruction &insn,

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InstrUID uid)

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{

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RecognizableInstr recogInstr(tables, insn, uid);

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recogInstr.emitInstructionSpecifier(tables);

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if (recogInstr.shouldBeEmitted())

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recogInstr.emitDecodePath(tables);

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}

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InstructionContext RecognizableInstr::insnContext() const {

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InstructionContext insnContext;

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if (Name.find("64") != Name.npos || HasREX_WPrefix) {

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if (HasREX_WPrefix && HasOpSizePrefix)

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insnContext = IC_64BIT_REXW_OPSIZE;

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else if (HasOpSizePrefix)

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insnContext = IC_64BIT_OPSIZE;

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else if (HasREX_WPrefix && Prefix == X86Local::XS)

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insnContext = IC_64BIT_REXW_XS;

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else if (HasREX_WPrefix && Prefix == X86Local::XD)

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insnContext = IC_64BIT_REXW_XD;

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else if (Prefix == X86Local::XD)

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insnContext = IC_64BIT_XD;

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else if (Prefix == X86Local::XS)

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insnContext = IC_64BIT_XS;

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else if (HasREX_WPrefix)

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insnContext = IC_64BIT_REXW;

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else

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insnContext = IC_64BIT;

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} else {

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if (HasOpSizePrefix)

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insnContext = IC_OPSIZE;

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else if (Prefix == X86Local::XD)

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insnContext = IC_XD;

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else if (Prefix == X86Local::XS)

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insnContext = IC_XS;

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else

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insnContext = IC;

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}

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return insnContext;

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}

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RecognizableInstr::filter_ret RecognizableInstr::filter() const {

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// Filter out intrinsics

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if (!Rec->isSubClassOf("X86Inst"))

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return FILTER_STRONG;

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if (Form == X86Local::Pseudo ||

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IsCodeGenOnly)

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return FILTER_STRONG;

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if (Form == X86Local::MRMInitReg)

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return FILTER_STRONG;

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// Filter out instructions with a LOCK prefix;

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// prefer forms that do not have the prefix

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if (HasLockPrefix)

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return FILTER_WEAK;

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// Filter out artificial instructions

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if (Name.find("TAILJMP") != Name.npos ||

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Name.find("_Int") != Name.npos ||

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Name.find("_int") != Name.npos ||

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Name.find("Int_") != Name.npos ||

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Name.find("_NOREX") != Name.npos ||

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Name.find("EH_RETURN") != Name.npos ||

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Name.find("V_SET") != Name.npos ||

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Name.find("LOCK_") != Name.npos ||

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Name.find("WIN") != Name.npos)

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return FILTER_STRONG;

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// Special cases.

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if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")

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return FILTER_WEAK;

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if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")

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return FILTER_WEAK;

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if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)

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return FILTER_WEAK;

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if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)

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return FILTER_WEAK;

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if (Name.find("Fs") != Name.npos)

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return FILTER_WEAK;

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if (Name == "MOVLPDrr" ||

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Name == "MOVLPSrr" ||

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Name == "PUSHFQ" ||

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Name == "BSF16rr" ||

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Name == "BSF16rm" ||

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Name == "BSR16rr" ||

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Name == "BSR16rm" ||

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Name == "MOVSX16rm8" ||

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Name == "MOVSX16rr8" ||

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Name == "MOVZX16rm8" ||

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Name == "MOVZX16rr8" ||

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Name == "PUSH32i16" ||

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Name == "PUSH64i16" ||

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Name == "MOVPQI2QImr" ||

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Name == "MOVSDmr" ||

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Name == "MOVSDrm" ||

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Name == "MOVSSmr" ||

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Name == "MOVSSrm" ||

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Name == "MMX_MOVD64rrv164" ||

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Name == "CRC32m16" ||

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Name == "MOV64ri64i32" ||

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Name == "CRC32r16")

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return FILTER_WEAK;

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// Filter out instructions with segment override prefixes.

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// They're too messy to handle now and we'll special case them if needed.

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347

if (SegOvr)

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return FILTER_STRONG;

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// Filter out instructions that can't be printed.

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if (AsmString.size() == 0)

353

return FILTER_STRONG;

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// Filter out instructions with subreg operands.

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if (AsmString.find("subreg") != AsmString.npos)

358

return FILTER_STRONG;

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if (HasFROperands && Name.find("MOV") != Name.npos &&

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((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||

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(Name.find("to") != Name.npos)))

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return FILTER_WEAK;

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return FILTER_NORMAL;

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}

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void RecognizableInstr::handleOperand(

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bool optional,

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unsigned &operandIndex,

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unsigned &physicalOperandIndex,

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unsigned &numPhysicalOperands,

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unsigned *operandMapping,

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OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {

375

if (optional) {

376

if (physicalOperandIndex >= numPhysicalOperands)

377

return;

378

} else {

379

assert(physicalOperandIndex < numPhysicalOperands);

380

}

381

382

while (operandMapping[operandIndex] != operandIndex) {

383

Spec->operands[operandIndex].encoding = ENCODING_DUP;

384

Spec->operands[operandIndex].type =

385

(OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);

386

++operandIndex;

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}

388

389

const std::string &typeName = (*Operands)[operandIndex].Rec->getName();

390

391

Spec->operands[operandIndex].encoding = encodingFromString(typeName,

392

HasOpSizePrefix);

393

Spec->operands[operandIndex].type = typeFromString(typeName,

394

IsSSE,

395

HasREX_WPrefix,

396

HasOpSizePrefix);

397

398

++operandIndex;

399

++physicalOperandIndex;

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}

401

402

void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {

403

Spec->name = Name;

404

405

if (!Rec->isSubClassOf("X86Inst"))

406

return;

407

408

switch (filter()) {

409

case FILTER_WEAK:

410

Spec->filtered = true;

411

break;

412

case FILTER_STRONG:

413

ShouldBeEmitted = false;

414

return;

415

case FILTER_NORMAL:

416

break;

417

}

418

419

Spec->insnContext = insnContext();

420

421

const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;

422

423

unsigned operandIndex;

424

unsigned numOperands = OperandList.size();

425

unsigned numPhysicalOperands = 0;

426

427

// operandMapping maps from operands in OperandList to their originals.

428

// If operandMapping[i] != i, then the entry is a duplicate.

429

unsigned operandMapping[X86_MAX_OPERANDS];

430

431

bool hasFROperands = false;

432

433

assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");

434

435

for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {

436

if (OperandList[operandIndex].Constraints.size()) {

437

const CodeGenInstruction::ConstraintInfo &Constraint =

438

OperandList[operandIndex].Constraints[0];

439

if (Constraint.isTied()) {

440

operandMapping[operandIndex] = Constraint.getTiedOperand();

441

} else {

442

++numPhysicalOperands;

443

operandMapping[operandIndex] = operandIndex;

444

}

445

} else {

446

++numPhysicalOperands;

447

operandMapping[operandIndex] = operandIndex;

448

}

449

450

const std::string &recName = OperandList[operandIndex].Rec->getName();

451

452

if (recName.find("FR") != recName.npos)

453

hasFROperands = true;

454

}

455

456

if (hasFROperands && Name.find("MOV") != Name.npos &&

457

((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||

458

(Name.find("to") != Name.npos)))

459

ShouldBeEmitted = false;

460

461

if (!ShouldBeEmitted)

462

return;

463

464

#define HANDLE_OPERAND(class) \

465

handleOperand(false, \

466

operandIndex, \

467

physicalOperandIndex, \

468

numPhysicalOperands, \

469

operandMapping, \

470

class##EncodingFromString);

471

472

#define HANDLE_OPTIONAL(class) \

473

handleOperand(true, \

474

operandIndex, \

475

physicalOperandIndex, \

476

numPhysicalOperands, \

477

operandMapping, \

478

class##EncodingFromString);

479

480

// operandIndex should always be < numOperands

481

operandIndex = 0;

482

// physicalOperandIndex should always be < numPhysicalOperands

483

unsigned physicalOperandIndex = 0;

484

485

switch (Form) {

486

case X86Local::RawFrm:

487

// Operand 1 (optional) is an address or immediate.

488

// Operand 2 (optional) is an immediate.

489

assert(numPhysicalOperands <= 2 &&

490

"Unexpected number of operands for RawFrm");

491

HANDLE_OPTIONAL(relocation)

492

HANDLE_OPTIONAL(immediate)

493

break;

494

case X86Local::AddRegFrm:

495

// Operand 1 is added to the opcode.

496

// Operand 2 (optional) is an address.

497

assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&

498

"Unexpected number of operands for AddRegFrm");

499

HANDLE_OPERAND(opcodeModifier)

500

HANDLE_OPTIONAL(relocation)

501

break;

502

case X86Local::MRMDestReg:

503

// Operand 1 is a register operand in the R/M field.

504

// Operand 2 is a register operand in the Reg/Opcode field.

505

// Operand 3 (optional) is an immediate.

506

assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&

507

"Unexpected number of operands for MRMDestRegFrm");

508

HANDLE_OPERAND(rmRegister)

509

HANDLE_OPERAND(roRegister)

510

HANDLE_OPTIONAL(immediate)

511

break;

512

case X86Local::MRMDestMem:

513

// Operand 1 is a memory operand (possibly SIB-extended)

514

// Operand 2 is a register operand in the Reg/Opcode field.

515

// Operand 3 (optional) is an immediate.

516

assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&

517

"Unexpected number of operands for MRMDestMemFrm");

518

HANDLE_OPERAND(memory)

519

HANDLE_OPERAND(roRegister)

520

HANDLE_OPTIONAL(immediate)

521

break;

522

case X86Local::MRMSrcReg:

523

// Operand 1 is a register operand in the Reg/Opcode field.

524

// Operand 2 is a register operand in the R/M field.

525

// Operand 3 (optional) is an immediate.

526

assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&

527

"Unexpected number of operands for MRMSrcRegFrm");

528

HANDLE_OPERAND(roRegister)

529

HANDLE_OPERAND(rmRegister)

530

HANDLE_OPTIONAL(immediate)

531

break;

532

case X86Local::MRMSrcMem:

533

// Operand 1 is a register operand in the Reg/Opcode field.

534

// Operand 2 is a memory operand (possibly SIB-extended)

535

// Operand 3 (optional) is an immediate.

536

assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&

537

"Unexpected number of operands for MRMSrcMemFrm");

538

HANDLE_OPERAND(roRegister)

539

HANDLE_OPERAND(memory)

540

HANDLE_OPTIONAL(immediate)

541

break;

542

case X86Local::MRM0r:

543

case X86Local::MRM1r:

544

case X86Local::MRM2r:

545

case X86Local::MRM3r:

546

case X86Local::MRM4r:

547

case X86Local::MRM5r:

548

case X86Local::MRM6r:

549

case X86Local::MRM7r:

550

// Operand 1 is a register operand in the R/M field.

551

// Operand 2 (optional) is an immediate or relocation.

552

assert(numPhysicalOperands <= 2 &&

553

"Unexpected number of operands for MRMnRFrm");

554

HANDLE_OPTIONAL(rmRegister)

555

HANDLE_OPTIONAL(relocation)

556

break;

557

case X86Local::MRM0m:

558

case X86Local::MRM1m:

559

case X86Local::MRM2m:

560

case X86Local::MRM3m:

561

case X86Local::MRM4m:

562

case X86Local::MRM5m:

563

case X86Local::MRM6m:

564

case X86Local::MRM7m:

565

// Operand 1 is a memory operand (possibly SIB-extended)

566

// Operand 2 (optional) is an immediate or relocation.

567

assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&

568

"Unexpected number of operands for MRMnMFrm");

569

HANDLE_OPERAND(memory)

570

HANDLE_OPTIONAL(relocation)

571

break;

572

case X86Local::MRMInitReg:

573

// Ignored.

574

break;

575

}

576

577

#undef HANDLE_OPERAND

578

#undef HANDLE_OPTIONAL

579

}

580

581

void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {

582

// Special cases where the LLVM tables are not complete

583

584

#define MAP(from, to) \

585

case X86Local::MRM_##from: \

586

filter = new ExactFilter(0x##from); \

587

break;

588

589

OpcodeType opcodeType = (OpcodeType)-1;

590

591

ModRMFilter* filter = NULL;

592

uint8_t opcodeToSet = 0;

593

594

switch (Prefix) {

595

// Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f

596

case X86Local::XD:

597

case X86Local::XS:

598

case X86Local::TB:

599

opcodeType = TWOBYTE;

600

601

switch (Opcode) {

602

default:

603

if (needsModRMForDecode(Form))

604

filter = new ModFilter(isRegFormat(Form));

605

else

606

filter = new DumbFilter();

607

break;

608

#define EXTENSION_TABLE(n) case 0x##n:

609

TWO_BYTE_EXTENSION_TABLES

610

#undef EXTENSION_TABLE

611

switch (Form) {

612

default:

613

llvm_unreachable("Unhandled two-byte extended opcode");

614

case X86Local::MRM0r:

615

case X86Local::MRM1r:

616

case X86Local::MRM2r:

617

case X86Local::MRM3r:

618

case X86Local::MRM4r:

619

case X86Local::MRM5r:

620

case X86Local::MRM6r:

621

case X86Local::MRM7r:

622

filter = new ExtendedFilter(true, Form - X86Local::MRM0r);

623

break;

624

case X86Local::MRM0m:

625

case X86Local::MRM1m:

626

case X86Local::MRM2m:

627

case X86Local::MRM3m:

628

case X86Local::MRM4m:

629

case X86Local::MRM5m:

630

case X86Local::MRM6m:

631

case X86Local::MRM7m:

632

filter = new ExtendedFilter(false, Form - X86Local::MRM0m);

633

break;

634

MRM_MAPPING

635

} // switch (Form)

636

break;

637

} // switch (Opcode)

638

opcodeToSet = Opcode;

639

break;

640

case X86Local::T8:

641

opcodeType = THREEBYTE_38;

642

if (needsModRMForDecode(Form))

643

filter = new ModFilter(isRegFormat(Form));

644

else

645

filter = new DumbFilter();

646

opcodeToSet = Opcode;

647

break;

648

case X86Local::P_TA:

649

opcodeType = THREEBYTE_3A;

650

if (needsModRMForDecode(Form))

651

filter = new ModFilter(isRegFormat(Form));

652

else

653

filter = new DumbFilter();

654

opcodeToSet = Opcode;

655

break;

656

case X86Local::D8:

657

case X86Local::D9:

658

case X86Local::DA:

659

case X86Local::DB:

660

case X86Local::DC:

661

case X86Local::DD:

662

case X86Local::DE:

663

case X86Local::DF:

664

assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");

665

opcodeType = ONEBYTE;

666

if (Form == X86Local::AddRegFrm) {

667

Spec->modifierType = MODIFIER_MODRM;

668

Spec->modifierBase = Opcode;

669

filter = new AddRegEscapeFilter(Opcode);

670

} else {

671

filter = new EscapeFilter(true, Opcode);

672

}

673

opcodeToSet = 0xd8 + (Prefix - X86Local::D8);

674

break;

675

default:

676

opcodeType = ONEBYTE;

677

switch (Opcode) {

678

#define EXTENSION_TABLE(n) case 0x##n:

679

ONE_BYTE_EXTENSION_TABLES

680

#undef EXTENSION_TABLE

681

switch (Form) {

682

default:

683

llvm_unreachable("Fell through the cracks of a single-byte "

684

"extended opcode");

685

case X86Local::MRM0r:

686

case X86Local::MRM1r:

687

case X86Local::MRM2r:

688

case X86Local::MRM3r:

689

case X86Local::MRM4r:

690

case X86Local::MRM5r:

691

case X86Local::MRM6r:

692

case X86Local::MRM7r:

693

filter = new ExtendedFilter(true, Form - X86Local::MRM0r);

694

break;

695

case X86Local::MRM0m:

696

case X86Local::MRM1m:

697

case X86Local::MRM2m:

698

case X86Local::MRM3m:

699

case X86Local::MRM4m:

700

case X86Local::MRM5m:

701

case X86Local::MRM6m:

702

case X86Local::MRM7m:

703

filter = new ExtendedFilter(false, Form - X86Local::MRM0m);

704

break;

705

MRM_MAPPING

706

} // switch (Form)

707

break;

708

case 0xd8:

709

case 0xd9:

710

case 0xda:

711

case 0xdb:

712

case 0xdc:

713

case 0xdd:

714

case 0xde:

715

case 0xdf:

716

filter = new EscapeFilter(false, Form - X86Local::MRM0m);

717

break;

718

default:

719

if (needsModRMForDecode(Form))

720

filter = new ModFilter(isRegFormat(Form));

721

else

722

filter = new DumbFilter();

723

break;

724

} // switch (Opcode)

725

opcodeToSet = Opcode;

726

} // switch (Prefix)

727

728

assert(opcodeType != (OpcodeType)-1 &&

729

"Opcode type not set");

730

assert(filter && "Filter not set");

731

732

if (Form == X86Local::AddRegFrm) {

733

if(Spec->modifierType != MODIFIER_MODRM) {

734

assert(opcodeToSet < 0xf9 &&

735

"Not enough room for all ADDREG_FRM operands");

736

737

uint8_t currentOpcode;

738

739

for (currentOpcode = opcodeToSet;

740

currentOpcode < opcodeToSet + 8;

741

++currentOpcode)

742

tables.setTableFields(opcodeType,

743

insnContext(),

744

currentOpcode,

745

*filter,

746

UID);

747

748

Spec->modifierType = MODIFIER_OPCODE;

749

Spec->modifierBase = opcodeToSet;

750

} else {

751

// modifierBase was set where MODIFIER_MODRM was set

752

tables.setTableFields(opcodeType,

753

insnContext(),

754

opcodeToSet,

755

*filter,

756

UID);

757

}

758

} else {

759

tables.setTableFields(opcodeType,

760

insnContext(),

761

opcodeToSet,

762

*filter,

763

UID);

764

765

Spec->modifierType = MODIFIER_NONE;

766

Spec->modifierBase = opcodeToSet;

767

}

768

769

delete filter;

770

771

#undef MAP

772

}

773

774

#define TYPE(str, type) if (s == str) return type;

775

OperandType RecognizableInstr::typeFromString(const std::string &s,

776

bool isSSE,

777

bool hasREX_WPrefix,

778

bool hasOpSizePrefix) {

779

if (isSSE) {

780

// For SSE instructions, we ignore the OpSize prefix and force operand

781

// sizes.

782

TYPE("GR16", TYPE_R16)

783

TYPE("GR32", TYPE_R32)

784

TYPE("GR64", TYPE_R64)

785

}

786

if(hasREX_WPrefix) {

787

// For instructions with a REX_W prefix, a declared 32-bit register encoding

788

// is special.

789

TYPE("GR32", TYPE_R32)

790

}

791

if(!hasOpSizePrefix) {

792

// For instructions without an OpSize prefix, a declared 16-bit register or

793

// immediate encoding is special.

794

TYPE("GR16", TYPE_R16)

795

TYPE("i16imm", TYPE_IMM16)

796

}

797

TYPE("i16mem", TYPE_Mv)

798

TYPE("i16imm", TYPE_IMMv)

799

TYPE("i16i8imm", TYPE_IMMv)

800

TYPE("GR16", TYPE_Rv)

801

TYPE("i32mem", TYPE_Mv)

802

TYPE("i32imm", TYPE_IMMv)

803

TYPE("i32i8imm", TYPE_IMM32)

804

TYPE("GR32", TYPE_Rv)

805

TYPE("i64mem", TYPE_Mv)

806

TYPE("i64i32imm", TYPE_IMM64)

807

TYPE("i64i8imm", TYPE_IMM64)

808

TYPE("GR64", TYPE_R64)

809

TYPE("i8mem", TYPE_M8)

810

TYPE("i8imm", TYPE_IMM8)

811

TYPE("GR8", TYPE_R8)

812

TYPE("VR128", TYPE_XMM128)

813

TYPE("f128mem", TYPE_M128)

814

TYPE("FR64", TYPE_XMM64)

815

TYPE("f64mem", TYPE_M64FP)

816

TYPE("FR32", TYPE_XMM32)

817

TYPE("f32mem", TYPE_M32FP)

818

TYPE("RST", TYPE_ST)

819

TYPE("i128mem", TYPE_M128)

820

TYPE("i64i32imm_pcrel", TYPE_REL64)

821

TYPE("i32imm_pcrel", TYPE_REL32)

822

TYPE("SSECC", TYPE_IMM8)

823

TYPE("brtarget", TYPE_RELv)

824

TYPE("brtarget8", TYPE_REL8)

825

TYPE("f80mem", TYPE_M80FP)

826

TYPE("lea32mem", TYPE_LEA)

827

TYPE("lea64_32mem", TYPE_LEA)

828

TYPE("lea64mem", TYPE_LEA)

829

TYPE("VR64", TYPE_MM64)

830

TYPE("i64imm", TYPE_IMMv)

831

TYPE("opaque32mem", TYPE_M1616)

832

TYPE("opaque48mem", TYPE_M1632)

833

TYPE("opaque80mem", TYPE_M1664)

834

TYPE("opaque512mem", TYPE_M512)

835

TYPE("SEGMENT_REG", TYPE_SEGMENTREG)

836

TYPE("DEBUG_REG", TYPE_DEBUGREG)

837

TYPE("CONTROL_REG_32", TYPE_CR32)

838

TYPE("CONTROL_REG_64", TYPE_CR64)

839

TYPE("offset8", TYPE_MOFFS8)

840

TYPE("offset16", TYPE_MOFFS16)

841

TYPE("offset32", TYPE_MOFFS32)

842

TYPE("offset64", TYPE_MOFFS64)

843

errs() << "Unhandled type string " << s << "\n";

844

llvm_unreachable("Unhandled type string");

845

}

846

#undef TYPE

847

848

#define ENCODING(str, encoding) if (s == str) return encoding;

849

OperandEncoding RecognizableInstr::immediateEncodingFromString

850

(const std::string &s,

851

bool hasOpSizePrefix) {

852

if(!hasOpSizePrefix) {

853

// For instructions without an OpSize prefix, a declared 16-bit register or

854

// immediate encoding is special.

855

ENCODING("i16imm", ENCODING_IW)

856

}

857

ENCODING("i32i8imm", ENCODING_IB)

858

ENCODING("SSECC", ENCODING_IB)

859

ENCODING("i16imm", ENCODING_Iv)

860

ENCODING("i16i8imm", ENCODING_IB)

861

ENCODING("i32imm", ENCODING_Iv)

862

ENCODING("i64i32imm", ENCODING_ID)

863

ENCODING("i64i8imm", ENCODING_IB)

864

ENCODING("i8imm", ENCODING_IB)

865

errs() << "Unhandled immediate encoding " << s << "\n";

866

llvm_unreachable("Unhandled immediate encoding");

867

}

868

869

OperandEncoding RecognizableInstr::rmRegisterEncodingFromString

870

(const std::string &s,

871

bool hasOpSizePrefix) {

872

ENCODING("GR16", ENCODING_RM)

873

ENCODING("GR32", ENCODING_RM)

874

ENCODING("GR64", ENCODING_RM)

875

ENCODING("GR8", ENCODING_RM)

876

ENCODING("VR128", ENCODING_RM)

877

ENCODING("FR64", ENCODING_RM)

878

ENCODING("FR32", ENCODING_RM)

879

ENCODING("VR64", ENCODING_RM)

880

errs() << "Unhandled R/M register encoding " << s << "\n";

881

llvm_unreachable("Unhandled R/M register encoding");

882

}

883

884

OperandEncoding RecognizableInstr::roRegisterEncodingFromString

885

(const std::string &s,

886

bool hasOpSizePrefix) {

887

ENCODING("GR16", ENCODING_REG)

888

ENCODING("GR32", ENCODING_REG)

889

ENCODING("GR64", ENCODING_REG)

890

ENCODING("GR8", ENCODING_REG)

891

ENCODING("VR128", ENCODING_REG)

892

ENCODING("FR64", ENCODING_REG)

893

ENCODING("FR32", ENCODING_REG)

894

ENCODING("VR64", ENCODING_REG)

895

ENCODING("SEGMENT_REG", ENCODING_REG)

896

ENCODING("DEBUG_REG", ENCODING_REG)

897

ENCODING("CONTROL_REG_32", ENCODING_REG)

898

ENCODING("CONTROL_REG_64", ENCODING_REG)

899

errs() << "Unhandled reg/opcode register encoding " << s << "\n";

900

llvm_unreachable("Unhandled reg/opcode register encoding");

901

}

902

903

OperandEncoding RecognizableInstr::memoryEncodingFromString

904

(const std::string &s,

905

bool hasOpSizePrefix) {

906

ENCODING("i16mem", ENCODING_RM)

907

ENCODING("i32mem", ENCODING_RM)

908

ENCODING("i64mem", ENCODING_RM)

909

ENCODING("i8mem", ENCODING_RM)

910

ENCODING("f128mem", ENCODING_RM)

911

ENCODING("f64mem", ENCODING_RM)

912

ENCODING("f32mem", ENCODING_RM)

913

ENCODING("i128mem", ENCODING_RM)

914

ENCODING("f80mem", ENCODING_RM)

915

ENCODING("lea32mem", ENCODING_RM)

916

ENCODING("lea64_32mem", ENCODING_RM)

917

ENCODING("lea64mem", ENCODING_RM)

918

ENCODING("opaque32mem", ENCODING_RM)

919

ENCODING("opaque48mem", ENCODING_RM)

920

ENCODING("opaque80mem", ENCODING_RM)

921

ENCODING("opaque512mem", ENCODING_RM)

922

errs() << "Unhandled memory encoding " << s << "\n";

923

llvm_unreachable("Unhandled memory encoding");

924

}

925

926

OperandEncoding RecognizableInstr::relocationEncodingFromString

927

(const std::string &s,

928

bool hasOpSizePrefix) {

929

if(!hasOpSizePrefix) {

930

// For instructions without an OpSize prefix, a declared 16-bit register or

931

// immediate encoding is special.

932

ENCODING("i16imm", ENCODING_IW)

933

}

934

ENCODING("i16imm", ENCODING_Iv)

935

ENCODING("i16i8imm", ENCODING_IB)

936

ENCODING("i32imm", ENCODING_Iv)

937

ENCODING("i32i8imm", ENCODING_IB)

938

ENCODING("i64i32imm", ENCODING_ID)

939

ENCODING("i64i8imm", ENCODING_IB)

940

ENCODING("i8imm", ENCODING_IB)

941

ENCODING("i64i32imm_pcrel", ENCODING_ID)

942

ENCODING("i32imm_pcrel", ENCODING_ID)

943

ENCODING("brtarget", ENCODING_Iv)

944

ENCODING("brtarget8", ENCODING_IB)

945

ENCODING("i64imm", ENCODING_IO)

946

ENCODING("offset8", ENCODING_Ia)

947

ENCODING("offset16", ENCODING_Ia)

948

ENCODING("offset32", ENCODING_Ia)

949

ENCODING("offset64", ENCODING_Ia)

950

errs() << "Unhandled relocation encoding " << s << "\n";

951

llvm_unreachable("Unhandled relocation encoding");

952

}

953

954

OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString

955

(const std::string &s,

956

bool hasOpSizePrefix) {

957

ENCODING("RST", ENCODING_I)

958

ENCODING("GR32", ENCODING_Rv)

959

ENCODING("GR64", ENCODING_RO)

960

ENCODING("GR16", ENCODING_Rv)

961

ENCODING("GR8", ENCODING_RB)

962

errs() << "Unhandled opcode modifier encoding " << s << "\n";

963

llvm_unreachable("Unhandled opcode modifier encoding");

964

}

965

#undef ENCODING

~louis/ubuntu/trusty/clamav/lp799623_fix_logrotate