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Viewing changes to libclamav/c++/llvm/lib/Target/PowerPC/PPC.td

  • Committer: Bazaar Package Importer
  • Author(s): Scott Kitterman
  • Date: 2010-03-12 11:30:04 UTC
  • mfrom: (0.41.1 upstream)
  • Revision ID: james.westby@ubuntu.com-20100312113004-b0fop4bkycszdd0z
Tags: 0.96~rc1+dfsg-0ubuntu1
https://launchpad.net/bugs/537636
* New upstream RC - FFE (LP: #537636):
  - Add OfficialDatabaseOnly option to clamav-base.postinst.in
  - Add LocalSocketGroup option to clamav-base.postinst.in
  - Add LocalSocketMode option to clamav-base.postinst.in
  - Add CrossFilesystems option to clamav-base.postinst.in
  - Add ClamukoScannerCount option to clamav-base.postinst.in
  - Add BytecodeSecurity opiton to clamav-base.postinst.in
  - Add DetectionStatsHostID option to clamav-freshclam.postinst.in
  - Add Bytecode option to clamav-freshclam.postinst.in
  - Add MilterSocketGroup option to clamav-milter.postinst.in
  - Add MilterSocketMode option to clamav-milter.postinst.in
  - Add ReportHostname option to clamav-milter.postinst.in
  - Bump libclamav SO version to 6.1.0 in libclamav6.install
  - Drop clamdmon from clamav.examples (no longer shipped by upstream)
  - Drop libclamav.a from libclamav-dev.install (not built by upstream)
  - Update SO version for lintian override for libclamav6
  - Add new Bytecode Testing Tool, usr/bin/clambc, to clamav.install
  - Add build-depends on python and python-setuptools for new test suite
  - Update debian/copyright for the embedded copy of llvm (using the system
    llvm is not currently feasible)

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libclamav/c++/llvm/lib/Target/PowerPC/PPC.td
 
1
//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
 
2
// 
 
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//                     The LLVM Compiler Infrastructure
 
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//
 
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// This file is distributed under the University of Illinois Open Source
 
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// License. See LICENSE.TXT for details.
 
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// 
 
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//===----------------------------------------------------------------------===//
 
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//
 
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// This is the top level entry point for the PowerPC target.
 
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//
 
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//===----------------------------------------------------------------------===//
 
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// Get the target-independent interfaces which we are implementing.
 
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//
 
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include "llvm/Target/Target.td"
 
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//===----------------------------------------------------------------------===//
 
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// PowerPC Subtarget features.
 
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//
 
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//===----------------------------------------------------------------------===//
 
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// CPU Directives                                                             //
 
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//===----------------------------------------------------------------------===//
 
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def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
 
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def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
 
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def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
 
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def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
 
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def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
 
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def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
 
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def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
 
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def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
 
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def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
 
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def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
 
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def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
 
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                                        "Enable 64-bit instructions">;
 
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def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
 
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                              "Enable 64-bit registers usage for ppc32 [beta]">;
 
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def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
 
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                                        "Enable Altivec instructions">;
 
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def FeatureGPUL      : SubtargetFeature<"gpul","IsGigaProcessor", "true",
 
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                                        "Enable GPUL instructions">;
 
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def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
 
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                                        "Enable the fsqrt instruction">; 
 
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def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
 
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                                        "Enable the stfiwx instruction">; 
 
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//===----------------------------------------------------------------------===//
 
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// Register File Description
 
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//===----------------------------------------------------------------------===//
 
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include "PPCRegisterInfo.td"
 
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include "PPCSchedule.td"
 
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include "PPCInstrInfo.td"
 
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//===----------------------------------------------------------------------===//
 
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// PowerPC processors supported.
 
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//
 
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def : Processor<"generic", G3Itineraries, [Directive32]>;
 
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def : Processor<"601", G3Itineraries, [Directive601]>;
 
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def : Processor<"602", G3Itineraries, [Directive602]>;
 
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def : Processor<"603", G3Itineraries, [Directive603]>;
 
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def : Processor<"603e", G3Itineraries, [Directive603]>;
 
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def : Processor<"603ev", G3Itineraries, [Directive603]>;
 
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def : Processor<"604", G3Itineraries, [Directive604]>;
 
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def : Processor<"604e", G3Itineraries, [Directive604]>;
 
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def : Processor<"620", G3Itineraries, [Directive620]>;
 
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def : Processor<"g3", G3Itineraries, [Directive7400]>;
 
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def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
 
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def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
 
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def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
 
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def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>;
 
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def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>;
 
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def : Processor<"970", G5Itineraries,
 
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                  [Directive970, FeatureAltivec,
 
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                   FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
 
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                   Feature64Bit /*, Feature64BitRegs */]>;
 
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def : Processor<"g5", G5Itineraries,
 
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                  [Directive970, FeatureAltivec,
 
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                   FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
 
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                   Feature64Bit /*, Feature64BitRegs */]>;
 
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def : Processor<"ppc", G3Itineraries, [Directive32]>;
 
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def : Processor<"ppc64", G5Itineraries,
 
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                  [Directive64, FeatureAltivec,
 
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                   FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
 
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                   Feature64Bit /*, Feature64BitRegs */]>;
 
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91
 
 
92
//===----------------------------------------------------------------------===//
 
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// Calling Conventions
 
94
//===----------------------------------------------------------------------===//
 
95
 
 
96
include "PPCCallingConv.td"
 
97
 
 
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def PPCInstrInfo : InstrInfo {
 
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  // Define how we want to layout our TargetSpecific information field... This
 
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  // should be kept up-to-date with the fields in the PPCInstrInfo.h file.
 
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  let TSFlagsFields = ["PPC970_First",
 
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                       "PPC970_Single",
 
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                       "PPC970_Cracked",
 
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                       "PPC970_Unit"];
 
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  let TSFlagsShifts = [0, 1, 2, 3];
 
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107
  let isLittleEndianEncoding = 1;
 
108
}
 
109
 
 
110
 
 
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def PPC : Target {
 
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  // Information about the instructions.
 
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  let InstructionSet = PPCInstrInfo;
 
114
}