1
//===---------------------------------------------------------------------===//
3
Common register allocation / spilling problem:
21
and then "merge" mul and mov:
29
It also increase the likelyhood the store may become dead.
31
//===---------------------------------------------------------------------===//
35
%reg1037 = ADDri %reg1039, 1
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%reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
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Successors according to CFG: 0x8b03bf0 (#5)
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bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
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Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
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%reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
43
Note ADDri is not a two-address instruction. However, its result %reg1037 is an
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operand of the PHI node in bb76 and its operand %reg1039 is the result of the
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PHI node. We should treat it as a two-address code and make sure the ADDri is
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scheduled after any node that reads %reg1039.
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//===---------------------------------------------------------------------===//
50
Use local info (i.e. register scavenger) to assign it a free register to allow
61
//===---------------------------------------------------------------------===//
63
LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
77
Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
78
to implement proper re-materialization to handle this:
85
R1 = X + 4 @ re-materialized
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R2 = X + 7 @ re-materialized
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R3 = X + 15 @ re-materialized
94
Furthermore, with re-association, we can enable sharing:
107
//===---------------------------------------------------------------------===//
109
It's not always a good idea to choose rematerialization over spilling. If all
110
the load / store instructions would be folded then spilling is cheaper because
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it won't require new live intervals / registers. See 2003-05-31-LongShifts for
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//===---------------------------------------------------------------------===//
116
With a copying garbage collector, derived pointers must not be retained across
117
collector safe points; the collector could move the objects and invalidate the
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derived pointer. This is bad enough in the first place, but safe points can
119
crop up unpredictably. Consider:
121
%array = load { i32, [0 x %obj] }** %array_addr
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%nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
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%old = load %obj** %nth_el
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store %obj* %new, %obj** %nth_el
127
If the i64 division is lowered to a libcall, then a safe point will (must)
128
appear for the call site. If a collection occurs, %array and %nth_el no longer
129
point into the correct object.
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The fix for this is to copy address calculations so that dependent pointers
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are never live across safe point boundaries. But the loads cannot be copied
133
like this if there was an intervening store, so may be hard to get right.
135
Only a concurrent mutator can trigger a collection at the libcall safe point.
136
So single-threaded programs do not have this requirement, even with a copying
137
collector. Still, LLVM optimizations would probably undo a front-end's careful
140
//===---------------------------------------------------------------------===//
142
The ocaml frametable structure supports liveness information. It would be good
145
//===---------------------------------------------------------------------===//
147
The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
148
revisited. The check is there to work around a misuse of directives in inline
151
//===---------------------------------------------------------------------===//
153
It would be good to detect collector/target compatibility instead of silently
154
doing the wrong thing.
156
//===---------------------------------------------------------------------===//
158
It would be really nice to be able to write patterns in .td files for copies,
159
which would eliminate a bunch of explicit predicates on them (e.g. no side
160
effects). Once this is in place, it would be even better to have tblgen
161
synthesize the various copy insertion/inspection methods in TargetInstrInfo.
163
//===---------------------------------------------------------------------===//
165
Stack coloring improvments:
167
1. Do proper LiveStackAnalysis on all stack objects including those which are
169
2. Reorder objects to fill in gaps between objects.
170
e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4
172
//===---------------------------------------------------------------------===//
174
The scheduler should be able to sort nearby instructions by their address. For
175
example, in an expanded memset sequence it's not uncommon to see code like this:
182
Each of the stores is independent, and the scheduler is currently making an
183
arbitrary decision about the order.
185
//===---------------------------------------------------------------------===//
187
Another opportunitiy in this code is that the $0 could be moved to a register:
194
This would save substantial code size, especially for longer sequences like
195
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
196
if the immediate has more than some fixed number of uses. It's more involved
197
to teach the register allocator how to do late folding to recover from
198
excessive register pressure.