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//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format ARM assembly language.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "ARMBuildAttrs.h"
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#include "ARMAddressingModes.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMInstPrinter.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMMCInstLower.h"
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#include "ARMTargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/Module.h"
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#include "llvm/Type.h"
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#include "llvm/Assembly/Writer.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/DwarfWriter.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/MathExtras.h"
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EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
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cl::desc("enable experimental asmprinter gunk in the arm backend"));
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class ARMAsmPrinter : public AsmPrinter {
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when printing asm code for different targets.
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const ARMSubtarget *Subtarget;
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/// AFI - Keep a pointer to ARMFunctionInfo for the current
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/// MCP - Keep a pointer to constantpool entries of the current
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const MachineConstantPool *MCP;
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explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
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MCContext &Ctx, MCStreamer &Streamer,
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: AsmPrinter(O, TM, Ctx, Streamer, T), AFI(NULL), MCP(NULL) {
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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virtual const char *getPassName() const {
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return "ARM Assembly Printer";
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void printInstructionThroughMCStreamer(const MachineInstr *MI);
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void printOperand(const MachineInstr *MI, int OpNum,
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const char *Modifier = 0);
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void printSOImmOperand(const MachineInstr *MI, int OpNum);
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void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
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void printSORegOperand(const MachineInstr *MI, int OpNum);
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void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
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void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
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void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
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void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
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void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
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const char *Modifier = 0);
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void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
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const char *Modifier = 0);
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void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
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void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
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const char *Modifier = 0);
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void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
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void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
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void printThumbITMask(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
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void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
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void printT2SOOperand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
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void printPredicateOperand(const MachineInstr *MI, int OpNum);
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void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum);
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void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
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void printPCLabel(const MachineInstr *MI, int OpNum);
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void printRegisterList(const MachineInstr *MI, int OpNum);
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void printCPInstOperand(const MachineInstr *MI, int OpNum,
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const char *Modifier);
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void printJTBlockOperand(const MachineInstr *MI, int OpNum);
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void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
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void printTBAddrMode(const MachineInstr *MI, int OpNum);
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void printNoHashImmediate(const MachineInstr *MI, int OpNum);
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void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
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void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
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void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
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O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
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void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
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O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
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void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
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O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
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void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
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O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
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virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode);
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virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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const char *ExtraCode);
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void printInstruction(const MachineInstr *MI); // autogenerated.
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static const char *getRegisterName(unsigned RegNo);
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virtual void EmitInstruction(const MachineInstr *MI);
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bool runOnMachineFunction(MachineFunction &F);
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virtual void EmitConstantPool() {} // we emit constant pools customly!
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virtual void EmitFunctionEntryLabel();
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void EmitStartOfAsmFile(Module &M);
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void EmitEndOfAsmFile(Module &M);
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MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
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const MachineBasicBlock *MBB) const;
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MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
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/// EmitMachineConstantPoolValue - Print a machine constantpool value to
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virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
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switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
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case 1: O << MAI->getData8bitsDirective(0); break;
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case 2: O << MAI->getData16bitsDirective(0); break;
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case 4: O << MAI->getData32bitsDirective(0); break;
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default: assert(0 && "Unknown CPV size");
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ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
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SmallString<128> TmpNameStr;
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if (ACPV->isLSDA()) {
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raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
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"_LSDA_" << getFunctionNumber();
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O << TmpNameStr.str();
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} else if (ACPV->isBlockAddress()) {
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O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
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} else if (ACPV->isGlobalValue()) {
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GlobalValue *GV = ACPV->getGV();
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bool isIndirect = Subtarget->isTargetDarwin() &&
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Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
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O << *GetGlobalValueSymbol(GV);
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// FIXME: Remove this when Darwin transition to @GOT like syntax.
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MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
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MachineModuleInfoMachO &MMIMachO =
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MMI->getObjFileInfo<MachineModuleInfoMachO>();
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GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
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MMIMachO.getGVStubEntry(Sym);
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StubSym = GetGlobalValueSymbol(GV);
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assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
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O << *GetExternalSymbolSymbol(ACPV->getSymbol());
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if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
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if (ACPV->getPCAdjustment() != 0) {
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O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
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<< getFunctionNumber() << "_" << ACPV->getLabelId()
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<< "+" << (unsigned)ACPV->getPCAdjustment();
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if (ACPV->mustAddCurrentAddress())
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OutStreamer.AddBlankLine();
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AsmPrinter::getAnalysisUsage(AU);
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AU.setPreservesAll();
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AU.addRequired<MachineModuleInfo>();
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AU.addRequired<DwarfWriter>();
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} // end of anonymous namespace
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#include "ARMGenAsmWriter.inc"
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void ARMAsmPrinter::EmitFunctionEntryLabel() {
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if (AFI->isThumbFunction()) {
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O << "\t.code\t16\n";
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O << "\t.thumb_func";
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if (Subtarget->isTargetDarwin())
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O << '\t' << *CurrentFnSym;
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OutStreamer.EmitLabel(CurrentFnSym);
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/// runOnMachineFunction - This uses the printInstruction()
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/// method to print assembly for each instruction.
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bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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AFI = MF.getInfo<ARMFunctionInfo>();
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MCP = MF.getConstantPool();
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return AsmPrinter::runOnMachineFunction(MF);
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void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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const char *Modifier) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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unsigned TF = MO.getTargetFlags();
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switch (MO.getType()) {
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assert(0 && "<unknown operand type>");
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case MachineOperand::MO_Register: {
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unsigned Reg = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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if (Modifier && strcmp(Modifier, "dregpair") == 0) {
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unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
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unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
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<< getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
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} else if (Modifier && strcmp(Modifier, "lane") == 0) {
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unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
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unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
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&ARM::DPR_VFP2RegClass);
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O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
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assert(!MO.getSubReg() && "Subregs should be eliminated!");
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O << getRegisterName(Reg);
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case MachineOperand::MO_Immediate: {
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int64_t Imm = MO.getImm();
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if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
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(TF & ARMII::MO_LO16))
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else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
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(TF & ARMII::MO_HI16))
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol(OutContext);
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case MachineOperand::MO_GlobalAddress: {
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bool isCallOp = Modifier && !strcmp(Modifier, "call");
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GlobalValue *GV = MO.getGlobal();
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if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
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(TF & ARMII::MO_LO16))
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else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
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(TF & ARMII::MO_HI16))
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O << *GetGlobalValueSymbol(GV);
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printOffset(MO.getOffset());
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if (isCallOp && Subtarget->isTargetELF() &&
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TM.getRelocationModel() == Reloc::PIC_)
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case MachineOperand::MO_ExternalSymbol: {
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bool isCallOp = Modifier && !strcmp(Modifier, "call");
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O << *GetExternalSymbolSymbol(MO.getSymbolName());
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if (isCallOp && Subtarget->isTargetELF() &&
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TM.getRelocationModel() == Reloc::PIC_)
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case MachineOperand::MO_ConstantPoolIndex:
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O << *GetCPISymbol(MO.getIndex());
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case MachineOperand::MO_JumpTableIndex:
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O << *GetJTISymbol(MO.getIndex());
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static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
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const MCAsmInfo *MAI) {
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// Break it up into two parts that make up a shifter immediate.
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V = ARM_AM::getSOImmVal(V);
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assert(V != -1 && "Not a valid so_imm value!");
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unsigned Imm = ARM_AM::getSOImmValImm(V);
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unsigned Rot = ARM_AM::getSOImmValRot(V);
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// Print low-level immediate formation info, per
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// A5.1.3: "Data-processing operands - Immediate".
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O << "#" << Imm << ", " << Rot;
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// Pretty printed version.
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O.PadToColumn(MAI->getCommentColumn());
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O << MAI->getCommentString() << ' ';
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O << (int)ARM_AM::rotr32(Imm, Rot);
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/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
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/// immediate in bits 0-7.
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void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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assert(MO.isImm() && "Not a valid so_imm value!");
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printSOImm(O, MO.getImm(), VerboseAsm, MAI);
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/// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
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/// followed by an 'orr' to materialize.
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void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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assert(MO.isImm() && "Not a valid so_imm value!");
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unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
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unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
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printSOImm(O, V1, VerboseAsm, MAI);
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printPredicateOperand(MI, 2);
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printSOImm(O, V2, VerboseAsm, MAI);
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// so_reg is a 4-operand unit corresponding to register forms of the A5.1
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// "Addressing Mode 1 - Data-processing operands" forms. This includes:
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// REG REG 0,SH_OPC - e.g. R5, ROR R3
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// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
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void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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const MachineOperand &MO3 = MI->getOperand(Op+2);
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O << getRegisterName(MO1.getReg());
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// Print the shift opc.
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<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
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O << getRegisterName(MO2.getReg());
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assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
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O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
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void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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const MachineOperand &MO3 = MI->getOperand(Op+2);
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if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
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printOperand(MI, Op);
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O << "[" << getRegisterName(MO1.getReg());
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if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
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<< (char)ARM_AM::getAM2Op(MO3.getImm())
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<< ARM_AM::getAM2Offset(MO3.getImm());
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<< (char)ARM_AM::getAM2Op(MO3.getImm())
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<< getRegisterName(MO2.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
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void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
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assert(ImmOffs && "Malformed indexed load / store!");
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<< (char)ARM_AM::getAM2Op(MO2.getImm())
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O << (char)ARM_AM::getAM2Op(MO2.getImm())
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<< getRegisterName(MO1.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
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void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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const MachineOperand &MO3 = MI->getOperand(Op+2);
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assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
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O << "[" << getRegisterName(MO1.getReg());
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<< (char)ARM_AM::getAM3Op(MO3.getImm())
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<< getRegisterName(MO2.getReg())
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if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
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<< (char)ARM_AM::getAM3Op(MO3.getImm())
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void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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O << (char)ARM_AM::getAM3Op(MO2.getImm())
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<< getRegisterName(MO1.getReg());
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unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
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assert(ImmOffs && "Malformed indexed load / store!");
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<< (char)ARM_AM::getAM3Op(MO2.getImm())
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void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
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const char *Modifier) {
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
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if (Modifier && strcmp(Modifier, "submode") == 0) {
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if (MO1.getReg() == ARM::SP) {
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bool isLDM = (MI->getOpcode() == ARM::LDM ||
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MI->getOpcode() == ARM::LDM_RET ||
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MI->getOpcode() == ARM::t2LDM ||
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MI->getOpcode() == ARM::t2LDM_RET);
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O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
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O << ARM_AM::getAMSubModeStr(Mode);
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} else if (Modifier && strcmp(Modifier, "wide") == 0) {
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ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
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if (Mode == ARM_AM::ia)
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printOperand(MI, Op);
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if (ARM_AM::getAM4WBFlag(MO2.getImm()))
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void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
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const char *Modifier) {
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
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printOperand(MI, Op);
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assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
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if (Modifier && strcmp(Modifier, "submode") == 0) {
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ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
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O << ARM_AM::getAMSubModeStr(Mode);
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} else if (Modifier && strcmp(Modifier, "base") == 0) {
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// Used for FSTM{D|S} and LSTM{D|S} operations.
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O << getRegisterName(MO1.getReg());
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if (ARM_AM::getAM5WBFlag(MO2.getImm()))
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O << "[" << getRegisterName(MO1.getReg());
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if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
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<< (char)ARM_AM::getAM5Op(MO2.getImm())
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void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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const MachineOperand &MO3 = MI->getOperand(Op+2);
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const MachineOperand &MO4 = MI->getOperand(Op+3);
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O << "[" << getRegisterName(MO1.getReg());
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// FIXME: Both darwin as and GNU as violate ARM docs here.
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O << ", :" << MO4.getImm();
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if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
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if (MO2.getReg() == 0)
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O << ", " << getRegisterName(MO2.getReg());
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void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
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const char *Modifier) {
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if (Modifier && strcmp(Modifier, "label") == 0) {
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printPCLabel(MI, Op+1);
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const MachineOperand &MO1 = MI->getOperand(Op);
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assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
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O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
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ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
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const MachineOperand &MO = MI->getOperand(Op);
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uint32_t v = ~MO.getImm();
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int32_t lsb = CountTrailingZeros_32(v);
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int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
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assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
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O << "#" << lsb << ", #" << width;
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//===--------------------------------------------------------------------===//
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void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
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O << "#" << MI->getOperand(Op).getImm() * 4;
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ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
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// (3 - the number of trailing zeros) is the number of then / else.
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unsigned Mask = MI->getOperand(Op).getImm();
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unsigned NumTZ = CountTrailingZeros_32(Mask);
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assert(NumTZ <= 3 && "Invalid IT mask!");
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for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
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bool T = (Mask & (1 << Pos)) == 0;
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ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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O << "[" << getRegisterName(MO1.getReg());
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O << ", " << getRegisterName(MO2.getReg()) << "]";
642
ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
644
const MachineOperand &MO1 = MI->getOperand(Op);
645
const MachineOperand &MO2 = MI->getOperand(Op+1);
646
const MachineOperand &MO3 = MI->getOperand(Op+2);
648
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
649
printOperand(MI, Op);
653
O << "[" << getRegisterName(MO1.getReg());
655
O << ", " << getRegisterName(MO3.getReg());
656
else if (unsigned ImmOffs = MO2.getImm())
657
O << ", #+" << ImmOffs * Scale;
662
ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
663
printThumbAddrModeRI5Operand(MI, Op, 1);
666
ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
667
printThumbAddrModeRI5Operand(MI, Op, 2);
670
ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
671
printThumbAddrModeRI5Operand(MI, Op, 4);
674
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
675
const MachineOperand &MO1 = MI->getOperand(Op);
676
const MachineOperand &MO2 = MI->getOperand(Op+1);
677
O << "[" << getRegisterName(MO1.getReg());
678
if (unsigned ImmOffs = MO2.getImm())
679
O << ", #+" << ImmOffs*4;
683
//===--------------------------------------------------------------------===//
685
// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
686
// register with shift forms.
688
// REG IMM, SH_OPC - e.g. R5, LSL #3
689
void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
690
const MachineOperand &MO1 = MI->getOperand(OpNum);
691
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
693
unsigned Reg = MO1.getReg();
694
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
695
O << getRegisterName(Reg);
697
// Print the shift opc.
699
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
702
assert(MO2.isImm() && "Not a valid t2_so_reg value!");
703
O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
706
void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
708
const MachineOperand &MO1 = MI->getOperand(OpNum);
709
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
711
O << "[" << getRegisterName(MO1.getReg());
713
unsigned OffImm = MO2.getImm();
714
if (OffImm) // Don't print +0.
715
O << ", #+" << OffImm;
719
void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
721
const MachineOperand &MO1 = MI->getOperand(OpNum);
722
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
724
O << "[" << getRegisterName(MO1.getReg());
726
int32_t OffImm = (int32_t)MO2.getImm();
729
O << ", #-" << -OffImm;
731
O << ", #+" << OffImm;
735
void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
737
const MachineOperand &MO1 = MI->getOperand(OpNum);
738
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
740
O << "[" << getRegisterName(MO1.getReg());
742
int32_t OffImm = (int32_t)MO2.getImm() / 4;
745
O << ", #-" << -OffImm * 4;
747
O << ", #+" << OffImm * 4;
751
void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
753
const MachineOperand &MO1 = MI->getOperand(OpNum);
754
int32_t OffImm = (int32_t)MO1.getImm();
757
O << "#-" << -OffImm;
762
void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
764
const MachineOperand &MO1 = MI->getOperand(OpNum);
765
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
766
const MachineOperand &MO3 = MI->getOperand(OpNum+2);
768
O << "[" << getRegisterName(MO1.getReg());
770
assert(MO2.getReg() && "Invalid so_reg load / store address!");
771
O << ", " << getRegisterName(MO2.getReg());
773
unsigned ShAmt = MO3.getImm();
775
assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
776
O << ", lsl #" << ShAmt;
782
//===--------------------------------------------------------------------===//
784
void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
785
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
787
O << ARMCondCodeToString(CC);
790
void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
792
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
793
O << ARMCondCodeToString(CC);
796
void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
797
unsigned Reg = MI->getOperand(OpNum).getReg();
799
assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
804
void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
805
int Id = (int)MI->getOperand(OpNum).getImm();
806
O << MAI->getPrivateGlobalPrefix()
807
<< "PC" << getFunctionNumber() << "_" << Id;
810
void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
812
// Always skip the first operand, it's the optional (and implicit writeback).
813
for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
814
if (MI->getOperand(i).isImplicit())
816
if ((int)i != OpNum+1) O << ", ";
822
void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
823
const char *Modifier) {
824
assert(Modifier && "This operand only works with a modifier!");
825
// There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
827
if (!strcmp(Modifier, "label")) {
828
unsigned ID = MI->getOperand(OpNum).getImm();
829
OutStreamer.EmitLabel(GetCPISymbol(ID));
831
assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
832
unsigned CPI = MI->getOperand(OpNum).getIndex();
834
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
836
if (MCPE.isMachineConstantPoolEntry()) {
837
EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
839
EmitGlobalConstant(MCPE.Val.ConstVal);
844
MCSymbol *ARMAsmPrinter::
845
GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
846
const MachineBasicBlock *MBB) const {
847
SmallString<60> Name;
848
raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
849
<< getFunctionNumber() << '_' << uid << '_' << uid2
850
<< "_set_" << MBB->getNumber();
851
return OutContext.GetOrCreateSymbol(Name.str());
854
MCSymbol *ARMAsmPrinter::
855
GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
856
SmallString<60> Name;
857
raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
858
<< getFunctionNumber() << '_' << uid << '_' << uid2;
859
return OutContext.GetOrCreateSymbol(Name.str());
862
void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
863
assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
865
const MachineOperand &MO1 = MI->getOperand(OpNum);
866
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
868
unsigned JTI = MO1.getIndex();
869
MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
870
OutStreamer.EmitLabel(JTISymbol);
872
const char *JTEntryDirective = MAI->getData32bitsDirective();
874
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
875
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
876
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
877
bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
878
SmallPtrSet<MachineBasicBlock*, 8> JTSets;
879
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
880
MachineBasicBlock *MBB = JTBBs[i];
881
bool isNew = JTSets.insert(MBB);
883
if (UseSet && isNew) {
885
<< *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
886
<< *MBB->getSymbol(OutContext) << '-' << *JTISymbol << '\n';
889
O << JTEntryDirective << ' ';
891
O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
892
else if (TM.getRelocationModel() == Reloc::PIC_)
893
O << *MBB->getSymbol(OutContext) << '-' << *JTISymbol;
895
O << *MBB->getSymbol(OutContext);
902
void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
903
const MachineOperand &MO1 = MI->getOperand(OpNum);
904
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
905
unsigned JTI = MO1.getIndex();
907
MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
908
OutStreamer.EmitLabel(JTISymbol);
910
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
911
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
912
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
913
bool ByteOffset = false, HalfWordOffset = false;
914
if (MI->getOpcode() == ARM::t2TBB)
916
else if (MI->getOpcode() == ARM::t2TBH)
917
HalfWordOffset = true;
919
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
920
MachineBasicBlock *MBB = JTBBs[i];
922
O << MAI->getData8bitsDirective();
923
else if (HalfWordOffset)
924
O << MAI->getData16bitsDirective();
926
if (ByteOffset || HalfWordOffset)
927
O << '(' << *MBB->getSymbol(OutContext) << "-" << *JTISymbol << ")/2";
929
O << "\tb.w " << *MBB->getSymbol(OutContext);
935
// Make sure the instruction that follows TBB is 2-byte aligned.
936
// FIXME: Constant island pass should insert an "ALIGN" instruction instead.
937
if (ByteOffset && (JTBBs.size() & 1)) {
943
void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
944
O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
945
if (MI->getOpcode() == ARM::t2TBH)
950
void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
951
O << MI->getOperand(OpNum).getImm();
954
void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
955
const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
956
O << '#' << FP->getValueAPF().convertToFloat();
958
O.PadToColumn(MAI->getCommentColumn());
959
O << MAI->getCommentString() << ' ';
960
WriteAsOperand(O, FP, /*PrintType=*/false);
964
void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
965
const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
966
O << '#' << FP->getValueAPF().convertToDouble();
968
O.PadToColumn(MAI->getCommentColumn());
969
O << MAI->getCommentString() << ' ';
970
WriteAsOperand(O, FP, /*PrintType=*/false);
974
bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
975
unsigned AsmVariant, const char *ExtraCode){
976
// Does this asm operand have a single letter operand modifier?
977
if (ExtraCode && ExtraCode[0]) {
978
if (ExtraCode[1] != 0) return true; // Unknown modifier.
980
switch (ExtraCode[0]) {
981
default: return true; // Unknown modifier.
982
case 'a': // Print as a memory address.
983
if (MI->getOperand(OpNum).isReg()) {
984
O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
988
case 'c': // Don't print "#" before an immediate operand.
989
if (!MI->getOperand(OpNum).isImm())
991
printNoHashImmediate(MI, OpNum);
993
case 'P': // Print a VFP double precision register.
994
case 'q': // Print a NEON quad precision register.
995
printOperand(MI, OpNum);
998
if (TM.getTargetData()->isLittleEndian())
1002
if (TM.getTargetData()->isBigEndian())
1005
case 'H': // Write second word of DI / DF reference.
1006
// Verify that this operand has two consecutive registers.
1007
if (!MI->getOperand(OpNum).isReg() ||
1008
OpNum+1 == MI->getNumOperands() ||
1009
!MI->getOperand(OpNum+1).isReg())
1011
++OpNum; // Return the high-part.
1015
printOperand(MI, OpNum);
1019
bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1020
unsigned OpNum, unsigned AsmVariant,
1021
const char *ExtraCode) {
1022
if (ExtraCode && ExtraCode[0])
1023
return true; // Unknown modifier.
1025
const MachineOperand &MO = MI->getOperand(OpNum);
1026
assert(MO.isReg() && "unexpected inline asm memory operand");
1027
O << "[" << getRegisterName(MO.getReg()) << "]";
1031
void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1033
printInstructionThroughMCStreamer(MI);
1035
int Opc = MI->getOpcode();
1036
if (Opc == ARM::CONSTPOOL_ENTRY)
1039
printInstruction(MI);
1040
OutStreamer.AddBlankLine();
1044
void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1045
if (Subtarget->isTargetDarwin()) {
1046
Reloc::Model RelocM = TM.getRelocationModel();
1047
if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1048
// Declare all the text sections up front (before the DWARF sections
1049
// emitted by AsmPrinter::doInitialization) so the assembler will keep
1050
// them together at the beginning of the object file. This helps
1051
// avoid out-of-range branches that are due a fundamental limitation of
1052
// the way symbol offsets are encoded with the current Darwin ARM
1054
TargetLoweringObjectFileMachO &TLOFMacho =
1055
static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1056
OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1057
OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1058
OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1059
if (RelocM == Reloc::DynamicNoPIC) {
1060
const MCSection *sect =
1061
TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1062
MCSectionMachO::S_SYMBOL_STUBS,
1063
12, SectionKind::getText());
1064
OutStreamer.SwitchSection(sect);
1066
const MCSection *sect =
1067
TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1068
MCSectionMachO::S_SYMBOL_STUBS,
1069
16, SectionKind::getText());
1070
OutStreamer.SwitchSection(sect);
1075
// Use unified assembler syntax.
1076
O << "\t.syntax unified\n";
1078
// Emit ARM Build Attributes
1079
if (Subtarget->isTargetELF()) {
1081
std::string CPUString = Subtarget->getCPUString();
1082
if (CPUString != "generic")
1083
O << "\t.cpu " << CPUString << '\n';
1085
// FIXME: Emit FPU type
1086
if (Subtarget->hasVFP2())
1087
O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1089
// Signal various FP modes.
1091
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1092
<< "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1094
if (FiniteOnlyFPMath())
1095
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1097
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1099
// 8-bytes alignment stuff.
1100
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1101
<< "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1103
// Hard float. Use both S and D registers and conform to AAPCS-VFP.
1104
if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1105
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1106
<< "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1108
// FIXME: Should we signal R9 usage?
1113
void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1114
if (Subtarget->isTargetDarwin()) {
1115
// All darwin targets use mach-o.
1116
TargetLoweringObjectFileMachO &TLOFMacho =
1117
static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1118
MachineModuleInfoMachO &MMIMacho =
1119
MMI->getObjFileInfo<MachineModuleInfoMachO>();
1123
// Output non-lazy-pointers for external and common global variables.
1124
MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1126
if (!Stubs.empty()) {
1127
// Switch with ".non_lazy_symbol_pointer" directive.
1128
OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1130
for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1131
O << *Stubs[i].first << ":\n\t.indirect_symbol ";
1132
O << *Stubs[i].second << "\n\t.long\t0\n";
1136
Stubs = MMIMacho.GetHiddenGVStubList();
1137
if (!Stubs.empty()) {
1138
OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1140
for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
1141
O << *Stubs[i].first << ":\n\t.long " << *Stubs[i].second << "\n";
1144
// Funny Darwin hack: This flag tells the linker that no global symbols
1145
// contain code that falls through to other global symbols (e.g. the obvious
1146
// implementation of multiple entry points). If this doesn't occur, the
1147
// linker can safely perform dead code stripping. Since LLVM never
1148
// generates code that does this, it is always safe to set.
1149
OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1153
//===----------------------------------------------------------------------===//
1155
void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1156
ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1157
switch (MI->getOpcode()) {
1158
case ARM::t2MOVi32imm:
1159
assert(0 && "Should be lowered by thumb2it pass");
1161
case ARM::PICADD: { // FIXME: Remove asm string from td file.
1162
// This is a pseudo op for a label + instruction sequence, which looks like:
1165
// This adds the address of LPC0 to r0.
1168
// FIXME: MOVE TO SHARED PLACE.
1169
unsigned Id = (unsigned)MI->getOperand(2).getImm();
1170
const char *Prefix = MAI->getPrivateGlobalPrefix();
1171
MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1172
+ "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1173
OutStreamer.EmitLabel(Label);
1176
// Form and emit tha dd.
1178
AddInst.setOpcode(ARM::ADDrr);
1179
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1180
AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1181
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1182
OutStreamer.EmitInstruction(AddInst);
1185
case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1186
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1187
/// in the function. The first operand is the ID# for this instruction, the
1188
/// second is the index into the MachineConstantPool that this is, the third
1189
/// is the size in bytes of this constant pool entry.
1190
unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1191
unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1194
OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1196
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1197
if (MCPE.isMachineConstantPoolEntry())
1198
EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1200
EmitGlobalConstant(MCPE.Val.ConstVal);
1204
case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1205
// This is a hack that lowers as a two instruction sequence.
1206
unsigned DstReg = MI->getOperand(0).getReg();
1207
unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1209
unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1210
unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1214
TmpInst.setOpcode(ARM::MOVi);
1215
TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1216
TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1219
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1220
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1222
TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1223
OutStreamer.EmitInstruction(TmpInst);
1228
TmpInst.setOpcode(ARM::ORRri);
1229
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1230
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1231
TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1233
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1234
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1236
TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1237
OutStreamer.EmitInstruction(TmpInst);
1241
case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1242
// This is a hack that lowers as a two instruction sequence.
1243
unsigned DstReg = MI->getOperand(0).getReg();
1244
unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1248
TmpInst.setOpcode(ARM::MOVi16);
1249
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1250
TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1253
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1254
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1256
OutStreamer.EmitInstruction(TmpInst);
1261
TmpInst.setOpcode(ARM::MOVTi16);
1262
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1263
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1264
TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1267
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1268
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1270
OutStreamer.EmitInstruction(TmpInst);
1278
MCInstLowering.Lower(MI, TmpInst);
1279
OutStreamer.EmitInstruction(TmpInst);
1282
//===----------------------------------------------------------------------===//
1283
// Target Registry Stuff
1284
//===----------------------------------------------------------------------===//
1286
static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1287
unsigned SyntaxVariant,
1288
const MCAsmInfo &MAI,
1290
if (SyntaxVariant == 0)
1291
return new ARMInstPrinter(O, MAI, false);
1295
// Force static initialization.
1296
extern "C" void LLVMInitializeARMAsmPrinter() {
1297
RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1298
RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1300
TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1301
TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);