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//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file implements the PPCISelLowering class.
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//===----------------------------------------------------------------------===//
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#include "PPCISelLowering.h"
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#include "PPCMachineFunctionInfo.h"
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#include "PPCPredicates.h"
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#include "PPCTargetMachine.h"
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#include "PPCPerfectShuffle.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/DerivedTypes.h"
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static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
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cl::desc("enable preincrement load/store generation on PPC (experimental)"),
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static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
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if (TM.getSubtargetImpl()->isDarwin())
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return new TargetLoweringObjectFileMachO();
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return new TargetLoweringObjectFileELF();
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PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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: TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
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// Use _setjmp/_longjmp instead of setjmp/longjmp.
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setUseUnderscoreSetJmp(true);
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setUseUnderscoreLongJmp(true);
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// Set up the register classes.
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addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
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addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
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addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
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// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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// PowerPC has pre-inc load and store's.
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setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
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setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
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setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
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setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
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setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
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setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
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setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
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setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
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setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
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setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
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// This is used in the ppcf128->int sequence. Note it has different semantics
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// from FP_ROUND: that rounds to nearest, this rounds to zero.
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setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
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// PowerPC has no SREM/UREM instructions
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i64, Expand);
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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// Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
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// We don't support sin/cos/sqrt/fmod/pow
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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setOperationAction(ISD::FPOW , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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setOperationAction(ISD::FPOW , MVT::f32, Expand);
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setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
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// If we're enabling GP optimizations, use hardware square root
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if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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// PowerPC does not have BSWAP, CTPOP or CTTZ
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setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
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setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
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setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
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setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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// PowerPC does not have ROTR
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setOperationAction(ISD::ROTR, MVT::i32 , Expand);
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setOperationAction(ISD::ROTR, MVT::i64 , Expand);
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// PowerPC does not have Select
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::i64, Expand);
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setOperationAction(ISD::SELECT, MVT::f32, Expand);
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setOperationAction(ISD::SELECT, MVT::f64, Expand);
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// PowerPC wants to turn select_cc of FP into fsel when possible.
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
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// PowerPC wants to optimize integer setcc a bit
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setOperationAction(ISD::SETCC, MVT::i32, Custom);
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// PowerPC does not have BRCOND which requires SetCC
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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// PowerPC does not have [U|S]INT_TO_FP
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
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// We cannot sextinreg(i1). Expand to shifts.
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
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setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
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setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
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setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
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// We want to legalize GlobalAddress and ConstantPool nodes into the
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// appropriate instructions to materialize the address.
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
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setOperationAction(ISD::JumpTable, MVT::i64, Custom);
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setOperationAction(ISD::TRAP, MVT::Other, Legal);
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// TRAMPOLINE is custom lowered.
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setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex
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setOperationAction(ISD::VASTART , MVT::Other, Custom);
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// VAARG is custom lowered with the 32-bit SVR4 ABI.
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if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
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&& !TM.getSubtarget<PPCSubtarget>().isPPC64())
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setOperationAction(ISD::VAARG, MVT::Other, Custom);
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setOperationAction(ISD::VAARG, MVT::Other, Expand);
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// Use the default implementation.
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setOperationAction(ISD::VACOPY , MVT::Other, Expand);
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setOperationAction(ISD::VAEND , MVT::Other, Expand);
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setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
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// We want to custom lower some of our intrinsics.
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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// Comparisons that require checking two conditions.
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setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
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setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
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setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
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setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
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setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
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setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
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setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
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setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
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setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
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setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
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setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
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setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
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if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
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// They also have instructions for converting between i64 and fp.
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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// This is just the low 32 bits of a (signed) fp->i64 conversion.
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// We cannot do this with Promote because i64 is not a legal type.
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
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// FIXME: disable this lowered code. This generates 64-bit register values,
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// and we don't model the fact that the top part is clobbered by calls. We
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// need to flag these together so that the value isn't live across a call.
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//setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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// PowerPC does not have FP_TO_UINT on 32-bit implementations.
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
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// 64-bit PowerPC implementations can support i64 types directly
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addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
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// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
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setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
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// 64-bit PowerPC wants to expand i128 shifts itself.
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setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
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setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
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setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
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// 32-bit PowerPC wants to expand i64 shifts itself.
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
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if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
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// First set operation action for all vector types to expand. Then we
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// will selectively turn on ones that can be effectively codegen'd.
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for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
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MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
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// add/sub are legal for all supported vector VT's.
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setOperationAction(ISD::ADD , VT, Legal);
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setOperationAction(ISD::SUB , VT, Legal);
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// We promote all shuffles to v16i8.
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
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AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
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// We promote all non-typed operations to v4i32.
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setOperationAction(ISD::AND , VT, Promote);
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AddPromotedToType (ISD::AND , VT, MVT::v4i32);
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setOperationAction(ISD::OR , VT, Promote);
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AddPromotedToType (ISD::OR , VT, MVT::v4i32);
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setOperationAction(ISD::XOR , VT, Promote);
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AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
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setOperationAction(ISD::LOAD , VT, Promote);
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AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
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setOperationAction(ISD::SELECT, VT, Promote);
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AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
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setOperationAction(ISD::STORE, VT, Promote);
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AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
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// No other operations are legal.
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setOperationAction(ISD::MUL , VT, Expand);
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setOperationAction(ISD::SDIV, VT, Expand);
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::UDIV, VT, Expand);
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setOperationAction(ISD::UREM, VT, Expand);
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setOperationAction(ISD::FDIV, VT, Expand);
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setOperationAction(ISD::FNEG, VT, Expand);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
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setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
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setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
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setOperationAction(ISD::UMUL_LOHI, VT, Expand);
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setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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setOperationAction(ISD::UDIVREM, VT, Expand);
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setOperationAction(ISD::SDIVREM, VT, Expand);
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setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
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setOperationAction(ISD::FPOW, VT, Expand);
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setOperationAction(ISD::CTPOP, VT, Expand);
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setOperationAction(ISD::CTLZ, VT, Expand);
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setOperationAction(ISD::CTTZ, VT, Expand);
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// We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
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// with merges, splats, etc.
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
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setOperationAction(ISD::AND , MVT::v4i32, Legal);
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setOperationAction(ISD::OR , MVT::v4i32, Legal);
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setOperationAction(ISD::XOR , MVT::v4i32, Legal);
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setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
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setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
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setOperationAction(ISD::STORE , MVT::v4i32, Legal);
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addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
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addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
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addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
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addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
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setOperationAction(ISD::MUL, MVT::v4f32, Legal);
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setOperationAction(ISD::MUL, MVT::v4i32, Custom);
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setOperationAction(ISD::MUL, MVT::v8i16, Custom);
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setOperationAction(ISD::MUL, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
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setShiftAmountType(MVT::i32);
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setBooleanContents(ZeroOrOneBooleanContent);
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if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
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setStackPointerRegisterToSaveRestore(PPC::X1);
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setExceptionPointerRegister(PPC::X3);
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setExceptionSelectorRegister(PPC::X4);
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setStackPointerRegisterToSaveRestore(PPC::R1);
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setExceptionPointerRegister(PPC::R3);
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setExceptionSelectorRegister(PPC::R4);
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// We have target-specific dag combine patterns for the following nodes:
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setTargetDAGCombine(ISD::SINT_TO_FP);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::BR_CC);
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setTargetDAGCombine(ISD::BSWAP);
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// Darwin long double math library functions have $LDBL128 appended.
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if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
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setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
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setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
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setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
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setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
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setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
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setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
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setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
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setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
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setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
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setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
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computeRegisterProperties();
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/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
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/// function arguments in the caller parameter area.
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unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
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TargetMachine &TM = getTargetMachine();
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// Darwin passes everything on 4 byte boundary.
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if (TM.getSubtarget<PPCSubtarget>().isDarwin())
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const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case PPCISD::FSEL: return "PPCISD::FSEL";
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case PPCISD::FCFID: return "PPCISD::FCFID";
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case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
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case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
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case PPCISD::STFIWX: return "PPCISD::STFIWX";
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case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
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case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
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case PPCISD::VPERM: return "PPCISD::VPERM";
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case PPCISD::Hi: return "PPCISD::Hi";
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case PPCISD::Lo: return "PPCISD::Lo";
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case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
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case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
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case PPCISD::LOAD: return "PPCISD::LOAD";
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case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
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case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
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case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
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case PPCISD::SRL: return "PPCISD::SRL";
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case PPCISD::SRA: return "PPCISD::SRA";
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case PPCISD::SHL: return "PPCISD::SHL";
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case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
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case PPCISD::STD_32: return "PPCISD::STD_32";
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case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
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case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
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case PPCISD::NOP: return "PPCISD::NOP";
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case PPCISD::MTCTR: return "PPCISD::MTCTR";
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case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
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case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
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case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
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case PPCISD::MFCR: return "PPCISD::MFCR";
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case PPCISD::VCMP: return "PPCISD::VCMP";
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case PPCISD::VCMPo: return "PPCISD::VCMPo";
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case PPCISD::LBRX: return "PPCISD::LBRX";
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case PPCISD::STBRX: return "PPCISD::STBRX";
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case PPCISD::LARX: return "PPCISD::LARX";
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case PPCISD::STCX: return "PPCISD::STCX";
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case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
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case PPCISD::MFFS: return "PPCISD::MFFS";
448
case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
449
case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
450
case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
451
case PPCISD::MTFSF: return "PPCISD::MTFSF";
452
case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
456
MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
460
/// getFunctionAlignment - Return the Log2 alignment of this function.
461
unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
462
if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
463
return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
468
//===----------------------------------------------------------------------===//
469
// Node matching predicates, for use by the tblgen matching code.
470
//===----------------------------------------------------------------------===//
472
/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
473
static bool isFloatingPointZero(SDValue Op) {
474
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
475
return CFP->getValueAPF().isZero();
476
else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
477
// Maybe this has already been legalized into the constant pool?
478
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
479
if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
480
return CFP->getValueAPF().isZero();
485
/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
486
/// true if Op is undef or if it matches the specified value.
487
static bool isConstantOrUndef(int Op, int Val) {
488
return Op < 0 || Op == Val;
491
/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
492
/// VPKUHUM instruction.
493
bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
495
for (unsigned i = 0; i != 16; ++i)
496
if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
499
for (unsigned i = 0; i != 8; ++i)
500
if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
501
!isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
507
/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
508
/// VPKUWUM instruction.
509
bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
511
for (unsigned i = 0; i != 16; i += 2)
512
if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
513
!isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
516
for (unsigned i = 0; i != 8; i += 2)
517
if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
518
!isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
519
!isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
520
!isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
526
/// isVMerge - Common function, used to match vmrg* shuffles.
528
static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
529
unsigned LHSStart, unsigned RHSStart) {
530
assert(N->getValueType(0) == MVT::v16i8 &&
531
"PPC only supports shuffles by bytes!");
532
assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
533
"Unsupported merge size!");
535
for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
536
for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
537
if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
538
LHSStart+j+i*UnitSize) ||
539
!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
540
RHSStart+j+i*UnitSize))
546
/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
547
/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
548
bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
551
return isVMerge(N, UnitSize, 8, 24);
552
return isVMerge(N, UnitSize, 8, 8);
555
/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
556
/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
557
bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
560
return isVMerge(N, UnitSize, 0, 16);
561
return isVMerge(N, UnitSize, 0, 0);
565
/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
566
/// amount, otherwise return -1.
567
int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
568
assert(N->getValueType(0) == MVT::v16i8 &&
569
"PPC only supports shuffles by bytes!");
571
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
573
// Find the first non-undef value in the shuffle mask.
575
for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
578
if (i == 16) return -1; // all undef.
580
// Otherwise, check to see if the rest of the elements are consecutively
581
// numbered from this value.
582
unsigned ShiftAmt = SVOp->getMaskElt(i);
583
if (ShiftAmt < i) return -1;
587
// Check the rest of the elements to see if they are consecutive.
588
for (++i; i != 16; ++i)
589
if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
592
// Check the rest of the elements to see if they are consecutive.
593
for (++i; i != 16; ++i)
594
if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
600
/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
601
/// specifies a splat of a single element that is suitable for input to
602
/// VSPLTB/VSPLTH/VSPLTW.
603
bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
604
assert(N->getValueType(0) == MVT::v16i8 &&
605
(EltSize == 1 || EltSize == 2 || EltSize == 4));
607
// This is a splat operation if each element of the permute is the same, and
608
// if the value doesn't reference the second vector.
609
unsigned ElementBase = N->getMaskElt(0);
611
// FIXME: Handle UNDEF elements too!
612
if (ElementBase >= 16)
615
// Check that the indices are consecutive, in the case of a multi-byte element
616
// splatted with a v16i8 mask.
617
for (unsigned i = 1; i != EltSize; ++i)
618
if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
621
for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
622
if (N->getMaskElt(i) < 0) continue;
623
for (unsigned j = 0; j != EltSize; ++j)
624
if (N->getMaskElt(i+j) != N->getMaskElt(j))
630
/// isAllNegativeZeroVector - Returns true if all elements of build_vector
632
bool PPC::isAllNegativeZeroVector(SDNode *N) {
633
BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
635
APInt APVal, APUndef;
639
if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
640
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
641
return CFP->getValueAPF().isNegZero();
646
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
647
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
648
unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
649
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
650
assert(isSplatShuffleMask(SVOp, EltSize));
651
return SVOp->getMaskElt(0) / EltSize;
654
/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
655
/// by using a vspltis[bhw] instruction of the specified element size, return
656
/// the constant being splatted. The ByteSize field indicates the number of
657
/// bytes of each element [124] -> [bhw].
658
SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
661
// If ByteSize of the splat is bigger than the element size of the
662
// build_vector, then we have a case where we are checking for a splat where
663
// multiple elements of the buildvector are folded together into a single
664
// logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
665
unsigned EltSize = 16/N->getNumOperands();
666
if (EltSize < ByteSize) {
667
unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
668
SDValue UniquedVals[4];
669
assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
671
// See if all of the elements in the buildvector agree across.
672
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
673
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
674
// If the element isn't a constant, bail fully out.
675
if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
678
if (UniquedVals[i&(Multiple-1)].getNode() == 0)
679
UniquedVals[i&(Multiple-1)] = N->getOperand(i);
680
else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
681
return SDValue(); // no match.
684
// Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
685
// either constant or undef values that are identical for each chunk. See
686
// if these chunks can form into a larger vspltis*.
688
// Check to see if all of the leading entries are either 0 or -1. If
689
// neither, then this won't fit into the immediate field.
690
bool LeadingZero = true;
691
bool LeadingOnes = true;
692
for (unsigned i = 0; i != Multiple-1; ++i) {
693
if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
695
LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
696
LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
698
// Finally, check the least significant entry.
700
if (UniquedVals[Multiple-1].getNode() == 0)
701
return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
702
int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
704
return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
707
if (UniquedVals[Multiple-1].getNode() == 0)
708
return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
709
int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
710
if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
711
return DAG.getTargetConstant(Val, MVT::i32);
717
// Check to see if this buildvec has a single non-undef value in its elements.
718
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
719
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
720
if (OpVal.getNode() == 0)
721
OpVal = N->getOperand(i);
722
else if (OpVal != N->getOperand(i))
726
if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
728
unsigned ValSizeInBytes = EltSize;
730
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
731
Value = CN->getZExtValue();
732
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
733
assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
734
Value = FloatToBits(CN->getValueAPF().convertToFloat());
737
// If the splat value is larger than the element value, then we can never do
738
// this splat. The only case that we could fit the replicated bits into our
739
// immediate field for would be zero, and we prefer to use vxor for it.
740
if (ValSizeInBytes < ByteSize) return SDValue();
742
// If the element value is larger than the splat value, cut it in half and
743
// check to see if the two halves are equal. Continue doing this until we
744
// get to ByteSize. This allows us to handle 0x01010101 as 0x01.
745
while (ValSizeInBytes > ByteSize) {
746
ValSizeInBytes >>= 1;
748
// If the top half equals the bottom half, we're still ok.
749
if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
750
(Value & ((1 << (8*ValSizeInBytes))-1)))
754
// Properly sign extend the value.
755
int ShAmt = (4-ByteSize)*8;
756
int MaskVal = ((int)Value << ShAmt) >> ShAmt;
758
// If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
759
if (MaskVal == 0) return SDValue();
761
// Finally, if this value fits in a 5 bit sext field, return it
762
if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
763
return DAG.getTargetConstant(MaskVal, MVT::i32);
767
//===----------------------------------------------------------------------===//
768
// Addressing Mode Selection
769
//===----------------------------------------------------------------------===//
771
/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
772
/// or 64-bit immediate, and if the value can be accurately represented as a
773
/// sign extension from a 16-bit value. If so, this returns true and the
775
static bool isIntS16Immediate(SDNode *N, short &Imm) {
776
if (N->getOpcode() != ISD::Constant)
779
Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
780
if (N->getValueType(0) == MVT::i32)
781
return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
783
return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
785
static bool isIntS16Immediate(SDValue Op, short &Imm) {
786
return isIntS16Immediate(Op.getNode(), Imm);
790
/// SelectAddressRegReg - Given the specified addressed, check to see if it
791
/// can be represented as an indexed [r+r] operation. Returns false if it
792
/// can be more efficiently represented with [r+imm].
793
bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
795
SelectionDAG &DAG) const {
797
if (N.getOpcode() == ISD::ADD) {
798
if (isIntS16Immediate(N.getOperand(1), imm))
800
if (N.getOperand(1).getOpcode() == PPCISD::Lo)
803
Base = N.getOperand(0);
804
Index = N.getOperand(1);
806
} else if (N.getOpcode() == ISD::OR) {
807
if (isIntS16Immediate(N.getOperand(1), imm))
808
return false; // r+i can fold it if we can.
810
// If this is an or of disjoint bitfields, we can codegen this as an add
811
// (for better address arithmetic) if the LHS and RHS of the OR are provably
813
APInt LHSKnownZero, LHSKnownOne;
814
APInt RHSKnownZero, RHSKnownOne;
815
DAG.ComputeMaskedBits(N.getOperand(0),
816
APInt::getAllOnesValue(N.getOperand(0)
817
.getValueSizeInBits()),
818
LHSKnownZero, LHSKnownOne);
820
if (LHSKnownZero.getBoolValue()) {
821
DAG.ComputeMaskedBits(N.getOperand(1),
822
APInt::getAllOnesValue(N.getOperand(1)
823
.getValueSizeInBits()),
824
RHSKnownZero, RHSKnownOne);
825
// If all of the bits are known zero on the LHS or RHS, the add won't
827
if (~(LHSKnownZero | RHSKnownZero) == 0) {
828
Base = N.getOperand(0);
829
Index = N.getOperand(1);
838
/// Returns true if the address N can be represented by a base register plus
839
/// a signed 16-bit displacement [r+imm], and if it is not better
840
/// represented as reg+reg.
841
bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
843
SelectionDAG &DAG) const {
844
// FIXME dl should come from parent load or store, not from address
845
DebugLoc dl = N.getDebugLoc();
846
// If this can be more profitably realized as r+r, fail.
847
if (SelectAddressRegReg(N, Disp, Base, DAG))
850
if (N.getOpcode() == ISD::ADD) {
852
if (isIntS16Immediate(N.getOperand(1), imm)) {
853
Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
854
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
855
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
857
Base = N.getOperand(0);
859
return true; // [r+i]
860
} else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
861
// Match LOAD (ADD (X, Lo(G))).
862
assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
863
&& "Cannot handle constant offsets yet!");
864
Disp = N.getOperand(1).getOperand(0); // The global address.
865
assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
866
Disp.getOpcode() == ISD::TargetConstantPool ||
867
Disp.getOpcode() == ISD::TargetJumpTable);
868
Base = N.getOperand(0);
869
return true; // [&g+r]
871
} else if (N.getOpcode() == ISD::OR) {
873
if (isIntS16Immediate(N.getOperand(1), imm)) {
874
// If this is an or of disjoint bitfields, we can codegen this as an add
875
// (for better address arithmetic) if the LHS and RHS of the OR are
876
// provably disjoint.
877
APInt LHSKnownZero, LHSKnownOne;
878
DAG.ComputeMaskedBits(N.getOperand(0),
879
APInt::getAllOnesValue(N.getOperand(0)
880
.getValueSizeInBits()),
881
LHSKnownZero, LHSKnownOne);
883
if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
884
// If all of the bits are known zero on the LHS or RHS, the add won't
886
Base = N.getOperand(0);
887
Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
891
} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
892
// Loading from a constant address.
894
// If this address fits entirely in a 16-bit sext immediate field, codegen
897
if (isIntS16Immediate(CN, Imm)) {
898
Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
899
Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
903
// Handle 32-bit sext immediates with LIS + addr mode.
904
if (CN->getValueType(0) == MVT::i32 ||
905
(int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
906
int Addr = (int)CN->getZExtValue();
908
// Otherwise, break this down into an LIS + disp.
909
Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
911
Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
912
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
913
Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
918
Disp = DAG.getTargetConstant(0, getPointerTy());
919
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
920
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
923
return true; // [r+0]
926
/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
927
/// represented as an indexed [r+r] operation.
928
bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
930
SelectionDAG &DAG) const {
931
// Check to see if we can easily represent this as an [r+r] address. This
932
// will fail if it thinks that the address is more profitably represented as
933
// reg+imm, e.g. where imm = 0.
934
if (SelectAddressRegReg(N, Base, Index, DAG))
937
// If the operand is an addition, always emit this as [r+r], since this is
938
// better (for code size, and execution, as the memop does the add for free)
939
// than emitting an explicit add.
940
if (N.getOpcode() == ISD::ADD) {
941
Base = N.getOperand(0);
942
Index = N.getOperand(1);
946
// Otherwise, do it the hard way, using R0 as the base register.
947
Base = DAG.getRegister(PPC::R0, N.getValueType());
952
/// SelectAddressRegImmShift - Returns true if the address N can be
953
/// represented by a base register plus a signed 14-bit displacement
954
/// [r+imm*4]. Suitable for use by STD and friends.
955
bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
957
SelectionDAG &DAG) const {
958
// FIXME dl should come from the parent load or store, not the address
959
DebugLoc dl = N.getDebugLoc();
960
// If this can be more profitably realized as r+r, fail.
961
if (SelectAddressRegReg(N, Disp, Base, DAG))
964
if (N.getOpcode() == ISD::ADD) {
966
if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
967
Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
968
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
969
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
971
Base = N.getOperand(0);
973
return true; // [r+i]
974
} else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
975
// Match LOAD (ADD (X, Lo(G))).
976
assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
977
&& "Cannot handle constant offsets yet!");
978
Disp = N.getOperand(1).getOperand(0); // The global address.
979
assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
980
Disp.getOpcode() == ISD::TargetConstantPool ||
981
Disp.getOpcode() == ISD::TargetJumpTable);
982
Base = N.getOperand(0);
983
return true; // [&g+r]
985
} else if (N.getOpcode() == ISD::OR) {
987
if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
988
// If this is an or of disjoint bitfields, we can codegen this as an add
989
// (for better address arithmetic) if the LHS and RHS of the OR are
990
// provably disjoint.
991
APInt LHSKnownZero, LHSKnownOne;
992
DAG.ComputeMaskedBits(N.getOperand(0),
993
APInt::getAllOnesValue(N.getOperand(0)
994
.getValueSizeInBits()),
995
LHSKnownZero, LHSKnownOne);
996
if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
997
// If all of the bits are known zero on the LHS or RHS, the add won't
999
Base = N.getOperand(0);
1000
Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1004
} else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1005
// Loading from a constant address. Verify low two bits are clear.
1006
if ((CN->getZExtValue() & 3) == 0) {
1007
// If this address fits entirely in a 14-bit sext immediate field, codegen
1010
if (isIntS16Immediate(CN, Imm)) {
1011
Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1012
Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1016
// Fold the low-part of 32-bit absolute addresses into addr mode.
1017
if (CN->getValueType(0) == MVT::i32 ||
1018
(int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1019
int Addr = (int)CN->getZExtValue();
1021
// Otherwise, break this down into an LIS + disp.
1022
Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1023
Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1024
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1025
Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1031
Disp = DAG.getTargetConstant(0, getPointerTy());
1032
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1033
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1036
return true; // [r+0]
1040
/// getPreIndexedAddressParts - returns true by value, base pointer and
1041
/// offset pointer and addressing mode by reference if the node's address
1042
/// can be legally represented as pre-indexed load / store address.
1043
bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1045
ISD::MemIndexedMode &AM,
1046
SelectionDAG &DAG) const {
1047
// Disabled by default for now.
1048
if (!EnablePPCPreinc) return false;
1052
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1053
Ptr = LD->getBasePtr();
1054
VT = LD->getMemoryVT();
1056
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1058
Ptr = ST->getBasePtr();
1059
VT = ST->getMemoryVT();
1063
// PowerPC doesn't have preinc load/store instructions for vectors.
1067
// TODO: Check reg+reg first.
1069
// LDU/STU use reg+imm*4, others use reg+imm.
1070
if (VT != MVT::i64) {
1072
if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1076
if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1080
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1081
// PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1082
// sext i32 to i64 when addr mode is r+i.
1083
if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1084
LD->getExtensionType() == ISD::SEXTLOAD &&
1085
isa<ConstantSDNode>(Offset))
1093
//===----------------------------------------------------------------------===//
1094
// LowerOperation implementation
1095
//===----------------------------------------------------------------------===//
1097
SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1098
SelectionDAG &DAG) {
1099
EVT PtrVT = Op.getValueType();
1100
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1101
Constant *C = CP->getConstVal();
1102
SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1103
SDValue Zero = DAG.getConstant(0, PtrVT);
1104
// FIXME there isn't really any debug info here
1105
DebugLoc dl = Op.getDebugLoc();
1107
const TargetMachine &TM = DAG.getTarget();
1109
SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
1110
SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
1112
// If this is a non-darwin platform, we don't support non-static relo models
1114
if (TM.getRelocationModel() == Reloc::Static ||
1115
!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1116
// Generate non-pic code that has direct accesses to the constant pool.
1117
// The address of the global is just (hi(&g)+lo(&g)).
1118
return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1121
if (TM.getRelocationModel() == Reloc::PIC_) {
1122
// With PIC, the first instruction is actually "GR+hi(&G)".
1123
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1124
DAG.getNode(PPCISD::GlobalBaseReg,
1125
DebugLoc::getUnknownLoc(), PtrVT), Hi);
1128
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1132
SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1133
EVT PtrVT = Op.getValueType();
1134
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1135
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1136
SDValue Zero = DAG.getConstant(0, PtrVT);
1137
// FIXME there isn't really any debug loc here
1138
DebugLoc dl = Op.getDebugLoc();
1140
const TargetMachine &TM = DAG.getTarget();
1142
SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
1143
SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
1145
// If this is a non-darwin platform, we don't support non-static relo models
1147
if (TM.getRelocationModel() == Reloc::Static ||
1148
!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1149
// Generate non-pic code that has direct accesses to the constant pool.
1150
// The address of the global is just (hi(&g)+lo(&g)).
1151
return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1154
if (TM.getRelocationModel() == Reloc::PIC_) {
1155
// With PIC, the first instruction is actually "GR+hi(&G)".
1156
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1157
DAG.getNode(PPCISD::GlobalBaseReg,
1158
DebugLoc::getUnknownLoc(), PtrVT), Hi);
1161
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1165
SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1166
SelectionDAG &DAG) {
1167
llvm_unreachable("TLS not implemented for PPC.");
1168
return SDValue(); // Not reached
1171
SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
1172
EVT PtrVT = Op.getValueType();
1173
DebugLoc DL = Op.getDebugLoc();
1175
BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1176
SDValue TgtBA = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true);
1177
SDValue Zero = DAG.getConstant(0, PtrVT);
1178
SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero);
1179
SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero);
1181
// If this is a non-darwin platform, we don't support non-static relo models
1183
const TargetMachine &TM = DAG.getTarget();
1184
if (TM.getRelocationModel() == Reloc::Static ||
1185
!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1186
// Generate non-pic code that has direct accesses to globals.
1187
// The address of the global is just (hi(&g)+lo(&g)).
1188
return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1191
if (TM.getRelocationModel() == Reloc::PIC_) {
1192
// With PIC, the first instruction is actually "GR+hi(&G)".
1193
Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1194
DAG.getNode(PPCISD::GlobalBaseReg,
1195
DebugLoc::getUnknownLoc(), PtrVT), Hi);
1198
return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1201
SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1202
SelectionDAG &DAG) {
1203
EVT PtrVT = Op.getValueType();
1204
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1205
GlobalValue *GV = GSDN->getGlobal();
1206
SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1207
SDValue Zero = DAG.getConstant(0, PtrVT);
1208
// FIXME there isn't really any debug info here
1209
DebugLoc dl = GSDN->getDebugLoc();
1211
const TargetMachine &TM = DAG.getTarget();
1213
// 64-bit SVR4 ABI code is always position-independent.
1214
// The actual address of the GlobalValue is stored in the TOC.
1215
if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1216
return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA,
1217
DAG.getRegister(PPC::X2, MVT::i64));
1220
SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1221
SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1223
// If this is a non-darwin platform, we don't support non-static relo models
1225
if (TM.getRelocationModel() == Reloc::Static ||
1226
!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1227
// Generate non-pic code that has direct accesses to globals.
1228
// The address of the global is just (hi(&g)+lo(&g)).
1229
return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1232
if (TM.getRelocationModel() == Reloc::PIC_) {
1233
// With PIC, the first instruction is actually "GR+hi(&G)".
1234
Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1235
DAG.getNode(PPCISD::GlobalBaseReg,
1236
DebugLoc::getUnknownLoc(), PtrVT), Hi);
1239
Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1241
if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM))
1244
// If the global is weak or external, we have to go through the lazy
1246
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0,
1250
SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1251
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1252
DebugLoc dl = Op.getDebugLoc();
1254
// If we're comparing for equality to zero, expose the fact that this is
1255
// implented as a ctlz/srl pair on ppc, so that the dag combiner can
1256
// fold the new nodes.
1257
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1258
if (C->isNullValue() && CC == ISD::SETEQ) {
1259
EVT VT = Op.getOperand(0).getValueType();
1260
SDValue Zext = Op.getOperand(0);
1261
if (VT.bitsLT(MVT::i32)) {
1263
Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1265
unsigned Log2b = Log2_32(VT.getSizeInBits());
1266
SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1267
SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1268
DAG.getConstant(Log2b, MVT::i32));
1269
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1271
// Leave comparisons against 0 and -1 alone for now, since they're usually
1272
// optimized. FIXME: revisit this when we can custom lower all setcc
1274
if (C->isAllOnesValue() || C->isNullValue())
1278
// If we have an integer seteq/setne, turn it into a compare against zero
1279
// by xor'ing the rhs with the lhs, which is faster than setting a
1280
// condition register, reading it back out, and masking the correct bit. The
1281
// normal approach here uses sub to do this instead of xor. Using xor exposes
1282
// the result to other bit-twiddling opportunities.
1283
EVT LHSVT = Op.getOperand(0).getValueType();
1284
if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1285
EVT VT = Op.getValueType();
1286
SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1288
return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1293
SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1294
int VarArgsFrameIndex,
1295
int VarArgsStackOffset,
1296
unsigned VarArgsNumGPR,
1297
unsigned VarArgsNumFPR,
1298
const PPCSubtarget &Subtarget) {
1300
llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1301
return SDValue(); // Not reached
1304
SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1305
SDValue Chain = Op.getOperand(0);
1306
SDValue Trmp = Op.getOperand(1); // trampoline
1307
SDValue FPtr = Op.getOperand(2); // nested function
1308
SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1309
DebugLoc dl = Op.getDebugLoc();
1311
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1312
bool isPPC64 = (PtrVT == MVT::i64);
1313
const Type *IntPtrTy =
1314
DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1317
TargetLowering::ArgListTy Args;
1318
TargetLowering::ArgListEntry Entry;
1320
Entry.Ty = IntPtrTy;
1321
Entry.Node = Trmp; Args.push_back(Entry);
1323
// TrampSize == (isPPC64 ? 48 : 40);
1324
Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1325
isPPC64 ? MVT::i64 : MVT::i32);
1326
Args.push_back(Entry);
1328
Entry.Node = FPtr; Args.push_back(Entry);
1329
Entry.Node = Nest; Args.push_back(Entry);
1331
// Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1332
std::pair<SDValue, SDValue> CallResult =
1333
LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
1334
false, false, false, false, 0, CallingConv::C, false,
1335
/*isReturnValueUsed=*/true,
1336
DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1340
{ CallResult.first, CallResult.second };
1342
return DAG.getMergeValues(Ops, 2, dl);
1345
SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1346
int VarArgsFrameIndex,
1347
int VarArgsStackOffset,
1348
unsigned VarArgsNumGPR,
1349
unsigned VarArgsNumFPR,
1350
const PPCSubtarget &Subtarget) {
1351
DebugLoc dl = Op.getDebugLoc();
1353
if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1354
// vastart just stores the address of the VarArgsFrameIndex slot into the
1355
// memory location argument.
1356
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1357
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1358
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1359
return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1363
// For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1364
// We suppose the given va_list is already allocated.
1367
// char gpr; /* index into the array of 8 GPRs
1368
// * stored in the register save area
1369
// * gpr=0 corresponds to r3,
1370
// * gpr=1 to r4, etc.
1372
// char fpr; /* index into the array of 8 FPRs
1373
// * stored in the register save area
1374
// * fpr=0 corresponds to f1,
1375
// * fpr=1 to f2, etc.
1377
// char *overflow_arg_area;
1378
// /* location on stack that holds
1379
// * the next overflow argument
1381
// char *reg_save_area;
1382
// /* where r3:r10 and f1:f8 (if saved)
1388
SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32);
1389
SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32);
1392
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1394
SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1395
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1397
uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1398
SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1400
uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1401
SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1403
uint64_t FPROffset = 1;
1404
SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1406
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1408
// Store first byte : number of int regs
1409
SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1410
Op.getOperand(1), SV, 0, MVT::i8,
1412
uint64_t nextOffset = FPROffset;
1413
SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1416
// Store second byte : number of float regs
1417
SDValue secondStore =
1418
DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8,
1420
nextOffset += StackOffset;
1421
nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1423
// Store second word : arguments given on stack
1424
SDValue thirdStore =
1425
DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset,
1427
nextOffset += FrameOffset;
1428
nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1430
// Store third word : arguments given in registers
1431
return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset,
1436
#include "PPCGenCallingConv.inc"
1438
static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
1439
CCValAssign::LocInfo &LocInfo,
1440
ISD::ArgFlagsTy &ArgFlags,
1445
static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
1447
CCValAssign::LocInfo &LocInfo,
1448
ISD::ArgFlagsTy &ArgFlags,
1450
static const unsigned ArgRegs[] = {
1451
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1452
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1454
const unsigned NumArgRegs = array_lengthof(ArgRegs);
1456
unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1458
// Skip one register if the first unallocated register has an even register
1459
// number and there are still argument registers available which have not been
1460
// allocated yet. RegNum is actually an index into ArgRegs, which means we
1461
// need to skip a register if RegNum is odd.
1462
if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1463
State.AllocateReg(ArgRegs[RegNum]);
1466
// Always return false here, as this function only makes sure that the first
1467
// unallocated register has an odd register number and does not actually
1468
// allocate a register for the current argument.
1472
static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
1474
CCValAssign::LocInfo &LocInfo,
1475
ISD::ArgFlagsTy &ArgFlags,
1477
static const unsigned ArgRegs[] = {
1478
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1482
const unsigned NumArgRegs = array_lengthof(ArgRegs);
1484
unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1486
// If there is only one Floating-point register left we need to put both f64
1487
// values of a split ppc_fp128 value on the stack.
1488
if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1489
State.AllocateReg(ArgRegs[RegNum]);
1492
// Always return false here, as this function only makes sure that the two f64
1493
// values a ppc_fp128 value is split into are both passed in registers or both
1494
// passed on the stack and does not actually allocate a register for the
1495
// current argument.
1499
/// GetFPR - Get the set of FP registers that should be allocated for arguments,
1501
static const unsigned *GetFPR() {
1502
static const unsigned FPR[] = {
1503
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1504
PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1510
/// CalculateStackSlotSize - Calculates the size reserved for this argument on
1512
static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1513
unsigned PtrByteSize) {
1514
unsigned ArgSize = ArgVT.getSizeInBits()/8;
1515
if (Flags.isByVal())
1516
ArgSize = Flags.getByValSize();
1517
ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1523
PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1524
CallingConv::ID CallConv, bool isVarArg,
1525
const SmallVectorImpl<ISD::InputArg>
1527
DebugLoc dl, SelectionDAG &DAG,
1528
SmallVectorImpl<SDValue> &InVals) {
1529
if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1530
return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1533
return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1539
PPCTargetLowering::LowerFormalArguments_SVR4(
1541
CallingConv::ID CallConv, bool isVarArg,
1542
const SmallVectorImpl<ISD::InputArg>
1544
DebugLoc dl, SelectionDAG &DAG,
1545
SmallVectorImpl<SDValue> &InVals) {
1547
// 32-bit SVR4 ABI Stack Frame Layout:
1548
// +-----------------------------------+
1549
// +--> | Back chain |
1550
// | +-----------------------------------+
1551
// | | Floating-point register save area |
1552
// | +-----------------------------------+
1553
// | | General register save area |
1554
// | +-----------------------------------+
1555
// | | CR save word |
1556
// | +-----------------------------------+
1557
// | | VRSAVE save word |
1558
// | +-----------------------------------+
1559
// | | Alignment padding |
1560
// | +-----------------------------------+
1561
// | | Vector register save area |
1562
// | +-----------------------------------+
1563
// | | Local variable space |
1564
// | +-----------------------------------+
1565
// | | Parameter list area |
1566
// | +-----------------------------------+
1567
// | | LR save word |
1568
// | +-----------------------------------+
1569
// SP--> +--- | Back chain |
1570
// +-----------------------------------+
1573
// System V Application Binary Interface PowerPC Processor Supplement
1574
// AltiVec Technology Programming Interface Manual
1576
MachineFunction &MF = DAG.getMachineFunction();
1577
MachineFrameInfo *MFI = MF.getFrameInfo();
1579
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1580
// Potential tail calls could cause overwriting of argument stack slots.
1581
bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1582
unsigned PtrByteSize = 4;
1584
// Assign locations to all of the incoming arguments.
1585
SmallVector<CCValAssign, 16> ArgLocs;
1586
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1589
// Reserve space for the linkage area on the stack.
1590
CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
1592
CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1594
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1595
CCValAssign &VA = ArgLocs[i];
1597
// Arguments stored in registers.
1598
if (VA.isRegLoc()) {
1599
TargetRegisterClass *RC;
1600
EVT ValVT = VA.getValVT();
1602
switch (ValVT.getSimpleVT().SimpleTy) {
1604
llvm_unreachable("ValVT not supported by formal arguments Lowering");
1606
RC = PPC::GPRCRegisterClass;
1609
RC = PPC::F4RCRegisterClass;
1612
RC = PPC::F8RCRegisterClass;
1618
RC = PPC::VRRCRegisterClass;
1622
// Transform the arguments stored in physical registers into virtual ones.
1623
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1624
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1626
InVals.push_back(ArgValue);
1628
// Argument stored in memory.
1629
assert(VA.isMemLoc());
1631
unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1632
int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1633
isImmutable, false);
1635
// Create load nodes to retrieve arguments from the stack.
1636
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1637
InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
1642
// Assign locations to all of the incoming aggregate by value arguments.
1643
// Aggregates passed by value are stored in the local variable space of the
1644
// caller's stack frame, right above the parameter list area.
1645
SmallVector<CCValAssign, 16> ByValArgLocs;
1646
CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1647
ByValArgLocs, *DAG.getContext());
1649
// Reserve stack space for the allocations in CCInfo.
1650
CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1652
CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1654
// Area that is at least reserved in the caller of this function.
1655
unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1657
// Set the size that is at least reserved in caller of this function. Tail
1658
// call optimized function's reserved stack space needs to be aligned so that
1659
// taking the difference between two stack areas will result in an aligned
1661
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1664
std::max(MinReservedArea,
1665
PPCFrameInfo::getMinCallFrameSize(false, false));
1667
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1668
getStackAlignment();
1669
unsigned AlignMask = TargetAlign-1;
1670
MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1672
FI->setMinReservedArea(MinReservedArea);
1674
SmallVector<SDValue, 8> MemOps;
1676
// If the function takes variable number of arguments, make a frame index for
1677
// the start of the first vararg value... for expansion of llvm.va_start.
1679
static const unsigned GPArgRegs[] = {
1680
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1681
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1683
const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1685
static const unsigned FPArgRegs[] = {
1686
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1689
const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1691
VarArgsNumGPR = CCInfo.getFirstUnallocated(GPArgRegs, NumGPArgRegs);
1692
VarArgsNumFPR = CCInfo.getFirstUnallocated(FPArgRegs, NumFPArgRegs);
1694
// Make room for NumGPArgRegs and NumFPArgRegs.
1695
int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1696
NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1698
VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1699
CCInfo.getNextStackOffset(),
1702
VarArgsFrameIndex = MFI->CreateStackObject(Depth, 8, false);
1703
SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1705
// The fixed integer arguments of a variadic function are
1706
// stored to the VarArgsFrameIndex on the stack.
1707
unsigned GPRIndex = 0;
1708
for (; GPRIndex != VarArgsNumGPR; ++GPRIndex) {
1709
SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT);
1710
SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0,
1712
MemOps.push_back(Store);
1713
// Increment the address by four for the next argument to store
1714
SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1715
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1718
// If this function is vararg, store any remaining integer argument regs
1719
// to their spots on the stack so that they may be loaded by deferencing the
1720
// result of va_next.
1721
for (; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1722
unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1724
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1725
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
1727
MemOps.push_back(Store);
1728
// Increment the address by four for the next argument to store
1729
SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1730
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1733
// FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1736
// The double arguments are stored to the VarArgsFrameIndex
1738
unsigned FPRIndex = 0;
1739
for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) {
1740
SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
1741
SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0,
1743
MemOps.push_back(Store);
1744
// Increment the address by eight for the next argument to store
1745
SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1747
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1750
for (; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1751
unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1753
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1754
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
1756
MemOps.push_back(Store);
1757
// Increment the address by eight for the next argument to store
1758
SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1760
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1764
if (!MemOps.empty())
1765
Chain = DAG.getNode(ISD::TokenFactor, dl,
1766
MVT::Other, &MemOps[0], MemOps.size());
1772
PPCTargetLowering::LowerFormalArguments_Darwin(
1774
CallingConv::ID CallConv, bool isVarArg,
1775
const SmallVectorImpl<ISD::InputArg>
1777
DebugLoc dl, SelectionDAG &DAG,
1778
SmallVectorImpl<SDValue> &InVals) {
1779
// TODO: add description of PPC stack frame format, or at least some docs.
1781
MachineFunction &MF = DAG.getMachineFunction();
1782
MachineFrameInfo *MFI = MF.getFrameInfo();
1784
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1785
bool isPPC64 = PtrVT == MVT::i64;
1786
// Potential tail calls could cause overwriting of argument stack slots.
1787
bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1788
unsigned PtrByteSize = isPPC64 ? 8 : 4;
1790
unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
1791
// Area that is at least reserved in caller of this function.
1792
unsigned MinReservedArea = ArgOffset;
1794
static const unsigned GPR_32[] = { // 32-bit registers.
1795
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1796
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1798
static const unsigned GPR_64[] = { // 64-bit registers.
1799
PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1800
PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1803
static const unsigned *FPR = GetFPR();
1805
static const unsigned VR[] = {
1806
PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1807
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1810
const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1811
const unsigned Num_FPR_Regs = 13;
1812
const unsigned Num_VR_Regs = array_lengthof( VR);
1814
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1816
const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1818
// In 32-bit non-varargs functions, the stack space for vectors is after the
1819
// stack space for non-vectors. We do not use this space unless we have
1820
// too many vectors to fit in registers, something that only occurs in
1821
// constructed examples:), but we have to walk the arglist to figure
1822
// that out...for the pathological case, compute VecArgOffset as the
1823
// start of the vector parameter area. Computing VecArgOffset is the
1824
// entire point of the following loop.
1825
unsigned VecArgOffset = ArgOffset;
1826
if (!isVarArg && !isPPC64) {
1827
for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1829
EVT ObjectVT = Ins[ArgNo].VT;
1830
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1831
ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1833
if (Flags.isByVal()) {
1834
// ObjSize is the true size, ArgSize rounded up to multiple of regs.
1835
ObjSize = Flags.getByValSize();
1837
((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1838
VecArgOffset += ArgSize;
1842
switch(ObjectVT.getSimpleVT().SimpleTy) {
1843
default: llvm_unreachable("Unhandled argument type!");
1846
VecArgOffset += isPPC64 ? 8 : 4;
1848
case MVT::i64: // PPC64
1856
// Nothing to do, we're only looking at Nonvector args here.
1861
// We've found where the vector parameter area in memory is. Skip the
1862
// first 12 parameters; these don't use that memory.
1863
VecArgOffset = ((VecArgOffset+15)/16)*16;
1864
VecArgOffset += 12*16;
1866
// Add DAG nodes to load the arguments or copy them out of registers. On
1867
// entry to a function on PPC, the arguments start after the linkage area,
1868
// although the first ones are often in registers.
1870
SmallVector<SDValue, 8> MemOps;
1871
unsigned nAltivecParamsAtEnd = 0;
1872
for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1874
bool needsLoad = false;
1875
EVT ObjectVT = Ins[ArgNo].VT;
1876
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1877
unsigned ArgSize = ObjSize;
1878
ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1880
unsigned CurArgOffset = ArgOffset;
1882
// Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1883
if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1884
ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1885
if (isVarArg || isPPC64) {
1886
MinReservedArea = ((MinReservedArea+15)/16)*16;
1887
MinReservedArea += CalculateStackSlotSize(ObjectVT,
1890
} else nAltivecParamsAtEnd++;
1892
// Calculate min reserved area.
1893
MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1897
// FIXME the codegen can be much improved in some cases.
1898
// We do not have to keep everything in memory.
1899
if (Flags.isByVal()) {
1900
// ObjSize is the true size, ArgSize rounded up to multiple of registers.
1901
ObjSize = Flags.getByValSize();
1902
ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1903
// Objects of size 1 and 2 are right justified, everything else is
1904
// left justified. This means the memory address is adjusted forwards.
1905
if (ObjSize==1 || ObjSize==2) {
1906
CurArgOffset = CurArgOffset + (4 - ObjSize);
1908
// The value of the object is its address.
1909
int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true, false);
1910
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1911
InVals.push_back(FIN);
1912
if (ObjSize==1 || ObjSize==2) {
1913
if (GPR_idx != Num_GPR_Regs) {
1914
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1915
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1916
SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1918
ObjSize==1 ? MVT::i8 : MVT::i16,
1920
MemOps.push_back(Store);
1924
ArgOffset += PtrByteSize;
1928
for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1929
// Store whatever pieces of the object are in registers
1930
// to memory. ArgVal will be address of the beginning of
1932
if (GPR_idx != Num_GPR_Regs) {
1933
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1934
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true, false);
1935
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1936
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1937
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
1939
MemOps.push_back(Store);
1941
ArgOffset += PtrByteSize;
1943
ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1950
switch (ObjectVT.getSimpleVT().SimpleTy) {
1951
default: llvm_unreachable("Unhandled argument type!");
1954
if (GPR_idx != Num_GPR_Regs) {
1955
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1956
ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1960
ArgSize = PtrByteSize;
1962
// All int arguments reserve stack space in the Darwin ABI.
1963
ArgOffset += PtrByteSize;
1967
case MVT::i64: // PPC64
1968
if (GPR_idx != Num_GPR_Regs) {
1969
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1970
ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1972
if (ObjectVT == MVT::i32) {
1973
// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1974
// value to MVT::i64 and then truncate to the correct register size.
1976
ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1977
DAG.getValueType(ObjectVT));
1978
else if (Flags.isZExt())
1979
ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1980
DAG.getValueType(ObjectVT));
1982
ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1988
ArgSize = PtrByteSize;
1990
// All int arguments reserve stack space in the Darwin ABI.
1996
// Every 4 bytes of argument space consumes one of the GPRs available for
1997
// argument passing.
1998
if (GPR_idx != Num_GPR_Regs) {
2000
if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2003
if (FPR_idx != Num_FPR_Regs) {
2006
if (ObjectVT == MVT::f32)
2007
VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2009
VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2011
ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2017
// All FP arguments reserve stack space in the Darwin ABI.
2018
ArgOffset += isPPC64 ? 8 : ObjSize;
2024
// Note that vector arguments in registers don't reserve stack space,
2025
// except in varargs functions.
2026
if (VR_idx != Num_VR_Regs) {
2027
unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2028
ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2030
while ((ArgOffset % 16) != 0) {
2031
ArgOffset += PtrByteSize;
2032
if (GPR_idx != Num_GPR_Regs)
2036
GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2040
if (!isVarArg && !isPPC64) {
2041
// Vectors go after all the nonvectors.
2042
CurArgOffset = VecArgOffset;
2045
// Vectors are aligned.
2046
ArgOffset = ((ArgOffset+15)/16)*16;
2047
CurArgOffset = ArgOffset;
2055
// We need to load the argument to a virtual register if we determined above
2056
// that we ran out of physical registers of the appropriate type.
2058
int FI = MFI->CreateFixedObject(ObjSize,
2059
CurArgOffset + (ArgSize - ObjSize),
2060
isImmutable, false);
2061
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2062
ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0,
2066
InVals.push_back(ArgVal);
2069
// Set the size that is at least reserved in caller of this function. Tail
2070
// call optimized function's reserved stack space needs to be aligned so that
2071
// taking the difference between two stack areas will result in an aligned
2073
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2074
// Add the Altivec parameters at the end, if needed.
2075
if (nAltivecParamsAtEnd) {
2076
MinReservedArea = ((MinReservedArea+15)/16)*16;
2077
MinReservedArea += 16*nAltivecParamsAtEnd;
2080
std::max(MinReservedArea,
2081
PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2082
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2083
getStackAlignment();
2084
unsigned AlignMask = TargetAlign-1;
2085
MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2086
FI->setMinReservedArea(MinReservedArea);
2088
// If the function takes variable number of arguments, make a frame index for
2089
// the start of the first vararg value... for expansion of llvm.va_start.
2091
int Depth = ArgOffset;
2093
VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2094
Depth, true, false);
2095
SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
2097
// If this function is vararg, store any remaining integer argument regs
2098
// to their spots on the stack so that they may be loaded by deferencing the
2099
// result of va_next.
2100
for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2104
VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2106
VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2108
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2109
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
2111
MemOps.push_back(Store);
2112
// Increment the address by four for the next argument to store
2113
SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2114
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2118
if (!MemOps.empty())
2119
Chain = DAG.getNode(ISD::TokenFactor, dl,
2120
MVT::Other, &MemOps[0], MemOps.size());
2125
/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2126
/// linkage area for the Darwin ABI.
2128
CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2132
const SmallVectorImpl<ISD::OutputArg>
2134
unsigned &nAltivecParamsAtEnd) {
2135
// Count how many bytes are to be pushed on the stack, including the linkage
2136
// area, and parameter passing area. We start with 24/48 bytes, which is
2137
// prereserved space for [SP][CR][LR][3 x unused].
2138
unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true);
2139
unsigned NumOps = Outs.size();
2140
unsigned PtrByteSize = isPPC64 ? 8 : 4;
2142
// Add up all the space actually used.
2143
// In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2144
// they all go in registers, but we must reserve stack space for them for
2145
// possible use by the caller. In varargs or 64-bit calls, parameters are
2146
// assigned stack space in order, with padding so Altivec parameters are
2148
nAltivecParamsAtEnd = 0;
2149
for (unsigned i = 0; i != NumOps; ++i) {
2150
SDValue Arg = Outs[i].Val;
2151
ISD::ArgFlagsTy Flags = Outs[i].Flags;
2152
EVT ArgVT = Arg.getValueType();
2153
// Varargs Altivec parameters are padded to a 16 byte boundary.
2154
if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2155
ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2156
if (!isVarArg && !isPPC64) {
2157
// Non-varargs Altivec parameters go after all the non-Altivec
2158
// parameters; handle those later so we know how much padding we need.
2159
nAltivecParamsAtEnd++;
2162
// Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2163
NumBytes = ((NumBytes+15)/16)*16;
2165
NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2168
// Allow for Altivec parameters at the end, if needed.
2169
if (nAltivecParamsAtEnd) {
2170
NumBytes = ((NumBytes+15)/16)*16;
2171
NumBytes += 16*nAltivecParamsAtEnd;
2174
// The prolog code of the callee may store up to 8 GPR argument registers to
2175
// the stack, allowing va_start to index over them in memory if its varargs.
2176
// Because we cannot tell if this is needed on the caller side, we have to
2177
// conservatively assume that it is needed. As such, make sure we have at
2178
// least enough stack space for the caller to store the 8 GPRs.
2179
NumBytes = std::max(NumBytes,
2180
PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2182
// Tail call needs the stack to be aligned.
2183
if (CC==CallingConv::Fast && GuaranteedTailCallOpt) {
2184
unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2185
getStackAlignment();
2186
unsigned AlignMask = TargetAlign-1;
2187
NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2193
/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2194
/// adjusted to accomodate the arguments for the tailcall.
2195
static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2196
unsigned ParamSize) {
2198
if (!isTailCall) return 0;
2200
PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2201
unsigned CallerMinReservedArea = FI->getMinReservedArea();
2202
int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2203
// Remember only if the new adjustement is bigger.
2204
if (SPDiff < FI->getTailCallSPDelta())
2205
FI->setTailCallSPDelta(SPDiff);
2210
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2211
/// for tail call optimization. Targets which want to do tail call
2212
/// optimization should implement this function.
2214
PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2215
CallingConv::ID CalleeCC,
2217
const SmallVectorImpl<ISD::InputArg> &Ins,
2218
SelectionDAG& DAG) const {
2219
if (!GuaranteedTailCallOpt)
2222
// Variable argument functions are not supported.
2226
MachineFunction &MF = DAG.getMachineFunction();
2227
CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2228
if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2229
// Functions containing by val parameters are not supported.
2230
for (unsigned i = 0; i != Ins.size(); i++) {
2231
ISD::ArgFlagsTy Flags = Ins[i].Flags;
2232
if (Flags.isByVal()) return false;
2235
// Non PIC/GOT tail calls are supported.
2236
if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2239
// At the moment we can only do local tail calls (in same module, hidden
2240
// or protected) if we are generating PIC.
2241
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2242
return G->getGlobal()->hasHiddenVisibility()
2243
|| G->getGlobal()->hasProtectedVisibility();
2249
/// isCallCompatibleAddress - Return the immediate to use if the specified
2250
/// 32-bit value is representable in the immediate field of a BxA instruction.
2251
static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2252
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2255
int Addr = C->getZExtValue();
2256
if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2257
(Addr << 6 >> 6) != Addr)
2258
return 0; // Top 6 bits have to be sext of immediate.
2260
return DAG.getConstant((int)C->getZExtValue() >> 2,
2261
DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2266
struct TailCallArgumentInfo {
2271
TailCallArgumentInfo() : FrameIdx(0) {}
2276
/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2278
StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2280
const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2281
SmallVector<SDValue, 8> &MemOpChains,
2283
for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2284
SDValue Arg = TailCallArgs[i].Arg;
2285
SDValue FIN = TailCallArgs[i].FrameIdxOp;
2286
int FI = TailCallArgs[i].FrameIdx;
2287
// Store relative to framepointer.
2288
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2289
PseudoSourceValue::getFixedStack(FI),
2290
0, false, false, 0));
2294
/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2295
/// the appropriate stack slot for the tail call optimized function call.
2296
static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2297
MachineFunction &MF,
2306
// Calculate the new stack slot for the return address.
2307
int SlotSize = isPPC64 ? 8 : 4;
2308
int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2310
int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2313
EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2314
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2315
Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2316
PseudoSourceValue::getFixedStack(NewRetAddr), 0,
2319
// When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2320
// slot as the FP is never overwritten.
2323
SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2324
int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2326
SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2327
Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2328
PseudoSourceValue::getFixedStack(NewFPIdx), 0,
2335
/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2336
/// the position of the argument.
2338
CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2339
SDValue Arg, int SPDiff, unsigned ArgOffset,
2340
SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2341
int Offset = ArgOffset + SPDiff;
2342
uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2343
int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true,false);
2344
EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2345
SDValue FIN = DAG.getFrameIndex(FI, VT);
2346
TailCallArgumentInfo Info;
2348
Info.FrameIdxOp = FIN;
2350
TailCallArguments.push_back(Info);
2353
/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2354
/// stack slot. Returns the chain as result and the loaded frame pointers in
2355
/// LROpOut/FPOpout. Used when tail calling.
2356
SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2364
// Load the LR and FP stack slot for later adjusting.
2365
EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2366
LROpOut = getReturnAddrFrameIndex(DAG);
2367
LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0,
2369
Chain = SDValue(LROpOut.getNode(), 1);
2371
// When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2372
// slot as the FP is never overwritten.
2374
FPOpOut = getFramePointerFrameIndex(DAG);
2375
FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0,
2377
Chain = SDValue(FPOpOut.getNode(), 1);
2383
/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2384
/// by "Src" to address "Dst" of size "Size". Alignment information is
2385
/// specified by the specific parameter attribute. The copy will be passed as
2386
/// a byval function parameter.
2387
/// Sometimes what we are copying is the end of a larger object, the part that
2388
/// does not fit in registers.
2390
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2391
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2393
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2394
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2395
false, NULL, 0, NULL, 0);
2398
/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2401
LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2402
SDValue Arg, SDValue PtrOff, int SPDiff,
2403
unsigned ArgOffset, bool isPPC64, bool isTailCall,
2404
bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2405
SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2407
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2412
StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2414
StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2415
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2416
DAG.getConstant(ArgOffset, PtrVT));
2418
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
2420
// Calculate and remember argument location.
2421
} else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2426
void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2427
DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2428
SDValue LROp, SDValue FPOp, bool isDarwinABI,
2429
SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2430
MachineFunction &MF = DAG.getMachineFunction();
2432
// Emit a sequence of copyto/copyfrom virtual registers for arguments that
2433
// might overwrite each other in case of tail call optimization.
2434
SmallVector<SDValue, 8> MemOpChains2;
2435
// Do not flag preceeding copytoreg stuff together with the following stuff.
2437
StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2439
if (!MemOpChains2.empty())
2440
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2441
&MemOpChains2[0], MemOpChains2.size());
2443
// Store the return address to the appropriate stack slot.
2444
Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2445
isPPC64, isDarwinABI, dl);
2447
// Emit callseq_end just before tailcall node.
2448
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2449
DAG.getIntPtrConstant(0, true), InFlag);
2450
InFlag = Chain.getValue(1);
2454
unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2455
SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2456
SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2457
SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2458
bool isPPC64, bool isSVR4ABI) {
2459
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2460
NodeTys.push_back(MVT::Other); // Returns a chain
2461
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2463
unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2465
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2466
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2467
// node so that legalize doesn't hack it.
2468
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2469
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2470
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2471
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2472
else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2473
// If this is an absolute destination address, use the munged value.
2474
Callee = SDValue(Dest, 0);
2476
// Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2477
// to do the call, we can't use PPCISD::CALL.
2478
SDValue MTCTROps[] = {Chain, Callee, InFlag};
2480
if (isSVR4ABI && isPPC64) {
2481
// Function pointers in the 64-bit SVR4 ABI do not point to the function
2482
// entry point, but to the function descriptor (the function entry point
2483
// address is part of the function descriptor though).
2484
// The function descriptor is a three doubleword structure with the
2485
// following fields: function entry point, TOC base address and
2486
// environment pointer.
2487
// Thus for a call through a function pointer, the following actions need
2489
// 1. Save the TOC of the caller in the TOC save area of its stack
2490
// frame (this is done in LowerCall_Darwin()).
2491
// 2. Load the address of the function entry point from the function
2493
// 3. Load the TOC of the callee from the function descriptor into r2.
2494
// 4. Load the environment pointer from the function descriptor into
2496
// 5. Branch to the function entry point address.
2497
// 6. On return of the callee, the TOC of the caller needs to be
2498
// restored (this is done in FinishCall()).
2500
// All those operations are flagged together to ensure that no other
2501
// operations can be scheduled in between. E.g. without flagging the
2502
// operations together, a TOC access in the caller could be scheduled
2503
// between the load of the callee TOC and the branch to the callee, which
2504
// results in the TOC access going through the TOC of the callee instead
2505
// of going through the TOC of the caller, which leads to incorrect code.
2507
// Load the address of the function entry point from the function
2509
SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Flag);
2510
SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2511
InFlag.getNode() ? 3 : 2);
2512
Chain = LoadFuncPtr.getValue(1);
2513
InFlag = LoadFuncPtr.getValue(2);
2515
// Load environment pointer into r11.
2516
// Offset of the environment pointer within the function descriptor.
2517
SDValue PtrOff = DAG.getIntPtrConstant(16);
2519
SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2520
SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2522
Chain = LoadEnvPtr.getValue(1);
2523
InFlag = LoadEnvPtr.getValue(2);
2525
SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2527
Chain = EnvVal.getValue(0);
2528
InFlag = EnvVal.getValue(1);
2530
// Load TOC of the callee into r2. We are using a target-specific load
2531
// with r2 hard coded, because the result of a target-independent load
2532
// would never go directly into r2, since r2 is a reserved register (which
2533
// prevents the register allocator from allocating it), resulting in an
2534
// additional register being allocated and an unnecessary move instruction
2536
VTs = DAG.getVTList(MVT::Other, MVT::Flag);
2537
SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2539
Chain = LoadTOCPtr.getValue(0);
2540
InFlag = LoadTOCPtr.getValue(1);
2542
MTCTROps[0] = Chain;
2543
MTCTROps[1] = LoadFuncPtr;
2544
MTCTROps[2] = InFlag;
2547
Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2548
2 + (InFlag.getNode() != 0));
2549
InFlag = Chain.getValue(1);
2552
NodeTys.push_back(MVT::Other);
2553
NodeTys.push_back(MVT::Flag);
2554
Ops.push_back(Chain);
2555
CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2557
// Add CTR register as callee so a bctr can be emitted later.
2559
Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2562
// If this is a direct call, pass the chain and the callee.
2563
if (Callee.getNode()) {
2564
Ops.push_back(Chain);
2565
Ops.push_back(Callee);
2567
// If this is a tail call add stack pointer delta.
2569
Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2571
// Add argument registers to the end of the list so that they are known live
2573
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2574
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2575
RegsToPass[i].second.getValueType()));
2581
PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2582
CallingConv::ID CallConv, bool isVarArg,
2583
const SmallVectorImpl<ISD::InputArg> &Ins,
2584
DebugLoc dl, SelectionDAG &DAG,
2585
SmallVectorImpl<SDValue> &InVals) {
2587
SmallVector<CCValAssign, 16> RVLocs;
2588
CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2589
RVLocs, *DAG.getContext());
2590
CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2592
// Copy all of the result registers out of their specified physreg.
2593
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2594
CCValAssign &VA = RVLocs[i];
2595
EVT VT = VA.getValVT();
2596
assert(VA.isRegLoc() && "Can only return in registers!");
2597
Chain = DAG.getCopyFromReg(Chain, dl,
2598
VA.getLocReg(), VT, InFlag).getValue(1);
2599
InVals.push_back(Chain.getValue(0));
2600
InFlag = Chain.getValue(2);
2607
PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2608
bool isTailCall, bool isVarArg,
2610
SmallVector<std::pair<unsigned, SDValue>, 8>
2612
SDValue InFlag, SDValue Chain,
2614
int SPDiff, unsigned NumBytes,
2615
const SmallVectorImpl<ISD::InputArg> &Ins,
2616
SmallVectorImpl<SDValue> &InVals) {
2617
std::vector<EVT> NodeTys;
2618
SmallVector<SDValue, 8> Ops;
2619
unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2620
isTailCall, RegsToPass, Ops, NodeTys,
2621
PPCSubTarget.isPPC64(),
2622
PPCSubTarget.isSVR4ABI());
2624
// When performing tail call optimization the callee pops its arguments off
2625
// the stack. Account for this here so these bytes can be pushed back on in
2626
// PPCRegisterInfo::eliminateCallFramePseudoInstr.
2627
int BytesCalleePops =
2628
(CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0;
2630
if (InFlag.getNode())
2631
Ops.push_back(InFlag);
2635
// If this is the first return lowered for this function, add the regs
2636
// to the liveout set for the function.
2637
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2638
SmallVector<CCValAssign, 16> RVLocs;
2639
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2641
CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2642
for (unsigned i = 0; i != RVLocs.size(); ++i)
2643
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2646
assert(((Callee.getOpcode() == ISD::Register &&
2647
cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2648
Callee.getOpcode() == ISD::TargetExternalSymbol ||
2649
Callee.getOpcode() == ISD::TargetGlobalAddress ||
2650
isa<ConstantSDNode>(Callee)) &&
2651
"Expecting an global address, external symbol, absolute value or register");
2653
return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2656
Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2657
InFlag = Chain.getValue(1);
2659
// Add a NOP immediately after the branch instruction when using the 64-bit
2660
// SVR4 ABI. At link time, if caller and callee are in a different module and
2661
// thus have a different TOC, the call will be replaced with a call to a stub
2662
// function which saves the current TOC, loads the TOC of the callee and
2663
// branches to the callee. The NOP will be replaced with a load instruction
2664
// which restores the TOC of the caller from the TOC save slot of the current
2665
// stack frame. If caller and callee belong to the same module (and have the
2666
// same TOC), the NOP will remain unchanged.
2667
if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2668
SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
2669
if (CallOpc == PPCISD::BCTRL_SVR4) {
2670
// This is a call through a function pointer.
2671
// Restore the caller TOC from the save area into R2.
2672
// See PrepareCall() for more information about calls through function
2673
// pointers in the 64-bit SVR4 ABI.
2674
// We are using a target-specific load with r2 hard coded, because the
2675
// result of a target-independent load would never go directly into r2,
2676
// since r2 is a reserved register (which prevents the register allocator
2677
// from allocating it), resulting in an additional register being
2678
// allocated and an unnecessary move instruction being generated.
2679
Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2680
InFlag = Chain.getValue(1);
2682
// Otherwise insert NOP.
2683
InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag);
2687
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2688
DAG.getIntPtrConstant(BytesCalleePops, true),
2691
InFlag = Chain.getValue(1);
2693
return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2694
Ins, dl, DAG, InVals);
2698
PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2699
CallingConv::ID CallConv, bool isVarArg,
2701
const SmallVectorImpl<ISD::OutputArg> &Outs,
2702
const SmallVectorImpl<ISD::InputArg> &Ins,
2703
DebugLoc dl, SelectionDAG &DAG,
2704
SmallVectorImpl<SDValue> &InVals) {
2706
isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2709
if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
2710
return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2711
isTailCall, Outs, Ins,
2714
return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2715
isTailCall, Outs, Ins,
2721
PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2722
CallingConv::ID CallConv, bool isVarArg,
2724
const SmallVectorImpl<ISD::OutputArg> &Outs,
2725
const SmallVectorImpl<ISD::InputArg> &Ins,
2726
DebugLoc dl, SelectionDAG &DAG,
2727
SmallVectorImpl<SDValue> &InVals) {
2728
// See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2729
// of the 32-bit SVR4 ABI stack frame layout.
2731
assert((CallConv == CallingConv::C ||
2732
CallConv == CallingConv::Fast) && "Unknown calling convention!");
2734
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2735
unsigned PtrByteSize = 4;
2737
MachineFunction &MF = DAG.getMachineFunction();
2739
// Mark this function as potentially containing a function that contains a
2740
// tail call. As a consequence the frame pointer will be used for dynamicalloc
2741
// and restoring the callers stack pointer in this functions epilog. This is
2742
// done because by tail calling the called function might overwrite the value
2743
// in this function's (MF) stack pointer stack slot 0(SP).
2744
if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2745
MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2747
// Count how many bytes are to be pushed on the stack, including the linkage
2748
// area, parameter list area and the part of the local variable space which
2749
// contains copies of aggregates which are passed by value.
2751
// Assign locations to all of the outgoing arguments.
2752
SmallVector<CCValAssign, 16> ArgLocs;
2753
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2754
ArgLocs, *DAG.getContext());
2756
// Reserve space for the linkage area on the stack.
2757
CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
2760
// Handle fixed and variable vector arguments differently.
2761
// Fixed vector arguments go into registers as long as registers are
2762
// available. Variable vector arguments always go into memory.
2763
unsigned NumArgs = Outs.size();
2765
for (unsigned i = 0; i != NumArgs; ++i) {
2766
EVT ArgVT = Outs[i].Val.getValueType();
2767
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2770
if (Outs[i].IsFixed) {
2771
Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2774
Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2780
errs() << "Call operand #" << i << " has unhandled type "
2781
<< ArgVT.getEVTString() << "\n";
2783
llvm_unreachable(0);
2787
// All arguments are treated the same.
2788
CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2791
// Assign locations to all of the outgoing aggregate by value arguments.
2792
SmallVector<CCValAssign, 16> ByValArgLocs;
2793
CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2796
// Reserve stack space for the allocations in CCInfo.
2797
CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2799
CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2801
// Size of the linkage area, parameter list area and the part of the local
2802
// space variable where copies of aggregates which are passed by value are
2804
unsigned NumBytes = CCByValInfo.getNextStackOffset();
2806
// Calculate by how many bytes the stack has to be adjusted in case of tail
2807
// call optimization.
2808
int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2810
// Adjust the stack pointer for the new arguments...
2811
// These operations are automatically eliminated by the prolog/epilog pass
2812
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2813
SDValue CallSeqStart = Chain;
2815
// Load the return address and frame pointer so it can be moved somewhere else
2818
Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2821
// Set up a copy of the stack pointer for use loading and storing any
2822
// arguments that may not fit in the registers available for argument
2824
SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2826
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2827
SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2828
SmallVector<SDValue, 8> MemOpChains;
2830
// Walk the register/memloc assignments, inserting copies/loads.
2831
for (unsigned i = 0, j = 0, e = ArgLocs.size();
2834
CCValAssign &VA = ArgLocs[i];
2835
SDValue Arg = Outs[i].Val;
2836
ISD::ArgFlagsTy Flags = Outs[i].Flags;
2838
if (Flags.isByVal()) {
2839
// Argument is an aggregate which is passed by value, thus we need to
2840
// create a copy of it in the local variable space of the current stack
2841
// frame (which is the stack frame of the caller) and pass the address of
2842
// this copy to the callee.
2843
assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2844
CCValAssign &ByValVA = ByValArgLocs[j++];
2845
assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2847
// Memory reserved in the local variable space of the callers stack frame.
2848
unsigned LocMemOffset = ByValVA.getLocMemOffset();
2850
SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2851
PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2853
// Create a copy of the argument in the local area of the current
2855
SDValue MemcpyCall =
2856
CreateCopyOfByValArgument(Arg, PtrOff,
2857
CallSeqStart.getNode()->getOperand(0),
2860
// This must go outside the CALLSEQ_START..END.
2861
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2862
CallSeqStart.getNode()->getOperand(1));
2863
DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2864
NewCallSeqStart.getNode());
2865
Chain = CallSeqStart = NewCallSeqStart;
2867
// Pass the address of the aggregate copy on the stack either in a
2868
// physical register or in the parameter list area of the current stack
2869
// frame to the callee.
2873
if (VA.isRegLoc()) {
2874
// Put argument in a physical register.
2875
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2877
// Put argument in the parameter list area of the current stack frame.
2878
assert(VA.isMemLoc());
2879
unsigned LocMemOffset = VA.getLocMemOffset();
2882
SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2883
PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2885
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2886
PseudoSourceValue::getStack(), LocMemOffset,
2889
// Calculate and remember argument location.
2890
CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2896
if (!MemOpChains.empty())
2897
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2898
&MemOpChains[0], MemOpChains.size());
2900
// Build a sequence of copy-to-reg nodes chained together with token chain
2901
// and flag operands which copy the outgoing args into the appropriate regs.
2903
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2904
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2905
RegsToPass[i].second, InFlag);
2906
InFlag = Chain.getValue(1);
2909
// Set CR6 to true if this is a vararg call.
2911
SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0);
2912
Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2913
InFlag = Chain.getValue(1);
2917
PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2918
false, TailCallArguments);
2921
return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
2922
RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
2927
PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
2928
CallingConv::ID CallConv, bool isVarArg,
2930
const SmallVectorImpl<ISD::OutputArg> &Outs,
2931
const SmallVectorImpl<ISD::InputArg> &Ins,
2932
DebugLoc dl, SelectionDAG &DAG,
2933
SmallVectorImpl<SDValue> &InVals) {
2935
unsigned NumOps = Outs.size();
2937
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2938
bool isPPC64 = PtrVT == MVT::i64;
2939
unsigned PtrByteSize = isPPC64 ? 8 : 4;
2941
MachineFunction &MF = DAG.getMachineFunction();
2943
// Mark this function as potentially containing a function that contains a
2944
// tail call. As a consequence the frame pointer will be used for dynamicalloc
2945
// and restoring the callers stack pointer in this functions epilog. This is
2946
// done because by tail calling the called function might overwrite the value
2947
// in this function's (MF) stack pointer stack slot 0(SP).
2948
if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2949
MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2951
unsigned nAltivecParamsAtEnd = 0;
2953
// Count how many bytes are to be pushed on the stack, including the linkage
2954
// area, and parameter passing area. We start with 24/48 bytes, which is
2955
// prereserved space for [SP][CR][LR][3 x unused].
2957
CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2959
nAltivecParamsAtEnd);
2961
// Calculate by how many bytes the stack has to be adjusted in case of tail
2962
// call optimization.
2963
int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2965
// To protect arguments on the stack from being clobbered in a tail call,
2966
// force all the loads to happen before doing any other lowering.
2968
Chain = DAG.getStackArgumentTokenFactor(Chain);
2970
// Adjust the stack pointer for the new arguments...
2971
// These operations are automatically eliminated by the prolog/epilog pass
2972
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2973
SDValue CallSeqStart = Chain;
2975
// Load the return address and frame pointer so it can be move somewhere else
2978
Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2981
// Set up a copy of the stack pointer for use loading and storing any
2982
// arguments that may not fit in the registers available for argument
2986
StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2988
StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2990
// Figure out which arguments are going to go in registers, and which in
2991
// memory. Also, if this is a vararg function, floating point operations
2992
// must be stored to our stack, and loaded into integer regs as well, if
2993
// any integer regs are available for argument passing.
2994
unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
2995
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2997
static const unsigned GPR_32[] = { // 32-bit registers.
2998
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2999
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3001
static const unsigned GPR_64[] = { // 64-bit registers.
3002
PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3003
PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3005
static const unsigned *FPR = GetFPR();
3007
static const unsigned VR[] = {
3008
PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3009
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3011
const unsigned NumGPRs = array_lengthof(GPR_32);
3012
const unsigned NumFPRs = 13;
3013
const unsigned NumVRs = array_lengthof(VR);
3015
const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
3017
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3018
SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3020
SmallVector<SDValue, 8> MemOpChains;
3021
for (unsigned i = 0; i != NumOps; ++i) {
3022
SDValue Arg = Outs[i].Val;
3023
ISD::ArgFlagsTy Flags = Outs[i].Flags;
3025
// PtrOff will be used to store the current argument to the stack if a
3026
// register cannot be found for it.
3029
PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3031
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3033
// On PPC64, promote integers to 64-bit values.
3034
if (isPPC64 && Arg.getValueType() == MVT::i32) {
3035
// FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3036
unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3037
Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3040
// FIXME memcpy is used way more than necessary. Correctness first.
3041
if (Flags.isByVal()) {
3042
unsigned Size = Flags.getByValSize();
3043
if (Size==1 || Size==2) {
3044
// Very small objects are passed right-justified.
3045
// Everything else is passed left-justified.
3046
EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3047
if (GPR_idx != NumGPRs) {
3048
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3049
NULL, 0, VT, false, false, 0);
3050
MemOpChains.push_back(Load.getValue(1));
3051
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3053
ArgOffset += PtrByteSize;
3055
SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3056
SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3057
SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3058
CallSeqStart.getNode()->getOperand(0),
3060
// This must go outside the CALLSEQ_START..END.
3061
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3062
CallSeqStart.getNode()->getOperand(1));
3063
DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3064
NewCallSeqStart.getNode());
3065
Chain = CallSeqStart = NewCallSeqStart;
3066
ArgOffset += PtrByteSize;
3070
// Copy entire object into memory. There are cases where gcc-generated
3071
// code assumes it is there, even if it could be put entirely into
3072
// registers. (This is not what the doc says.)
3073
SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3074
CallSeqStart.getNode()->getOperand(0),
3076
// This must go outside the CALLSEQ_START..END.
3077
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3078
CallSeqStart.getNode()->getOperand(1));
3079
DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3080
Chain = CallSeqStart = NewCallSeqStart;
3081
// And copy the pieces of it that fit into registers.
3082
for (unsigned j=0; j<Size; j+=PtrByteSize) {
3083
SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3084
SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3085
if (GPR_idx != NumGPRs) {
3086
SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0,
3088
MemOpChains.push_back(Load.getValue(1));
3089
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3090
ArgOffset += PtrByteSize;
3092
ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3099
switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3100
default: llvm_unreachable("Unexpected ValueType for argument!");
3103
if (GPR_idx != NumGPRs) {
3104
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3106
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3107
isPPC64, isTailCall, false, MemOpChains,
3108
TailCallArguments, dl);
3110
ArgOffset += PtrByteSize;
3114
if (FPR_idx != NumFPRs) {
3115
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3118
SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
3120
MemOpChains.push_back(Store);
3122
// Float varargs are always shadowed in available integer registers
3123
if (GPR_idx != NumGPRs) {
3124
SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0,
3126
MemOpChains.push_back(Load.getValue(1));
3127
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3129
if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3130
SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3131
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3132
SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0,
3134
MemOpChains.push_back(Load.getValue(1));
3135
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3138
// If we have any FPRs remaining, we may also have GPRs remaining.
3139
// Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3141
if (GPR_idx != NumGPRs)
3143
if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3144
!isPPC64) // PPC64 has 64-bit GPR's obviously :)
3148
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3149
isPPC64, isTailCall, false, MemOpChains,
3150
TailCallArguments, dl);
3155
ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3162
// These go aligned on the stack, or in the corresponding R registers
3163
// when within range. The Darwin PPC ABI doc claims they also go in
3164
// V registers; in fact gcc does this only for arguments that are
3165
// prototyped, not for those that match the ... We do it for all
3166
// arguments, seems to work.
3167
while (ArgOffset % 16 !=0) {
3168
ArgOffset += PtrByteSize;
3169
if (GPR_idx != NumGPRs)
3172
// We could elide this store in the case where the object fits
3173
// entirely in R registers. Maybe later.
3174
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3175
DAG.getConstant(ArgOffset, PtrVT));
3176
SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
3178
MemOpChains.push_back(Store);
3179
if (VR_idx != NumVRs) {
3180
SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0,
3182
MemOpChains.push_back(Load.getValue(1));
3183
RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3186
for (unsigned i=0; i<16; i+=PtrByteSize) {
3187
if (GPR_idx == NumGPRs)
3189
SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3190
DAG.getConstant(i, PtrVT));
3191
SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0,
3193
MemOpChains.push_back(Load.getValue(1));
3194
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3199
// Non-varargs Altivec params generally go in registers, but have
3200
// stack space allocated at the end.
3201
if (VR_idx != NumVRs) {
3202
// Doesn't have GPR space allocated.
3203
RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3204
} else if (nAltivecParamsAtEnd==0) {
3205
// We are emitting Altivec params in order.
3206
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3207
isPPC64, isTailCall, true, MemOpChains,
3208
TailCallArguments, dl);
3214
// If all Altivec parameters fit in registers, as they usually do,
3215
// they get stack space following the non-Altivec parameters. We
3216
// don't track this here because nobody below needs it.
3217
// If there are more Altivec parameters than fit in registers emit
3219
if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3221
// Offset is aligned; skip 1st 12 params which go in V registers.
3222
ArgOffset = ((ArgOffset+15)/16)*16;
3224
for (unsigned i = 0; i != NumOps; ++i) {
3225
SDValue Arg = Outs[i].Val;
3226
EVT ArgType = Arg.getValueType();
3227
if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3228
ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3231
// We are emitting Altivec params in order.
3232
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3233
isPPC64, isTailCall, true, MemOpChains,
3234
TailCallArguments, dl);
3241
if (!MemOpChains.empty())
3242
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3243
&MemOpChains[0], MemOpChains.size());
3245
// Check if this is an indirect call (MTCTR/BCTRL).
3246
// See PrepareCall() for more information about calls through function
3247
// pointers in the 64-bit SVR4 ABI.
3248
if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3249
!dyn_cast<GlobalAddressSDNode>(Callee) &&
3250
!dyn_cast<ExternalSymbolSDNode>(Callee) &&
3251
!isBLACompatibleAddress(Callee, DAG)) {
3252
// Load r2 into a virtual register and store it to the TOC save area.
3253
SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3254
// TOC save area offset.
3255
SDValue PtrOff = DAG.getIntPtrConstant(40);
3256
SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3257
Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, NULL, 0,
3261
// Build a sequence of copy-to-reg nodes chained together with token chain
3262
// and flag operands which copy the outgoing args into the appropriate regs.
3264
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3265
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3266
RegsToPass[i].second, InFlag);
3267
InFlag = Chain.getValue(1);
3271
PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3272
FPOp, true, TailCallArguments);
3275
return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3276
RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3281
PPCTargetLowering::LowerReturn(SDValue Chain,
3282
CallingConv::ID CallConv, bool isVarArg,
3283
const SmallVectorImpl<ISD::OutputArg> &Outs,
3284
DebugLoc dl, SelectionDAG &DAG) {
3286
SmallVector<CCValAssign, 16> RVLocs;
3287
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3288
RVLocs, *DAG.getContext());
3289
CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3291
// If this is the first return lowered for this function, add the regs to the
3292
// liveout set for the function.
3293
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3294
for (unsigned i = 0; i != RVLocs.size(); ++i)
3295
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3300
// Copy the result values into the output registers.
3301
for (unsigned i = 0; i != RVLocs.size(); ++i) {
3302
CCValAssign &VA = RVLocs[i];
3303
assert(VA.isRegLoc() && "Can only return in registers!");
3304
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3306
Flag = Chain.getValue(1);
3310
return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3312
return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3315
SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3316
const PPCSubtarget &Subtarget) {
3317
// When we pop the dynamic allocation we need to restore the SP link.
3318
DebugLoc dl = Op.getDebugLoc();
3320
// Get the corect type for pointers.
3321
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3323
// Construct the stack pointer operand.
3324
bool isPPC64 = Subtarget.isPPC64();
3325
unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3326
SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3328
// Get the operands for the STACKRESTORE.
3329
SDValue Chain = Op.getOperand(0);
3330
SDValue SaveSP = Op.getOperand(1);
3332
// Load the old link SP.
3333
SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0,
3336
// Restore the stack pointer.
3337
Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3339
// Store the old link SP.
3340
return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0,
3347
PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3348
MachineFunction &MF = DAG.getMachineFunction();
3349
bool isPPC64 = PPCSubTarget.isPPC64();
3350
bool isDarwinABI = PPCSubTarget.isDarwinABI();
3351
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3353
// Get current frame pointer save index. The users of this index will be
3354
// primarily DYNALLOC instructions.
3355
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3356
int RASI = FI->getReturnAddrSaveIndex();
3358
// If the frame pointer save index hasn't been defined yet.
3360
// Find out what the fix offset of the frame pointer save area.
3361
int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
3362
// Allocate the frame index for frame pointer save area.
3363
RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset,
3366
FI->setReturnAddrSaveIndex(RASI);
3368
return DAG.getFrameIndex(RASI, PtrVT);
3372
PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3373
MachineFunction &MF = DAG.getMachineFunction();
3374
bool isPPC64 = PPCSubTarget.isPPC64();
3375
bool isDarwinABI = PPCSubTarget.isDarwinABI();
3376
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3378
// Get current frame pointer save index. The users of this index will be
3379
// primarily DYNALLOC instructions.
3380
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3381
int FPSI = FI->getFramePointerSaveIndex();
3383
// If the frame pointer save index hasn't been defined yet.
3385
// Find out what the fix offset of the frame pointer save area.
3386
int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
3389
// Allocate the frame index for frame pointer save area.
3390
FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset,
3393
FI->setFramePointerSaveIndex(FPSI);
3395
return DAG.getFrameIndex(FPSI, PtrVT);
3398
SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3400
const PPCSubtarget &Subtarget) {
3402
SDValue Chain = Op.getOperand(0);
3403
SDValue Size = Op.getOperand(1);
3404
DebugLoc dl = Op.getDebugLoc();
3406
// Get the corect type for pointers.
3407
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3409
SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3410
DAG.getConstant(0, PtrVT), Size);
3411
// Construct a node for the frame pointer save index.
3412
SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3413
// Build a DYNALLOC node.
3414
SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3415
SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3416
return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3419
/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3421
SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
3422
// Not FP? Not a fsel.
3423
if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3424
!Op.getOperand(2).getValueType().isFloatingPoint())
3427
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3429
// Cannot handle SETEQ/SETNE.
3430
if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3432
EVT ResVT = Op.getValueType();
3433
EVT CmpVT = Op.getOperand(0).getValueType();
3434
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3435
SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3436
DebugLoc dl = Op.getDebugLoc();
3438
// If the RHS of the comparison is a 0.0, we don't need to do the
3439
// subtraction at all.
3440
if (isFloatingPointZero(RHS))
3442
default: break; // SETUO etc aren't handled by fsel.
3445
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3448
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3449
LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3450
return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3453
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3456
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3457
LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3458
return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3459
DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3464
default: break; // SETUO etc aren't handled by fsel.
3467
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3468
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3469
Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3470
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3473
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3474
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3475
Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3476
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3479
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3480
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3481
Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3482
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3485
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3486
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3487
Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3488
return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3493
// FIXME: Split this code up when LegalizeDAGTypes lands.
3494
SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3496
assert(Op.getOperand(0).getValueType().isFloatingPoint());
3497
SDValue Src = Op.getOperand(0);
3498
if (Src.getValueType() == MVT::f32)
3499
Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3502
switch (Op.getValueType().getSimpleVT().SimpleTy) {
3503
default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3505
Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3510
Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3514
// Convert the FP value to an int value through memory.
3515
SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3517
// Emit a store to the stack slot.
3518
SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0,
3521
// Result is a load from the stack slot. If loading 4 bytes, make sure to
3523
if (Op.getValueType() == MVT::i32)
3524
FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3525
DAG.getConstant(4, FIPtr.getValueType()));
3526
return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0,
3530
SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3531
DebugLoc dl = Op.getDebugLoc();
3532
// Don't handle ppc_fp128 here; let it be lowered to a libcall.
3533
if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3536
if (Op.getOperand(0).getValueType() == MVT::i64) {
3537
SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
3538
MVT::f64, Op.getOperand(0));
3539
SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3540
if (Op.getValueType() == MVT::f32)
3541
FP = DAG.getNode(ISD::FP_ROUND, dl,
3542
MVT::f32, FP, DAG.getIntPtrConstant(0));
3546
assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3547
"Unhandled SINT_TO_FP type in custom expander!");
3548
// Since we only generate this in 64-bit mode, we can take advantage of
3549
// 64-bit registers. In particular, sign extend the input value into the
3550
// 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3551
// then lfd it and fcfid it.
3552
MachineFunction &MF = DAG.getMachineFunction();
3553
MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3554
int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3555
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3556
SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3558
SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3561
// STD the extended value into the stack slot.
3562
MachineMemOperand *MMO =
3563
MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
3564
MachineMemOperand::MOStore, 0, 8, 8);
3565
SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3567
DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3568
Ops, 4, MVT::i64, MMO);
3569
// Load the value as a double.
3570
SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0, false, false, 0);
3572
// FCFID it and return it.
3573
SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3574
if (Op.getValueType() == MVT::f32)
3575
FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3579
SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
3580
DebugLoc dl = Op.getDebugLoc();
3582
The rounding mode is in bits 30:31 of FPSR, and has the following
3589
FLT_ROUNDS, on the other hand, expects the following:
3596
To perform the conversion, we do:
3597
((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3600
MachineFunction &MF = DAG.getMachineFunction();
3601
EVT VT = Op.getValueType();
3602
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3603
std::vector<EVT> NodeTys;
3604
SDValue MFFSreg, InFlag;
3606
// Save FP Control Word to register
3607
NodeTys.push_back(MVT::f64); // return register
3608
NodeTys.push_back(MVT::Flag); // unused in this context
3609
SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3611
// Save FP register to stack slot
3612
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3613
SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3614
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3615
StackSlot, NULL, 0, false, false, 0);
3617
// Load FP Control Word from low 32 bits of stack slot.
3618
SDValue Four = DAG.getConstant(4, PtrVT);
3619
SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3620
SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0,
3623
// Transform as necessary
3625
DAG.getNode(ISD::AND, dl, MVT::i32,
3626
CWD, DAG.getConstant(3, MVT::i32));
3628
DAG.getNode(ISD::SRL, dl, MVT::i32,
3629
DAG.getNode(ISD::AND, dl, MVT::i32,
3630
DAG.getNode(ISD::XOR, dl, MVT::i32,
3631
CWD, DAG.getConstant(3, MVT::i32)),
3632
DAG.getConstant(3, MVT::i32)),
3633
DAG.getConstant(1, MVT::i32));
3636
DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3638
return DAG.getNode((VT.getSizeInBits() < 16 ?
3639
ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3642
SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
3643
EVT VT = Op.getValueType();
3644
unsigned BitWidth = VT.getSizeInBits();
3645
DebugLoc dl = Op.getDebugLoc();
3646
assert(Op.getNumOperands() == 3 &&
3647
VT == Op.getOperand(1).getValueType() &&
3650
// Expand into a bunch of logical ops. Note that these ops
3651
// depend on the PPC behavior for oversized shift amounts.
3652
SDValue Lo = Op.getOperand(0);
3653
SDValue Hi = Op.getOperand(1);
3654
SDValue Amt = Op.getOperand(2);
3655
EVT AmtVT = Amt.getValueType();
3657
SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3658
DAG.getConstant(BitWidth, AmtVT), Amt);
3659
SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3660
SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3661
SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3662
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3663
DAG.getConstant(-BitWidth, AmtVT));
3664
SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3665
SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3666
SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3667
SDValue OutOps[] = { OutLo, OutHi };
3668
return DAG.getMergeValues(OutOps, 2, dl);
3671
SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3672
EVT VT = Op.getValueType();
3673
DebugLoc dl = Op.getDebugLoc();
3674
unsigned BitWidth = VT.getSizeInBits();
3675
assert(Op.getNumOperands() == 3 &&
3676
VT == Op.getOperand(1).getValueType() &&
3679
// Expand into a bunch of logical ops. Note that these ops
3680
// depend on the PPC behavior for oversized shift amounts.
3681
SDValue Lo = Op.getOperand(0);
3682
SDValue Hi = Op.getOperand(1);
3683
SDValue Amt = Op.getOperand(2);
3684
EVT AmtVT = Amt.getValueType();
3686
SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3687
DAG.getConstant(BitWidth, AmtVT), Amt);
3688
SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3689
SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3690
SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3691
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3692
DAG.getConstant(-BitWidth, AmtVT));
3693
SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3694
SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3695
SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3696
SDValue OutOps[] = { OutLo, OutHi };
3697
return DAG.getMergeValues(OutOps, 2, dl);
3700
SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3701
DebugLoc dl = Op.getDebugLoc();
3702
EVT VT = Op.getValueType();
3703
unsigned BitWidth = VT.getSizeInBits();
3704
assert(Op.getNumOperands() == 3 &&
3705
VT == Op.getOperand(1).getValueType() &&
3708
// Expand into a bunch of logical ops, followed by a select_cc.
3709
SDValue Lo = Op.getOperand(0);
3710
SDValue Hi = Op.getOperand(1);
3711
SDValue Amt = Op.getOperand(2);
3712
EVT AmtVT = Amt.getValueType();
3714
SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3715
DAG.getConstant(BitWidth, AmtVT), Amt);
3716
SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3717
SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3718
SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3719
SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3720
DAG.getConstant(-BitWidth, AmtVT));
3721
SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3722
SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3723
SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3724
Tmp4, Tmp6, ISD::SETLE);
3725
SDValue OutOps[] = { OutLo, OutHi };
3726
return DAG.getMergeValues(OutOps, 2, dl);
3729
//===----------------------------------------------------------------------===//
3730
// Vector related lowering.
3733
/// BuildSplatI - Build a canonical splati of Val with an element size of
3734
/// SplatSize. Cast the result to VT.
3735
static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3736
SelectionDAG &DAG, DebugLoc dl) {
3737
assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3739
static const EVT VTys[] = { // canonical VT to use for each size.
3740
MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3743
EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3745
// Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3749
EVT CanonicalVT = VTys[SplatSize-1];
3751
// Build a canonical splat for this value.
3752
SDValue Elt = DAG.getConstant(Val, MVT::i32);
3753
SmallVector<SDValue, 8> Ops;
3754
Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3755
SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3756
&Ops[0], Ops.size());
3757
return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3760
/// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3761
/// specified intrinsic ID.
3762
static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3763
SelectionDAG &DAG, DebugLoc dl,
3764
EVT DestVT = MVT::Other) {
3765
if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3766
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3767
DAG.getConstant(IID, MVT::i32), LHS, RHS);
3770
/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3771
/// specified intrinsic ID.
3772
static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3773
SDValue Op2, SelectionDAG &DAG,
3774
DebugLoc dl, EVT DestVT = MVT::Other) {
3775
if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3776
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3777
DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3781
/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3782
/// amount. The result has the specified value type.
3783
static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3784
EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3785
// Force LHS/RHS to be the right type.
3786
LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3787
RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3790
for (unsigned i = 0; i != 16; ++i)
3792
SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3793
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3796
// If this is a case we can't handle, return null and let the default
3797
// expansion code take care of it. If we CAN select this case, and if it
3798
// selects to a single instruction, return Op. Otherwise, if we can codegen
3799
// this case more efficiently than a constant pool load, lower it to the
3800
// sequence of ops that should be used.
3801
SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3802
DebugLoc dl = Op.getDebugLoc();
3803
BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3804
assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3806
// Check if this is a splat of a constant value.
3807
APInt APSplatBits, APSplatUndef;
3808
unsigned SplatBitSize;
3810
if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3811
HasAnyUndefs, 0, true) || SplatBitSize > 32)
3814
unsigned SplatBits = APSplatBits.getZExtValue();
3815
unsigned SplatUndef = APSplatUndef.getZExtValue();
3816
unsigned SplatSize = SplatBitSize / 8;
3818
// First, handle single instruction cases.
3821
if (SplatBits == 0) {
3822
// Canonicalize all zero vectors to be v4i32.
3823
if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3824
SDValue Z = DAG.getConstant(0, MVT::i32);
3825
Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3826
Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3831
// If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3832
int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3834
if (SextVal >= -16 && SextVal <= 15)
3835
return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3838
// Two instruction sequences.
3840
// If this value is in the range [-32,30] and is even, use:
3841
// tmp = VSPLTI[bhw], result = add tmp, tmp
3842
if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3843
SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3844
Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3845
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3848
// If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3849
// 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3851
if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3852
// Make -1 and vspltisw -1:
3853
SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3855
// Make the VSLW intrinsic, computing 0x8000_0000.
3856
SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3859
// xor by OnesV to invert it.
3860
Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3861
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3864
// Check to see if this is a wide variety of vsplti*, binop self cases.
3865
static const signed char SplatCsts[] = {
3866
-1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3867
-8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3870
for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3871
// Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3872
// cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3873
int i = SplatCsts[idx];
3875
// Figure out what shift amount will be used by altivec if shifted by i in
3877
unsigned TypeShiftAmt = i & (SplatBitSize-1);
3879
// vsplti + shl self.
3880
if (SextVal == (i << (int)TypeShiftAmt)) {
3881
SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3882
static const unsigned IIDs[] = { // Intrinsic to use for each size.
3883
Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3884
Intrinsic::ppc_altivec_vslw
3886
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3887
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3890
// vsplti + srl self.
3891
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3892
SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3893
static const unsigned IIDs[] = { // Intrinsic to use for each size.
3894
Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3895
Intrinsic::ppc_altivec_vsrw
3897
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3898
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3901
// vsplti + sra self.
3902
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3903
SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3904
static const unsigned IIDs[] = { // Intrinsic to use for each size.
3905
Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3906
Intrinsic::ppc_altivec_vsraw
3908
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3909
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3912
// vsplti + rol self.
3913
if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3914
((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3915
SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3916
static const unsigned IIDs[] = { // Intrinsic to use for each size.
3917
Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3918
Intrinsic::ppc_altivec_vrlw
3920
Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3921
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3924
// t = vsplti c, result = vsldoi t, t, 1
3925
if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3926
SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3927
return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3929
// t = vsplti c, result = vsldoi t, t, 2
3930
if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3931
SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3932
return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3934
// t = vsplti c, result = vsldoi t, t, 3
3935
if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3936
SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3937
return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3941
// Three instruction sequences.
3943
// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3944
if (SextVal >= 0 && SextVal <= 31) {
3945
SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3946
SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3947
LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3948
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3950
// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3951
if (SextVal >= -31 && SextVal <= 0) {
3952
SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3953
SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3954
LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3955
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3961
/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3962
/// the specified operations to build the shuffle.
3963
static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3964
SDValue RHS, SelectionDAG &DAG,
3966
unsigned OpNum = (PFEntry >> 26) & 0x0F;
3967
unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3968
unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3971
OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3983
if (OpNum == OP_COPY) {
3984
if (LHSID == (1*9+2)*9+3) return LHS;
3985
assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3989
SDValue OpLHS, OpRHS;
3990
OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3991
OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3995
default: llvm_unreachable("Unknown i32 permute!");
3997
ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3998
ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3999
ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
4000
ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
4003
ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
4004
ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
4005
ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
4006
ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
4009
for (unsigned i = 0; i != 16; ++i)
4010
ShufIdxs[i] = (i&3)+0;
4013
for (unsigned i = 0; i != 16; ++i)
4014
ShufIdxs[i] = (i&3)+4;
4017
for (unsigned i = 0; i != 16; ++i)
4018
ShufIdxs[i] = (i&3)+8;
4021
for (unsigned i = 0; i != 16; ++i)
4022
ShufIdxs[i] = (i&3)+12;
4025
return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4027
return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4029
return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4031
EVT VT = OpLHS.getValueType();
4032
OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
4033
OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
4034
SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
4035
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
4038
/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
4039
/// is a shuffle we can handle in a single instruction, return it. Otherwise,
4040
/// return the code it can be lowered into. Worst case, it can always be
4041
/// lowered into a vperm.
4042
SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4043
SelectionDAG &DAG) {
4044
DebugLoc dl = Op.getDebugLoc();
4045
SDValue V1 = Op.getOperand(0);
4046
SDValue V2 = Op.getOperand(1);
4047
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4048
EVT VT = Op.getValueType();
4050
// Cases that are handled by instructions that take permute immediates
4051
// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4052
// selected by the instruction selector.
4053
if (V2.getOpcode() == ISD::UNDEF) {
4054
if (PPC::isSplatShuffleMask(SVOp, 1) ||
4055
PPC::isSplatShuffleMask(SVOp, 2) ||
4056
PPC::isSplatShuffleMask(SVOp, 4) ||
4057
PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4058
PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4059
PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4060
PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4061
PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4062
PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4063
PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4064
PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4065
PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4070
// Altivec has a variety of "shuffle immediates" that take two vector inputs
4071
// and produce a fixed permutation. If any of these match, do not lower to
4073
if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4074
PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4075
PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4076
PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4077
PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4078
PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4079
PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4080
PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4081
PPC::isVMRGHShuffleMask(SVOp, 4, false))
4084
// Check to see if this is a shuffle of 4-byte values. If so, we can use our
4085
// perfect shuffle table to emit an optimal matching sequence.
4086
SmallVector<int, 16> PermMask;
4087
SVOp->getMask(PermMask);
4089
unsigned PFIndexes[4];
4090
bool isFourElementShuffle = true;
4091
for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4092
unsigned EltNo = 8; // Start out undef.
4093
for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
4094
if (PermMask[i*4+j] < 0)
4095
continue; // Undef, ignore it.
4097
unsigned ByteSource = PermMask[i*4+j];
4098
if ((ByteSource & 3) != j) {
4099
isFourElementShuffle = false;
4104
EltNo = ByteSource/4;
4105
} else if (EltNo != ByteSource/4) {
4106
isFourElementShuffle = false;
4110
PFIndexes[i] = EltNo;
4113
// If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4114
// perfect shuffle vector to determine if it is cost effective to do this as
4115
// discrete instructions, or whether we should use a vperm.
4116
if (isFourElementShuffle) {
4117
// Compute the index in the perfect shuffle table.
4118
unsigned PFTableIndex =
4119
PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4121
unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4122
unsigned Cost = (PFEntry >> 30);
4124
// Determining when to avoid vperm is tricky. Many things affect the cost
4125
// of vperm, particularly how many times the perm mask needs to be computed.
4126
// For example, if the perm mask can be hoisted out of a loop or is already
4127
// used (perhaps because there are multiple permutes with the same shuffle
4128
// mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
4129
// the loop requires an extra register.
4131
// As a compromise, we only emit discrete instructions if the shuffle can be
4132
// generated in 3 or fewer operations. When we have loop information
4133
// available, if this block is within a loop, we should avoid using vperm
4134
// for 3-operation perms and use a constant pool load instead.
4136
return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4139
// Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4140
// vector that will get spilled to the constant pool.
4141
if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4143
// The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4144
// that it is in input element units, not in bytes. Convert now.
4145
EVT EltVT = V1.getValueType().getVectorElementType();
4146
unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4148
SmallVector<SDValue, 16> ResultMask;
4149
for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4150
unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4152
for (unsigned j = 0; j != BytesPerElement; ++j)
4153
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4157
SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4158
&ResultMask[0], ResultMask.size());
4159
return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4162
/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4163
/// altivec comparison. If it is, return true and fill in Opc/isDot with
4164
/// information about the intrinsic.
4165
static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4167
unsigned IntrinsicID =
4168
cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4171
switch (IntrinsicID) {
4172
default: return false;
4173
// Comparison predicates.
4174
case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4175
case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4176
case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4177
case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4178
case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4179
case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4180
case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4181
case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4182
case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4183
case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4184
case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4185
case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4186
case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4188
// Normal Comparisons.
4189
case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4190
case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4191
case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4192
case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4193
case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4194
case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4195
case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4196
case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4197
case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4198
case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4199
case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4200
case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4201
case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4206
/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4207
/// lower, do it, otherwise return null.
4208
SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4209
SelectionDAG &DAG) {
4210
// If this is a lowered altivec predicate compare, CompareOpc is set to the
4211
// opcode number of the comparison.
4212
DebugLoc dl = Op.getDebugLoc();
4215
if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4216
return SDValue(); // Don't custom lower most intrinsics.
4218
// If this is a non-dot comparison, make the VCMP node and we are done.
4220
SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4221
Op.getOperand(1), Op.getOperand(2),
4222
DAG.getConstant(CompareOpc, MVT::i32));
4223
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
4226
// Create the PPCISD altivec 'dot' comparison node.
4228
Op.getOperand(2), // LHS
4229
Op.getOperand(3), // RHS
4230
DAG.getConstant(CompareOpc, MVT::i32)
4232
std::vector<EVT> VTs;
4233
VTs.push_back(Op.getOperand(2).getValueType());
4234
VTs.push_back(MVT::Flag);
4235
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4237
// Now that we have the comparison, emit a copy from the CR to a GPR.
4238
// This is flagged to the above dot comparison.
4239
SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4240
DAG.getRegister(PPC::CR6, MVT::i32),
4241
CompNode.getValue(1));
4243
// Unpack the result based on how the target uses it.
4244
unsigned BitNo; // Bit # of CR6.
4245
bool InvertBit; // Invert result?
4246
switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4247
default: // Can't happen, don't crash on invalid number though.
4248
case 0: // Return the value of the EQ bit of CR6.
4249
BitNo = 0; InvertBit = false;
4251
case 1: // Return the inverted value of the EQ bit of CR6.
4252
BitNo = 0; InvertBit = true;
4254
case 2: // Return the value of the LT bit of CR6.
4255
BitNo = 2; InvertBit = false;
4257
case 3: // Return the inverted value of the LT bit of CR6.
4258
BitNo = 2; InvertBit = true;
4262
// Shift the bit into the low position.
4263
Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4264
DAG.getConstant(8-(3-BitNo), MVT::i32));
4266
Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4267
DAG.getConstant(1, MVT::i32));
4269
// If we are supposed to, toggle the bit.
4271
Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4272
DAG.getConstant(1, MVT::i32));
4276
SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4277
SelectionDAG &DAG) {
4278
DebugLoc dl = Op.getDebugLoc();
4279
// Create a stack slot that is 16-byte aligned.
4280
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4281
int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4282
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4283
SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4285
// Store the input value into Value#0 of the stack slot.
4286
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4287
Op.getOperand(0), FIdx, NULL, 0,
4290
return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0,
4294
SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
4295
DebugLoc dl = Op.getDebugLoc();
4296
if (Op.getValueType() == MVT::v4i32) {
4297
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4299
SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4300
SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4302
SDValue RHSSwap = // = vrlw RHS, 16
4303
BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4305
// Shrinkify inputs to v8i16.
4306
LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
4307
RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
4308
RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
4310
// Low parts multiplied together, generating 32-bit results (we ignore the
4312
SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4313
LHS, RHS, DAG, dl, MVT::v4i32);
4315
SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4316
LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4317
// Shift the high parts up 16 bits.
4318
HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4320
return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4321
} else if (Op.getValueType() == MVT::v8i16) {
4322
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4324
SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4326
return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4327
LHS, RHS, Zero, DAG, dl);
4328
} else if (Op.getValueType() == MVT::v16i8) {
4329
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4331
// Multiply the even 8-bit parts, producing 16-bit sums.
4332
SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4333
LHS, RHS, DAG, dl, MVT::v8i16);
4334
EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
4336
// Multiply the odd 8-bit parts, producing 16-bit sums.
4337
SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4338
LHS, RHS, DAG, dl, MVT::v8i16);
4339
OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
4341
// Merge the results together.
4343
for (unsigned i = 0; i != 8; ++i) {
4345
Ops[i*2+1] = 2*i+1+16;
4347
return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4349
llvm_unreachable("Unknown mul to lower!");
4353
/// LowerOperation - Provide custom lowering hooks for some operations.
4355
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4356
switch (Op.getOpcode()) {
4357
default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4358
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4359
case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4360
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4361
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4362
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4363
case ISD::SETCC: return LowerSETCC(Op, DAG);
4364
case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4366
return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4367
VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4370
return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4371
VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4373
case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4374
case ISD::DYNAMIC_STACKALLOC:
4375
return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4377
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4378
case ISD::FP_TO_UINT:
4379
case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4381
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4382
case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4384
// Lower 64-bit shifts.
4385
case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4386
case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4387
case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4389
// Vector-related lowering.
4390
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4391
case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4392
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4393
case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4394
case ISD::MUL: return LowerMUL(Op, DAG);
4396
// Frame & Return address.
4397
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4398
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4403
void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4404
SmallVectorImpl<SDValue>&Results,
4405
SelectionDAG &DAG) {
4406
DebugLoc dl = N->getDebugLoc();
4407
switch (N->getOpcode()) {
4409
assert(false && "Do not know how to custom type legalize this operation!");
4411
case ISD::FP_ROUND_INREG: {
4412
assert(N->getValueType(0) == MVT::ppcf128);
4413
assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4414
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4415
MVT::f64, N->getOperand(0),
4416
DAG.getIntPtrConstant(0));
4417
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4418
MVT::f64, N->getOperand(0),
4419
DAG.getIntPtrConstant(1));
4421
// This sequence changes FPSCR to do round-to-zero, adds the two halves
4422
// of the long double, and puts FPSCR back the way it was. We do not
4423
// actually model FPSCR.
4424
std::vector<EVT> NodeTys;
4425
SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4427
NodeTys.push_back(MVT::f64); // Return register
4428
NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
4429
Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4430
MFFSreg = Result.getValue(0);
4431
InFlag = Result.getValue(1);
4434
NodeTys.push_back(MVT::Flag); // Returns a flag
4435
Ops[0] = DAG.getConstant(31, MVT::i32);
4437
Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4438
InFlag = Result.getValue(0);
4441
NodeTys.push_back(MVT::Flag); // Returns a flag
4442
Ops[0] = DAG.getConstant(30, MVT::i32);
4444
Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4445
InFlag = Result.getValue(0);
4448
NodeTys.push_back(MVT::f64); // result of add
4449
NodeTys.push_back(MVT::Flag); // Returns a flag
4453
Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4454
FPreg = Result.getValue(0);
4455
InFlag = Result.getValue(1);
4458
NodeTys.push_back(MVT::f64);
4459
Ops[0] = DAG.getConstant(1, MVT::i32);
4463
Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4464
FPreg = Result.getValue(0);
4466
// We know the low half is about to be thrown away, so just use something
4468
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4472
case ISD::FP_TO_SINT:
4473
Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4479
//===----------------------------------------------------------------------===//
4480
// Other Lowering Code
4481
//===----------------------------------------------------------------------===//
4484
PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4485
bool is64bit, unsigned BinOpcode) const {
4486
// This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4487
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4489
const BasicBlock *LLVM_BB = BB->getBasicBlock();
4490
MachineFunction *F = BB->getParent();
4491
MachineFunction::iterator It = BB;
4494
unsigned dest = MI->getOperand(0).getReg();
4495
unsigned ptrA = MI->getOperand(1).getReg();
4496
unsigned ptrB = MI->getOperand(2).getReg();
4497
unsigned incr = MI->getOperand(3).getReg();
4498
DebugLoc dl = MI->getDebugLoc();
4500
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4501
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4502
F->insert(It, loopMBB);
4503
F->insert(It, exitMBB);
4504
exitMBB->transferSuccessors(BB);
4506
MachineRegisterInfo &RegInfo = F->getRegInfo();
4507
unsigned TmpReg = (!BinOpcode) ? incr :
4508
RegInfo.createVirtualRegister(
4509
is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4510
(const TargetRegisterClass *) &PPC::GPRCRegClass);
4514
// fallthrough --> loopMBB
4515
BB->addSuccessor(loopMBB);
4518
// l[wd]arx dest, ptr
4519
// add r0, dest, incr
4520
// st[wd]cx. r0, ptr
4522
// fallthrough --> exitMBB
4524
BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4525
.addReg(ptrA).addReg(ptrB);
4527
BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4528
BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4529
.addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4530
BuildMI(BB, dl, TII->get(PPC::BCC))
4531
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4532
BB->addSuccessor(loopMBB);
4533
BB->addSuccessor(exitMBB);
4542
PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4543
MachineBasicBlock *BB,
4544
bool is8bit, // operation
4545
unsigned BinOpcode) const {
4546
// This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4547
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4548
// In 64 bit mode we have to use 64 bits for addresses, even though the
4549
// lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4550
// registers without caring whether they're 32 or 64, but here we're
4551
// doing actual arithmetic on the addresses.
4552
bool is64bit = PPCSubTarget.isPPC64();
4554
const BasicBlock *LLVM_BB = BB->getBasicBlock();
4555
MachineFunction *F = BB->getParent();
4556
MachineFunction::iterator It = BB;
4559
unsigned dest = MI->getOperand(0).getReg();
4560
unsigned ptrA = MI->getOperand(1).getReg();
4561
unsigned ptrB = MI->getOperand(2).getReg();
4562
unsigned incr = MI->getOperand(3).getReg();
4563
DebugLoc dl = MI->getDebugLoc();
4565
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4566
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4567
F->insert(It, loopMBB);
4568
F->insert(It, exitMBB);
4569
exitMBB->transferSuccessors(BB);
4571
MachineRegisterInfo &RegInfo = F->getRegInfo();
4572
const TargetRegisterClass *RC =
4573
is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4574
(const TargetRegisterClass *) &PPC::GPRCRegClass;
4575
unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4576
unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4577
unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4578
unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4579
unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4580
unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4581
unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4582
unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4583
unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4584
unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4585
unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4587
unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4591
// fallthrough --> loopMBB
4592
BB->addSuccessor(loopMBB);
4594
// The 4-byte load must be aligned, while a char or short may be
4595
// anywhere in the word. Hence all this nasty bookkeeping code.
4596
// add ptr1, ptrA, ptrB [copy if ptrA==0]
4597
// rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4598
// xori shift, shift1, 24 [16]
4599
// rlwinm ptr, ptr1, 0, 0, 29
4600
// slw incr2, incr, shift
4601
// li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4602
// slw mask, mask2, shift
4604
// lwarx tmpDest, ptr
4605
// add tmp, tmpDest, incr2
4606
// andc tmp2, tmpDest, mask
4607
// and tmp3, tmp, mask
4608
// or tmp4, tmp3, tmp2
4611
// fallthrough --> exitMBB
4612
// srw dest, tmpDest, shift
4614
if (ptrA!=PPC::R0) {
4615
Ptr1Reg = RegInfo.createVirtualRegister(RC);
4616
BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4617
.addReg(ptrA).addReg(ptrB);
4621
BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4622
.addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4623
BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4624
.addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4626
BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4627
.addReg(Ptr1Reg).addImm(0).addImm(61);
4629
BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4630
.addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4631
BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4632
.addReg(incr).addReg(ShiftReg);
4634
BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4636
BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4637
BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4639
BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4640
.addReg(Mask2Reg).addReg(ShiftReg);
4643
BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4644
.addReg(PPC::R0).addReg(PtrReg);
4646
BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4647
.addReg(Incr2Reg).addReg(TmpDestReg);
4648
BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4649
.addReg(TmpDestReg).addReg(MaskReg);
4650
BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4651
.addReg(TmpReg).addReg(MaskReg);
4652
BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4653
.addReg(Tmp3Reg).addReg(Tmp2Reg);
4654
BuildMI(BB, dl, TII->get(PPC::STWCX))
4655
.addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4656
BuildMI(BB, dl, TII->get(PPC::BCC))
4657
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4658
BB->addSuccessor(loopMBB);
4659
BB->addSuccessor(exitMBB);
4664
BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4669
PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4670
MachineBasicBlock *BB,
4671
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
4672
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4674
// To "insert" these instructions we actually have to insert their
4675
// control-flow patterns.
4676
const BasicBlock *LLVM_BB = BB->getBasicBlock();
4677
MachineFunction::iterator It = BB;
4680
MachineFunction *F = BB->getParent();
4682
if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4683
MI->getOpcode() == PPC::SELECT_CC_I8 ||
4684
MI->getOpcode() == PPC::SELECT_CC_F4 ||
4685
MI->getOpcode() == PPC::SELECT_CC_F8 ||
4686
MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4688
// The incoming instruction knows the destination vreg to set, the
4689
// condition code register to branch on, the true/false values to
4690
// select between, and a branch opcode to use.
4695
// cmpTY ccX, r1, r2
4697
// fallthrough --> copy0MBB
4698
MachineBasicBlock *thisMBB = BB;
4699
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4700
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4701
unsigned SelectPred = MI->getOperand(4).getImm();
4702
DebugLoc dl = MI->getDebugLoc();
4703
BuildMI(BB, dl, TII->get(PPC::BCC))
4704
.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4705
F->insert(It, copy0MBB);
4706
F->insert(It, sinkMBB);
4707
// Update machine-CFG edges by first adding all successors of the current
4708
// block to the new block which will contain the Phi node for the select.
4709
// Also inform sdisel of the edge changes.
4710
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
4711
E = BB->succ_end(); I != E; ++I) {
4712
EM->insert(std::make_pair(*I, sinkMBB));
4713
sinkMBB->addSuccessor(*I);
4715
// Next, remove all successors of the current block, and add the true
4716
// and fallthrough blocks as its successors.
4717
while (!BB->succ_empty())
4718
BB->removeSuccessor(BB->succ_begin());
4719
// Next, add the true and fallthrough blocks as its successors.
4720
BB->addSuccessor(copy0MBB);
4721
BB->addSuccessor(sinkMBB);
4724
// %FalseValue = ...
4725
// # fallthrough to sinkMBB
4728
// Update machine-CFG edges
4729
BB->addSuccessor(sinkMBB);
4732
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4735
BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4736
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4737
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4739
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4740
BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4741
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4742
BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4743
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4744
BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4745
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4746
BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4748
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4749
BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4750
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4751
BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4752
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4753
BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4754
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4755
BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4757
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4758
BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4759
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4760
BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4761
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4762
BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4763
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4764
BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4766
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4767
BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4768
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4769
BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4770
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4771
BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4772
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4773
BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4775
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4776
BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4777
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4778
BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4779
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4780
BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4781
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4782
BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4784
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4785
BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4786
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4787
BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4788
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4789
BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4790
else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4791
BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4793
else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4794
BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4795
else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4796
BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4797
else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4798
BB = EmitAtomicBinary(MI, BB, false, 0);
4799
else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4800
BB = EmitAtomicBinary(MI, BB, true, 0);
4802
else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4803
MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4804
bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4806
unsigned dest = MI->getOperand(0).getReg();
4807
unsigned ptrA = MI->getOperand(1).getReg();
4808
unsigned ptrB = MI->getOperand(2).getReg();
4809
unsigned oldval = MI->getOperand(3).getReg();
4810
unsigned newval = MI->getOperand(4).getReg();
4811
DebugLoc dl = MI->getDebugLoc();
4813
MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4814
MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4815
MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4816
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4817
F->insert(It, loop1MBB);
4818
F->insert(It, loop2MBB);
4819
F->insert(It, midMBB);
4820
F->insert(It, exitMBB);
4821
exitMBB->transferSuccessors(BB);
4825
// fallthrough --> loopMBB
4826
BB->addSuccessor(loop1MBB);
4829
// l[wd]arx dest, ptr
4830
// cmp[wd] dest, oldval
4833
// st[wd]cx. newval, ptr
4837
// st[wd]cx. dest, ptr
4840
BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4841
.addReg(ptrA).addReg(ptrB);
4842
BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4843
.addReg(oldval).addReg(dest);
4844
BuildMI(BB, dl, TII->get(PPC::BCC))
4845
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4846
BB->addSuccessor(loop2MBB);
4847
BB->addSuccessor(midMBB);
4850
BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4851
.addReg(newval).addReg(ptrA).addReg(ptrB);
4852
BuildMI(BB, dl, TII->get(PPC::BCC))
4853
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4854
BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4855
BB->addSuccessor(loop1MBB);
4856
BB->addSuccessor(exitMBB);
4859
BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4860
.addReg(dest).addReg(ptrA).addReg(ptrB);
4861
BB->addSuccessor(exitMBB);
4866
} else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4867
MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4868
// We must use 64-bit registers for addresses when targeting 64-bit,
4869
// since we're actually doing arithmetic on them. Other registers
4871
bool is64bit = PPCSubTarget.isPPC64();
4872
bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4874
unsigned dest = MI->getOperand(0).getReg();
4875
unsigned ptrA = MI->getOperand(1).getReg();
4876
unsigned ptrB = MI->getOperand(2).getReg();
4877
unsigned oldval = MI->getOperand(3).getReg();
4878
unsigned newval = MI->getOperand(4).getReg();
4879
DebugLoc dl = MI->getDebugLoc();
4881
MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4882
MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4883
MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4884
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4885
F->insert(It, loop1MBB);
4886
F->insert(It, loop2MBB);
4887
F->insert(It, midMBB);
4888
F->insert(It, exitMBB);
4889
exitMBB->transferSuccessors(BB);
4891
MachineRegisterInfo &RegInfo = F->getRegInfo();
4892
const TargetRegisterClass *RC =
4893
is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4894
(const TargetRegisterClass *) &PPC::GPRCRegClass;
4895
unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4896
unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4897
unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4898
unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4899
unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4900
unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4901
unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4902
unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4903
unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4904
unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4905
unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4906
unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4907
unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4909
unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4912
// fallthrough --> loopMBB
4913
BB->addSuccessor(loop1MBB);
4915
// The 4-byte load must be aligned, while a char or short may be
4916
// anywhere in the word. Hence all this nasty bookkeeping code.
4917
// add ptr1, ptrA, ptrB [copy if ptrA==0]
4918
// rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4919
// xori shift, shift1, 24 [16]
4920
// rlwinm ptr, ptr1, 0, 0, 29
4921
// slw newval2, newval, shift
4922
// slw oldval2, oldval,shift
4923
// li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4924
// slw mask, mask2, shift
4925
// and newval3, newval2, mask
4926
// and oldval3, oldval2, mask
4928
// lwarx tmpDest, ptr
4929
// and tmp, tmpDest, mask
4930
// cmpw tmp, oldval3
4933
// andc tmp2, tmpDest, mask
4934
// or tmp4, tmp2, newval3
4939
// stwcx. tmpDest, ptr
4941
// srw dest, tmpDest, shift
4942
if (ptrA!=PPC::R0) {
4943
Ptr1Reg = RegInfo.createVirtualRegister(RC);
4944
BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4945
.addReg(ptrA).addReg(ptrB);
4949
BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4950
.addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4951
BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4952
.addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4954
BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4955
.addReg(Ptr1Reg).addImm(0).addImm(61);
4957
BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4958
.addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4959
BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4960
.addReg(newval).addReg(ShiftReg);
4961
BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4962
.addReg(oldval).addReg(ShiftReg);
4964
BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4966
BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4967
BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4968
.addReg(Mask3Reg).addImm(65535);
4970
BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4971
.addReg(Mask2Reg).addReg(ShiftReg);
4972
BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
4973
.addReg(NewVal2Reg).addReg(MaskReg);
4974
BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
4975
.addReg(OldVal2Reg).addReg(MaskReg);
4978
BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4979
.addReg(PPC::R0).addReg(PtrReg);
4980
BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
4981
.addReg(TmpDestReg).addReg(MaskReg);
4982
BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
4983
.addReg(TmpReg).addReg(OldVal3Reg);
4984
BuildMI(BB, dl, TII->get(PPC::BCC))
4985
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4986
BB->addSuccessor(loop2MBB);
4987
BB->addSuccessor(midMBB);
4990
BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
4991
.addReg(TmpDestReg).addReg(MaskReg);
4992
BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
4993
.addReg(Tmp2Reg).addReg(NewVal3Reg);
4994
BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4995
.addReg(PPC::R0).addReg(PtrReg);
4996
BuildMI(BB, dl, TII->get(PPC::BCC))
4997
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4998
BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4999
BB->addSuccessor(loop1MBB);
5000
BB->addSuccessor(exitMBB);
5003
BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
5004
.addReg(PPC::R0).addReg(PtrReg);
5005
BB->addSuccessor(exitMBB);
5010
BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
5012
llvm_unreachable("Unexpected instr type to insert");
5015
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
5019
//===----------------------------------------------------------------------===//
5020
// Target Optimization Hooks
5021
//===----------------------------------------------------------------------===//
5023
SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
5024
DAGCombinerInfo &DCI) const {
5025
TargetMachine &TM = getTargetMachine();
5026
SelectionDAG &DAG = DCI.DAG;
5027
DebugLoc dl = N->getDebugLoc();
5028
switch (N->getOpcode()) {
5031
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5032
if (C->getZExtValue() == 0) // 0 << V -> 0.
5033
return N->getOperand(0);
5037
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5038
if (C->getZExtValue() == 0) // 0 >>u V -> 0.
5039
return N->getOperand(0);
5043
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5044
if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
5045
C->isAllOnesValue()) // -1 >>s V -> -1.
5046
return N->getOperand(0);
5050
case ISD::SINT_TO_FP:
5051
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5052
if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5053
// Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5054
// We allow the src/dst to be either f32/f64, but the intermediate
5055
// type must be i64.
5056
if (N->getOperand(0).getValueType() == MVT::i64 &&
5057
N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5058
SDValue Val = N->getOperand(0).getOperand(0);
5059
if (Val.getValueType() == MVT::f32) {
5060
Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5061
DCI.AddToWorklist(Val.getNode());
5064
Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5065
DCI.AddToWorklist(Val.getNode());
5066
Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5067
DCI.AddToWorklist(Val.getNode());
5068
if (N->getValueType(0) == MVT::f32) {
5069
Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5070
DAG.getIntPtrConstant(0));
5071
DCI.AddToWorklist(Val.getNode());
5074
} else if (N->getOperand(0).getValueType() == MVT::i32) {
5075
// If the intermediate type is i32, we can avoid the load/store here
5082
// Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5083
if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5084
!cast<StoreSDNode>(N)->isTruncatingStore() &&
5085
N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5086
N->getOperand(1).getValueType() == MVT::i32 &&
5087
N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5088
SDValue Val = N->getOperand(1).getOperand(0);
5089
if (Val.getValueType() == MVT::f32) {
5090
Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5091
DCI.AddToWorklist(Val.getNode());
5093
Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5094
DCI.AddToWorklist(Val.getNode());
5096
Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5097
N->getOperand(2), N->getOperand(3));
5098
DCI.AddToWorklist(Val.getNode());
5102
// Turn STORE (BSWAP) -> sthbrx/stwbrx.
5103
if (cast<StoreSDNode>(N)->isUnindexed() &&
5104
N->getOperand(1).getOpcode() == ISD::BSWAP &&
5105
N->getOperand(1).getNode()->hasOneUse() &&
5106
(N->getOperand(1).getValueType() == MVT::i32 ||
5107
N->getOperand(1).getValueType() == MVT::i16)) {
5108
SDValue BSwapOp = N->getOperand(1).getOperand(0);
5109
// Do an any-extend to 32-bits if this is a half-word input.
5110
if (BSwapOp.getValueType() == MVT::i16)
5111
BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5114
N->getOperand(0), BSwapOp, N->getOperand(2),
5115
DAG.getValueType(N->getOperand(1).getValueType())
5118
DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5119
Ops, array_lengthof(Ops),
5120
cast<StoreSDNode>(N)->getMemoryVT(),
5121
cast<StoreSDNode>(N)->getMemOperand());
5125
// Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5126
if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5127
N->getOperand(0).hasOneUse() &&
5128
(N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5129
SDValue Load = N->getOperand(0);
5130
LoadSDNode *LD = cast<LoadSDNode>(Load);
5131
// Create the byte-swapping load.
5133
LD->getChain(), // Chain
5134
LD->getBasePtr(), // Ptr
5135
DAG.getValueType(N->getValueType(0)) // VT
5138
DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5139
DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5140
LD->getMemoryVT(), LD->getMemOperand());
5142
// If this is an i16 load, insert the truncate.
5143
SDValue ResVal = BSLoad;
5144
if (N->getValueType(0) == MVT::i16)
5145
ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5147
// First, combine the bswap away. This makes the value produced by the
5149
DCI.CombineTo(N, ResVal);
5151
// Next, combine the load away, we give it a bogus result value but a real
5152
// chain result. The result value is dead because the bswap is dead.
5153
DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5155
// Return N so it doesn't get rechecked!
5156
return SDValue(N, 0);
5160
case PPCISD::VCMP: {
5161
// If a VCMPo node already exists with exactly the same operands as this
5162
// node, use its result instead of this node (VCMPo computes both a CR6 and
5163
// a normal output).
5165
if (!N->getOperand(0).hasOneUse() &&
5166
!N->getOperand(1).hasOneUse() &&
5167
!N->getOperand(2).hasOneUse()) {
5169
// Scan all of the users of the LHS, looking for VCMPo's that match.
5170
SDNode *VCMPoNode = 0;
5172
SDNode *LHSN = N->getOperand(0).getNode();
5173
for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5175
if (UI->getOpcode() == PPCISD::VCMPo &&
5176
UI->getOperand(1) == N->getOperand(1) &&
5177
UI->getOperand(2) == N->getOperand(2) &&
5178
UI->getOperand(0) == N->getOperand(0)) {
5183
// If there is no VCMPo node, or if the flag value has a single use, don't
5185
if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5188
// Look at the (necessarily single) use of the flag value. If it has a
5189
// chain, this transformation is more complex. Note that multiple things
5190
// could use the value result, which we should ignore.
5191
SDNode *FlagUser = 0;
5192
for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5193
FlagUser == 0; ++UI) {
5194
assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5196
for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5197
if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5204
// If the user is a MFCR instruction, we know this is safe. Otherwise we
5205
// give up for right now.
5206
if (FlagUser->getOpcode() == PPCISD::MFCR)
5207
return SDValue(VCMPoNode, 0);
5212
// If this is a branch on an altivec predicate comparison, lower this so
5213
// that we don't have to do a MFCR: instead, branch directly on CR6. This
5214
// lowering is done pre-legalize, because the legalizer lowers the predicate
5215
// compare down to code that is difficult to reassemble.
5216
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5217
SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5221
if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5222
isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5223
getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5224
assert(isDot && "Can't compare against a vector result!");
5226
// If this is a comparison against something other than 0/1, then we know
5227
// that the condition is never/always true.
5228
unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5229
if (Val != 0 && Val != 1) {
5230
if (CC == ISD::SETEQ) // Cond never true, remove branch.
5231
return N->getOperand(0);
5232
// Always !=, turn it into an unconditional branch.
5233
return DAG.getNode(ISD::BR, dl, MVT::Other,
5234
N->getOperand(0), N->getOperand(4));
5237
bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5239
// Create the PPCISD altivec 'dot' comparison node.
5240
std::vector<EVT> VTs;
5242
LHS.getOperand(2), // LHS of compare
5243
LHS.getOperand(3), // RHS of compare
5244
DAG.getConstant(CompareOpc, MVT::i32)
5246
VTs.push_back(LHS.getOperand(2).getValueType());
5247
VTs.push_back(MVT::Flag);
5248
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5250
// Unpack the result based on how the target uses it.
5251
PPC::Predicate CompOpc;
5252
switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5253
default: // Can't happen, don't crash on invalid number though.
5254
case 0: // Branch on the value of the EQ bit of CR6.
5255
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5257
case 1: // Branch on the inverted value of the EQ bit of CR6.
5258
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5260
case 2: // Branch on the value of the LT bit of CR6.
5261
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5263
case 3: // Branch on the inverted value of the LT bit of CR6.
5264
CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5268
return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5269
DAG.getConstant(CompOpc, MVT::i32),
5270
DAG.getRegister(PPC::CR6, MVT::i32),
5271
N->getOperand(4), CompNode.getValue(1));
5280
//===----------------------------------------------------------------------===//
5281
// Inline Assembly Support
5282
//===----------------------------------------------------------------------===//
5284
void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5288
const SelectionDAG &DAG,
5289
unsigned Depth) const {
5290
KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5291
switch (Op.getOpcode()) {
5293
case PPCISD::LBRX: {
5294
// lhbrx is known to have the top bits cleared out.
5295
if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5296
KnownZero = 0xFFFF0000;
5299
case ISD::INTRINSIC_WO_CHAIN: {
5300
switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5302
case Intrinsic::ppc_altivec_vcmpbfp_p:
5303
case Intrinsic::ppc_altivec_vcmpeqfp_p:
5304
case Intrinsic::ppc_altivec_vcmpequb_p:
5305
case Intrinsic::ppc_altivec_vcmpequh_p:
5306
case Intrinsic::ppc_altivec_vcmpequw_p:
5307
case Intrinsic::ppc_altivec_vcmpgefp_p:
5308
case Intrinsic::ppc_altivec_vcmpgtfp_p:
5309
case Intrinsic::ppc_altivec_vcmpgtsb_p:
5310
case Intrinsic::ppc_altivec_vcmpgtsh_p:
5311
case Intrinsic::ppc_altivec_vcmpgtsw_p:
5312
case Intrinsic::ppc_altivec_vcmpgtub_p:
5313
case Intrinsic::ppc_altivec_vcmpgtuh_p:
5314
case Intrinsic::ppc_altivec_vcmpgtuw_p:
5315
KnownZero = ~1U; // All bits but the low one are known to be zero.
5323
/// getConstraintType - Given a constraint, return the type of
5324
/// constraint it is for this target.
5325
PPCTargetLowering::ConstraintType
5326
PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5327
if (Constraint.size() == 1) {
5328
switch (Constraint[0]) {
5335
return C_RegisterClass;
5338
return TargetLowering::getConstraintType(Constraint);
5341
std::pair<unsigned, const TargetRegisterClass*>
5342
PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5344
if (Constraint.size() == 1) {
5345
// GCC RS6000 Constraint Letters
5346
switch (Constraint[0]) {
5349
if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5350
return std::make_pair(0U, PPC::G8RCRegisterClass);
5351
return std::make_pair(0U, PPC::GPRCRegisterClass);
5354
return std::make_pair(0U, PPC::F4RCRegisterClass);
5355
else if (VT == MVT::f64)
5356
return std::make_pair(0U, PPC::F8RCRegisterClass);
5359
return std::make_pair(0U, PPC::VRRCRegisterClass);
5361
return std::make_pair(0U, PPC::CRRCRegisterClass);
5365
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5369
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5370
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
5371
/// it means one of the asm constraint of the inline asm instruction being
5372
/// processed is 'm'.
5373
void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5375
std::vector<SDValue>&Ops,
5376
SelectionDAG &DAG) const {
5377
SDValue Result(0,0);
5388
ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5389
if (!CST) return; // Must be an immediate to match.
5390
unsigned Value = CST->getZExtValue();
5392
default: llvm_unreachable("Unknown constraint letter!");
5393
case 'I': // "I" is a signed 16-bit constant.
5394
if ((short)Value == (int)Value)
5395
Result = DAG.getTargetConstant(Value, Op.getValueType());
5397
case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5398
case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5399
if ((short)Value == 0)
5400
Result = DAG.getTargetConstant(Value, Op.getValueType());
5402
case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5403
if ((Value >> 16) == 0)
5404
Result = DAG.getTargetConstant(Value, Op.getValueType());
5406
case 'M': // "M" is a constant that is greater than 31.
5408
Result = DAG.getTargetConstant(Value, Op.getValueType());
5410
case 'N': // "N" is a positive constant that is an exact power of two.
5411
if ((int)Value > 0 && isPowerOf2_32(Value))
5412
Result = DAG.getTargetConstant(Value, Op.getValueType());
5414
case 'O': // "O" is the constant zero.
5416
Result = DAG.getTargetConstant(Value, Op.getValueType());
5418
case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5419
if ((short)-Value == (int)-Value)
5420
Result = DAG.getTargetConstant(Value, Op.getValueType());
5427
if (Result.getNode()) {
5428
Ops.push_back(Result);
5432
// Handle standard constraint letters.
5433
TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
5436
// isLegalAddressingMode - Return true if the addressing mode represented
5437
// by AM is legal for this target, for a load/store of the specified type.
5438
bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5439
const Type *Ty) const {
5440
// FIXME: PPC does not allow r+i addressing modes for vectors!
5442
// PPC allows a sign-extended 16-bit immediate field.
5443
if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5446
// No global is ever allowed as a base.
5450
// PPC only support r+r,
5452
case 0: // "r+i" or just "i", depending on HasBaseReg.
5455
if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5457
// Otherwise we have r+r or r+i.
5460
if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5462
// Allow 2*r as r+r.
5465
// No other scales are supported.
5472
/// isLegalAddressImmediate - Return true if the integer value can be used
5473
/// as the offset of the target addressing mode for load / store of the
5475
bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5476
// PPC allows a sign-extended 16-bit immediate field.
5477
return (V > -(1 << 16) && V < (1 << 16)-1);
5480
bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5484
SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5485
DebugLoc dl = Op.getDebugLoc();
5486
// Depths > 0 not supported yet!
5487
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5490
MachineFunction &MF = DAG.getMachineFunction();
5491
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5493
// Just load the return address off the stack.
5494
SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5496
// Make sure the function really does not optimize away the store of the RA
5498
FuncInfo->setLRStoreRequired();
5499
return DAG.getLoad(getPointerTy(), dl,
5500
DAG.getEntryNode(), RetAddrFI, NULL, 0,
5504
SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5505
DebugLoc dl = Op.getDebugLoc();
5506
// Depths > 0 not supported yet!
5507
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5510
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5511
bool isPPC64 = PtrVT == MVT::i64;
5513
MachineFunction &MF = DAG.getMachineFunction();
5514
MachineFrameInfo *MFI = MF.getFrameInfo();
5515
bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
5516
&& MFI->getStackSize();
5519
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
5522
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
5527
PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5528
// The PowerPC target isn't yet aware of offsets.
5532
EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
5533
bool isSrcConst, bool isSrcStr,
5534
SelectionDAG &DAG) const {
5535
if (this->PPCSubTarget.isPPC64()) {
added
removed
libclamav/c++/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
