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//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//===----------------------------------------------------------------------===//
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#include "X86InstrInfo.h"
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#include "X86GenInstrInfo.inc"
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#include "X86InstrBuilder.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/LLVMContext.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/MC/MCAsmInfo.h"
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NoFusing("disable-spill-fusing",
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cl::desc("Disable fusing of spill code into instructions"));
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PrintFailedFusing("print-failed-fuse-candidates",
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cl::desc("Print instructions that the allocator wants to"
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" fuse, but the X86 backend currently can't"),
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ReMatPICStubLoad("remat-pic-stub-load",
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cl::desc("Re-materialize load from stub in PIC mode"),
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cl::init(false), cl::Hidden);
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X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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: TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
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TM(tm), RI(tm, *this) {
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SmallVector<unsigned,16> AmbEntries;
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static const unsigned OpTbl2Addr[][2] = {
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{ X86::ADC32ri, X86::ADC32mi },
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{ X86::ADC32ri8, X86::ADC32mi8 },
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{ X86::ADC32rr, X86::ADC32mr },
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{ X86::ADC64ri32, X86::ADC64mi32 },
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{ X86::ADC64ri8, X86::ADC64mi8 },
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{ X86::ADC64rr, X86::ADC64mr },
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{ X86::ADD16ri, X86::ADD16mi },
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{ X86::ADD16ri8, X86::ADD16mi8 },
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{ X86::ADD16rr, X86::ADD16mr },
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{ X86::ADD32ri, X86::ADD32mi },
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{ X86::ADD32ri8, X86::ADD32mi8 },
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{ X86::ADD32rr, X86::ADD32mr },
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{ X86::ADD64ri32, X86::ADD64mi32 },
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{ X86::ADD64ri8, X86::ADD64mi8 },
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{ X86::ADD64rr, X86::ADD64mr },
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{ X86::ADD8ri, X86::ADD8mi },
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{ X86::ADD8rr, X86::ADD8mr },
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{ X86::AND16ri, X86::AND16mi },
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{ X86::AND16ri8, X86::AND16mi8 },
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{ X86::AND16rr, X86::AND16mr },
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{ X86::AND32ri, X86::AND32mi },
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{ X86::AND32ri8, X86::AND32mi8 },
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{ X86::AND32rr, X86::AND32mr },
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{ X86::AND64ri32, X86::AND64mi32 },
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{ X86::AND64ri8, X86::AND64mi8 },
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{ X86::AND64rr, X86::AND64mr },
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{ X86::AND8ri, X86::AND8mi },
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{ X86::AND8rr, X86::AND8mr },
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{ X86::DEC16r, X86::DEC16m },
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{ X86::DEC32r, X86::DEC32m },
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{ X86::DEC64_16r, X86::DEC64_16m },
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{ X86::DEC64_32r, X86::DEC64_32m },
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{ X86::DEC64r, X86::DEC64m },
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{ X86::DEC8r, X86::DEC8m },
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{ X86::INC16r, X86::INC16m },
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{ X86::INC32r, X86::INC32m },
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{ X86::INC64_16r, X86::INC64_16m },
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{ X86::INC64_32r, X86::INC64_32m },
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{ X86::INC64r, X86::INC64m },
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{ X86::INC8r, X86::INC8m },
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{ X86::NEG16r, X86::NEG16m },
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{ X86::NEG32r, X86::NEG32m },
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{ X86::NEG64r, X86::NEG64m },
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{ X86::NEG8r, X86::NEG8m },
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{ X86::NOT16r, X86::NOT16m },
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{ X86::NOT32r, X86::NOT32m },
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{ X86::NOT64r, X86::NOT64m },
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{ X86::NOT8r, X86::NOT8m },
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{ X86::OR16ri, X86::OR16mi },
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{ X86::OR16ri8, X86::OR16mi8 },
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{ X86::OR16rr, X86::OR16mr },
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{ X86::OR32ri, X86::OR32mi },
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{ X86::OR32ri8, X86::OR32mi8 },
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{ X86::OR32rr, X86::OR32mr },
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{ X86::OR64ri32, X86::OR64mi32 },
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{ X86::OR64ri8, X86::OR64mi8 },
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{ X86::OR64rr, X86::OR64mr },
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{ X86::OR8ri, X86::OR8mi },
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{ X86::OR8rr, X86::OR8mr },
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{ X86::ROL16r1, X86::ROL16m1 },
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{ X86::ROL16rCL, X86::ROL16mCL },
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{ X86::ROL16ri, X86::ROL16mi },
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{ X86::ROL32r1, X86::ROL32m1 },
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{ X86::ROL32rCL, X86::ROL32mCL },
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{ X86::ROL32ri, X86::ROL32mi },
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{ X86::ROL64r1, X86::ROL64m1 },
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{ X86::ROL64rCL, X86::ROL64mCL },
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{ X86::ROL64ri, X86::ROL64mi },
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{ X86::ROL8r1, X86::ROL8m1 },
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{ X86::ROL8rCL, X86::ROL8mCL },
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{ X86::ROL8ri, X86::ROL8mi },
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{ X86::ROR16r1, X86::ROR16m1 },
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{ X86::ROR16rCL, X86::ROR16mCL },
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{ X86::ROR16ri, X86::ROR16mi },
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{ X86::ROR32r1, X86::ROR32m1 },
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{ X86::ROR32rCL, X86::ROR32mCL },
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{ X86::ROR32ri, X86::ROR32mi },
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{ X86::ROR64r1, X86::ROR64m1 },
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{ X86::ROR64rCL, X86::ROR64mCL },
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{ X86::ROR64ri, X86::ROR64mi },
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{ X86::ROR8r1, X86::ROR8m1 },
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{ X86::ROR8rCL, X86::ROR8mCL },
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{ X86::ROR8ri, X86::ROR8mi },
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{ X86::SAR16r1, X86::SAR16m1 },
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{ X86::SAR16rCL, X86::SAR16mCL },
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{ X86::SAR16ri, X86::SAR16mi },
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{ X86::SAR32r1, X86::SAR32m1 },
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{ X86::SAR32rCL, X86::SAR32mCL },
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{ X86::SAR32ri, X86::SAR32mi },
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{ X86::SAR64r1, X86::SAR64m1 },
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{ X86::SAR64rCL, X86::SAR64mCL },
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{ X86::SAR64ri, X86::SAR64mi },
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{ X86::SAR8r1, X86::SAR8m1 },
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{ X86::SAR8rCL, X86::SAR8mCL },
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{ X86::SAR8ri, X86::SAR8mi },
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{ X86::SBB32ri, X86::SBB32mi },
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{ X86::SBB32ri8, X86::SBB32mi8 },
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{ X86::SBB32rr, X86::SBB32mr },
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{ X86::SBB64ri32, X86::SBB64mi32 },
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{ X86::SBB64ri8, X86::SBB64mi8 },
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{ X86::SBB64rr, X86::SBB64mr },
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{ X86::SHL16rCL, X86::SHL16mCL },
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{ X86::SHL16ri, X86::SHL16mi },
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{ X86::SHL32rCL, X86::SHL32mCL },
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{ X86::SHL32ri, X86::SHL32mi },
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{ X86::SHL64rCL, X86::SHL64mCL },
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{ X86::SHL64ri, X86::SHL64mi },
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{ X86::SHL8rCL, X86::SHL8mCL },
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{ X86::SHL8ri, X86::SHL8mi },
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{ X86::SHLD16rrCL, X86::SHLD16mrCL },
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{ X86::SHLD16rri8, X86::SHLD16mri8 },
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{ X86::SHLD32rrCL, X86::SHLD32mrCL },
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{ X86::SHLD32rri8, X86::SHLD32mri8 },
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{ X86::SHLD64rrCL, X86::SHLD64mrCL },
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{ X86::SHLD64rri8, X86::SHLD64mri8 },
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{ X86::SHR16r1, X86::SHR16m1 },
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{ X86::SHR16rCL, X86::SHR16mCL },
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{ X86::SHR16ri, X86::SHR16mi },
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{ X86::SHR32r1, X86::SHR32m1 },
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{ X86::SHR32rCL, X86::SHR32mCL },
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{ X86::SHR32ri, X86::SHR32mi },
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{ X86::SHR64r1, X86::SHR64m1 },
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{ X86::SHR64rCL, X86::SHR64mCL },
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{ X86::SHR64ri, X86::SHR64mi },
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{ X86::SHR8r1, X86::SHR8m1 },
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{ X86::SHR8rCL, X86::SHR8mCL },
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{ X86::SHR8ri, X86::SHR8mi },
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{ X86::SHRD16rrCL, X86::SHRD16mrCL },
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{ X86::SHRD16rri8, X86::SHRD16mri8 },
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{ X86::SHRD32rrCL, X86::SHRD32mrCL },
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{ X86::SHRD32rri8, X86::SHRD32mri8 },
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{ X86::SHRD64rrCL, X86::SHRD64mrCL },
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{ X86::SHRD64rri8, X86::SHRD64mri8 },
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{ X86::SUB16ri, X86::SUB16mi },
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{ X86::SUB16ri8, X86::SUB16mi8 },
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{ X86::SUB16rr, X86::SUB16mr },
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{ X86::SUB32ri, X86::SUB32mi },
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{ X86::SUB32ri8, X86::SUB32mi8 },
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{ X86::SUB32rr, X86::SUB32mr },
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{ X86::SUB64ri32, X86::SUB64mi32 },
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{ X86::SUB64ri8, X86::SUB64mi8 },
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{ X86::SUB64rr, X86::SUB64mr },
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{ X86::SUB8ri, X86::SUB8mi },
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{ X86::SUB8rr, X86::SUB8mr },
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{ X86::XOR16ri, X86::XOR16mi },
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{ X86::XOR16ri8, X86::XOR16mi8 },
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{ X86::XOR16rr, X86::XOR16mr },
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{ X86::XOR32ri, X86::XOR32mi },
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{ X86::XOR32ri8, X86::XOR32mi8 },
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{ X86::XOR32rr, X86::XOR32mr },
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{ X86::XOR64ri32, X86::XOR64mi32 },
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{ X86::XOR64ri8, X86::XOR64mi8 },
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{ X86::XOR64rr, X86::XOR64mr },
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{ X86::XOR8ri, X86::XOR8mi },
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{ X86::XOR8rr, X86::XOR8mr }
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for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
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unsigned RegOp = OpTbl2Addr[i][0];
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unsigned MemOp = OpTbl2Addr[i][1];
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if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
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std::make_pair(MemOp,0))).second)
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assert(false && "Duplicated entries?");
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// Index 0, folded load and store, no alignment requirement.
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unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
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if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
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std::make_pair(RegOp,
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AmbEntries.push_back(MemOp);
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// If the third value is 1, then it's folding either a load or a store.
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static const unsigned OpTbl0[][4] = {
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{ X86::BT16ri8, X86::BT16mi8, 1, 0 },
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{ X86::BT32ri8, X86::BT32mi8, 1, 0 },
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{ X86::BT64ri8, X86::BT64mi8, 1, 0 },
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{ X86::CALL32r, X86::CALL32m, 1, 0 },
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{ X86::CALL64r, X86::CALL64m, 1, 0 },
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{ X86::CMP16ri, X86::CMP16mi, 1, 0 },
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{ X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
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{ X86::CMP16rr, X86::CMP16mr, 1, 0 },
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{ X86::CMP32ri, X86::CMP32mi, 1, 0 },
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{ X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
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{ X86::CMP32rr, X86::CMP32mr, 1, 0 },
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{ X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
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{ X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
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{ X86::CMP64rr, X86::CMP64mr, 1, 0 },
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{ X86::CMP8ri, X86::CMP8mi, 1, 0 },
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{ X86::CMP8rr, X86::CMP8mr, 1, 0 },
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{ X86::DIV16r, X86::DIV16m, 1, 0 },
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{ X86::DIV32r, X86::DIV32m, 1, 0 },
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{ X86::DIV64r, X86::DIV64m, 1, 0 },
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{ X86::DIV8r, X86::DIV8m, 1, 0 },
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{ X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
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{ X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
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{ X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
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{ X86::IDIV16r, X86::IDIV16m, 1, 0 },
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{ X86::IDIV32r, X86::IDIV32m, 1, 0 },
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{ X86::IDIV64r, X86::IDIV64m, 1, 0 },
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{ X86::IDIV8r, X86::IDIV8m, 1, 0 },
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{ X86::IMUL16r, X86::IMUL16m, 1, 0 },
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{ X86::IMUL32r, X86::IMUL32m, 1, 0 },
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{ X86::IMUL64r, X86::IMUL64m, 1, 0 },
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{ X86::IMUL8r, X86::IMUL8m, 1, 0 },
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{ X86::JMP32r, X86::JMP32m, 1, 0 },
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{ X86::JMP64r, X86::JMP64m, 1, 0 },
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{ X86::MOV16ri, X86::MOV16mi, 0, 0 },
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{ X86::MOV16rr, X86::MOV16mr, 0, 0 },
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{ X86::MOV32ri, X86::MOV32mi, 0, 0 },
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{ X86::MOV32rr, X86::MOV32mr, 0, 0 },
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{ X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
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{ X86::MOV64rr, X86::MOV64mr, 0, 0 },
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{ X86::MOV8ri, X86::MOV8mi, 0, 0 },
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{ X86::MOV8rr, X86::MOV8mr, 0, 0 },
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{ X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
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{ X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
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{ X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
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{ X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
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{ X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
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{ X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
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{ X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
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{ X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
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{ X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
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{ X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
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{ X86::MUL16r, X86::MUL16m, 1, 0 },
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{ X86::MUL32r, X86::MUL32m, 1, 0 },
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{ X86::MUL64r, X86::MUL64m, 1, 0 },
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{ X86::MUL8r, X86::MUL8m, 1, 0 },
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{ X86::SETAEr, X86::SETAEm, 0, 0 },
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{ X86::SETAr, X86::SETAm, 0, 0 },
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{ X86::SETBEr, X86::SETBEm, 0, 0 },
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{ X86::SETBr, X86::SETBm, 0, 0 },
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{ X86::SETEr, X86::SETEm, 0, 0 },
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{ X86::SETGEr, X86::SETGEm, 0, 0 },
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{ X86::SETGr, X86::SETGm, 0, 0 },
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{ X86::SETLEr, X86::SETLEm, 0, 0 },
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{ X86::SETLr, X86::SETLm, 0, 0 },
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{ X86::SETNEr, X86::SETNEm, 0, 0 },
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{ X86::SETNOr, X86::SETNOm, 0, 0 },
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{ X86::SETNPr, X86::SETNPm, 0, 0 },
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{ X86::SETNSr, X86::SETNSm, 0, 0 },
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{ X86::SETOr, X86::SETOm, 0, 0 },
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{ X86::SETPr, X86::SETPm, 0, 0 },
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{ X86::SETSr, X86::SETSm, 0, 0 },
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{ X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
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{ X86::TEST16ri, X86::TEST16mi, 1, 0 },
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{ X86::TEST32ri, X86::TEST32mi, 1, 0 },
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{ X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
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{ X86::TEST8ri, X86::TEST8mi, 1, 0 }
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for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
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unsigned RegOp = OpTbl0[i][0];
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unsigned MemOp = OpTbl0[i][1];
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unsigned Align = OpTbl0[i][3];
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if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
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std::make_pair(MemOp,Align))).second)
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assert(false && "Duplicated entries?");
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unsigned FoldedLoad = OpTbl0[i][2];
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// Index 0, folded load or store.
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unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
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if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
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if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
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std::make_pair(RegOp, AuxInfo))).second)
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AmbEntries.push_back(MemOp);
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static const unsigned OpTbl1[][3] = {
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{ X86::CMP16rr, X86::CMP16rm, 0 },
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{ X86::CMP32rr, X86::CMP32rm, 0 },
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{ X86::CMP64rr, X86::CMP64rm, 0 },
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{ X86::CMP8rr, X86::CMP8rm, 0 },
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{ X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
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{ X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
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{ X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
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{ X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
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{ X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
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{ X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
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{ X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
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{ X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
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{ X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
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{ X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
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{ X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
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{ X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
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{ X86::IMUL16rri, X86::IMUL16rmi, 0 },
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{ X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
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{ X86::IMUL32rri, X86::IMUL32rmi, 0 },
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{ X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
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{ X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
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{ X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
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{ X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
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{ X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
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{ X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
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{ X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
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{ X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
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{ X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
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{ X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
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{ X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
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{ X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
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{ X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
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{ X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
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{ X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
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{ X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
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{ X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
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{ X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
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{ X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
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{ X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
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{ X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
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{ X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
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{ X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
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{ X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
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{ X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
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{ X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
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{ X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
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{ X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
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{ X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
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{ X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
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{ X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
377
{ X86::MOV16rr, X86::MOV16rm, 0 },
378
{ X86::MOV32rr, X86::MOV32rm, 0 },
379
{ X86::MOV64rr, X86::MOV64rm, 0 },
380
{ X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
381
{ X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
382
{ X86::MOV8rr, X86::MOV8rm, 0 },
383
{ X86::MOVAPDrr, X86::MOVAPDrm, 16 },
384
{ X86::MOVAPSrr, X86::MOVAPSrm, 16 },
385
{ X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
386
{ X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
387
{ X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
388
{ X86::MOVDQArr, X86::MOVDQArm, 16 },
389
{ X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
390
{ X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
391
{ X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
392
{ X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
393
{ X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
394
{ X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
395
{ X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
396
{ X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
397
{ X86::MOVUPDrr, X86::MOVUPDrm, 16 },
398
{ X86::MOVUPSrr, X86::MOVUPSrm, 0 },
399
{ X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
400
{ X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
401
{ X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
402
{ X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
403
{ X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
404
{ X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
405
{ X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
406
{ X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
407
{ X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
408
{ X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
409
{ X86::PSHUFDri, X86::PSHUFDmi, 16 },
410
{ X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
411
{ X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
412
{ X86::RCPPSr, X86::RCPPSm, 16 },
413
{ X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
414
{ X86::RSQRTPSr, X86::RSQRTPSm, 16 },
415
{ X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
416
{ X86::RSQRTSSr, X86::RSQRTSSm, 0 },
417
{ X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
418
{ X86::SQRTPDr, X86::SQRTPDm, 16 },
419
{ X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
420
{ X86::SQRTPSr, X86::SQRTPSm, 16 },
421
{ X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
422
{ X86::SQRTSDr, X86::SQRTSDm, 0 },
423
{ X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
424
{ X86::SQRTSSr, X86::SQRTSSm, 0 },
425
{ X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
426
{ X86::TEST16rr, X86::TEST16rm, 0 },
427
{ X86::TEST32rr, X86::TEST32rm, 0 },
428
{ X86::TEST64rr, X86::TEST64rm, 0 },
429
{ X86::TEST8rr, X86::TEST8rm, 0 },
430
// FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
431
{ X86::UCOMISDrr, X86::UCOMISDrm, 0 },
432
{ X86::UCOMISSrr, X86::UCOMISSrm, 0 }
435
for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
436
unsigned RegOp = OpTbl1[i][0];
437
unsigned MemOp = OpTbl1[i][1];
438
unsigned Align = OpTbl1[i][2];
439
if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
440
std::make_pair(MemOp,Align))).second)
441
assert(false && "Duplicated entries?");
442
// Index 1, folded load
443
unsigned AuxInfo = 1 | (1 << 4);
444
if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
445
if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
446
std::make_pair(RegOp, AuxInfo))).second)
447
AmbEntries.push_back(MemOp);
450
static const unsigned OpTbl2[][3] = {
451
{ X86::ADC32rr, X86::ADC32rm, 0 },
452
{ X86::ADC64rr, X86::ADC64rm, 0 },
453
{ X86::ADD16rr, X86::ADD16rm, 0 },
454
{ X86::ADD32rr, X86::ADD32rm, 0 },
455
{ X86::ADD64rr, X86::ADD64rm, 0 },
456
{ X86::ADD8rr, X86::ADD8rm, 0 },
457
{ X86::ADDPDrr, X86::ADDPDrm, 16 },
458
{ X86::ADDPSrr, X86::ADDPSrm, 16 },
459
{ X86::ADDSDrr, X86::ADDSDrm, 0 },
460
{ X86::ADDSSrr, X86::ADDSSrm, 0 },
461
{ X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
462
{ X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
463
{ X86::AND16rr, X86::AND16rm, 0 },
464
{ X86::AND32rr, X86::AND32rm, 0 },
465
{ X86::AND64rr, X86::AND64rm, 0 },
466
{ X86::AND8rr, X86::AND8rm, 0 },
467
{ X86::ANDNPDrr, X86::ANDNPDrm, 16 },
468
{ X86::ANDNPSrr, X86::ANDNPSrm, 16 },
469
{ X86::ANDPDrr, X86::ANDPDrm, 16 },
470
{ X86::ANDPSrr, X86::ANDPSrm, 16 },
471
{ X86::CMOVA16rr, X86::CMOVA16rm, 0 },
472
{ X86::CMOVA32rr, X86::CMOVA32rm, 0 },
473
{ X86::CMOVA64rr, X86::CMOVA64rm, 0 },
474
{ X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
475
{ X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
476
{ X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
477
{ X86::CMOVB16rr, X86::CMOVB16rm, 0 },
478
{ X86::CMOVB32rr, X86::CMOVB32rm, 0 },
479
{ X86::CMOVB64rr, X86::CMOVB64rm, 0 },
480
{ X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
481
{ X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
482
{ X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
483
{ X86::CMOVE16rr, X86::CMOVE16rm, 0 },
484
{ X86::CMOVE32rr, X86::CMOVE32rm, 0 },
485
{ X86::CMOVE64rr, X86::CMOVE64rm, 0 },
486
{ X86::CMOVG16rr, X86::CMOVG16rm, 0 },
487
{ X86::CMOVG32rr, X86::CMOVG32rm, 0 },
488
{ X86::CMOVG64rr, X86::CMOVG64rm, 0 },
489
{ X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
490
{ X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
491
{ X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
492
{ X86::CMOVL16rr, X86::CMOVL16rm, 0 },
493
{ X86::CMOVL32rr, X86::CMOVL32rm, 0 },
494
{ X86::CMOVL64rr, X86::CMOVL64rm, 0 },
495
{ X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
496
{ X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
497
{ X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
498
{ X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
499
{ X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
500
{ X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
501
{ X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
502
{ X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
503
{ X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
504
{ X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
505
{ X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
506
{ X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
507
{ X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
508
{ X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
509
{ X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
510
{ X86::CMOVO16rr, X86::CMOVO16rm, 0 },
511
{ X86::CMOVO32rr, X86::CMOVO32rm, 0 },
512
{ X86::CMOVO64rr, X86::CMOVO64rm, 0 },
513
{ X86::CMOVP16rr, X86::CMOVP16rm, 0 },
514
{ X86::CMOVP32rr, X86::CMOVP32rm, 0 },
515
{ X86::CMOVP64rr, X86::CMOVP64rm, 0 },
516
{ X86::CMOVS16rr, X86::CMOVS16rm, 0 },
517
{ X86::CMOVS32rr, X86::CMOVS32rm, 0 },
518
{ X86::CMOVS64rr, X86::CMOVS64rm, 0 },
519
{ X86::CMPPDrri, X86::CMPPDrmi, 16 },
520
{ X86::CMPPSrri, X86::CMPPSrmi, 16 },
521
{ X86::CMPSDrr, X86::CMPSDrm, 0 },
522
{ X86::CMPSSrr, X86::CMPSSrm, 0 },
523
{ X86::DIVPDrr, X86::DIVPDrm, 16 },
524
{ X86::DIVPSrr, X86::DIVPSrm, 16 },
525
{ X86::DIVSDrr, X86::DIVSDrm, 0 },
526
{ X86::DIVSSrr, X86::DIVSSrm, 0 },
527
{ X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
528
{ X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
529
{ X86::FsANDPDrr, X86::FsANDPDrm, 16 },
530
{ X86::FsANDPSrr, X86::FsANDPSrm, 16 },
531
{ X86::FsORPDrr, X86::FsORPDrm, 16 },
532
{ X86::FsORPSrr, X86::FsORPSrm, 16 },
533
{ X86::FsXORPDrr, X86::FsXORPDrm, 16 },
534
{ X86::FsXORPSrr, X86::FsXORPSrm, 16 },
535
{ X86::HADDPDrr, X86::HADDPDrm, 16 },
536
{ X86::HADDPSrr, X86::HADDPSrm, 16 },
537
{ X86::HSUBPDrr, X86::HSUBPDrm, 16 },
538
{ X86::HSUBPSrr, X86::HSUBPSrm, 16 },
539
{ X86::IMUL16rr, X86::IMUL16rm, 0 },
540
{ X86::IMUL32rr, X86::IMUL32rm, 0 },
541
{ X86::IMUL64rr, X86::IMUL64rm, 0 },
542
{ X86::MAXPDrr, X86::MAXPDrm, 16 },
543
{ X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
544
{ X86::MAXPSrr, X86::MAXPSrm, 16 },
545
{ X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
546
{ X86::MAXSDrr, X86::MAXSDrm, 0 },
547
{ X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
548
{ X86::MAXSSrr, X86::MAXSSrm, 0 },
549
{ X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
550
{ X86::MINPDrr, X86::MINPDrm, 16 },
551
{ X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
552
{ X86::MINPSrr, X86::MINPSrm, 16 },
553
{ X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
554
{ X86::MINSDrr, X86::MINSDrm, 0 },
555
{ X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
556
{ X86::MINSSrr, X86::MINSSrm, 0 },
557
{ X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
558
{ X86::MULPDrr, X86::MULPDrm, 16 },
559
{ X86::MULPSrr, X86::MULPSrm, 16 },
560
{ X86::MULSDrr, X86::MULSDrm, 0 },
561
{ X86::MULSSrr, X86::MULSSrm, 0 },
562
{ X86::OR16rr, X86::OR16rm, 0 },
563
{ X86::OR32rr, X86::OR32rm, 0 },
564
{ X86::OR64rr, X86::OR64rm, 0 },
565
{ X86::OR8rr, X86::OR8rm, 0 },
566
{ X86::ORPDrr, X86::ORPDrm, 16 },
567
{ X86::ORPSrr, X86::ORPSrm, 16 },
568
{ X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
569
{ X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
570
{ X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
571
{ X86::PADDBrr, X86::PADDBrm, 16 },
572
{ X86::PADDDrr, X86::PADDDrm, 16 },
573
{ X86::PADDQrr, X86::PADDQrm, 16 },
574
{ X86::PADDSBrr, X86::PADDSBrm, 16 },
575
{ X86::PADDSWrr, X86::PADDSWrm, 16 },
576
{ X86::PADDWrr, X86::PADDWrm, 16 },
577
{ X86::PANDNrr, X86::PANDNrm, 16 },
578
{ X86::PANDrr, X86::PANDrm, 16 },
579
{ X86::PAVGBrr, X86::PAVGBrm, 16 },
580
{ X86::PAVGWrr, X86::PAVGWrm, 16 },
581
{ X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
582
{ X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
583
{ X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
584
{ X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
585
{ X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
586
{ X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
587
{ X86::PINSRWrri, X86::PINSRWrmi, 16 },
588
{ X86::PMADDWDrr, X86::PMADDWDrm, 16 },
589
{ X86::PMAXSWrr, X86::PMAXSWrm, 16 },
590
{ X86::PMAXUBrr, X86::PMAXUBrm, 16 },
591
{ X86::PMINSWrr, X86::PMINSWrm, 16 },
592
{ X86::PMINUBrr, X86::PMINUBrm, 16 },
593
{ X86::PMULDQrr, X86::PMULDQrm, 16 },
594
{ X86::PMULHUWrr, X86::PMULHUWrm, 16 },
595
{ X86::PMULHWrr, X86::PMULHWrm, 16 },
596
{ X86::PMULLDrr, X86::PMULLDrm, 16 },
597
{ X86::PMULLDrr_int, X86::PMULLDrm_int, 16 },
598
{ X86::PMULLWrr, X86::PMULLWrm, 16 },
599
{ X86::PMULUDQrr, X86::PMULUDQrm, 16 },
600
{ X86::PORrr, X86::PORrm, 16 },
601
{ X86::PSADBWrr, X86::PSADBWrm, 16 },
602
{ X86::PSLLDrr, X86::PSLLDrm, 16 },
603
{ X86::PSLLQrr, X86::PSLLQrm, 16 },
604
{ X86::PSLLWrr, X86::PSLLWrm, 16 },
605
{ X86::PSRADrr, X86::PSRADrm, 16 },
606
{ X86::PSRAWrr, X86::PSRAWrm, 16 },
607
{ X86::PSRLDrr, X86::PSRLDrm, 16 },
608
{ X86::PSRLQrr, X86::PSRLQrm, 16 },
609
{ X86::PSRLWrr, X86::PSRLWrm, 16 },
610
{ X86::PSUBBrr, X86::PSUBBrm, 16 },
611
{ X86::PSUBDrr, X86::PSUBDrm, 16 },
612
{ X86::PSUBSBrr, X86::PSUBSBrm, 16 },
613
{ X86::PSUBSWrr, X86::PSUBSWrm, 16 },
614
{ X86::PSUBWrr, X86::PSUBWrm, 16 },
615
{ X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
616
{ X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
617
{ X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
618
{ X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
619
{ X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
620
{ X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
621
{ X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
622
{ X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
623
{ X86::PXORrr, X86::PXORrm, 16 },
624
{ X86::SBB32rr, X86::SBB32rm, 0 },
625
{ X86::SBB64rr, X86::SBB64rm, 0 },
626
{ X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
627
{ X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
628
{ X86::SUB16rr, X86::SUB16rm, 0 },
629
{ X86::SUB32rr, X86::SUB32rm, 0 },
630
{ X86::SUB64rr, X86::SUB64rm, 0 },
631
{ X86::SUB8rr, X86::SUB8rm, 0 },
632
{ X86::SUBPDrr, X86::SUBPDrm, 16 },
633
{ X86::SUBPSrr, X86::SUBPSrm, 16 },
634
{ X86::SUBSDrr, X86::SUBSDrm, 0 },
635
{ X86::SUBSSrr, X86::SUBSSrm, 0 },
636
// FIXME: TEST*rr -> swapped operand of TEST*mr.
637
{ X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
638
{ X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
639
{ X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
640
{ X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
641
{ X86::XOR16rr, X86::XOR16rm, 0 },
642
{ X86::XOR32rr, X86::XOR32rm, 0 },
643
{ X86::XOR64rr, X86::XOR64rm, 0 },
644
{ X86::XOR8rr, X86::XOR8rm, 0 },
645
{ X86::XORPDrr, X86::XORPDrm, 16 },
646
{ X86::XORPSrr, X86::XORPSrm, 16 }
649
for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
650
unsigned RegOp = OpTbl2[i][0];
651
unsigned MemOp = OpTbl2[i][1];
652
unsigned Align = OpTbl2[i][2];
653
if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
654
std::make_pair(MemOp,Align))).second)
655
assert(false && "Duplicated entries?");
656
// Index 2, folded load
657
unsigned AuxInfo = 2 | (1 << 4);
658
if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
659
std::make_pair(RegOp, AuxInfo))).second)
660
AmbEntries.push_back(MemOp);
663
// Remove ambiguous entries.
664
assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
667
bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
668
unsigned &SrcReg, unsigned &DstReg,
669
unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
670
switch (MI.getOpcode()) {
674
case X86::MOV8rr_NOREX:
679
// FP Stack register class copies
680
case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
681
case X86::MOV_Fp3264: case X86::MOV_Fp3280:
682
case X86::MOV_Fp6432: case X86::MOV_Fp8032:
684
// Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64
685
// copies are done with FsMOVAPSrr and FsMOVAPDrr.
687
case X86::FsMOVAPSrr:
688
case X86::FsMOVAPDrr:
692
case X86::MMX_MOVQ64rr:
693
assert(MI.getNumOperands() >= 2 &&
694
MI.getOperand(0).isReg() &&
695
MI.getOperand(1).isReg() &&
696
"invalid register-register move instruction");
697
SrcReg = MI.getOperand(1).getReg();
698
DstReg = MI.getOperand(0).getReg();
699
SrcSubIdx = MI.getOperand(1).getSubReg();
700
DstSubIdx = MI.getOperand(0).getSubReg();
706
X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
707
unsigned &SrcReg, unsigned &DstReg,
708
unsigned &SubIdx) const {
709
switch (MI.getOpcode()) {
711
case X86::MOVSX16rr8:
712
case X86::MOVZX16rr8:
713
case X86::MOVSX32rr8:
714
case X86::MOVZX32rr8:
715
case X86::MOVSX64rr8:
716
case X86::MOVZX64rr8:
717
if (!TM.getSubtarget<X86Subtarget>().is64Bit())
718
// It's not always legal to reference the low 8-bit of the larger
719
// register in 32-bit mode.
721
case X86::MOVSX32rr16:
722
case X86::MOVZX32rr16:
723
case X86::MOVSX64rr16:
724
case X86::MOVZX64rr16:
725
case X86::MOVSX64rr32:
726
case X86::MOVZX64rr32: {
727
if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
730
SrcReg = MI.getOperand(1).getReg();
731
DstReg = MI.getOperand(0).getReg();
732
switch (MI.getOpcode()) {
736
case X86::MOVSX16rr8:
737
case X86::MOVZX16rr8:
738
case X86::MOVSX32rr8:
739
case X86::MOVZX32rr8:
740
case X86::MOVSX64rr8:
741
case X86::MOVZX64rr8:
744
case X86::MOVSX32rr16:
745
case X86::MOVZX32rr16:
746
case X86::MOVSX64rr16:
747
case X86::MOVZX64rr16:
750
case X86::MOVSX64rr32:
751
case X86::MOVZX64rr32:
761
/// isFrameOperand - Return true and the FrameIndex if the specified
762
/// operand and follow operands form a reference to the stack frame.
763
bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
764
int &FrameIndex) const {
765
if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
766
MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
767
MI->getOperand(Op+1).getImm() == 1 &&
768
MI->getOperand(Op+2).getReg() == 0 &&
769
MI->getOperand(Op+3).getImm() == 0) {
770
FrameIndex = MI->getOperand(Op).getIndex();
776
static bool isFrameLoadOpcode(int Opcode) {
789
case X86::MMX_MOVD64rm:
790
case X86::MMX_MOVQ64rm:
797
static bool isFrameStoreOpcode(int Opcode) {
810
case X86::MMX_MOVD64mr:
811
case X86::MMX_MOVQ64mr:
812
case X86::MMX_MOVNTQmr:
818
unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
819
int &FrameIndex) const {
820
if (isFrameLoadOpcode(MI->getOpcode()))
821
if (isFrameOperand(MI, 1, FrameIndex))
822
return MI->getOperand(0).getReg();
826
unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
827
int &FrameIndex) const {
828
if (isFrameLoadOpcode(MI->getOpcode())) {
830
if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
832
// Check for post-frame index elimination operations
833
const MachineMemOperand *Dummy;
834
return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
839
bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
840
const MachineMemOperand *&MMO,
841
int &FrameIndex) const {
842
for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
843
oe = MI->memoperands_end();
846
if ((*o)->isLoad() && (*o)->getValue())
847
if (const FixedStackPseudoSourceValue *Value =
848
dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
849
FrameIndex = Value->getFrameIndex();
857
unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
858
int &FrameIndex) const {
859
if (isFrameStoreOpcode(MI->getOpcode()))
860
if (isFrameOperand(MI, 0, FrameIndex))
861
return MI->getOperand(X86AddrNumOperands).getReg();
865
unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
866
int &FrameIndex) const {
867
if (isFrameStoreOpcode(MI->getOpcode())) {
869
if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
871
// Check for post-frame index elimination operations
872
const MachineMemOperand *Dummy;
873
return hasStoreToStackSlot(MI, Dummy, FrameIndex);
878
bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
879
const MachineMemOperand *&MMO,
880
int &FrameIndex) const {
881
for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
882
oe = MI->memoperands_end();
885
if ((*o)->isStore() && (*o)->getValue())
886
if (const FixedStackPseudoSourceValue *Value =
887
dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
888
FrameIndex = Value->getFrameIndex();
896
/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
898
static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
899
bool isPICBase = false;
900
for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
901
E = MRI.def_end(); I != E; ++I) {
902
MachineInstr *DefMI = I.getOperand().getParent();
903
if (DefMI->getOpcode() != X86::MOVPC32r)
905
assert(!isPICBase && "More than one PIC base?");
912
X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
913
AliasAnalysis *AA) const {
914
switch (MI->getOpcode()) {
925
case X86::MOVUPSrm_Int:
928
case X86::MMX_MOVD64rm:
929
case X86::MMX_MOVQ64rm:
930
case X86::FsMOVAPSrm:
931
case X86::FsMOVAPDrm: {
932
// Loads from constant pools are trivially rematerializable.
933
if (MI->getOperand(1).isReg() &&
934
MI->getOperand(2).isImm() &&
935
MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
936
MI->isInvariantLoad(AA)) {
937
unsigned BaseReg = MI->getOperand(1).getReg();
938
if (BaseReg == 0 || BaseReg == X86::RIP)
940
// Allow re-materialization of PIC load.
941
if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
943
const MachineFunction &MF = *MI->getParent()->getParent();
944
const MachineRegisterInfo &MRI = MF.getRegInfo();
945
bool isPICBase = false;
946
for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
947
E = MRI.def_end(); I != E; ++I) {
948
MachineInstr *DefMI = I.getOperand().getParent();
949
if (DefMI->getOpcode() != X86::MOVPC32r)
951
assert(!isPICBase && "More than one PIC base?");
961
if (MI->getOperand(2).isImm() &&
962
MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
963
!MI->getOperand(4).isReg()) {
964
// lea fi#, lea GV, etc. are all rematerializable.
965
if (!MI->getOperand(1).isReg())
967
unsigned BaseReg = MI->getOperand(1).getReg();
970
// Allow re-materialization of lea PICBase + x.
971
const MachineFunction &MF = *MI->getParent()->getParent();
972
const MachineRegisterInfo &MRI = MF.getRegInfo();
973
return regIsPICBase(BaseReg, MRI);
979
// All other instructions marked M_REMATERIALIZABLE are always trivially
984
/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
985
/// would clobber the EFLAGS condition register. Note the result may be
986
/// conservative. If it cannot definitely determine the safety after visiting
987
/// a few instructions in each direction it assumes it's not safe.
988
static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
989
MachineBasicBlock::iterator I) {
990
// It's always safe to clobber EFLAGS at the end of a block.
994
// For compile time consideration, if we are not able to determine the
995
// safety after visiting 4 instructions in each direction, we will assume
997
MachineBasicBlock::iterator Iter = I;
998
for (unsigned i = 0; i < 4; ++i) {
999
bool SeenDef = false;
1000
for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1001
MachineOperand &MO = Iter->getOperand(j);
1004
if (MO.getReg() == X86::EFLAGS) {
1012
// This instruction defines EFLAGS, no need to look any further.
1016
// If we make it to the end of the block, it's safe to clobber EFLAGS.
1017
if (Iter == MBB.end())
1022
for (unsigned i = 0; i < 4; ++i) {
1023
// If we make it to the beginning of the block, it's safe to clobber
1024
// EFLAGS iff EFLAGS is not live-in.
1025
if (Iter == MBB.begin())
1026
return !MBB.isLiveIn(X86::EFLAGS);
1029
bool SawKill = false;
1030
for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1031
MachineOperand &MO = Iter->getOperand(j);
1032
if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1033
if (MO.isDef()) return MO.isDead();
1034
if (MO.isKill()) SawKill = true;
1039
// This instruction kills EFLAGS and doesn't redefine it, so
1040
// there's no need to look further.
1044
// Conservative answer.
1048
void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1049
MachineBasicBlock::iterator I,
1050
unsigned DestReg, unsigned SubIdx,
1051
const MachineInstr *Orig,
1052
const TargetRegisterInfo *TRI) const {
1053
DebugLoc DL = MBB.findDebugLoc(I);
1055
if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1056
DestReg = TRI->getSubReg(DestReg, SubIdx);
1060
// MOV32r0 etc. are implemented with xor which clobbers condition code.
1061
// Re-materialize them as movri instructions to avoid side effects.
1063
unsigned Opc = Orig->getOpcode();
1069
case X86::MOV64r0: {
1070
if (!isSafeToClobberEFLAGS(MBB, I)) {
1073
case X86::MOV8r0: Opc = X86::MOV8ri; break;
1074
case X86::MOV16r0: Opc = X86::MOV16ri; break;
1075
case X86::MOV32r0: Opc = X86::MOV32ri; break;
1076
case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1085
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1086
MI->getOperand(0).setReg(DestReg);
1089
BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
1092
MachineInstr *NewMI = prior(I);
1093
NewMI->getOperand(0).setSubReg(SubIdx);
1096
/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1097
/// is not marked dead.
1098
static bool hasLiveCondCodeDef(MachineInstr *MI) {
1099
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1100
MachineOperand &MO = MI->getOperand(i);
1101
if (MO.isReg() && MO.isDef() &&
1102
MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1109
/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1110
/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1111
/// to a 32-bit superregister and then truncating back down to a 16-bit
1114
X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1115
MachineFunction::iterator &MFI,
1116
MachineBasicBlock::iterator &MBBI,
1117
LiveVariables *LV) const {
1118
MachineInstr *MI = MBBI;
1119
unsigned Dest = MI->getOperand(0).getReg();
1120
unsigned Src = MI->getOperand(1).getReg();
1121
bool isDead = MI->getOperand(0).isDead();
1122
bool isKill = MI->getOperand(1).isKill();
1124
unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1125
? X86::LEA64_32r : X86::LEA32r;
1126
MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1127
unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1128
unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1130
// Build and insert into an implicit UNDEF value. This is OK because
1131
// well be shifting and then extracting the lower 16-bits.
1132
// This has the potential to cause partial register stall. e.g.
1133
// movw (%rbp,%rcx,2), %dx
1134
// leal -65(%rdx), %esi
1135
// But testing has shown this *does* help performance in 64-bit mode (at
1136
// least on modern x86 machines).
1137
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1138
MachineInstr *InsMI =
1139
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1141
.addReg(Src, getKillRegState(isKill))
1142
.addImm(X86::SUBREG_16BIT);
1144
MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1145
get(Opc), leaOutReg);
1148
llvm_unreachable(0);
1150
case X86::SHL16ri: {
1151
unsigned ShAmt = MI->getOperand(2).getImm();
1152
MIB.addReg(0).addImm(1 << ShAmt)
1153
.addReg(leaInReg, RegState::Kill).addImm(0);
1157
case X86::INC64_16r:
1158
addLeaRegOffset(MIB, leaInReg, true, 1);
1161
case X86::DEC64_16r:
1162
addLeaRegOffset(MIB, leaInReg, true, -1);
1166
addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1168
case X86::ADD16rr: {
1169
unsigned Src2 = MI->getOperand(2).getReg();
1170
bool isKill2 = MI->getOperand(2).isKill();
1171
unsigned leaInReg2 = 0;
1172
MachineInstr *InsMI2 = 0;
1174
// ADD16rr %reg1028<kill>, %reg1028
1175
// just a single insert_subreg.
1176
addRegReg(MIB, leaInReg, true, leaInReg, false);
1178
leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1179
// Build and insert into an implicit UNDEF value. This is OK because
1180
// well be shifting and then extracting the lower 16-bits.
1181
BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1183
BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2)
1185
.addReg(Src2, getKillRegState(isKill2))
1186
.addImm(X86::SUBREG_16BIT);
1187
addRegReg(MIB, leaInReg, true, leaInReg2, true);
1189
if (LV && isKill2 && InsMI2)
1190
LV->replaceKillInstruction(Src2, MI, InsMI2);
1195
MachineInstr *NewMI = MIB;
1196
MachineInstr *ExtMI =
1197
BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1198
.addReg(Dest, RegState::Define | getDeadRegState(isDead))
1199
.addReg(leaOutReg, RegState::Kill)
1200
.addImm(X86::SUBREG_16BIT);
1203
// Update live variables
1204
LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1205
LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1207
LV->replaceKillInstruction(Src, MI, InsMI);
1209
LV->replaceKillInstruction(Dest, MI, ExtMI);
1215
/// convertToThreeAddress - This method must be implemented by targets that
1216
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1217
/// may be able to convert a two-address instruction into a true
1218
/// three-address instruction on demand. This allows the X86 target (for
1219
/// example) to convert ADD and SHL instructions into LEA instructions if they
1220
/// would require register copies due to two-addressness.
1222
/// This method returns a null pointer if the transformation cannot be
1223
/// performed, otherwise it returns the new instruction.
1226
X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1227
MachineBasicBlock::iterator &MBBI,
1228
LiveVariables *LV) const {
1229
MachineInstr *MI = MBBI;
1230
MachineFunction &MF = *MI->getParent()->getParent();
1231
// All instructions input are two-addr instructions. Get the known operands.
1232
unsigned Dest = MI->getOperand(0).getReg();
1233
unsigned Src = MI->getOperand(1).getReg();
1234
bool isDead = MI->getOperand(0).isDead();
1235
bool isKill = MI->getOperand(1).isKill();
1237
MachineInstr *NewMI = NULL;
1238
// FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1239
// we have better subtarget support, enable the 16-bit LEA generation here.
1240
// 16-bit LEA is also slow on Core2.
1241
bool DisableLEA16 = true;
1242
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1244
unsigned MIOpc = MI->getOpcode();
1246
case X86::SHUFPSrri: {
1247
assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1248
if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1250
unsigned B = MI->getOperand(1).getReg();
1251
unsigned C = MI->getOperand(2).getReg();
1252
if (B != C) return 0;
1253
unsigned A = MI->getOperand(0).getReg();
1254
unsigned M = MI->getOperand(3).getImm();
1255
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1256
.addReg(A, RegState::Define | getDeadRegState(isDead))
1257
.addReg(B, getKillRegState(isKill)).addImm(M);
1260
case X86::SHL64ri: {
1261
assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1262
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1263
// the flags produced by a shift yet, so this is safe.
1264
unsigned ShAmt = MI->getOperand(2).getImm();
1265
if (ShAmt == 0 || ShAmt >= 4) return 0;
1267
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1268
.addReg(Dest, RegState::Define | getDeadRegState(isDead))
1269
.addReg(0).addImm(1 << ShAmt)
1270
.addReg(Src, getKillRegState(isKill))
1274
case X86::SHL32ri: {
1275
assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1276
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1277
// the flags produced by a shift yet, so this is safe.
1278
unsigned ShAmt = MI->getOperand(2).getImm();
1279
if (ShAmt == 0 || ShAmt >= 4) return 0;
1281
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1282
NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1283
.addReg(Dest, RegState::Define | getDeadRegState(isDead))
1284
.addReg(0).addImm(1 << ShAmt)
1285
.addReg(Src, getKillRegState(isKill)).addImm(0);
1288
case X86::SHL16ri: {
1289
assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1290
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1291
// the flags produced by a shift yet, so this is safe.
1292
unsigned ShAmt = MI->getOperand(2).getImm();
1293
if (ShAmt == 0 || ShAmt >= 4) return 0;
1296
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1297
NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1298
.addReg(Dest, RegState::Define | getDeadRegState(isDead))
1299
.addReg(0).addImm(1 << ShAmt)
1300
.addReg(Src, getKillRegState(isKill))
1305
// The following opcodes also sets the condition code register(s). Only
1306
// convert them to equivalent lea if the condition code register def's
1308
if (hasLiveCondCodeDef(MI))
1315
case X86::INC64_32r: {
1316
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1317
unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1318
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1319
NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1320
.addReg(Dest, RegState::Define |
1321
getDeadRegState(isDead)),
1326
case X86::INC64_16r:
1328
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1329
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1330
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1331
.addReg(Dest, RegState::Define |
1332
getDeadRegState(isDead)),
1337
case X86::DEC64_32r: {
1338
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1339
unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1340
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1341
NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1342
.addReg(Dest, RegState::Define |
1343
getDeadRegState(isDead)),
1348
case X86::DEC64_16r:
1350
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1351
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1352
NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1353
.addReg(Dest, RegState::Define |
1354
getDeadRegState(isDead)),
1358
case X86::ADD32rr: {
1359
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1360
unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1361
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1362
unsigned Src2 = MI->getOperand(2).getReg();
1363
bool isKill2 = MI->getOperand(2).isKill();
1364
NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1365
.addReg(Dest, RegState::Define |
1366
getDeadRegState(isDead)),
1367
Src, isKill, Src2, isKill2);
1369
LV->replaceKillInstruction(Src2, MI, NewMI);
1372
case X86::ADD16rr: {
1374
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1375
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1376
unsigned Src2 = MI->getOperand(2).getReg();
1377
bool isKill2 = MI->getOperand(2).isKill();
1378
NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1379
.addReg(Dest, RegState::Define |
1380
getDeadRegState(isDead)),
1381
Src, isKill, Src2, isKill2);
1383
LV->replaceKillInstruction(Src2, MI, NewMI);
1386
case X86::ADD64ri32:
1388
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1389
NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1390
.addReg(Dest, RegState::Define |
1391
getDeadRegState(isDead)),
1392
Src, isKill, MI->getOperand(2).getImm());
1395
case X86::ADD32ri8: {
1396
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1397
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1398
NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1399
.addReg(Dest, RegState::Define |
1400
getDeadRegState(isDead)),
1401
Src, isKill, MI->getOperand(2).getImm());
1407
return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1408
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1409
NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1410
.addReg(Dest, RegState::Define |
1411
getDeadRegState(isDead)),
1412
Src, isKill, MI->getOperand(2).getImm());
1418
if (!NewMI) return 0;
1420
if (LV) { // Update live variables
1422
LV->replaceKillInstruction(Src, MI, NewMI);
1424
LV->replaceKillInstruction(Dest, MI, NewMI);
1427
MFI->insert(MBBI, NewMI); // Insert the new inst
1431
/// commuteInstruction - We have a few instructions that must be hacked on to
1435
X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1436
switch (MI->getOpcode()) {
1437
case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1438
case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1439
case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1440
case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1441
case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1442
case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1445
switch (MI->getOpcode()) {
1446
default: llvm_unreachable("Unreachable!");
1447
case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1448
case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1449
case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1450
case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1451
case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1452
case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1454
unsigned Amt = MI->getOperand(3).getImm();
1456
MachineFunction &MF = *MI->getParent()->getParent();
1457
MI = MF.CloneMachineInstr(MI);
1460
MI->setDesc(get(Opc));
1461
MI->getOperand(3).setImm(Size-Amt);
1462
return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1464
case X86::CMOVB16rr:
1465
case X86::CMOVB32rr:
1466
case X86::CMOVB64rr:
1467
case X86::CMOVAE16rr:
1468
case X86::CMOVAE32rr:
1469
case X86::CMOVAE64rr:
1470
case X86::CMOVE16rr:
1471
case X86::CMOVE32rr:
1472
case X86::CMOVE64rr:
1473
case X86::CMOVNE16rr:
1474
case X86::CMOVNE32rr:
1475
case X86::CMOVNE64rr:
1476
case X86::CMOVBE16rr:
1477
case X86::CMOVBE32rr:
1478
case X86::CMOVBE64rr:
1479
case X86::CMOVA16rr:
1480
case X86::CMOVA32rr:
1481
case X86::CMOVA64rr:
1482
case X86::CMOVL16rr:
1483
case X86::CMOVL32rr:
1484
case X86::CMOVL64rr:
1485
case X86::CMOVGE16rr:
1486
case X86::CMOVGE32rr:
1487
case X86::CMOVGE64rr:
1488
case X86::CMOVLE16rr:
1489
case X86::CMOVLE32rr:
1490
case X86::CMOVLE64rr:
1491
case X86::CMOVG16rr:
1492
case X86::CMOVG32rr:
1493
case X86::CMOVG64rr:
1494
case X86::CMOVS16rr:
1495
case X86::CMOVS32rr:
1496
case X86::CMOVS64rr:
1497
case X86::CMOVNS16rr:
1498
case X86::CMOVNS32rr:
1499
case X86::CMOVNS64rr:
1500
case X86::CMOVP16rr:
1501
case X86::CMOVP32rr:
1502
case X86::CMOVP64rr:
1503
case X86::CMOVNP16rr:
1504
case X86::CMOVNP32rr:
1505
case X86::CMOVNP64rr:
1506
case X86::CMOVO16rr:
1507
case X86::CMOVO32rr:
1508
case X86::CMOVO64rr:
1509
case X86::CMOVNO16rr:
1510
case X86::CMOVNO32rr:
1511
case X86::CMOVNO64rr: {
1513
switch (MI->getOpcode()) {
1515
case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1516
case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1517
case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1518
case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1519
case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1520
case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1521
case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1522
case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1523
case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1524
case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1525
case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1526
case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1527
case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1528
case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1529
case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1530
case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1531
case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1532
case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1533
case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1534
case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1535
case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1536
case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1537
case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1538
case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1539
case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1540
case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1541
case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1542
case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1543
case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1544
case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1545
case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1546
case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1547
case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1548
case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1549
case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1550
case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1551
case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1552
case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1553
case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1554
case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1555
case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1556
case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1557
case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1558
case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1559
case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1560
case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1561
case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1562
case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1565
MachineFunction &MF = *MI->getParent()->getParent();
1566
MI = MF.CloneMachineInstr(MI);
1569
MI->setDesc(get(Opc));
1570
// Fallthrough intended.
1573
return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1577
static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1579
default: return X86::COND_INVALID;
1580
case X86::JE_4: return X86::COND_E;
1581
case X86::JNE_4: return X86::COND_NE;
1582
case X86::JL_4: return X86::COND_L;
1583
case X86::JLE_4: return X86::COND_LE;
1584
case X86::JG_4: return X86::COND_G;
1585
case X86::JGE_4: return X86::COND_GE;
1586
case X86::JB_4: return X86::COND_B;
1587
case X86::JBE_4: return X86::COND_BE;
1588
case X86::JA_4: return X86::COND_A;
1589
case X86::JAE_4: return X86::COND_AE;
1590
case X86::JS_4: return X86::COND_S;
1591
case X86::JNS_4: return X86::COND_NS;
1592
case X86::JP_4: return X86::COND_P;
1593
case X86::JNP_4: return X86::COND_NP;
1594
case X86::JO_4: return X86::COND_O;
1595
case X86::JNO_4: return X86::COND_NO;
1599
unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1601
default: llvm_unreachable("Illegal condition code!");
1602
case X86::COND_E: return X86::JE_4;
1603
case X86::COND_NE: return X86::JNE_4;
1604
case X86::COND_L: return X86::JL_4;
1605
case X86::COND_LE: return X86::JLE_4;
1606
case X86::COND_G: return X86::JG_4;
1607
case X86::COND_GE: return X86::JGE_4;
1608
case X86::COND_B: return X86::JB_4;
1609
case X86::COND_BE: return X86::JBE_4;
1610
case X86::COND_A: return X86::JA_4;
1611
case X86::COND_AE: return X86::JAE_4;
1612
case X86::COND_S: return X86::JS_4;
1613
case X86::COND_NS: return X86::JNS_4;
1614
case X86::COND_P: return X86::JP_4;
1615
case X86::COND_NP: return X86::JNP_4;
1616
case X86::COND_O: return X86::JO_4;
1617
case X86::COND_NO: return X86::JNO_4;
1621
/// GetOppositeBranchCondition - Return the inverse of the specified condition,
1622
/// e.g. turning COND_E to COND_NE.
1623
X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1625
default: llvm_unreachable("Illegal condition code!");
1626
case X86::COND_E: return X86::COND_NE;
1627
case X86::COND_NE: return X86::COND_E;
1628
case X86::COND_L: return X86::COND_GE;
1629
case X86::COND_LE: return X86::COND_G;
1630
case X86::COND_G: return X86::COND_LE;
1631
case X86::COND_GE: return X86::COND_L;
1632
case X86::COND_B: return X86::COND_AE;
1633
case X86::COND_BE: return X86::COND_A;
1634
case X86::COND_A: return X86::COND_BE;
1635
case X86::COND_AE: return X86::COND_B;
1636
case X86::COND_S: return X86::COND_NS;
1637
case X86::COND_NS: return X86::COND_S;
1638
case X86::COND_P: return X86::COND_NP;
1639
case X86::COND_NP: return X86::COND_P;
1640
case X86::COND_O: return X86::COND_NO;
1641
case X86::COND_NO: return X86::COND_O;
1645
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1646
const TargetInstrDesc &TID = MI->getDesc();
1647
if (!TID.isTerminator()) return false;
1649
// Conditional branch is a special case.
1650
if (TID.isBranch() && !TID.isBarrier())
1652
if (!TID.isPredicable())
1654
return !isPredicated(MI);
1657
// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1658
static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1659
const X86InstrInfo &TII) {
1660
if (MI->getOpcode() == X86::FP_REG_KILL)
1662
return TII.isUnpredicatedTerminator(MI);
1665
bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1666
MachineBasicBlock *&TBB,
1667
MachineBasicBlock *&FBB,
1668
SmallVectorImpl<MachineOperand> &Cond,
1669
bool AllowModify) const {
1670
// Start from the bottom of the block and work up, examining the
1671
// terminator instructions.
1672
MachineBasicBlock::iterator I = MBB.end();
1673
while (I != MBB.begin()) {
1676
// Working from the bottom, when we see a non-terminator instruction, we're
1678
if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1681
// A terminator that isn't a branch can't easily be handled by this
1683
if (!I->getDesc().isBranch())
1686
// Handle unconditional branches.
1687
if (I->getOpcode() == X86::JMP_4) {
1689
TBB = I->getOperand(0).getMBB();
1693
// If the block has any instructions after a JMP, delete them.
1694
while (llvm::next(I) != MBB.end())
1695
llvm::next(I)->eraseFromParent();
1700
// Delete the JMP if it's equivalent to a fall-through.
1701
if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1703
I->eraseFromParent();
1708
// TBB is used to indicate the unconditinal destination.
1709
TBB = I->getOperand(0).getMBB();
1713
// Handle conditional branches.
1714
X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1715
if (BranchCode == X86::COND_INVALID)
1716
return true; // Can't handle indirect branch.
1718
// Working from the bottom, handle the first conditional branch.
1721
TBB = I->getOperand(0).getMBB();
1722
Cond.push_back(MachineOperand::CreateImm(BranchCode));
1726
// Handle subsequent conditional branches. Only handle the case where all
1727
// conditional branches branch to the same destination and their condition
1728
// opcodes fit one of the special multi-branch idioms.
1729
assert(Cond.size() == 1);
1732
// Only handle the case where all conditional branches branch to the same
1734
if (TBB != I->getOperand(0).getMBB())
1737
// If the conditions are the same, we can leave them alone.
1738
X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1739
if (OldBranchCode == BranchCode)
1742
// If they differ, see if they fit one of the known patterns. Theoretically,
1743
// we could handle more patterns here, but we shouldn't expect to see them
1744
// if instruction selection has done a reasonable job.
1745
if ((OldBranchCode == X86::COND_NP &&
1746
BranchCode == X86::COND_E) ||
1747
(OldBranchCode == X86::COND_E &&
1748
BranchCode == X86::COND_NP))
1749
BranchCode = X86::COND_NP_OR_E;
1750
else if ((OldBranchCode == X86::COND_P &&
1751
BranchCode == X86::COND_NE) ||
1752
(OldBranchCode == X86::COND_NE &&
1753
BranchCode == X86::COND_P))
1754
BranchCode = X86::COND_NE_OR_P;
1758
// Update the MachineOperand.
1759
Cond[0].setImm(BranchCode);
1765
unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1766
MachineBasicBlock::iterator I = MBB.end();
1769
while (I != MBB.begin()) {
1771
if (I->getOpcode() != X86::JMP_4 &&
1772
GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1774
// Remove the branch.
1775
I->eraseFromParent();
1784
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1785
MachineBasicBlock *FBB,
1786
const SmallVectorImpl<MachineOperand> &Cond) const {
1787
// FIXME this should probably have a DebugLoc operand
1788
DebugLoc dl = DebugLoc::getUnknownLoc();
1789
// Shouldn't be a fall through.
1790
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1791
assert((Cond.size() == 1 || Cond.size() == 0) &&
1792
"X86 branch conditions have one component!");
1795
// Unconditional branch?
1796
assert(!FBB && "Unconditional branch with multiple successors!");
1797
BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB);
1801
// Conditional branch.
1803
X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1805
case X86::COND_NP_OR_E:
1806
// Synthesize NP_OR_E with two branches.
1807
BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB);
1809
BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB);
1812
case X86::COND_NE_OR_P:
1813
// Synthesize NE_OR_P with two branches.
1814
BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB);
1816
BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB);
1820
unsigned Opc = GetCondBranchFromCond(CC);
1821
BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1826
// Two-way Conditional branch. Insert the second branch.
1827
BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB);
1833
/// isHReg - Test if the given register is a physical h register.
1834
static bool isHReg(unsigned Reg) {
1835
return X86::GR8_ABCD_HRegClass.contains(Reg);
1838
bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1839
MachineBasicBlock::iterator MI,
1840
unsigned DestReg, unsigned SrcReg,
1841
const TargetRegisterClass *DestRC,
1842
const TargetRegisterClass *SrcRC) const {
1843
DebugLoc DL = MBB.findDebugLoc(MI);
1845
// Determine if DstRC and SrcRC have a common superclass in common.
1846
const TargetRegisterClass *CommonRC = DestRC;
1847
if (DestRC == SrcRC)
1848
/* Source and destination have the same register class. */;
1849
else if (CommonRC->hasSuperClass(SrcRC))
1851
else if (!DestRC->hasSubClass(SrcRC)) {
1852
// Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1853
// but we want to copy them as GR64. Similarly, for GR32_NOREX and
1854
// GR32_NOSP, copy as GR32.
1855
if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1856
DestRC->hasSuperClass(&X86::GR64RegClass))
1857
CommonRC = &X86::GR64RegClass;
1858
else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1859
DestRC->hasSuperClass(&X86::GR32RegClass))
1860
CommonRC = &X86::GR32RegClass;
1867
if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1869
} else if (CommonRC == &X86::GR32RegClass ||
1870
CommonRC == &X86::GR32_NOSPRegClass) {
1872
} else if (CommonRC == &X86::GR16RegClass) {
1874
} else if (CommonRC == &X86::GR8RegClass) {
1875
// Copying to or from a physical H register on x86-64 requires a NOREX
1876
// move. Otherwise use a normal move.
1877
if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1878
TM.getSubtarget<X86Subtarget>().is64Bit())
1879
Opc = X86::MOV8rr_NOREX;
1882
} else if (CommonRC == &X86::GR64_ABCDRegClass) {
1884
} else if (CommonRC == &X86::GR32_ABCDRegClass) {
1886
} else if (CommonRC == &X86::GR16_ABCDRegClass) {
1888
} else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1890
} else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1891
if (TM.getSubtarget<X86Subtarget>().is64Bit())
1892
Opc = X86::MOV8rr_NOREX;
1895
} else if (CommonRC == &X86::GR64_NOREXRegClass ||
1896
CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1898
} else if (CommonRC == &X86::GR32_NOREXRegClass) {
1900
} else if (CommonRC == &X86::GR16_NOREXRegClass) {
1902
} else if (CommonRC == &X86::GR8_NOREXRegClass) {
1904
} else if (CommonRC == &X86::RFP32RegClass) {
1905
Opc = X86::MOV_Fp3232;
1906
} else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1907
Opc = X86::MOV_Fp6464;
1908
} else if (CommonRC == &X86::RFP80RegClass) {
1909
Opc = X86::MOV_Fp8080;
1910
} else if (CommonRC == &X86::FR32RegClass) {
1911
Opc = X86::FsMOVAPSrr;
1912
} else if (CommonRC == &X86::FR64RegClass) {
1913
Opc = X86::FsMOVAPDrr;
1914
} else if (CommonRC == &X86::VR128RegClass) {
1915
Opc = X86::MOVAPSrr;
1916
} else if (CommonRC == &X86::VR64RegClass) {
1917
Opc = X86::MMX_MOVQ64rr;
1921
BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1925
// Moving EFLAGS to / from another register requires a push and a pop.
1926
if (SrcRC == &X86::CCRRegClass) {
1927
if (SrcReg != X86::EFLAGS)
1929
if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1930
BuildMI(MBB, MI, DL, get(X86::PUSHFQ64));
1931
BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1933
} else if (DestRC == &X86::GR32RegClass ||
1934
DestRC == &X86::GR32_NOSPRegClass) {
1935
BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1936
BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1939
} else if (DestRC == &X86::CCRRegClass) {
1940
if (DestReg != X86::EFLAGS)
1942
if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1943
BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1944
BuildMI(MBB, MI, DL, get(X86::POPFQ));
1946
} else if (SrcRC == &X86::GR32RegClass ||
1947
DestRC == &X86::GR32_NOSPRegClass) {
1948
BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1949
BuildMI(MBB, MI, DL, get(X86::POPFD));
1954
// Moving from ST(0) turns into FpGET_ST0_32 etc.
1955
if (SrcRC == &X86::RSTRegClass) {
1956
// Copying from ST(0)/ST(1).
1957
if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1958
// Can only copy from ST(0)/ST(1) right now
1960
bool isST0 = SrcReg == X86::ST0;
1962
if (DestRC == &X86::RFP32RegClass)
1963
Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1964
else if (DestRC == &X86::RFP64RegClass)
1965
Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1967
if (DestRC != &X86::RFP80RegClass)
1969
Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1971
BuildMI(MBB, MI, DL, get(Opc), DestReg);
1975
// Moving to ST(0) turns into FpSET_ST0_32 etc.
1976
if (DestRC == &X86::RSTRegClass) {
1977
// Copying to ST(0) / ST(1).
1978
if (DestReg != X86::ST0 && DestReg != X86::ST1)
1979
// Can only copy to TOS right now
1981
bool isST0 = DestReg == X86::ST0;
1983
if (SrcRC == &X86::RFP32RegClass)
1984
Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1985
else if (SrcRC == &X86::RFP64RegClass)
1986
Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1988
if (SrcRC != &X86::RFP80RegClass)
1990
Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1992
BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1996
// Not yet supported!
2000
static unsigned getStoreRegOpcode(unsigned SrcReg,
2001
const TargetRegisterClass *RC,
2002
bool isStackAligned,
2003
TargetMachine &TM) {
2005
if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2007
} else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2009
} else if (RC == &X86::GR16RegClass) {
2011
} else if (RC == &X86::GR8RegClass) {
2012
// Copying to or from a physical H register on x86-64 requires a NOREX
2013
// move. Otherwise use a normal move.
2014
if (isHReg(SrcReg) &&
2015
TM.getSubtarget<X86Subtarget>().is64Bit())
2016
Opc = X86::MOV8mr_NOREX;
2019
} else if (RC == &X86::GR64_ABCDRegClass) {
2021
} else if (RC == &X86::GR32_ABCDRegClass) {
2023
} else if (RC == &X86::GR16_ABCDRegClass) {
2025
} else if (RC == &X86::GR8_ABCD_LRegClass) {
2027
} else if (RC == &X86::GR8_ABCD_HRegClass) {
2028
if (TM.getSubtarget<X86Subtarget>().is64Bit())
2029
Opc = X86::MOV8mr_NOREX;
2032
} else if (RC == &X86::GR64_NOREXRegClass ||
2033
RC == &X86::GR64_NOREX_NOSPRegClass) {
2035
} else if (RC == &X86::GR32_NOREXRegClass) {
2037
} else if (RC == &X86::GR16_NOREXRegClass) {
2039
} else if (RC == &X86::GR8_NOREXRegClass) {
2041
} else if (RC == &X86::RFP80RegClass) {
2042
Opc = X86::ST_FpP80m; // pops
2043
} else if (RC == &X86::RFP64RegClass) {
2044
Opc = X86::ST_Fp64m;
2045
} else if (RC == &X86::RFP32RegClass) {
2046
Opc = X86::ST_Fp32m;
2047
} else if (RC == &X86::FR32RegClass) {
2049
} else if (RC == &X86::FR64RegClass) {
2051
} else if (RC == &X86::VR128RegClass) {
2052
// If stack is realigned we can use aligned stores.
2053
Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
2054
} else if (RC == &X86::VR64RegClass) {
2055
Opc = X86::MMX_MOVQ64mr;
2057
llvm_unreachable("Unknown regclass");
2063
void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2064
MachineBasicBlock::iterator MI,
2065
unsigned SrcReg, bool isKill, int FrameIdx,
2066
const TargetRegisterClass *RC) const {
2067
const MachineFunction &MF = *MBB.getParent();
2068
bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2069
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2070
DebugLoc DL = MBB.findDebugLoc(MI);
2071
addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2072
.addReg(SrcReg, getKillRegState(isKill));
2075
void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2077
SmallVectorImpl<MachineOperand> &Addr,
2078
const TargetRegisterClass *RC,
2079
MachineInstr::mmo_iterator MMOBegin,
2080
MachineInstr::mmo_iterator MMOEnd,
2081
SmallVectorImpl<MachineInstr*> &NewMIs) const {
2082
bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2083
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2084
DebugLoc DL = DebugLoc::getUnknownLoc();
2085
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2086
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2087
MIB.addOperand(Addr[i]);
2088
MIB.addReg(SrcReg, getKillRegState(isKill));
2089
(*MIB).setMemRefs(MMOBegin, MMOEnd);
2090
NewMIs.push_back(MIB);
2093
static unsigned getLoadRegOpcode(unsigned DestReg,
2094
const TargetRegisterClass *RC,
2095
bool isStackAligned,
2096
const TargetMachine &TM) {
2098
if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2100
} else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2102
} else if (RC == &X86::GR16RegClass) {
2104
} else if (RC == &X86::GR8RegClass) {
2105
// Copying to or from a physical H register on x86-64 requires a NOREX
2106
// move. Otherwise use a normal move.
2107
if (isHReg(DestReg) &&
2108
TM.getSubtarget<X86Subtarget>().is64Bit())
2109
Opc = X86::MOV8rm_NOREX;
2112
} else if (RC == &X86::GR64_ABCDRegClass) {
2114
} else if (RC == &X86::GR32_ABCDRegClass) {
2116
} else if (RC == &X86::GR16_ABCDRegClass) {
2118
} else if (RC == &X86::GR8_ABCD_LRegClass) {
2120
} else if (RC == &X86::GR8_ABCD_HRegClass) {
2121
if (TM.getSubtarget<X86Subtarget>().is64Bit())
2122
Opc = X86::MOV8rm_NOREX;
2125
} else if (RC == &X86::GR64_NOREXRegClass ||
2126
RC == &X86::GR64_NOREX_NOSPRegClass) {
2128
} else if (RC == &X86::GR32_NOREXRegClass) {
2130
} else if (RC == &X86::GR16_NOREXRegClass) {
2132
} else if (RC == &X86::GR8_NOREXRegClass) {
2134
} else if (RC == &X86::RFP80RegClass) {
2135
Opc = X86::LD_Fp80m;
2136
} else if (RC == &X86::RFP64RegClass) {
2137
Opc = X86::LD_Fp64m;
2138
} else if (RC == &X86::RFP32RegClass) {
2139
Opc = X86::LD_Fp32m;
2140
} else if (RC == &X86::FR32RegClass) {
2142
} else if (RC == &X86::FR64RegClass) {
2144
} else if (RC == &X86::VR128RegClass) {
2145
// If stack is realigned we can use aligned loads.
2146
Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
2147
} else if (RC == &X86::VR64RegClass) {
2148
Opc = X86::MMX_MOVQ64rm;
2150
llvm_unreachable("Unknown regclass");
2156
void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2157
MachineBasicBlock::iterator MI,
2158
unsigned DestReg, int FrameIdx,
2159
const TargetRegisterClass *RC) const{
2160
const MachineFunction &MF = *MBB.getParent();
2161
bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2162
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2163
DebugLoc DL = MBB.findDebugLoc(MI);
2164
addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2167
void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2168
SmallVectorImpl<MachineOperand> &Addr,
2169
const TargetRegisterClass *RC,
2170
MachineInstr::mmo_iterator MMOBegin,
2171
MachineInstr::mmo_iterator MMOEnd,
2172
SmallVectorImpl<MachineInstr*> &NewMIs) const {
2173
bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2174
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2175
DebugLoc DL = DebugLoc::getUnknownLoc();
2176
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2177
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2178
MIB.addOperand(Addr[i]);
2179
(*MIB).setMemRefs(MMOBegin, MMOEnd);
2180
NewMIs.push_back(MIB);
2183
bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2184
MachineBasicBlock::iterator MI,
2185
const std::vector<CalleeSavedInfo> &CSI) const {
2189
DebugLoc DL = MBB.findDebugLoc(MI);
2191
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2192
bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2193
unsigned SlotSize = is64Bit ? 8 : 4;
2195
MachineFunction &MF = *MBB.getParent();
2196
unsigned FPReg = RI.getFrameRegister(MF);
2197
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2198
unsigned CalleeFrameSize = 0;
2200
unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2201
for (unsigned i = CSI.size(); i != 0; --i) {
2202
unsigned Reg = CSI[i-1].getReg();
2203
const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2204
// Add the callee-saved register as live-in. It's killed at the spill.
2207
// X86RegisterInfo::emitPrologue will handle spilling of frame register.
2209
if (RegClass != &X86::VR128RegClass && !isWin64) {
2210
CalleeFrameSize += SlotSize;
2211
BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2213
storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2217
X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2221
bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2222
MachineBasicBlock::iterator MI,
2223
const std::vector<CalleeSavedInfo> &CSI) const {
2227
DebugLoc DL = MBB.findDebugLoc(MI);
2229
MachineFunction &MF = *MBB.getParent();
2230
unsigned FPReg = RI.getFrameRegister(MF);
2231
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2232
bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2233
unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2234
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2235
unsigned Reg = CSI[i].getReg();
2237
// X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2239
const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2240
if (RegClass != &X86::VR128RegClass && !isWin64) {
2241
BuildMI(MBB, MI, DL, get(Opc), Reg);
2243
loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2249
static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2250
const SmallVectorImpl<MachineOperand> &MOs,
2252
const TargetInstrInfo &TII) {
2253
// Create the base instruction with the memory operand as the first part.
2254
MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2255
MI->getDebugLoc(), true);
2256
MachineInstrBuilder MIB(NewMI);
2257
unsigned NumAddrOps = MOs.size();
2258
for (unsigned i = 0; i != NumAddrOps; ++i)
2259
MIB.addOperand(MOs[i]);
2260
if (NumAddrOps < 4) // FrameIndex only
2263
// Loop over the rest of the ri operands, converting them over.
2264
unsigned NumOps = MI->getDesc().getNumOperands()-2;
2265
for (unsigned i = 0; i != NumOps; ++i) {
2266
MachineOperand &MO = MI->getOperand(i+2);
2269
for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2270
MachineOperand &MO = MI->getOperand(i);
2276
static MachineInstr *FuseInst(MachineFunction &MF,
2277
unsigned Opcode, unsigned OpNo,
2278
const SmallVectorImpl<MachineOperand> &MOs,
2279
MachineInstr *MI, const TargetInstrInfo &TII) {
2280
MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2281
MI->getDebugLoc(), true);
2282
MachineInstrBuilder MIB(NewMI);
2284
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2285
MachineOperand &MO = MI->getOperand(i);
2287
assert(MO.isReg() && "Expected to fold into reg operand!");
2288
unsigned NumAddrOps = MOs.size();
2289
for (unsigned i = 0; i != NumAddrOps; ++i)
2290
MIB.addOperand(MOs[i]);
2291
if (NumAddrOps < 4) // FrameIndex only
2300
static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2301
const SmallVectorImpl<MachineOperand> &MOs,
2303
MachineFunction &MF = *MI->getParent()->getParent();
2304
MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2306
unsigned NumAddrOps = MOs.size();
2307
for (unsigned i = 0; i != NumAddrOps; ++i)
2308
MIB.addOperand(MOs[i]);
2309
if (NumAddrOps < 4) // FrameIndex only
2311
return MIB.addImm(0);
2315
X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2316
MachineInstr *MI, unsigned i,
2317
const SmallVectorImpl<MachineOperand> &MOs,
2318
unsigned Size, unsigned Align) const {
2319
const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2320
bool isTwoAddrFold = false;
2321
unsigned NumOps = MI->getDesc().getNumOperands();
2322
bool isTwoAddr = NumOps > 1 &&
2323
MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2325
MachineInstr *NewMI = NULL;
2326
// Folding a memory location into the two-address part of a two-address
2327
// instruction is different than folding it other places. It requires
2328
// replacing the *two* registers with the memory location.
2329
if (isTwoAddr && NumOps >= 2 && i < 2 &&
2330
MI->getOperand(0).isReg() &&
2331
MI->getOperand(1).isReg() &&
2332
MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2333
OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2334
isTwoAddrFold = true;
2335
} else if (i == 0) { // If operand 0
2336
if (MI->getOpcode() == X86::MOV64r0)
2337
NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2338
else if (MI->getOpcode() == X86::MOV32r0)
2339
NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2340
else if (MI->getOpcode() == X86::MOV16r0)
2341
NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2342
else if (MI->getOpcode() == X86::MOV8r0)
2343
NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2347
OpcodeTablePtr = &RegOp2MemOpTable0;
2348
} else if (i == 1) {
2349
OpcodeTablePtr = &RegOp2MemOpTable1;
2350
} else if (i == 2) {
2351
OpcodeTablePtr = &RegOp2MemOpTable2;
2354
// If table selected...
2355
if (OpcodeTablePtr) {
2356
// Find the Opcode to fuse
2357
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2358
OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2359
if (I != OpcodeTablePtr->end()) {
2360
unsigned Opcode = I->second.first;
2361
unsigned MinAlign = I->second.second;
2362
if (Align < MinAlign)
2364
bool NarrowToMOV32rm = false;
2366
unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2367
if (Size < RCSize) {
2368
// Check if it's safe to fold the load. If the size of the object is
2369
// narrower than the load width, then it's not.
2370
if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2372
// If this is a 64-bit load, but the spill slot is 32, then we can do
2373
// a 32-bit load which is implicitly zero-extended. This likely is due
2374
// to liveintervalanalysis remat'ing a load from stack slot.
2375
if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2377
Opcode = X86::MOV32rm;
2378
NarrowToMOV32rm = true;
2383
NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2385
NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2387
if (NarrowToMOV32rm) {
2388
// If this is the special case where we use a MOV32rm to load a 32-bit
2389
// value and zero-extend the top bits. Change the destination register
2391
unsigned DstReg = NewMI->getOperand(0).getReg();
2392
if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2393
NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2394
4/*x86_subreg_32bit*/));
2396
NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2403
if (PrintFailedFusing)
2404
dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2409
MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2411
const SmallVectorImpl<unsigned> &Ops,
2412
int FrameIndex) const {
2413
// Check switch flag
2414
if (NoFusing) return NULL;
2416
if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2417
switch (MI->getOpcode()) {
2418
case X86::CVTSD2SSrr:
2419
case X86::Int_CVTSD2SSrr:
2420
case X86::CVTSS2SDrr:
2421
case X86::Int_CVTSS2SDrr:
2423
case X86::RCPSSr_Int:
2424
case X86::ROUNDSDr_Int:
2425
case X86::ROUNDSSr_Int:
2427
case X86::RSQRTSSr_Int:
2429
case X86::SQRTSSr_Int:
2433
const MachineFrameInfo *MFI = MF.getFrameInfo();
2434
unsigned Size = MFI->getObjectSize(FrameIndex);
2435
unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2436
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2437
unsigned NewOpc = 0;
2438
unsigned RCSize = 0;
2439
switch (MI->getOpcode()) {
2440
default: return NULL;
2441
case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2442
case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2443
case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2444
case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2446
// Check if it's safe to fold the load. If the size of the object is
2447
// narrower than the load width, then it's not.
2450
// Change to CMPXXri r, 0 first.
2451
MI->setDesc(get(NewOpc));
2452
MI->getOperand(1).ChangeToImmediate(0);
2453
} else if (Ops.size() != 1)
2456
SmallVector<MachineOperand,4> MOs;
2457
MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2458
return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2461
MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2463
const SmallVectorImpl<unsigned> &Ops,
2464
MachineInstr *LoadMI) const {
2465
// Check switch flag
2466
if (NoFusing) return NULL;
2468
if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2469
switch (MI->getOpcode()) {
2470
case X86::CVTSD2SSrr:
2471
case X86::Int_CVTSD2SSrr:
2472
case X86::CVTSS2SDrr:
2473
case X86::Int_CVTSS2SDrr:
2475
case X86::RCPSSr_Int:
2476
case X86::ROUNDSDr_Int:
2477
case X86::ROUNDSSr_Int:
2479
case X86::RSQRTSSr_Int:
2481
case X86::SQRTSSr_Int:
2485
// Determine the alignment of the load.
2486
unsigned Alignment = 0;
2487
if (LoadMI->hasOneMemOperand())
2488
Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2490
switch (LoadMI->getOpcode()) {
2492
case X86::V_SETALLONES:
2502
llvm_unreachable("Don't know how to fold this instruction!");
2504
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2505
unsigned NewOpc = 0;
2506
switch (MI->getOpcode()) {
2507
default: return NULL;
2508
case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2509
case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2510
case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2511
case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2513
// Change to CMPXXri r, 0 first.
2514
MI->setDesc(get(NewOpc));
2515
MI->getOperand(1).ChangeToImmediate(0);
2516
} else if (Ops.size() != 1)
2519
SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2520
switch (LoadMI->getOpcode()) {
2522
case X86::V_SETALLONES:
2524
case X86::FsFLD0SS: {
2525
// Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2526
// Create a constant-pool entry and operands to load from it.
2528
// x86-32 PIC requires a PIC base register for constant pools.
2529
unsigned PICBase = 0;
2530
if (TM.getRelocationModel() == Reloc::PIC_) {
2531
if (TM.getSubtarget<X86Subtarget>().is64Bit())
2534
// FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2535
// This doesn't work for several reasons.
2536
// 1. GlobalBaseReg may have been spilled.
2537
// 2. It may not be live at MI.
2541
// Create a constant-pool entry.
2542
MachineConstantPool &MCP = *MF.getConstantPool();
2544
if (LoadMI->getOpcode() == X86::FsFLD0SS)
2545
Ty = Type::getFloatTy(MF.getFunction()->getContext());
2546
else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2547
Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2549
Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2550
Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2551
Constant::getAllOnesValue(Ty) :
2552
Constant::getNullValue(Ty);
2553
unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2555
// Create operands to load from the constant pool entry.
2556
MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2557
MOs.push_back(MachineOperand::CreateImm(1));
2558
MOs.push_back(MachineOperand::CreateReg(0, false));
2559
MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2560
MOs.push_back(MachineOperand::CreateReg(0, false));
2564
// Folding a normal load. Just copy the load's address operands.
2565
unsigned NumOps = LoadMI->getDesc().getNumOperands();
2566
for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2567
MOs.push_back(LoadMI->getOperand(i));
2571
return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2575
bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2576
const SmallVectorImpl<unsigned> &Ops) const {
2577
// Check switch flag
2578
if (NoFusing) return 0;
2580
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2581
switch (MI->getOpcode()) {
2582
default: return false;
2591
if (Ops.size() != 1)
2594
unsigned OpNum = Ops[0];
2595
unsigned Opc = MI->getOpcode();
2596
unsigned NumOps = MI->getDesc().getNumOperands();
2597
bool isTwoAddr = NumOps > 1 &&
2598
MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2600
// Folding a memory location into the two-address part of a two-address
2601
// instruction is different than folding it other places. It requires
2602
// replacing the *two* registers with the memory location.
2603
const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2604
if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2605
OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2606
} else if (OpNum == 0) { // If operand 0
2615
OpcodeTablePtr = &RegOp2MemOpTable0;
2616
} else if (OpNum == 1) {
2617
OpcodeTablePtr = &RegOp2MemOpTable1;
2618
} else if (OpNum == 2) {
2619
OpcodeTablePtr = &RegOp2MemOpTable2;
2622
if (OpcodeTablePtr) {
2623
// Find the Opcode to fuse
2624
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2625
OpcodeTablePtr->find((unsigned*)Opc);
2626
if (I != OpcodeTablePtr->end())
2632
bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2633
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2634
SmallVectorImpl<MachineInstr*> &NewMIs) const {
2635
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2636
MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2637
if (I == MemOp2RegOpTable.end())
2639
unsigned Opc = I->second.first;
2640
unsigned Index = I->second.second & 0xf;
2641
bool FoldedLoad = I->second.second & (1 << 4);
2642
bool FoldedStore = I->second.second & (1 << 5);
2643
if (UnfoldLoad && !FoldedLoad)
2645
UnfoldLoad &= FoldedLoad;
2646
if (UnfoldStore && !FoldedStore)
2648
UnfoldStore &= FoldedStore;
2650
const TargetInstrDesc &TID = get(Opc);
2651
const TargetOperandInfo &TOI = TID.OpInfo[Index];
2652
const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2653
SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2654
SmallVector<MachineOperand,2> BeforeOps;
2655
SmallVector<MachineOperand,2> AfterOps;
2656
SmallVector<MachineOperand,4> ImpOps;
2657
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2658
MachineOperand &Op = MI->getOperand(i);
2659
if (i >= Index && i < Index + X86AddrNumOperands)
2660
AddrOps.push_back(Op);
2661
else if (Op.isReg() && Op.isImplicit())
2662
ImpOps.push_back(Op);
2664
BeforeOps.push_back(Op);
2666
AfterOps.push_back(Op);
2669
// Emit the load instruction.
2671
std::pair<MachineInstr::mmo_iterator,
2672
MachineInstr::mmo_iterator> MMOs =
2673
MF.extractLoadMemRefs(MI->memoperands_begin(),
2674
MI->memoperands_end());
2675
loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2677
// Address operands cannot be marked isKill.
2678
for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2679
MachineOperand &MO = NewMIs[0]->getOperand(i);
2681
MO.setIsKill(false);
2686
// Emit the data processing instruction.
2687
MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2688
MachineInstrBuilder MIB(DataMI);
2691
MIB.addReg(Reg, RegState::Define);
2692
for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2693
MIB.addOperand(BeforeOps[i]);
2696
for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2697
MIB.addOperand(AfterOps[i]);
2698
for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2699
MachineOperand &MO = ImpOps[i];
2700
MIB.addReg(MO.getReg(),
2701
getDefRegState(MO.isDef()) |
2702
RegState::Implicit |
2703
getKillRegState(MO.isKill()) |
2704
getDeadRegState(MO.isDead()) |
2705
getUndefRegState(MO.isUndef()));
2707
// Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2708
unsigned NewOpc = 0;
2709
switch (DataMI->getOpcode()) {
2711
case X86::CMP64ri32:
2715
MachineOperand &MO0 = DataMI->getOperand(0);
2716
MachineOperand &MO1 = DataMI->getOperand(1);
2717
if (MO1.getImm() == 0) {
2718
switch (DataMI->getOpcode()) {
2720
case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2721
case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2722
case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2723
case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2725
DataMI->setDesc(get(NewOpc));
2726
MO1.ChangeToRegister(MO0.getReg(), false);
2730
NewMIs.push_back(DataMI);
2732
// Emit the store instruction.
2734
const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2735
std::pair<MachineInstr::mmo_iterator,
2736
MachineInstr::mmo_iterator> MMOs =
2737
MF.extractStoreMemRefs(MI->memoperands_begin(),
2738
MI->memoperands_end());
2739
storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2746
X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2747
SmallVectorImpl<SDNode*> &NewNodes) const {
2748
if (!N->isMachineOpcode())
2751
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2752
MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2753
if (I == MemOp2RegOpTable.end())
2755
unsigned Opc = I->second.first;
2756
unsigned Index = I->second.second & 0xf;
2757
bool FoldedLoad = I->second.second & (1 << 4);
2758
bool FoldedStore = I->second.second & (1 << 5);
2759
const TargetInstrDesc &TID = get(Opc);
2760
const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2761
unsigned NumDefs = TID.NumDefs;
2762
std::vector<SDValue> AddrOps;
2763
std::vector<SDValue> BeforeOps;
2764
std::vector<SDValue> AfterOps;
2765
DebugLoc dl = N->getDebugLoc();
2766
unsigned NumOps = N->getNumOperands();
2767
for (unsigned i = 0; i != NumOps-1; ++i) {
2768
SDValue Op = N->getOperand(i);
2769
if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2770
AddrOps.push_back(Op);
2771
else if (i < Index-NumDefs)
2772
BeforeOps.push_back(Op);
2773
else if (i > Index-NumDefs)
2774
AfterOps.push_back(Op);
2776
SDValue Chain = N->getOperand(NumOps-1);
2777
AddrOps.push_back(Chain);
2779
// Emit the load instruction.
2781
MachineFunction &MF = DAG.getMachineFunction();
2783
EVT VT = *RC->vt_begin();
2784
std::pair<MachineInstr::mmo_iterator,
2785
MachineInstr::mmo_iterator> MMOs =
2786
MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2787
cast<MachineSDNode>(N)->memoperands_end());
2788
bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2789
Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2790
VT, MVT::Other, &AddrOps[0], AddrOps.size());
2791
NewNodes.push_back(Load);
2793
// Preserve memory reference information.
2794
cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2797
// Emit the data processing instruction.
2798
std::vector<EVT> VTs;
2799
const TargetRegisterClass *DstRC = 0;
2800
if (TID.getNumDefs() > 0) {
2801
DstRC = TID.OpInfo[0].getRegClass(&RI);
2802
VTs.push_back(*DstRC->vt_begin());
2804
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2805
EVT VT = N->getValueType(i);
2806
if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2810
BeforeOps.push_back(SDValue(Load, 0));
2811
std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2812
SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2814
NewNodes.push_back(NewNode);
2816
// Emit the store instruction.
2819
AddrOps.push_back(SDValue(NewNode, 0));
2820
AddrOps.push_back(Chain);
2821
std::pair<MachineInstr::mmo_iterator,
2822
MachineInstr::mmo_iterator> MMOs =
2823
MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2824
cast<MachineSDNode>(N)->memoperands_end());
2825
bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2826
SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2829
&AddrOps[0], AddrOps.size());
2830
NewNodes.push_back(Store);
2832
// Preserve memory reference information.
2833
cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2839
unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2840
bool UnfoldLoad, bool UnfoldStore,
2841
unsigned *LoadRegIndex) const {
2842
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2843
MemOp2RegOpTable.find((unsigned*)Opc);
2844
if (I == MemOp2RegOpTable.end())
2846
bool FoldedLoad = I->second.second & (1 << 4);
2847
bool FoldedStore = I->second.second & (1 << 5);
2848
if (UnfoldLoad && !FoldedLoad)
2850
if (UnfoldStore && !FoldedStore)
2853
*LoadRegIndex = I->second.second & 0xf;
2854
return I->second.first;
2858
X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2859
int64_t &Offset1, int64_t &Offset2) const {
2860
if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2862
unsigned Opc1 = Load1->getMachineOpcode();
2863
unsigned Opc2 = Load2->getMachineOpcode();
2865
default: return false;
2875
case X86::MMX_MOVD64rm:
2876
case X86::MMX_MOVQ64rm:
2877
case X86::FsMOVAPSrm:
2878
case X86::FsMOVAPDrm:
2881
case X86::MOVUPSrm_Int:
2885
case X86::MOVDQUrm_Int:
2889
default: return false;
2899
case X86::MMX_MOVD64rm:
2900
case X86::MMX_MOVQ64rm:
2901
case X86::FsMOVAPSrm:
2902
case X86::FsMOVAPDrm:
2905
case X86::MOVUPSrm_Int:
2909
case X86::MOVDQUrm_Int:
2913
// Check if chain operands and base addresses match.
2914
if (Load1->getOperand(0) != Load2->getOperand(0) ||
2915
Load1->getOperand(5) != Load2->getOperand(5))
2917
// Segment operands should match as well.
2918
if (Load1->getOperand(4) != Load2->getOperand(4))
2920
// Scale should be 1, Index should be Reg0.
2921
if (Load1->getOperand(1) == Load2->getOperand(1) &&
2922
Load1->getOperand(2) == Load2->getOperand(2)) {
2923
if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
2925
SDValue Op2 = Load1->getOperand(2);
2926
if (!isa<RegisterSDNode>(Op2) ||
2927
cast<RegisterSDNode>(Op2)->getReg() != 0)
2930
// Now let's examine the displacements.
2931
if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
2932
isa<ConstantSDNode>(Load2->getOperand(3))) {
2933
Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
2934
Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
2941
bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2942
int64_t Offset1, int64_t Offset2,
2943
unsigned NumLoads) const {
2944
assert(Offset2 > Offset1);
2945
if ((Offset2 - Offset1) / 8 > 64)
2948
unsigned Opc1 = Load1->getMachineOpcode();
2949
unsigned Opc2 = Load2->getMachineOpcode();
2951
return false; // FIXME: overly conservative?
2958
case X86::MMX_MOVD64rm:
2959
case X86::MMX_MOVQ64rm:
2963
EVT VT = Load1->getValueType(0);
2964
switch (VT.getSimpleVT().SimpleTy) {
2966
// XMM registers. In 64-bit mode we can be a bit more aggressive since we
2967
// have 16 of them to play with.
2968
if (TM.getSubtargetImpl()->is64Bit()) {
2971
} else if (NumLoads)
2990
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2991
assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2992
X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2993
if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2995
Cond[0].setImm(GetOppositeBranchCondition(CC));
3000
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3001
// FIXME: Return false for x87 stack register classes for now. We can't
3002
// allow any loads of these registers before FpGet_ST0_80.
3003
return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3004
RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3008
/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
3009
/// register? e.g. r8, xmm8, xmm13, etc.
3010
bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
3013
case X86::R8: case X86::R9: case X86::R10: case X86::R11:
3014
case X86::R12: case X86::R13: case X86::R14: case X86::R15:
3015
case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
3016
case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
3017
case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
3018
case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
3019
case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
3020
case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
3021
case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
3022
case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
3029
/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
3030
/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
3031
/// size, and 3) use of X86-64 extended registers.
3032
unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
3034
const TargetInstrDesc &Desc = MI.getDesc();
3036
// Pseudo instructions do not need REX prefix byte.
3037
if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
3039
if (Desc.TSFlags & X86II::REX_W)
3042
unsigned NumOps = Desc.getNumOperands();
3044
bool isTwoAddr = NumOps > 1 &&
3045
Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
3047
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
3048
unsigned i = isTwoAddr ? 1 : 0;
3049
for (unsigned e = NumOps; i != e; ++i) {
3050
const MachineOperand& MO = MI.getOperand(i);
3052
unsigned Reg = MO.getReg();
3053
if (isX86_64NonExtLowByteReg(Reg))
3058
switch (Desc.TSFlags & X86II::FormMask) {
3059
case X86II::MRMInitReg:
3060
if (isX86_64ExtendedReg(MI.getOperand(0)))
3061
REX |= (1 << 0) | (1 << 2);
3063
case X86II::MRMSrcReg: {
3064
if (isX86_64ExtendedReg(MI.getOperand(0)))
3066
i = isTwoAddr ? 2 : 1;
3067
for (unsigned e = NumOps; i != e; ++i) {
3068
const MachineOperand& MO = MI.getOperand(i);
3069
if (isX86_64ExtendedReg(MO))
3074
case X86II::MRMSrcMem: {
3075
if (isX86_64ExtendedReg(MI.getOperand(0)))
3078
i = isTwoAddr ? 2 : 1;
3079
for (; i != NumOps; ++i) {
3080
const MachineOperand& MO = MI.getOperand(i);
3082
if (isX86_64ExtendedReg(MO))
3089
case X86II::MRM0m: case X86II::MRM1m:
3090
case X86II::MRM2m: case X86II::MRM3m:
3091
case X86II::MRM4m: case X86II::MRM5m:
3092
case X86II::MRM6m: case X86II::MRM7m:
3093
case X86II::MRMDestMem: {
3094
unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
3095
i = isTwoAddr ? 1 : 0;
3096
if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
3099
for (; i != e; ++i) {
3100
const MachineOperand& MO = MI.getOperand(i);
3102
if (isX86_64ExtendedReg(MO))
3110
if (isX86_64ExtendedReg(MI.getOperand(0)))
3112
i = isTwoAddr ? 2 : 1;
3113
for (unsigned e = NumOps; i != e; ++i) {
3114
const MachineOperand& MO = MI.getOperand(i);
3115
if (isX86_64ExtendedReg(MO))
3125
/// sizePCRelativeBlockAddress - This method returns the size of a PC
3126
/// relative block address instruction
3128
static unsigned sizePCRelativeBlockAddress() {
3132
/// sizeGlobalAddress - Give the size of the emission of this global address
3134
static unsigned sizeGlobalAddress(bool dword) {
3135
return dword ? 8 : 4;
3138
/// sizeConstPoolAddress - Give the size of the emission of this constant
3141
static unsigned sizeConstPoolAddress(bool dword) {
3142
return dword ? 8 : 4;
3145
/// sizeExternalSymbolAddress - Give the size of the emission of this external
3148
static unsigned sizeExternalSymbolAddress(bool dword) {
3149
return dword ? 8 : 4;
3152
/// sizeJumpTableAddress - Give the size of the emission of this jump
3155
static unsigned sizeJumpTableAddress(bool dword) {
3156
return dword ? 8 : 4;
3159
static unsigned sizeConstant(unsigned Size) {
3163
static unsigned sizeRegModRMByte(){
3167
static unsigned sizeSIBByte(){
3171
static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
3172
unsigned FinalSize = 0;
3173
// If this is a simple integer displacement that doesn't require a relocation.
3175
FinalSize += sizeConstant(4);
3179
// Otherwise, this is something that requires a relocation.
3180
if (RelocOp->isGlobal()) {
3181
FinalSize += sizeGlobalAddress(false);
3182
} else if (RelocOp->isCPI()) {
3183
FinalSize += sizeConstPoolAddress(false);
3184
} else if (RelocOp->isJTI()) {
3185
FinalSize += sizeJumpTableAddress(false);
3187
llvm_unreachable("Unknown value to relocate!");
3192
static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
3193
bool IsPIC, bool Is64BitMode) {
3194
const MachineOperand &Op3 = MI.getOperand(Op+3);
3196
const MachineOperand *DispForReloc = 0;
3197
unsigned FinalSize = 0;
3199
// Figure out what sort of displacement we have to handle here.
3200
if (Op3.isGlobal()) {
3201
DispForReloc = &Op3;
3202
} else if (Op3.isCPI()) {
3203
if (Is64BitMode || IsPIC) {
3204
DispForReloc = &Op3;
3208
} else if (Op3.isJTI()) {
3209
if (Is64BitMode || IsPIC) {
3210
DispForReloc = &Op3;
3218
const MachineOperand &Base = MI.getOperand(Op);
3219
const MachineOperand &IndexReg = MI.getOperand(Op+2);
3221
unsigned BaseReg = Base.getReg();
3223
// Is a SIB byte needed?
3224
if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
3225
IndexReg.getReg() == 0 &&
3226
(BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
3227
if (BaseReg == 0) { // Just a displacement?
3228
// Emit special case [disp32] encoding
3230
FinalSize += getDisplacementFieldSize(DispForReloc);
3232
unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
3233
if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
3234
// Emit simple indirect register encoding... [EAX] f.e.
3236
// Be pessimistic and assume it's a disp32, not a disp8
3238
// Emit the most general non-SIB encoding: [REG+disp32]
3240
FinalSize += getDisplacementFieldSize(DispForReloc);
3244
} else { // We need a SIB byte, so start by outputting the ModR/M byte first
3245
assert(IndexReg.getReg() != X86::ESP &&
3246
IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
3248
bool ForceDisp32 = false;
3249
if (BaseReg == 0 || DispForReloc) {
3250
// Emit the normal disp32 encoding.
3257
FinalSize += sizeSIBByte();
3259
// Do we need to output a displacement?
3260
if (DispVal != 0 || ForceDisp32) {
3261
FinalSize += getDisplacementFieldSize(DispForReloc);
3268
static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
3269
const TargetInstrDesc *Desc,
3270
bool IsPIC, bool Is64BitMode) {
3272
unsigned Opcode = Desc->Opcode;
3273
unsigned FinalSize = 0;
3275
// Emit the lock opcode prefix as needed.
3276
if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
3278
// Emit segment override opcode prefix as needed.
3279
switch (Desc->TSFlags & X86II::SegOvrMask) {
3284
default: llvm_unreachable("Invalid segment!");
3285
case 0: break; // No segment override!
3288
// Emit the repeat opcode prefix as needed.
3289
if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
3291
// Emit the operand size opcode prefix as needed.
3292
if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
3294
// Emit the address size opcode prefix as needed.
3295
if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
3297
bool Need0FPrefix = false;
3298
switch (Desc->TSFlags & X86II::Op0Mask) {
3299
case X86II::TB: // Two-byte opcode prefix
3300
case X86II::T8: // 0F 38
3301
case X86II::TA: // 0F 3A
3302
Need0FPrefix = true;
3304
case X86II::TF: // F2 0F 38
3306
Need0FPrefix = true;
3308
case X86II::REP: break; // already handled.
3309
case X86II::XS: // F3 0F
3311
Need0FPrefix = true;
3313
case X86II::XD: // F2 0F
3315
Need0FPrefix = true;
3317
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3318
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3320
break; // Two-byte opcode prefix
3321
default: llvm_unreachable("Invalid prefix!");
3322
case 0: break; // No prefix!
3327
unsigned REX = X86InstrInfo::determineREX(MI);
3332
// 0x0F escape code must be emitted just before the opcode.
3336
switch (Desc->TSFlags & X86II::Op0Mask) {
3337
case X86II::T8: // 0F 38
3340
case X86II::TA: // 0F 3A
3343
case X86II::TF: // F2 0F 38
3348
// If this is a two-address instruction, skip one of the register operands.
3349
unsigned NumOps = Desc->getNumOperands();
3351
if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3353
else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3354
// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3357
switch (Desc->TSFlags & X86II::FormMask) {
3358
default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3360
// Remember the current PC offset, this is the PIC relocation
3365
case TargetOpcode::INLINEASM: {
3366
const MachineFunction *MF = MI.getParent()->getParent();
3367
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3368
FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3369
*MF->getTarget().getMCAsmInfo());
3372
case TargetOpcode::DBG_LABEL:
3373
case TargetOpcode::EH_LABEL:
3375
case TargetOpcode::IMPLICIT_DEF:
3376
case TargetOpcode::KILL:
3377
case X86::FP_REG_KILL:
3379
case X86::MOVPC32r: {
3380
// This emits the "call" portion of this pseudo instruction.
3382
FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3391
if (CurOp != NumOps) {
3392
const MachineOperand &MO = MI.getOperand(CurOp++);
3394
FinalSize += sizePCRelativeBlockAddress();
3395
} else if (MO.isGlobal()) {
3396
FinalSize += sizeGlobalAddress(false);
3397
} else if (MO.isSymbol()) {
3398
FinalSize += sizeExternalSymbolAddress(false);
3399
} else if (MO.isImm()) {
3400
FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3402
llvm_unreachable("Unknown RawFrm operand!");
3407
case X86II::AddRegFrm:
3411
if (CurOp != NumOps) {
3412
const MachineOperand &MO1 = MI.getOperand(CurOp++);
3413
unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3415
FinalSize += sizeConstant(Size);
3418
if (Opcode == X86::MOV64ri)
3420
if (MO1.isGlobal()) {
3421
FinalSize += sizeGlobalAddress(dword);
3422
} else if (MO1.isSymbol())
3423
FinalSize += sizeExternalSymbolAddress(dword);
3424
else if (MO1.isCPI())
3425
FinalSize += sizeConstPoolAddress(dword);
3426
else if (MO1.isJTI())
3427
FinalSize += sizeJumpTableAddress(dword);
3432
case X86II::MRMDestReg: {
3434
FinalSize += sizeRegModRMByte();
3436
if (CurOp != NumOps) {
3438
FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3442
case X86II::MRMDestMem: {
3444
FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3445
CurOp += X86AddrNumOperands + 1;
3446
if (CurOp != NumOps) {
3448
FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3453
case X86II::MRMSrcReg:
3455
FinalSize += sizeRegModRMByte();
3457
if (CurOp != NumOps) {
3459
FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3463
case X86II::MRMSrcMem: {
3465
if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3466
Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3467
AddrOperands = X86AddrNumOperands - 1; // No segment register
3469
AddrOperands = X86AddrNumOperands;
3472
FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3473
CurOp += AddrOperands + 1;
3474
if (CurOp != NumOps) {
3476
FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3481
case X86II::MRM0r: case X86II::MRM1r:
3482
case X86II::MRM2r: case X86II::MRM3r:
3483
case X86II::MRM4r: case X86II::MRM5r:
3484
case X86II::MRM6r: case X86II::MRM7r:
3486
if (Desc->getOpcode() == X86::LFENCE ||
3487
Desc->getOpcode() == X86::MFENCE) {
3488
// Special handling of lfence and mfence;
3489
FinalSize += sizeRegModRMByte();
3490
} else if (Desc->getOpcode() == X86::MONITOR ||
3491
Desc->getOpcode() == X86::MWAIT) {
3492
// Special handling of monitor and mwait.
3493
FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3496
FinalSize += sizeRegModRMByte();
3499
if (CurOp != NumOps) {
3500
const MachineOperand &MO1 = MI.getOperand(CurOp++);
3501
unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3503
FinalSize += sizeConstant(Size);
3506
if (Opcode == X86::MOV64ri32)
3508
if (MO1.isGlobal()) {
3509
FinalSize += sizeGlobalAddress(dword);
3510
} else if (MO1.isSymbol())
3511
FinalSize += sizeExternalSymbolAddress(dword);
3512
else if (MO1.isCPI())
3513
FinalSize += sizeConstPoolAddress(dword);
3514
else if (MO1.isJTI())
3515
FinalSize += sizeJumpTableAddress(dword);
3520
case X86II::MRM0m: case X86II::MRM1m:
3521
case X86II::MRM2m: case X86II::MRM3m:
3522
case X86II::MRM4m: case X86II::MRM5m:
3523
case X86II::MRM6m: case X86II::MRM7m: {
3526
FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3527
CurOp += X86AddrNumOperands;
3529
if (CurOp != NumOps) {
3530
const MachineOperand &MO = MI.getOperand(CurOp++);
3531
unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3533
FinalSize += sizeConstant(Size);
3536
if (Opcode == X86::MOV64mi32)
3538
if (MO.isGlobal()) {
3539
FinalSize += sizeGlobalAddress(dword);
3540
} else if (MO.isSymbol())
3541
FinalSize += sizeExternalSymbolAddress(dword);
3542
else if (MO.isCPI())
3543
FinalSize += sizeConstPoolAddress(dword);
3544
else if (MO.isJTI())
3545
FinalSize += sizeJumpTableAddress(dword);
3559
case X86II::MRMInitReg:
3561
// Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3562
FinalSize += sizeRegModRMByte();
3567
if (!Desc->isVariadic() && CurOp != NumOps) {
3569
raw_string_ostream Msg(msg);
3570
Msg << "Cannot determine size: " << MI;
3571
llvm_report_error(Msg.str());
3579
unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3580
const TargetInstrDesc &Desc = MI->getDesc();
3581
bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3582
bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3583
unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3584
if (Desc.getOpcode() == X86::MOVPC32r)
3585
Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3589
/// getGlobalBaseReg - Return a virtual register initialized with the
3590
/// the global base register value. Output instructions required to
3591
/// initialize the register in the function entry block, if necessary.
3593
unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3594
assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3595
"X86-64 PIC uses RIP relative addressing");
3597
X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3598
unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3599
if (GlobalBaseReg != 0)
3600
return GlobalBaseReg;
3602
// Insert the set of GlobalBaseReg into the first MBB of the function
3603
MachineBasicBlock &FirstMBB = MF->front();
3604
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3605
DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3606
MachineRegisterInfo &RegInfo = MF->getRegInfo();
3607
unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3609
const TargetInstrInfo *TII = TM.getInstrInfo();
3610
// Operand of MovePCtoStack is completely ignored by asm printer. It's
3611
// only used in JIT code emission as displacement to pc.
3612
BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3614
// If we're using vanilla 'GOT' PIC style, we should use relative addressing
3615
// not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3616
if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3617
GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3618
// Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3619
BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3620
.addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3621
X86II::MO_GOT_ABSOLUTE_ADDRESS);
3626
X86FI->setGlobalBaseReg(GlobalBaseReg);
3627
return GlobalBaseReg;
added
removed
libclamav/c++/llvm/lib/Target/X86/X86InstrInfo.cpp
