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//===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This register allocator allocates registers to a basic block at a time,
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// attempting to keep values in registers and reusing registers as appropriate.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "llvm/BasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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STATISTIC(NumStores, "Number of stores added");
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STATISTIC(NumLoads , "Number of loads added");
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static RegisterRegAlloc
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localRegAlloc("local", "local register allocator",
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createLocalRegisterAllocator);
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class RALocal : public MachineFunctionPass {
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RALocal() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
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const TargetMachine *TM;
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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// StackSlotForVirtReg - Maps virtual regs to the frame index where these
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// values are spilled.
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IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
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// Virt2PhysRegMap - This map contains entries for each virtual register
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// that is currently available in a physical register.
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IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
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unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
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return Virt2PhysRegMap[VirtReg];
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// PhysRegsUsed - This array is effectively a map, containing entries for
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// each physical register that currently has a value (ie, it is in
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// Virt2PhysRegMap). The value mapped to is the virtual register
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// corresponding to the physical register (the inverse of the
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// Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
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// because it is used by a future instruction, and to -2 if it is not
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// allocatable. If the entry for a physical register is -1, then the
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// physical register is "not in the map".
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std::vector<int> PhysRegsUsed;
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// PhysRegsUseOrder - This contains a list of the physical registers that
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// currently have a virtual register value in them. This list provides an
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// ordering of registers, imposing a reallocation order. This list is only
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// used if all registers are allocated and we have to spill one, in which
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// case we spill the least recently used register. Entries at the front of
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// the list are the least recently used registers, entries at the back are
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// the most recently used.
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std::vector<unsigned> PhysRegsUseOrder;
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// Virt2LastUseMap - This maps each virtual register to its last use
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// (MachineInstr*, operand index pair).
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IndexedMap<std::pair<MachineInstr*, unsigned>, VirtReg2IndexFunctor>
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std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) {
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assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
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return Virt2LastUseMap[Reg];
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// VirtRegModified - This bitset contains information about which virtual
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// registers need to be spilled back to memory when their registers are
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// scavenged. If a virtual register has simply been rematerialized, there
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// is no reason to spill it to memory when we need the register back.
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BitVector VirtRegModified;
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// UsedInMultipleBlocks - Tracks whether a particular register is used in
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// more than one block.
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BitVector UsedInMultipleBlocks;
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void markVirtRegModified(unsigned Reg, bool Val = true) {
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assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
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Reg -= TargetRegisterInfo::FirstVirtualRegister;
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VirtRegModified.set(Reg);
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VirtRegModified.reset(Reg);
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bool isVirtRegModified(unsigned Reg) const {
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assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
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assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
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&& "Illegal virtual register!");
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return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
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void AddToPhysRegsUseOrder(unsigned Reg) {
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std::vector<unsigned>::iterator It =
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std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg);
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if (It != PhysRegsUseOrder.end())
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PhysRegsUseOrder.erase(It);
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PhysRegsUseOrder.push_back(Reg);
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void MarkPhysRegRecentlyUsed(unsigned Reg) {
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if (PhysRegsUseOrder.empty() ||
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PhysRegsUseOrder.back() == Reg) return; // Already most recently used
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for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
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if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
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unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
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PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
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// Add it to the end of the list
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PhysRegsUseOrder.push_back(RegMatch);
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return; // Found an exact match, exit early
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virtual const char *getPassName() const {
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return "Local Register Allocator";
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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MachineFunctionPass::getAnalysisUsage(AU);
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/// runOnMachineFunction - Register allocate the whole function
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bool runOnMachineFunction(MachineFunction &Fn);
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/// AllocateBasicBlock - Register allocate the specified basic block.
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void AllocateBasicBlock(MachineBasicBlock &MBB);
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/// areRegsEqual - This method returns true if the specified registers are
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/// related to each other. To do this, it checks to see if they are equal
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/// or if the first register is in the alias set of the second register.
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bool areRegsEqual(unsigned R1, unsigned R2) const {
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if (R1 == R2) return true;
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for (const unsigned *AliasSet = TRI->getAliasSet(R2);
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*AliasSet; ++AliasSet) {
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if (*AliasSet == R1) return true;
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/// getStackSpaceFor - This returns the frame index of the specified virtual
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/// register on the stack, allocating space if necessary.
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int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
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/// removePhysReg - This method marks the specified physical register as no
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/// longer being in use.
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void removePhysReg(unsigned PhysReg);
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/// spillVirtReg - This method spills the value specified by PhysReg into
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/// the virtual register slot specified by VirtReg. It then updates the RA
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/// data structures to indicate the fact that PhysReg is now available.
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void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned VirtReg, unsigned PhysReg);
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/// spillPhysReg - This method spills the specified physical register into
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/// the virtual register slot associated with it. If OnlyVirtRegs is set to
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/// true, then the request is ignored if the physical register does not
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/// contain a virtual register.
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void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
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unsigned PhysReg, bool OnlyVirtRegs = false);
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/// assignVirtToPhysReg - This method updates local state so that we know
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/// that PhysReg is the proper container for VirtReg now. The physical
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/// register must not be used for anything else when this is called.
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void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
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/// isPhysRegAvailable - Return true if the specified physical register is
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/// free and available for use. This also includes checking to see if
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/// aliased registers are all free...
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bool isPhysRegAvailable(unsigned PhysReg) const;
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/// getFreeReg - Look to see if there is a free register available in the
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/// specified register class. If not, return 0.
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unsigned getFreeReg(const TargetRegisterClass *RC);
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/// getReg - Find a physical register to hold the specified virtual
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/// register. If all compatible physical registers are used, this method
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/// spills the last used virtual register to the stack, and uses that
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/// register. If NoFree is true, that means the caller knows there isn't
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/// a free register, do not call getFreeReg().
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unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned VirtReg, bool NoFree = false);
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/// reloadVirtReg - This method transforms the specified virtual
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/// register use to refer to a physical register. This method may do this
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/// in one of several ways: if the register is available in a physical
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/// register already, it uses that physical register. If the value is not
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/// in a physical register, and if there are physical registers available,
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/// it loads it into a register: PhysReg if that is an available physical
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/// register, otherwise any physical register of the right class.
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/// If register pressure is high, and it is possible, it tries to fold the
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/// load of the virtual register into the instruction itself. It avoids
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/// doing this if register pressure is low to improve the chance that
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/// subsequent instructions can use the reloaded value. This method
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/// returns the modified instruction.
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MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned OpNum, SmallSet<unsigned, 4> &RRegs,
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/// ComputeLocalLiveness - Computes liveness of registers within a basic
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/// block, setting the killed/dead flags as appropriate.
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void ComputeLocalLiveness(MachineBasicBlock& MBB);
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void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
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char RALocal::ID = 0;
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/// getStackSpaceFor - This allocates space for the specified virtual register
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/// to be held on the stack.
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int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
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// Find the location Reg would belong...
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int SS = StackSlotForVirtReg[VirtReg];
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return SS; // Already has space allocated?
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// Allocate a new stack object for this spill location...
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int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
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// Assign the slot...
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StackSlotForVirtReg[VirtReg] = FrameIdx;
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/// removePhysReg - This method marks the specified physical register as no
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/// longer being in use.
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void RALocal::removePhysReg(unsigned PhysReg) {
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PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
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std::vector<unsigned>::iterator It =
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std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
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if (It != PhysRegsUseOrder.end())
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PhysRegsUseOrder.erase(It);
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/// spillVirtReg - This method spills the value specified by PhysReg into the
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/// virtual register slot specified by VirtReg. It then updates the RA data
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/// structures to indicate the fact that PhysReg is now available.
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void RALocal::spillVirtReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned VirtReg, unsigned PhysReg) {
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assert(VirtReg && "Spilling a physical register is illegal!"
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" Must not have appropriate kill for the register or use exists beyond"
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" the intended one.");
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DEBUG(dbgs() << " Spilling register " << TRI->getName(PhysReg)
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<< " containing %reg" << VirtReg);
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if (!isVirtRegModified(VirtReg)) {
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DEBUG(dbgs() << " which has not been modified, so no store necessary!");
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std::pair<MachineInstr*, unsigned> &LastUse = getVirtRegLastUse(VirtReg);
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LastUse.first->getOperand(LastUse.second).setIsKill();
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// Otherwise, there is a virtual register corresponding to this physical
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// register. We only need to spill it into its stack slot if it has been
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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DEBUG(dbgs() << " to stack slot #" << FrameIndex);
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// If the instruction reads the register that's spilled, (e.g. this can
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// happen if it is a move to a physical register), then the spill
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// instruction is not a kill.
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bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
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TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
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++NumStores; // Update statistics
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getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
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DEBUG(dbgs() << '\n');
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removePhysReg(PhysReg);
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/// spillPhysReg - This method spills the specified physical register into the
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/// virtual register slot associated with it. If OnlyVirtRegs is set to true,
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/// then the request is ignored if the physical register does not contain a
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/// virtual register.
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void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
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unsigned PhysReg, bool OnlyVirtRegs) {
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if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
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assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
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if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
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spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
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// If the selected register aliases any other registers, we must make
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// sure that one of the aliases isn't alive.
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for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
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*AliasSet; ++AliasSet)
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if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
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PhysRegsUsed[*AliasSet] != -2) // If allocatable.
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if (PhysRegsUsed[*AliasSet])
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spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
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/// assignVirtToPhysReg - This method updates local state so that we know
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/// that PhysReg is the proper container for VirtReg now. The physical
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/// register must not be used for anything else when this is called.
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void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
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assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
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// Update information to note the fact that this register was just used, and
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PhysRegsUsed[PhysReg] = VirtReg;
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getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
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AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg
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/// isPhysRegAvailable - Return true if the specified physical register is free
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/// and available for use. This also includes checking to see if aliased
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/// registers are all free...
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bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
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if (PhysRegsUsed[PhysReg] != -1) return false;
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// If the selected register aliases any other allocated registers, it is
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for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
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*AliasSet; ++AliasSet)
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if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use?
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return false; // Can't use this reg then.
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/// getFreeReg - Look to see if there is a free register available in the
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/// specified register class. If not, return 0.
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unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
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// Get iterators defining the range of registers that are valid to allocate in
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// this class, which also specifies the preferred allocation order.
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TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
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TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
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for (; RI != RE; ++RI)
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if (isPhysRegAvailable(*RI)) { // Is reg unused?
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assert(*RI != 0 && "Cannot use register!");
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return *RI; // Found an unused register!
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/// getReg - Find a physical register to hold the specified virtual
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/// register. If all compatible physical registers are used, this method spills
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/// the last used virtual register to the stack, and uses that register.
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unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
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unsigned VirtReg, bool NoFree) {
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
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// First check to see if we have a free register of the requested type...
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unsigned PhysReg = NoFree ? 0 : getFreeReg(RC);
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// If we didn't find an unused register, scavenge one now!
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assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
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// Loop over all of the preallocated registers from the least recently used
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// to the most recently used. When we find one that is capable of holding
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// our register, use it.
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for (unsigned i = 0; PhysReg == 0; ++i) {
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assert(i != PhysRegsUseOrder.size() &&
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"Couldn't find a register of the appropriate class!");
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unsigned R = PhysRegsUseOrder[i];
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// We can only use this register if it holds a virtual register (ie, it
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// can be spilled). Do not use it if it is an explicitly allocated
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// physical register!
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assert(PhysRegsUsed[R] != -1 &&
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"PhysReg in PhysRegsUseOrder, but is not allocated?");
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if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
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// If the current register is compatible, use it.
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if (RC->contains(R)) {
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// If one of the registers aliased to the current register is
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// compatible, use it.
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for (const unsigned *AliasIt = TRI->getAliasSet(R);
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*AliasIt; ++AliasIt) {
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if (RC->contains(*AliasIt) &&
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// If this is pinned down for some reason, don't use it. For
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// example, if CL is pinned, and we run across CH, don't use
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// CH as justification for using scavenging ECX (which will
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PhysRegsUsed[*AliasIt] != 0 &&
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// Make sure the register is allocatable. Don't allocate SIL on
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PhysRegsUsed[*AliasIt] != -2) {
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PhysReg = *AliasIt; // Take an aliased register
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assert(PhysReg && "Physical register not assigned!?!?");
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// At this point PhysRegsUseOrder[i] is the least recently used register of
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// compatible register class. Spill it to memory and reap its remains.
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spillPhysReg(MBB, I, PhysReg);
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// Now that we know which register we need to assign this to, do it now!
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assignVirtToPhysReg(VirtReg, PhysReg);
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/// reloadVirtReg - This method transforms the specified virtual
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/// register use to refer to a physical register. This method may do this in
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/// one of several ways: if the register is available in a physical register
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/// already, it uses that physical register. If the value is not in a physical
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/// register, and if there are physical registers available, it loads it into a
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/// register: PhysReg if that is an available physical register, otherwise any
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/// register. If register pressure is high, and it is possible, it tries to
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/// fold the load of the virtual register into the instruction itself. It
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/// avoids doing this if register pressure is low to improve the chance that
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/// subsequent instructions can use the reloaded value. This method returns
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/// the modified instruction.
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MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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SmallSet<unsigned, 4> &ReloadedRegs,
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unsigned VirtReg = MI->getOperand(OpNum).getReg();
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// If the virtual register is already available, just update the instruction
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if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
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MI->getOperand(OpNum).setReg(PR); // Assign the input register
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if (!MI->isDebugValue()) {
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// Do not do these for DBG_VALUE as they can affect codegen.
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MarkPhysRegRecentlyUsed(PR); // Already have this value available!
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getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
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// Otherwise, we need to fold it into the current instruction, or reload it.
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// If we have registers available to hold the value, use them.
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
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// If we already have a PhysReg (this happens when the instruction is a
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// reg-to-reg copy with a PhysReg destination) use that.
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if (!PhysReg || !TargetRegisterInfo::isPhysicalRegister(PhysReg) ||
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!isPhysRegAvailable(PhysReg))
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PhysReg = getFreeReg(RC);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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if (PhysReg) { // Register is available, allocate it!
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assignVirtToPhysReg(VirtReg, PhysReg);
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} else { // No registers available.
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// Force some poor hapless value out of the register file to
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// make room for the new register, and reload it.
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PhysReg = getReg(MBB, MI, VirtReg, true);
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markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
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DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into "
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<< TRI->getName(PhysReg) << "\n");
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// Add move instruction(s)
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TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
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++NumLoads; // Update statistics
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MF->getRegInfo().setPhysRegUsed(PhysReg);
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MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
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getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
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if (!ReloadedRegs.insert(PhysReg)) {
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raw_string_ostream Msg(msg);
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Msg << "Ran out of registers during register allocation!";
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if (MI->isInlineAsm()) {
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Msg << "\nPlease check your inline asm statement for invalid "
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llvm_report_error(Msg.str());
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for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
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*SubRegs; ++SubRegs) {
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if (!ReloadedRegs.insert(*SubRegs)) {
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raw_string_ostream Msg(msg);
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Msg << "Ran out of registers during register allocation!";
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if (MI->isInlineAsm()) {
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Msg << "\nPlease check your inline asm statement for invalid "
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llvm_report_error(Msg.str());
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/// isReadModWriteImplicitKill - True if this is an implicit kill for a
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/// read/mod/write register, i.e. update partial register.
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static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
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MO.isDef() && !MO.isDead())
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/// isReadModWriteImplicitDef - True if this is an implicit def for a
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/// read/mod/write register, i.e. update partial register.
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static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
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!MO.isDef() && MO.isKill())
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// precedes - Helper function to determine with MachineInstr A
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// precedes MachineInstr B within the same MBB.
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static bool precedes(MachineBasicBlock::iterator A,
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MachineBasicBlock::iterator B) {
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MachineBasicBlock::iterator I = A->getParent()->begin();
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while (I != A->getParent()->end()) {
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/// ComputeLocalLiveness - Computes liveness of registers within a basic
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/// block, setting the killed/dead flags as appropriate.
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void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
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MachineRegisterInfo& MRI = MBB.getParent()->getRegInfo();
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// Keep track of the most recently seen previous use or def of each reg,
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// so that we can update them with dead/kill markers.
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DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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if (I->isDebugValue())
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = I->getOperand(i);
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// Uses don't trigger any flags, but we need to save
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// them for later. Also, we have to process these
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// _before_ processing the defs, since an instr
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// uses regs before it defs them.
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if (MO.isReg() && MO.getReg() && MO.isUse()) {
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LastUseDef[MO.getReg()] = std::make_pair(I, i);
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if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
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const unsigned* Aliases = TRI->getAliasSet(MO.getReg());
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DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
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alias = LastUseDef.find(*Aliases);
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if (alias != LastUseDef.end() && alias->second.first != I)
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LastUseDef[*Aliases] = std::make_pair(I, i);
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = I->getOperand(i);
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// Defs others than 2-addr redefs _do_ trigger flag changes:
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// - A def followed by a def is dead
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// - A use followed by a def is a kill
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if (MO.isReg() && MO.getReg() && MO.isDef()) {
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DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
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last = LastUseDef.find(MO.getReg());
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if (last != LastUseDef.end()) {
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// Check if this is a two address instruction. If so, then
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// the def does not kill the use.
655
if (last->second.first == I &&
656
I->isRegTiedToUseOperand(i))
659
MachineOperand& lastUD =
660
last->second.first->getOperand(last->second.second);
662
lastUD.setIsDead(true);
664
lastUD.setIsKill(true);
667
LastUseDef[MO.getReg()] = std::make_pair(I, i);
672
// Live-out (of the function) registers contain return values of the function,
673
// so we need to make sure they are alive at return time.
674
if (!MBB.empty() && MBB.back().getDesc().isReturn()) {
675
MachineInstr* Ret = &MBB.back();
676
for (MachineRegisterInfo::liveout_iterator
677
I = MF->getRegInfo().liveout_begin(),
678
E = MF->getRegInfo().liveout_end(); I != E; ++I)
679
if (!Ret->readsRegister(*I)) {
680
Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
681
LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
685
// Finally, loop over the final use/def of each reg
686
// in the block and determine if it is dead.
687
for (DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
688
I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
689
MachineInstr* MI = I->second.first;
690
unsigned idx = I->second.second;
691
MachineOperand& MO = MI->getOperand(idx);
693
bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
695
// A crude approximation of "live-out" calculation
696
bool usedOutsideBlock = isPhysReg ? false :
697
UsedInMultipleBlocks.test(MO.getReg() -
698
TargetRegisterInfo::FirstVirtualRegister);
699
if (!isPhysReg && !usedOutsideBlock) {
700
// DBG_VALUE complicates this: if the only refs of a register outside
701
// this block are DBG_VALUE, we can't keep the reg live just for that,
702
// as it will cause the reg to be spilled at the end of this block when
703
// it wouldn't have been otherwise. Nullify the DBG_VALUEs when that
705
bool UsedByDebugValueOnly = false;
706
for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
707
UE = MRI.reg_end(); UI != UE; ++UI)
709
// - used in another block
710
// - used in the same block before it is defined (loop)
711
if (UI->getParent() != &MBB ||
712
(MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI))) {
713
if (UI->isDebugValue()) {
714
UsedByDebugValueOnly = true;
717
// A non-DBG_VALUE use means we can leave DBG_VALUE uses alone.
718
UsedInMultipleBlocks.set(MO.getReg() -
719
TargetRegisterInfo::FirstVirtualRegister);
720
usedOutsideBlock = true;
721
UsedByDebugValueOnly = false;
724
if (UsedByDebugValueOnly)
725
for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
726
UE = MRI.reg_end(); UI != UE; ++UI)
727
if (UI->isDebugValue() &&
728
(UI->getParent() != &MBB ||
729
(MO.isDef() && precedes(&*UI, MI))))
730
UI.getOperand().setReg(0U);
733
// Physical registers and those that are not live-out of the block
734
// are killed/dead at their last use/def within this block.
735
if (isPhysReg || !usedOutsideBlock) {
737
// Don't mark uses that are tied to defs as kills.
738
if (!MI->isRegTiedToDefOperand(idx))
746
void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
747
// loop over each instruction
748
MachineBasicBlock::iterator MII = MBB.begin();
751
const BasicBlock *LBB = MBB.getBasicBlock();
753
dbgs() << "\nStarting RegAlloc of BB: " << LBB->getName();
756
// Add live-in registers as active.
757
for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
758
E = MBB.livein_end(); I != E; ++I) {
760
MF->getRegInfo().setPhysRegUsed(Reg);
761
PhysRegsUsed[Reg] = 0; // It is free and reserved now
762
AddToPhysRegsUseOrder(Reg);
763
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
764
*SubRegs; ++SubRegs) {
765
if (PhysRegsUsed[*SubRegs] != -2) {
766
AddToPhysRegsUseOrder(*SubRegs);
767
PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
768
MF->getRegInfo().setPhysRegUsed(*SubRegs);
773
ComputeLocalLiveness(MBB);
775
// Otherwise, sequentially allocate each instruction in the MBB.
776
while (MII != MBB.end()) {
777
MachineInstr *MI = MII++;
778
const TargetInstrDesc &TID = MI->getDesc();
780
dbgs() << "\nStarting RegAlloc of: " << *MI;
781
dbgs() << " Regs have values: ";
782
for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
783
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
784
dbgs() << "[" << TRI->getName(i)
785
<< ",%reg" << PhysRegsUsed[i] << "] ";
789
// Determine whether this is a copy instruction. The cases where the
790
// source or destination are phys regs are handled specially.
791
unsigned SrcCopyReg, DstCopyReg, SrcCopySubReg, DstCopySubReg;
792
unsigned SrcCopyPhysReg = 0U;
793
bool isCopy = TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
794
SrcCopySubReg, DstCopySubReg);
795
if (isCopy && TargetRegisterInfo::isVirtualRegister(SrcCopyReg))
796
SrcCopyPhysReg = getVirt2PhysRegMapSlot(SrcCopyReg);
798
// Loop over the implicit uses, making sure that they are at the head of the
799
// use order list, so they don't get reallocated.
800
if (TID.ImplicitUses) {
801
for (const unsigned *ImplicitUses = TID.ImplicitUses;
802
*ImplicitUses; ++ImplicitUses)
803
MarkPhysRegRecentlyUsed(*ImplicitUses);
806
SmallVector<unsigned, 8> Kills;
807
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
808
MachineOperand& MO = MI->getOperand(i);
809
if (MO.isReg() && MO.isKill()) {
810
if (!MO.isImplicit())
811
Kills.push_back(MO.getReg());
812
else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
813
// These are extra physical register kills when a sub-register
814
// is defined (def of a sub-register is a read/mod/write of the
815
// larger registers). Ignore.
816
Kills.push_back(MO.getReg());
820
// If any physical regs are earlyclobber, spill any value they might
821
// have in them, then mark them unallocatable.
822
// If any virtual regs are earlyclobber, allocate them now (before
823
// freeing inputs that are killed).
824
if (MI->isInlineAsm()) {
825
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
826
MachineOperand& MO = MI->getOperand(i);
827
if (MO.isReg() && MO.isDef() && MO.isEarlyClobber() &&
829
if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
830
unsigned DestVirtReg = MO.getReg();
831
unsigned DestPhysReg;
833
// If DestVirtReg already has a value, use it.
834
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
835
DestPhysReg = getReg(MBB, MI, DestVirtReg);
836
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
837
markVirtRegModified(DestVirtReg);
838
getVirtRegLastUse(DestVirtReg) =
839
std::make_pair((MachineInstr*)0, 0);
840
DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
841
<< " to %reg" << DestVirtReg << "\n");
842
MO.setReg(DestPhysReg); // Assign the earlyclobber register
844
unsigned Reg = MO.getReg();
845
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
846
// These are extra physical register defs when a sub-register
847
// is defined (def of a sub-register is a read/mod/write of the
848
// larger registers). Ignore.
849
if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
851
MF->getRegInfo().setPhysRegUsed(Reg);
852
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
853
PhysRegsUsed[Reg] = 0; // It is free and reserved now
854
AddToPhysRegsUseOrder(Reg);
856
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
857
*SubRegs; ++SubRegs) {
858
if (PhysRegsUsed[*SubRegs] != -2) {
859
MF->getRegInfo().setPhysRegUsed(*SubRegs);
860
PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
861
AddToPhysRegsUseOrder(*SubRegs);
869
// If a DBG_VALUE says something is located in a spilled register,
870
// change the DBG_VALUE to be undef, which prevents the register
871
// from being reloaded here. Doing that would change the generated
872
// code, unless another use immediately follows this instruction.
873
if (MI->isDebugValue() &&
874
MI->getNumOperands()==3 && MI->getOperand(0).isReg()) {
875
unsigned VirtReg = MI->getOperand(0).getReg();
876
if (VirtReg && TargetRegisterInfo::isVirtualRegister(VirtReg) &&
877
!getVirt2PhysRegMapSlot(VirtReg))
878
MI->getOperand(0).setReg(0U);
881
// Get the used operands into registers. This has the potential to spill
882
// incoming values if we are out of registers. Note that we completely
883
// ignore physical register uses here. We assume that if an explicit
884
// physical register is referenced by the instruction, that it is guaranteed
885
// to be live-in, or the input is badly hosed.
887
SmallSet<unsigned, 4> ReloadedRegs;
888
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
889
MachineOperand& MO = MI->getOperand(i);
890
// here we are looking for only used operands (never def&use)
891
if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
892
TargetRegisterInfo::isVirtualRegister(MO.getReg()))
893
MI = reloadVirtReg(MBB, MI, i, ReloadedRegs,
894
isCopy ? DstCopyReg : 0);
897
// If this instruction is the last user of this register, kill the
898
// value, freeing the register being used, so it doesn't need to be
899
// spilled to memory.
901
for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
902
unsigned VirtReg = Kills[i];
903
unsigned PhysReg = VirtReg;
904
if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
905
// If the virtual register was never materialized into a register, it
906
// might not be in the map, but it won't hurt to zero it out anyway.
907
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
908
PhysReg = PhysRegSlot;
910
} else if (PhysRegsUsed[PhysReg] == -2) {
911
// Unallocatable register dead, ignore.
914
assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
915
"Silently clearing a virtual register?");
919
DEBUG(dbgs() << " Last use of " << TRI->getName(PhysReg)
920
<< "[%reg" << VirtReg <<"], removing it from live set\n");
921
removePhysReg(PhysReg);
922
for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
923
*SubRegs; ++SubRegs) {
924
if (PhysRegsUsed[*SubRegs] != -2) {
925
DEBUG(dbgs() << " Last use of "
926
<< TRI->getName(*SubRegs) << "[%reg" << VirtReg
927
<<"], removing it from live set\n");
928
removePhysReg(*SubRegs);
934
// Loop over all of the operands of the instruction, spilling registers that
935
// are defined, and marking explicit destinations in the PhysRegsUsed map.
936
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
937
MachineOperand& MO = MI->getOperand(i);
938
if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
939
!MO.isEarlyClobber() &&
940
TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
941
unsigned Reg = MO.getReg();
942
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
943
// These are extra physical register defs when a sub-register
944
// is defined (def of a sub-register is a read/mod/write of the
945
// larger registers). Ignore.
946
if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
948
MF->getRegInfo().setPhysRegUsed(Reg);
949
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
950
PhysRegsUsed[Reg] = 0; // It is free and reserved now
951
AddToPhysRegsUseOrder(Reg);
953
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
954
*SubRegs; ++SubRegs) {
955
if (PhysRegsUsed[*SubRegs] != -2) {
956
MF->getRegInfo().setPhysRegUsed(*SubRegs);
957
PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
958
AddToPhysRegsUseOrder(*SubRegs);
964
// Loop over the implicit defs, spilling them as well.
965
if (TID.ImplicitDefs) {
966
for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
967
*ImplicitDefs; ++ImplicitDefs) {
968
unsigned Reg = *ImplicitDefs;
969
if (PhysRegsUsed[Reg] != -2) {
970
spillPhysReg(MBB, MI, Reg, true);
971
AddToPhysRegsUseOrder(Reg);
972
PhysRegsUsed[Reg] = 0; // It is free and reserved now
974
MF->getRegInfo().setPhysRegUsed(Reg);
975
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
976
*SubRegs; ++SubRegs) {
977
if (PhysRegsUsed[*SubRegs] != -2) {
978
AddToPhysRegsUseOrder(*SubRegs);
979
PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
980
MF->getRegInfo().setPhysRegUsed(*SubRegs);
986
SmallVector<unsigned, 8> DeadDefs;
987
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
988
MachineOperand& MO = MI->getOperand(i);
989
if (MO.isReg() && MO.isDead())
990
DeadDefs.push_back(MO.getReg());
993
// Okay, we have allocated all of the source operands and spilled any values
994
// that would be destroyed by defs of this instruction. Loop over the
995
// explicit defs and assign them to a register, spilling incoming values if
996
// we need to scavenge a register.
998
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
999
MachineOperand& MO = MI->getOperand(i);
1000
if (MO.isReg() && MO.isDef() && MO.getReg() &&
1001
!MO.isEarlyClobber() &&
1002
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1003
unsigned DestVirtReg = MO.getReg();
1004
unsigned DestPhysReg;
1006
// If DestVirtReg already has a value, use it.
1007
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) {
1008
// If this is a copy try to reuse the input as the output;
1009
// that will make the copy go away.
1010
// If this is a copy, the source reg is a phys reg, and
1011
// that reg is available, use that phys reg for DestPhysReg.
1012
// If this is a copy, the source reg is a virtual reg, and
1013
// the phys reg that was assigned to that virtual reg is now
1014
// available, use that phys reg for DestPhysReg. (If it's now
1015
// available that means this was the last use of the source.)
1017
TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) &&
1018
isPhysRegAvailable(SrcCopyReg)) {
1019
DestPhysReg = SrcCopyReg;
1020
assignVirtToPhysReg(DestVirtReg, DestPhysReg);
1021
} else if (isCopy &&
1022
TargetRegisterInfo::isVirtualRegister(SrcCopyReg) &&
1023
SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg) &&
1024
MF->getRegInfo().getRegClass(DestVirtReg)->
1025
contains(SrcCopyPhysReg)) {
1026
DestPhysReg = SrcCopyPhysReg;
1027
assignVirtToPhysReg(DestVirtReg, DestPhysReg);
1029
DestPhysReg = getReg(MBB, MI, DestVirtReg);
1031
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
1032
markVirtRegModified(DestVirtReg);
1033
getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
1034
DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
1035
<< " to %reg" << DestVirtReg << "\n");
1036
MO.setReg(DestPhysReg); // Assign the output register
1040
// If this instruction defines any registers that are immediately dead,
1043
for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
1044
unsigned VirtReg = DeadDefs[i];
1045
unsigned PhysReg = VirtReg;
1046
if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
1047
unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
1048
PhysReg = PhysRegSlot;
1049
assert(PhysReg != 0);
1051
} else if (PhysRegsUsed[PhysReg] == -2) {
1052
// Unallocatable register dead, ignore.
1057
DEBUG(dbgs() << " Register " << TRI->getName(PhysReg)
1058
<< " [%reg" << VirtReg
1059
<< "] is never used, removing it from live set\n");
1060
removePhysReg(PhysReg);
1061
for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
1062
*AliasSet; ++AliasSet) {
1063
if (PhysRegsUsed[*AliasSet] != -2) {
1064
DEBUG(dbgs() << " Register " << TRI->getName(*AliasSet)
1065
<< " [%reg" << *AliasSet
1066
<< "] is never used, removing it from live set\n");
1067
removePhysReg(*AliasSet);
1073
// Finally, if this is a noop copy instruction, zap it. (Except that if
1074
// the copy is dead, it must be kept to avoid messing up liveness info for
1075
// the register scavenger. See pr4100.)
1076
if (TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
1077
SrcCopySubReg, DstCopySubReg) &&
1078
SrcCopyReg == DstCopyReg && DeadDefs.empty())
1082
MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
1084
// Spill all physical registers holding virtual registers now.
1085
for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
1086
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
1087
if (unsigned VirtReg = PhysRegsUsed[i])
1088
spillVirtReg(MBB, MI, VirtReg, i);
1094
// This checking code is very expensive.
1096
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
1097
e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
1098
if (unsigned PR = Virt2PhysRegMap[i]) {
1099
cerr << "Register still mapped: " << i << " -> " << PR << "\n";
1102
assert(AllOk && "Virtual registers still in phys regs?");
1105
// Clear any physical register which appear live at the end of the basic
1106
// block, but which do not hold any virtual registers. e.g., the stack
1108
PhysRegsUseOrder.clear();
1111
/// runOnMachineFunction - Register allocate the whole function
1113
bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
1114
DEBUG(dbgs() << "Machine Function\n");
1116
TM = &Fn.getTarget();
1117
TRI = TM->getRegisterInfo();
1118
TII = TM->getInstrInfo();
1120
PhysRegsUsed.assign(TRI->getNumRegs(), -1);
1122
// At various places we want to efficiently check to see whether a register
1123
// is allocatable. To handle this, we mark all unallocatable registers as
1124
// being pinned down, permanently.
1126
BitVector Allocable = TRI->getAllocatableSet(Fn);
1127
for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
1129
PhysRegsUsed[i] = -2; // Mark the reg unallocable.
1132
// initialize the virtual->physical register map to have a 'null'
1133
// mapping for all virtual registers
1134
unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
1135
StackSlotForVirtReg.grow(LastVirtReg);
1136
Virt2PhysRegMap.grow(LastVirtReg);
1137
Virt2LastUseMap.grow(LastVirtReg);
1138
VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
1139
UsedInMultipleBlocks.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
1141
// Loop over all of the basic blocks, eliminating virtual register references
1142
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
1144
AllocateBasicBlock(*MBB);
1146
StackSlotForVirtReg.clear();
1147
PhysRegsUsed.clear();
1148
VirtRegModified.clear();
1149
UsedInMultipleBlocks.clear();
1150
Virt2PhysRegMap.clear();
1151
Virt2LastUseMap.clear();
1155
FunctionPass *llvm::createLocalRegisterAllocator() {
1156
return new RALocal();
added
removed
libclamav/c++/llvm/lib/CodeGen/RegAllocLocal.cpp
