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Viewing changes to arch/arm/mach-at91/at91sam9260.c

  • Committer: Package Import Robot
  • Author(s): Paolo Pisati, Paolo Pisati
  • Date: 2011-12-06 15:56:07 UTC
  • Revision ID: package-import@ubuntu.com-20111206155607-pcf44kv5fmhk564f
Tags: 3.2.0-1401.1
[ Paolo Pisati ]

* Rebased on top of Ubuntu-3.2.0-3.8
* Tilt-tracking @ ef2487af4bb15bdd0689631774b5a5e3a59f74e2
* Delete debian.ti-omap4/control, it shoudln't be tracked
* Fix architecture spelling (s/armel/armhf/)
* [Config] Update configs following 3.2 import
* [Config] Fix compilation: disable CODA and ARCH_OMAP3
* [Config] Fix compilation: disable Ethernet Faraday
* Update series to precise

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arch/arm/mach-at91/at91sam9260.c
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/cpu.h>
 
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#include <mach/at91_dbgu.h>
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#include <mach/at91sam9260.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_rstc.h>
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#include <mach/at91_shdwc.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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static struct map_desc at91sam9260_io_desc[] __initdata = {
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        {
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                .virtual        = AT91_VA_BASE_SYS,
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                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
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                .length         = SZ_16K,
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                .type           = MT_DEVICE,
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        }
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};
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static struct map_desc at91sam9260_sram_desc[] __initdata = {
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        {
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                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
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                .pfn            = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
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                .length         = AT91SAM9260_SRAM0_SIZE,
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                .type           = MT_DEVICE,
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        }, {
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                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
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                .pfn            = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
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                .length         = AT91SAM9260_SRAM1_SIZE,
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                .type           = MT_DEVICE,
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        }
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};
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static struct map_desc at91sam9g20_sram_desc[] __initdata = {
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        {
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                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
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                .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
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                .length         = AT91SAM9G20_SRAM0_SIZE,
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                .type           = MT_DEVICE,
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        }, {
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                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
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                .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
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                .length         = AT91SAM9G20_SRAM1_SIZE,
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                .type           = MT_DEVICE,
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        }
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};
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static struct map_desc at91sam9xe_sram_desc[] __initdata = {
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        {
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                .pfn            = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
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                .type           = MT_DEVICE,
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        }
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};
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/* --------------------------------------------------------------------
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 *  Clocks
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 * -------------------------------------------------------------------- */
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        CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
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        CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
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        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
 
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        /* more usart lookup table for DT entries */
 
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        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 
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        CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
 
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        CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
 
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        CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
 
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        CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
 
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        CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
 
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        CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
 
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        /* fake hclk clock */
 
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        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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static void __init at91sam9xe_map_io(void)
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{
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        unsigned long cidr, sram_size;
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        cidr = at91_sys_read(AT91_DBGU_CIDR);
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        switch (cidr & AT91_CIDR_SRAMSIZ) {
 
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        unsigned long sram_size;
 
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        switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
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                case AT91_CIDR_SRAMSIZ_32K:
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                        sram_size = 2 * SZ_16K;
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                        break;
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                        sram_size = SZ_16K;
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        }
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        at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
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        at91sam9xe_sram_desc->length = sram_size;
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        iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
 
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        at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
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}
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void __init at91sam9260_map_io(void)
 
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static void __init at91sam9260_map_io(void)
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{
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        /* Map peripherals */
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        iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
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        if (cpu_is_at91sam9xe())
 
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        if (cpu_is_at91sam9xe()) {
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                at91sam9xe_map_io();
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        else if (cpu_is_at91sam9g20())
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                iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
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        else
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                iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
 
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        } else if (cpu_is_at91sam9g20()) {
 
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                at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
 
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                at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
 
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        } else {
 
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                at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
 
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                at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
 
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        }
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}
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void __init at91sam9260_initialize(unsigned long main_clock)
 
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static void __init at91sam9260_initialize(void)
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{
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        at91_arch_reset = at91sam9_alt_reset;
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        pm_power_off = at91sam9260_poweroff;
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        at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
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                        | (1 << AT91SAM9260_ID_IRQ2);
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        /* Init clock subsystem */
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        at91_clock_init(main_clock);
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        /* Register the processor-specific clocks */
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        at91sam9260_register_clocks();
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        /* Register GPIO subsystem */
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        at91_gpio_init(at91sam9260_gpio, 3);
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}
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        0,      /* Advanced Interrupt Controller */
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};
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void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
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{
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        if (!priority)
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                priority = at91sam9260_default_irq_priority;
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        /* Initialize the AIC interrupt controller */
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        at91_aic_init(priority);
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        /* Enable GPIO interrupts */
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        at91_gpio_irq_setup();
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}
 
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struct at91_init_soc __initdata at91sam9260_soc = {
 
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        .map_io = at91sam9260_map_io,
 
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        .default_irq_priority = at91sam9260_default_irq_priority,
 
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        .register_clocks = at91sam9260_register_clocks,
 
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        .init = at91sam9260_initialize,
 
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};