1
/*******************************************************************************
3
Intel(R) Gigabit Ethernet Linux driver
4
Copyright(c) 2007-2011 Intel Corporation.
6
This program is free software; you can redistribute it and/or modify it
7
under the terms and conditions of the GNU General Public License,
8
version 2, as published by the Free Software Foundation.
10
This program is distributed in the hope it will be useful, but WITHOUT
11
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15
You should have received a copy of the GNU General Public License along with
16
this program; if not, write to the Free Software Foundation, Inc.,
17
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
The full GNU General Public License is included in this distribution in
20
the file called "COPYING".
23
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
*******************************************************************************/
28
#ifndef _E1000_DEFINES_H_
29
#define _E1000_DEFINES_H_
31
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
32
#define REQ_TX_DESCRIPTOR_MULTIPLE 8
33
#define REQ_RX_DESCRIPTOR_MULTIPLE 8
35
/* Definitions for power management and wakeup registers */
37
#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
39
/* Wake Up Filter Control */
40
#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
41
#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
42
#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
43
#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
44
#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
46
/* Extended Device Control */
47
#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
48
/* Physical Func Reset Done Indication */
49
#define E1000_CTRL_EXT_PFRSTD 0x00004000
50
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
51
#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
52
#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
53
#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
54
#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
55
#define E1000_CTRL_EXT_EIAME 0x01000000
56
#define E1000_CTRL_EXT_IRCA 0x00000001
57
/* Interrupt delay cancellation */
58
/* Driver loaded bit for FW */
59
#define E1000_CTRL_EXT_DRV_LOAD 0x10000000
60
/* Interrupt acknowledge Auto-mask */
61
/* Clear Interrupt timers after IMS clear */
62
/* packet buffer parity error detection enabled */
63
/* descriptor FIFO parity error detection enable */
64
#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
65
#define E1000_I2CCMD_REG_ADDR_SHIFT 16
66
#define E1000_I2CCMD_PHY_ADDR_SHIFT 24
67
#define E1000_I2CCMD_OPCODE_READ 0x08000000
68
#define E1000_I2CCMD_OPCODE_WRITE 0x00000000
69
#define E1000_I2CCMD_READY 0x20000000
70
#define E1000_I2CCMD_ERROR 0x80000000
71
#define E1000_MAX_SGMII_PHY_REG_ADDR 255
72
#define E1000_I2CCMD_PHY_TIMEOUT 200
73
#define E1000_IVAR_VALID 0x80
74
#define E1000_GPIE_NSICR 0x00000001
75
#define E1000_GPIE_MSIX_MODE 0x00000010
76
#define E1000_GPIE_EIAME 0x40000000
77
#define E1000_GPIE_PBA 0x80000000
79
/* Receive Descriptor bit definitions */
80
#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
81
#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
82
#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
83
#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
84
#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
85
#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
86
#define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */
88
#define E1000_RXDEXT_STATERR_LB 0x00040000
89
#define E1000_RXDEXT_STATERR_CE 0x01000000
90
#define E1000_RXDEXT_STATERR_SE 0x02000000
91
#define E1000_RXDEXT_STATERR_SEQ 0x04000000
92
#define E1000_RXDEXT_STATERR_CXE 0x10000000
93
#define E1000_RXDEXT_STATERR_TCPE 0x20000000
94
#define E1000_RXDEXT_STATERR_IPE 0x40000000
95
#define E1000_RXDEXT_STATERR_RXE 0x80000000
97
/* Same mask, but for extended and packet split descriptors */
98
#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
99
E1000_RXDEXT_STATERR_CE | \
100
E1000_RXDEXT_STATERR_SE | \
101
E1000_RXDEXT_STATERR_SEQ | \
102
E1000_RXDEXT_STATERR_CXE | \
103
E1000_RXDEXT_STATERR_RXE)
105
#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
106
#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
107
#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
108
#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
109
#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
112
/* Management Control */
113
#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
114
#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
115
#define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */
116
/* Enable Neighbor Discovery Filtering */
117
#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
118
#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
119
/* Enable MAC address filtering */
120
#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
122
/* Receive Control */
123
#define E1000_RCTL_EN 0x00000002 /* enable */
124
#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
125
#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
126
#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
127
#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
128
#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
129
#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
130
#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
131
#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
132
#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
133
#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
134
#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
135
#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
136
#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
137
#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
140
* Use byte values for the following shift parameters
142
* psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
143
* E1000_PSRCTL_BSIZE0_MASK) |
144
* ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
145
* E1000_PSRCTL_BSIZE1_MASK) |
146
* ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
147
* E1000_PSRCTL_BSIZE2_MASK) |
148
* ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
149
* E1000_PSRCTL_BSIZE3_MASK))
150
* where value0 = [128..16256], default=256
151
* value1 = [1024..64512], default=4096
152
* value2 = [0..64512], default=4096
153
* value3 = [0..64512], default=0
156
#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
157
#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
158
#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
159
#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
161
#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
162
#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
163
#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
164
#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
166
/* SWFW_SYNC Definitions */
167
#define E1000_SWFW_EEP_SM 0x1
168
#define E1000_SWFW_PHY0_SM 0x2
169
#define E1000_SWFW_PHY1_SM 0x4
170
#define E1000_SWFW_PHY2_SM 0x20
171
#define E1000_SWFW_PHY3_SM 0x40
173
/* FACTPS Definitions */
175
#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
176
#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
177
#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
178
#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
179
#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
180
#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
181
#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
182
#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
183
#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
184
#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
185
#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
186
/* Defined polarity of Dock/Undock indication in SDP[0] */
187
/* Reset both PHY ports, through PHYRST_N pin */
188
/* enable link status from external LINK_0 and LINK_1 pins */
189
#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
190
#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
191
#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
192
#define E1000_CTRL_RST 0x04000000 /* Global reset */
193
#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
194
#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
195
#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
196
#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
197
/* Initiate an interrupt to manageability engine */
198
#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
200
/* Bit definitions for the Management Data IO (MDIO) and Management Data
201
* Clock (MDC) pins in the Device Control Register.
204
#define E1000_CONNSW_ENRGSRC 0x4
205
#define E1000_PCS_CFG_PCS_EN 8
206
#define E1000_PCS_LCTL_FLV_LINK_UP 1
207
#define E1000_PCS_LCTL_FSV_100 2
208
#define E1000_PCS_LCTL_FSV_1000 4
209
#define E1000_PCS_LCTL_FDV_FULL 8
210
#define E1000_PCS_LCTL_FSD 0x10
211
#define E1000_PCS_LCTL_FORCE_LINK 0x20
212
#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
213
#define E1000_PCS_LCTL_AN_ENABLE 0x10000
214
#define E1000_PCS_LCTL_AN_RESTART 0x20000
215
#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
216
#define E1000_ENABLE_SERDES_LOOPBACK 0x0410
218
#define E1000_PCS_LSTS_LINK_OK 1
219
#define E1000_PCS_LSTS_SPEED_100 2
220
#define E1000_PCS_LSTS_SPEED_1000 4
221
#define E1000_PCS_LSTS_DUPLEX_FULL 8
222
#define E1000_PCS_LSTS_SYNK_OK 0x10
225
#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
226
#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
227
#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
228
#define E1000_STATUS_FUNC_SHIFT 2
229
#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
230
#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
231
#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
232
#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
233
/* Change in Dock/Undock state. Clear on write '0'. */
234
/* Status of Master requests. */
235
#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
236
/* BMC external code execution disabled */
238
/* Constants used to intrepret the masked PCI-X bus speed. */
241
#define SPEED_100 100
242
#define SPEED_1000 1000
243
#define HALF_DUPLEX 1
244
#define FULL_DUPLEX 2
247
#define ADVERTISE_10_HALF 0x0001
248
#define ADVERTISE_10_FULL 0x0002
249
#define ADVERTISE_100_HALF 0x0004
250
#define ADVERTISE_100_FULL 0x0008
251
#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
252
#define ADVERTISE_1000_FULL 0x0020
254
/* 1000/H is not supported, nor spec-compliant. */
255
#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
256
ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
258
#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
259
ADVERTISE_100_HALF | ADVERTISE_100_FULL)
260
#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
261
#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
262
#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
264
#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
266
#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
269
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
270
#define E1000_LEDCTL_LED0_BLINK 0x00000080
272
#define E1000_LEDCTL_MODE_LED_ON 0xE
273
#define E1000_LEDCTL_MODE_LED_OFF 0xF
275
/* Transmit Descriptor bit definitions */
276
#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
277
#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
278
#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
279
#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
280
#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
281
#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
282
#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
283
/* Extended desc bits for Linksec and timesync */
285
/* Transmit Control */
286
#define E1000_TCTL_EN 0x00000002 /* enable tx */
287
#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
288
#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
289
#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
290
#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
292
/* DMA Coalescing register fields */
293
#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing
295
#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Receive
297
#define E1000_DMACR_DMACTHR_SHIFT 16
298
#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe
300
#define E1000_DMACR_DMAC_LX_SHIFT 28
301
#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
303
#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit
306
#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
308
#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Receive Traffic Rate
310
#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rcv packet rate in
313
#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rcv Traffic
316
#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rcv Threshold
318
#define E1000_FCRTC_RTH_COAL_SHIFT 4
319
#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */
322
#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
324
/* Receive Checksum Control */
325
#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
326
#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
327
#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
328
#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
330
/* Header split receive */
331
#define E1000_RFCTL_LEF 0x00040000
333
/* Collision related configuration parameters */
334
#define E1000_COLLISION_THRESHOLD 15
335
#define E1000_CT_SHIFT 4
336
#define E1000_COLLISION_DISTANCE 63
337
#define E1000_COLD_SHIFT 12
339
/* Ethertype field values */
340
#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
342
#define MAX_JUMBO_FRAME_SIZE 0x3F00
345
#define E1000_PBA_34K 0x0022
346
#define E1000_PBA_64K 0x0040 /* 64KB */
348
/* SW Semaphore Register */
349
#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
350
#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
352
/* Interrupt Cause Read */
353
#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
354
#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
355
#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
356
#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
357
#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
358
#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
359
#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
360
/* If this bit asserted, the driver should claim the interrupt */
361
#define E1000_ICR_INT_ASSERTED 0x80000000
362
/* LAN connected device generates an interrupt */
363
#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
365
/* Extended Interrupt Cause Read */
366
#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
367
#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
368
#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
369
#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
370
#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
371
#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
372
#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
373
#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
374
#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
378
* This defines the bits that are set in the Interrupt Mask
379
* Set/Read Register. Each bit is documented below:
380
* o RXT0 = Receiver Timer Interrupt (ring 0)
381
* o TXDW = Transmit Descriptor Written Back
382
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
383
* o RXSEQ = Receive Sequence Error
384
* o LSC = Link Status Change
386
#define IMS_ENABLE_MASK ( \
394
/* Interrupt Mask Set */
395
#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
396
#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
397
#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
398
#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
399
#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
400
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
401
#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
402
#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
404
/* Extended Interrupt Mask Set */
405
#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
407
/* Interrupt Cause Set */
408
#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
409
#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
410
#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
412
/* Extended Interrupt Cause Set */
413
/* E1000_EITR_CNT_IGNR is only for 82576 and newer */
414
#define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
417
/* Transmit Descriptor Control */
418
/* Enable the counting of descriptors still to be processed. */
420
/* Flow Control Constants */
421
#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
422
#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
423
#define FLOW_CONTROL_TYPE 0x8808
425
/* 802.1q VLAN Packet Size */
426
#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
427
#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
429
/* Receive Address */
431
* Number of high/low register pairs in the RAR. The RAR (Receive Address
432
* Registers) holds the directed and multicast addresses that we monitor.
433
* Technically, we have 16 spots. However, we reserve one of these spots
434
* (RAR[15]) for our directed address used by controllers with
435
* manageability enabled, allowing us room for 15 multicast addresses.
437
#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
438
#define E1000_RAL_MAC_ADDR_LEN 4
439
#define E1000_RAH_MAC_ADDR_LEN 2
440
#define E1000_RAH_POOL_MASK 0x03FC0000
441
#define E1000_RAH_POOL_1 0x00040000
444
#define E1000_SUCCESS 0
445
#define E1000_ERR_NVM 1
446
#define E1000_ERR_PHY 2
447
#define E1000_ERR_CONFIG 3
448
#define E1000_ERR_PARAM 4
449
#define E1000_ERR_MAC_INIT 5
450
#define E1000_ERR_RESET 9
451
#define E1000_ERR_MASTER_REQUESTS_PENDING 10
452
#define E1000_BLK_PHY_RESET 12
453
#define E1000_ERR_SWFW_SYNC 13
454
#define E1000_NOT_IMPLEMENTED 14
455
#define E1000_ERR_MBX 15
456
#define E1000_ERR_INVALID_ARGUMENT 16
457
#define E1000_ERR_NO_SPACE 17
458
#define E1000_ERR_NVM_PBA_SECTION 18
460
/* Loop limit on how long we wait for auto-negotiation to complete */
461
#define COPPER_LINK_UP_LIMIT 10
462
#define PHY_AUTO_NEG_LIMIT 45
463
#define PHY_FORCE_LIMIT 20
464
/* Number of 100 microseconds we wait for PCI Express master disable */
465
#define MASTER_DISABLE_TIMEOUT 800
466
/* Number of milliseconds we wait for PHY configuration done after MAC reset */
467
#define PHY_CFG_TIMEOUT 100
468
/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
469
/* Number of milliseconds for NVM auto read done after MAC reset. */
470
#define AUTO_READ_DONE_TIMEOUT 10
473
#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
475
#define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */
476
#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */
478
#define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */
479
#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */
480
#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
481
#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
482
#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
483
#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
484
#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
485
#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */
487
#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
488
#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
489
#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
490
#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
491
#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
492
#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
494
#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
495
#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
496
#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
497
#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
498
#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
499
#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
500
#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
501
#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
502
#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
503
#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
504
#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
506
#define E1000_TIMINCA_16NS_SHIFT 24
508
#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
509
#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
510
#define E1000_MDICNFG_PHY_MASK 0x03E00000
511
#define E1000_MDICNFG_PHY_SHIFT 21
513
/* PCI Express Control */
514
#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
515
#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
516
#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
517
#define E1000_GCR_CAP_VER2 0x00040000
519
/* mPHY Address Control and Data Registers */
520
#define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */
521
#define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
522
#define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */
524
/* mPHY PCS CLK Register */
525
#define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */
526
/* mPHY Near End Digital Loopback Override Bit */
527
#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
529
/* PHY Control Register */
530
#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
531
#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
532
#define MII_CR_POWER_DOWN 0x0800 /* Power down */
533
#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
534
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
535
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
536
#define MII_CR_SPEED_1000 0x0040
537
#define MII_CR_SPEED_100 0x2000
538
#define MII_CR_SPEED_10 0x0000
540
/* PHY Status Register */
541
#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
542
#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
544
/* Autoneg Advertisement Register */
545
#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
546
#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
547
#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
548
#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
549
#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
550
#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
552
/* Link Partner Ability Register (Base Page) */
553
#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
554
#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
556
/* Autoneg Expansion Register */
558
/* 1000BASE-T Control Register */
559
#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
560
#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
561
#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
562
/* 0=Configure PHY as Slave */
563
#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
564
/* 0=Automatic Master/Slave config */
566
/* 1000BASE-T Status Register */
567
#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
568
#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
571
/* PHY 1000 MII Register/Bit Definitions */
572
/* PHY Registers defined by IEEE */
573
#define PHY_CONTROL 0x00 /* Control Register */
574
#define PHY_STATUS 0x01 /* Status Register */
575
#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
576
#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
577
#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
578
#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
579
#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
580
#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
583
#define E1000_EECD_SK 0x00000001 /* NVM Clock */
584
#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
585
#define E1000_EECD_DI 0x00000004 /* NVM Data In */
586
#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
587
#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
588
#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
589
#define E1000_EECD_PRES 0x00000100 /* NVM Present */
590
/* NVM Addressing bits based on type 0=small, 1=large */
591
#define E1000_EECD_ADDR_BITS 0x00000400
592
#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
593
#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
594
#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
595
#define E1000_EECD_SIZE_EX_SHIFT 11
597
/* Offset to data in NVM read/write registers */
598
#define E1000_NVM_RW_REG_DATA 16
599
#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
600
#define E1000_NVM_RW_REG_START 1 /* Start operation */
601
#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
602
#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
604
/* NVM Word Offsets */
605
#define NVM_COMPAT 0x0003
606
#define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */
607
#define NVM_INIT_CONTROL2_REG 0x000F
608
#define NVM_INIT_CONTROL3_PORT_B 0x0014
609
#define NVM_INIT_CONTROL3_PORT_A 0x0024
610
#define NVM_ALT_MAC_ADDR_PTR 0x0037
611
#define NVM_CHECKSUM_REG 0x003F
612
#define NVM_COMPATIBILITY_REG_3 0x0003
613
#define NVM_COMPATIBILITY_BIT_MASK 0x8000
615
#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
616
#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
617
#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
618
#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
620
#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
622
/* Mask bits for fields in Word 0x24 of the NVM */
623
#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
624
#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */
626
/* Mask bits for fields in Word 0x0f of the NVM */
627
#define NVM_WORD0F_PAUSE_MASK 0x3000
628
#define NVM_WORD0F_ASM_DIR 0x2000
630
/* Mask bits for fields in Word 0x1a of the NVM */
632
/* length of string needed to store part num */
633
#define E1000_PBANUM_LENGTH 11
635
/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
636
#define NVM_SUM 0xBABA
638
#define NVM_PBA_OFFSET_0 8
639
#define NVM_PBA_OFFSET_1 9
640
#define NVM_PBA_PTR_GUARD 0xFAFA
641
#define NVM_WORD_SIZE_BASE_SHIFT 6
643
/* NVM Commands - Microwire */
645
/* NVM Commands - SPI */
646
#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
647
#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
648
#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
649
#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
650
#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
651
#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
653
/* SPI NVM Status Register */
654
#define NVM_STATUS_RDY_SPI 0x01
656
/* Word definitions for ID LED Settings */
657
#define ID_LED_RESERVED_0000 0x0000
658
#define ID_LED_RESERVED_FFFF 0xFFFF
659
#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
660
(ID_LED_OFF1_OFF2 << 8) | \
661
(ID_LED_DEF1_DEF2 << 4) | \
663
#define ID_LED_DEF1_DEF2 0x1
664
#define ID_LED_DEF1_ON2 0x2
665
#define ID_LED_DEF1_OFF2 0x3
666
#define ID_LED_ON1_DEF2 0x4
667
#define ID_LED_ON1_ON2 0x5
668
#define ID_LED_ON1_OFF2 0x6
669
#define ID_LED_OFF1_DEF2 0x7
670
#define ID_LED_OFF1_ON2 0x8
671
#define ID_LED_OFF1_OFF2 0x9
673
#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
674
#define IGP_ACTIVITY_LED_ENABLE 0x0300
675
#define IGP_LED3_MODE 0x07000000
677
/* PCI/PCI-X/PCI-EX Config space */
678
#define PCIE_DEVICE_CONTROL2 0x28
679
#define PCIE_DEVICE_CONTROL2_16ms 0x0005
681
#define PHY_REVISION_MASK 0xFFFFFFF0
682
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
683
#define MAX_PHY_MULTI_PAGE_REG 0xF
685
/* Bit definitions for valid PHY IDs. */
690
#define M88E1111_I_PHY_ID 0x01410CC0
691
#define M88E1112_E_PHY_ID 0x01410C90
692
#define I347AT4_E_PHY_ID 0x01410DC0
693
#define IGP03E1000_E_PHY_ID 0x02A80390
694
#define I82580_I_PHY_ID 0x015403A0
695
#define I350_I_PHY_ID 0x015403B0
696
#define M88_VENDOR 0x0141
698
/* M88E1000 Specific Registers */
699
#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
700
#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
701
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
703
#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
704
#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
706
/* M88E1000 PHY Specific Control Register */
707
#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
708
/* 1=CLK125 low, 0=CLK125 toggling */
709
#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
710
/* Manual MDI configuration */
711
#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
712
/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
713
#define M88E1000_PSCR_AUTO_X_1000T 0x0040
714
/* Auto crossover enabled all speeds */
715
#define M88E1000_PSCR_AUTO_X_MODE 0x0060
717
* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
718
* 0=Normal 10BASE-T Rx Threshold
720
/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
721
#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
723
/* M88E1000 PHY Specific Status Register */
724
#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
725
#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
726
#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
734
#define M88E1000_PSSR_CABLE_LENGTH 0x0380
735
#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
736
#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
738
#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
740
/* M88E1000 Extended PHY Specific Control Register */
742
* 1 = Lost lock detect enabled.
743
* Will assert lost lock and bring
744
* link down if idle not seen
745
* within 1ms in 1000BASE-T
748
* Number of times we will attempt to autonegotiate before downshifting if we
751
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
752
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
754
* Number of times we will attempt to autonegotiate before downshifting if we
757
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
758
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
759
#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
761
/* Intel i347-AT4 Registers */
763
#define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
764
#define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
765
#define I347AT4_PAGE_SELECT 0x16
767
/* i347-AT4 Extended PHY Specific Control Register */
770
* Number of times we will attempt to autonegotiate before downshifting if we
773
#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
774
#define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
775
#define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
776
#define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
777
#define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
778
#define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
779
#define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
780
#define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
781
#define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
782
#define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
784
/* i347-AT4 PHY Cable Diagnostics Control */
785
#define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
787
/* Marvell 1112 only registers */
788
#define M88E1112_VCT_DSP_DISTANCE 0x001A
790
/* M88EC018 Rev 2 specific DownShift settings */
791
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
792
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
795
#define E1000_MDIC_DATA_MASK 0x0000FFFF
796
#define E1000_MDIC_REG_MASK 0x001F0000
797
#define E1000_MDIC_REG_SHIFT 16
798
#define E1000_MDIC_PHY_MASK 0x03E00000
799
#define E1000_MDIC_PHY_SHIFT 21
800
#define E1000_MDIC_OP_WRITE 0x04000000
801
#define E1000_MDIC_OP_READ 0x08000000
802
#define E1000_MDIC_READY 0x10000000
803
#define E1000_MDIC_INT_EN 0x20000000
804
#define E1000_MDIC_ERROR 0x40000000
805
#define E1000_MDIC_DEST 0x80000000
808
#define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
809
#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */
811
/* Energy Efficient Ethernet */
812
#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */
813
#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */
814
#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */
815
#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */
816
#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */
819
#define E1000_GEN_CTL_READY 0x80000000
820
#define E1000_GEN_CTL_ADDRESS_SHIFT 8
821
#define E1000_GEN_POLL_TIMEOUT 640
823
#define E1000_VFTA_ENTRY_SHIFT 5
824
#define E1000_VFTA_ENTRY_MASK 0x7F
825
#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
827
/* DMA Coalescing register fields */
828
#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based
831
/* Tx Rate-Scheduler Config fields */
832
#define E1000_RTTBCNRC_RS_ENA 0x80000000
833
#define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
834
#define E1000_RTTBCNRC_RF_INT_SHIFT 14
835
#define E1000_RTTBCNRC_RF_INT_MASK \
836
(E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
added
removed
drivers/net/ethernet/intel/igb/e1000_defines.h
