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* Freescale GPMI NAND Flash Driver
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* Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
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* Copyright (C) 2008 Embedded Alley Solutions, Inc.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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#include <linux/mtd/gpmi-nand.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include "gpmi-nand.h"
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#include "gpmi-regs.h"
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struct timing_threshod timing_default_threshold = {
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.max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
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BP_GPMI_TIMING0_DATA_SETUP),
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.internal_data_setup_in_ns = 0,
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.max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
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BP_GPMI_CTRL1_RDN_DELAY),
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.max_dll_clock_period_in_ns = 32,
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.max_dll_delay_in_ns = 16,
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* Clear the bit and poll it cleared. This is usually called with
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* a reset address and mask being either SFTRST(bit 31) or CLKGATE
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static int clear_poll_bit(void __iomem *addr, u32 mask)
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__mxs_clrl(mask, addr);
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* SFTRST needs 3 GPMI clocks to settle, the reference manual
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* recommends to wait 1us.
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/* poll the bit becoming clear */
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while ((readl(addr) & mask) && --timeout)
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#define MODULE_CLKGATE (1 << 30)
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#define MODULE_SFTRST (1 << 31)
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* The current mxs_reset_block() will do two things:
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* [1] enable the module.
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* [2] reset the module.
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* In most of the cases, it's ok. But there is a hardware bug in the BCH block.
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* If you try to soft reset the BCH block, it becomes unusable until
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* the next hard reset. This case occurs in the NAND boot mode. When the board
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* boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
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* So If the driver tries to reset the BCH again, the BCH will not work anymore.
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* You will see a DMA timeout in this case.
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* To avoid this bug, just add a new parameter `just_enable` for
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* the mxs_reset_block(), and rewrite it here.
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int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
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/* clear and poll SFTRST */
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ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
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__mxs_clrl(MODULE_CLKGATE, reset_addr);
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/* set SFTRST to reset the block */
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__mxs_setl(MODULE_SFTRST, reset_addr);
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/* poll CLKGATE becoming set */
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while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
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if (unlikely(!timeout))
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/* clear and poll SFTRST */
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ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
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/* clear and poll CLKGATE */
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ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
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pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
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int gpmi_init(struct gpmi_nand_data *this)
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struct resources *r = &this->resources;
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ret = clk_enable(r->clock);
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ret = gpmi_reset_block(r->gpmi_regs, false);
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/* Choose NAND mode. */
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writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
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/* Set the IRQ polarity. */
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writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
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r->gpmi_regs + HW_GPMI_CTRL1_SET);
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/* Disable Write-Protection. */
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writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
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/* Select BCH ECC. */
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writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
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clk_disable(r->clock);
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/* This function is very useful. It is called only when the bug occur. */
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void gpmi_dump_info(struct gpmi_nand_data *this)
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struct resources *r = &this->resources;
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struct bch_geometry *geo = &this->bch_geometry;
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pr_err("Show GPMI registers :\n");
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for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
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reg = readl(r->gpmi_regs + i * 0x10);
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pr_err("offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
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/* start to print out the BCH info */
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pr_err("BCH Geometry :\n");
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pr_err("GF length : %u\n", geo->gf_len);
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pr_err("ECC Strength : %u\n", geo->ecc_strength);
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pr_err("Page Size in Bytes : %u\n", geo->page_size);
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pr_err("Metadata Size in Bytes : %u\n", geo->metadata_size);
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pr_err("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size);
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pr_err("ECC Chunk Count : %u\n", geo->ecc_chunk_count);
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pr_err("Payload Size in Bytes : %u\n", geo->payload_size);
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pr_err("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size);
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pr_err("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
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pr_err("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
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pr_err("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset);
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/* Configures the geometry for BCH. */
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int bch_set_geometry(struct gpmi_nand_data *this)
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struct resources *r = &this->resources;
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struct bch_geometry *bch_geo = &this->bch_geometry;
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unsigned int block_count;
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unsigned int block_size;
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unsigned int metadata_size;
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unsigned int ecc_strength;
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unsigned int page_size;
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if (common_nfc_set_geometry(this))
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block_count = bch_geo->ecc_chunk_count - 1;
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block_size = bch_geo->ecc_chunk_size;
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metadata_size = bch_geo->metadata_size;
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ecc_strength = bch_geo->ecc_strength >> 1;
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page_size = bch_geo->page_size;
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ret = clk_enable(r->clock);
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ret = gpmi_reset_block(r->bch_regs, true);
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/* Configure layout 0. */
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writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
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| BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
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| BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength)
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| BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size),
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r->bch_regs + HW_BCH_FLASH0LAYOUT0);
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writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
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| BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength)
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| BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size),
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r->bch_regs + HW_BCH_FLASH0LAYOUT1);
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/* Set *all* chip selects to use layout 0. */
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writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
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/* Enable interrupts. */
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writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
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r->bch_regs + HW_BCH_CTRL_SET);
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clk_disable(r->clock);
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/* Converts time in nanoseconds to cycles. */
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static unsigned int ns_to_cycles(unsigned int time,
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unsigned int period, unsigned int min)
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k = (time + period - 1) / period;
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/* Apply timing to current hardware conditions. */
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static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
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struct gpmi_nfc_hardware_timing *hw)
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struct gpmi_nand_platform_data *pdata = this->pdata;
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struct timing_threshod *nfc = &timing_default_threshold;
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struct nand_chip *nand = &this->nand;
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struct nand_timing target = this->timing;
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bool improved_timing_is_available;
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unsigned long clock_frequency_in_hz;
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unsigned int clock_period_in_ns;
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bool dll_use_half_periods;
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unsigned int dll_delay_shift;
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unsigned int max_sample_delay_in_ns;
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unsigned int address_setup_in_cycles;
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unsigned int data_setup_in_ns;
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unsigned int data_setup_in_cycles;
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unsigned int data_hold_in_cycles;
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int ideal_sample_delay_in_ns;
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unsigned int sample_delay_factor;
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unsigned int min_prop_delay_in_ns = pdata->min_prop_delay_in_ns;
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unsigned int max_prop_delay_in_ns = pdata->max_prop_delay_in_ns;
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* If there are multiple chips, we need to relax the timings to allow
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* for signal distortion due to higher capacitance.
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if (nand->numchips > 2) {
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target.data_setup_in_ns += 10;
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target.data_hold_in_ns += 10;
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target.address_setup_in_ns += 10;
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} else if (nand->numchips > 1) {
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target.data_setup_in_ns += 5;
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target.data_hold_in_ns += 5;
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target.address_setup_in_ns += 5;
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/* Check if improved timing information is available. */
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improved_timing_is_available =
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(target.tREA_in_ns >= 0) &&
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(target.tRLOH_in_ns >= 0) &&
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(target.tRHOH_in_ns >= 0) ;
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/* Inspect the clock. */
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clock_frequency_in_hz = nfc->clock_frequency_in_hz;
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clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
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* The NFC quantizes setup and hold parameters in terms of clock cycles.
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* Here, we quantize the setup and hold timing parameters to the
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* next-highest clock period to make sure we apply at least the
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* For data setup and data hold, the hardware interprets a value of zero
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* as the largest possible delay. This is not what's intended by a zero
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* in the input parameter, so we impose a minimum of one cycle.
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data_setup_in_cycles = ns_to_cycles(target.data_setup_in_ns,
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clock_period_in_ns, 1);
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data_hold_in_cycles = ns_to_cycles(target.data_hold_in_ns,
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clock_period_in_ns, 1);
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address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
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clock_period_in_ns, 0);
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* The clock's period affects the sample delay in a number of ways:
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* (1) The NFC HAL tells us the maximum clock period the sample delay
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* DLL can tolerate. If the clock period is greater than half that
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* maximum, we must configure the DLL to be driven by half periods.
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* (2) We need to convert from an ideal sample delay, in ns, to a
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* "sample delay factor," which the NFC uses. This factor depends on
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* whether we're driving the DLL with full or half periods.
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* Paraphrasing the reference manual:
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* AD = SDF x 0.125 x RP
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* AD is the applied delay, in ns.
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* SDF is the sample delay factor, which is dimensionless.
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* RP is the reference period, in ns, which is a full clock period
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* if the DLL is being driven by full periods, or half that if
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* the DLL is being driven by half periods.
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* Let's re-arrange this in a way that's more useful to us:
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* The reference period is either the clock period or half that, so this
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* SDF = AD x ----- = --------
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* f is 1 or 1/2, depending on how we're driving the DLL.
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* P is the clock period.
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* DDF is the DLL Delay Factor, a dimensionless value that
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* incorporates all the constants in the conversion.
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* DDF will be either 8 or 16, both of which are powers of two. We can
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* reduce the cost of this conversion by using bit shifts instead of
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* multiplication or division. Thus:
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* AD = (SDF >> DDS) x P
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* DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF.
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if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
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dll_use_half_periods = true;
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dll_delay_shift = 3 + 1;
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dll_use_half_periods = false;
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* Compute the maximum sample delay the NFC allows, under current
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* conditions. If the clock is running too slowly, no sample delay is
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if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
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max_sample_delay_in_ns = 0;
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* Compute the delay implied by the largest sample delay factor
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max_sample_delay_in_ns =
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(nfc->max_sample_delay_factor * clock_period_in_ns) >>
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* Check if the implied sample delay larger than the NFC
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if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
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max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
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* Check if improved timing information is available. If not, we have to
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* use a less-sophisticated algorithm.
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if (!improved_timing_is_available) {
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* Fold the read setup time required by the NFC into the ideal
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ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
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nfc->internal_data_setup_in_ns;
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* The ideal sample delay may be greater than the maximum
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* allowed by the NFC. If so, we can trade off sample delay time
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* for more data setup time.
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* In each iteration of the following loop, we add a cycle to
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* the data setup time and subtract a corresponding amount from
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* the sample delay until we've satisified the constraints or
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* can't do any better.
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while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
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(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
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data_setup_in_cycles++;
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ideal_sample_delay_in_ns -= clock_period_in_ns;
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if (ideal_sample_delay_in_ns < 0)
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ideal_sample_delay_in_ns = 0;
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* Compute the sample delay factor that corresponds most closely
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* to the ideal sample delay. If the result is too large for the
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* NFC, use the maximum value.
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* Notice that we use the ns_to_cycles function to compute the
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* sample delay factor. We do this because the form of the
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* computation is the same as that for calculating cycles.
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sample_delay_factor =
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ideal_sample_delay_in_ns << dll_delay_shift,
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clock_period_in_ns, 0);
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if (sample_delay_factor > nfc->max_sample_delay_factor)
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sample_delay_factor = nfc->max_sample_delay_factor;
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/* Skip to the part where we return our results. */
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* If control arrives here, we have more detailed timing information,
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* so we can use a better algorithm.
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* Fold the read setup time required by the NFC into the maximum
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max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
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* Earlier, we computed the number of clock cycles required to satisfy
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* the data setup time. Now, we need to know the actual nanoseconds.
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data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
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* Compute tEYE, the width of the data eye when reading from the NAND
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* Flash. The eye width is fundamentally determined by the data setup
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* time, perturbed by propagation delays and some characteristics of the
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* start of the eye = max_prop_delay + tREA
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* end of the eye = min_prop_delay + tRHOH + data_setup
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tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
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(int)data_setup_in_ns;
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tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
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* The eye must be open. If it's not, we can try to open it by
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* increasing its main forcer, the data setup time.
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* In each iteration of the following loop, we increase the data setup
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* time by a single clock cycle. We do this until either the eye is
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* open or we run into NFC limits.
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while ((tEYE <= 0) &&
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(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
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/* Give a cycle to data setup. */
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data_setup_in_cycles++;
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/* Synchronize the data setup time with the cycles. */
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data_setup_in_ns += clock_period_in_ns;
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/* Adjust tEYE accordingly. */
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tEYE += clock_period_in_ns;
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* When control arrives here, the eye is open. The ideal time to sample
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* the data is in the center of the eye:
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* end of the eye + start of the eye
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* --------------------------------- - data_setup
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* After some algebra, this simplifies to the code immediately below.
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ideal_sample_delay_in_ns =
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((int)max_prop_delay_in_ns +
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(int)target.tREA_in_ns +
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(int)min_prop_delay_in_ns +
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(int)target.tRHOH_in_ns -
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(int)data_setup_in_ns) >> 1;
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* The following figure illustrates some aspects of a NAND Flash read:
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* __ _____________________________________
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* RDN \_________________/
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* /-----------------\
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* Read Data ----------------------------< >---------
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* \-----------------/
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* |<--Data Setup -->|<--Delay Time -->| |
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* | |<-- Quantized Delay Time -->|
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* We have some issues we must now address:
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* (1) The *ideal* sample delay time must not be negative. If it is, we
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* (2) The *ideal* sample delay time must not be greater than that
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* allowed by the NFC. If it is, we can increase the data setup
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* time, which will reduce the delay between the end of the data
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* setup and the center of the eye. It will also make the eye
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* larger, which might help with the next issue...
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* (3) The *quantized* sample delay time must not fall either before the
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* eye opens or after it closes (the latter is the problem
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* illustrated in the above figure).
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/* Jam a negative ideal sample delay to zero. */
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if (ideal_sample_delay_in_ns < 0)
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ideal_sample_delay_in_ns = 0;
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* Extend the data setup as needed to reduce the ideal sample delay
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* below the maximum permitted by the NFC.
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while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
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(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
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/* Give a cycle to data setup. */
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data_setup_in_cycles++;
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/* Synchronize the data setup time with the cycles. */
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data_setup_in_ns += clock_period_in_ns;
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/* Adjust tEYE accordingly. */
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tEYE += clock_period_in_ns;
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* Decrease the ideal sample delay by one half cycle, to keep it
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* in the middle of the eye.
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ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
583
/* Jam a negative ideal sample delay to zero. */
584
if (ideal_sample_delay_in_ns < 0)
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ideal_sample_delay_in_ns = 0;
589
* Compute the sample delay factor that corresponds to the ideal sample
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* delay. If the result is too large, then use the maximum allowed
593
* Notice that we use the ns_to_cycles function to compute the sample
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* delay factor. We do this because the form of the computation is the
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* same as that for calculating cycles.
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sample_delay_factor =
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ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
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clock_period_in_ns, 0);
601
if (sample_delay_factor > nfc->max_sample_delay_factor)
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sample_delay_factor = nfc->max_sample_delay_factor;
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* These macros conveniently encapsulate a computation we'll use to
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* continuously evaluate whether or not the data sample delay is inside
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#define IDEAL_DELAY ((int) ideal_sample_delay_in_ns)
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#define QUANTIZED_DELAY \
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((int) ((sample_delay_factor * clock_period_in_ns) >> \
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#define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY))
617
#define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1))
620
* While the quantized sample time falls outside the eye, reduce the
621
* sample delay or extend the data setup to move the sampling point back
622
* toward the eye. Do not allow the number of data setup cycles to
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* exceed the maximum allowed by the NFC.
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while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
626
(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
628
* If control arrives here, the quantized sample delay falls
629
* outside the eye. Check if it's before the eye opens, or after
632
if (QUANTIZED_DELAY > IDEAL_DELAY) {
634
* If control arrives here, the quantized sample delay
635
* falls after the eye closes. Decrease the quantized
636
* delay time and then go back to re-evaluate.
638
if (sample_delay_factor != 0)
639
sample_delay_factor--;
644
* If control arrives here, the quantized sample delay falls
645
* before the eye opens. Shift the sample point by increasing
646
* data setup time. This will also make the eye larger.
649
/* Give a cycle to data setup. */
650
data_setup_in_cycles++;
651
/* Synchronize the data setup time with the cycles. */
652
data_setup_in_ns += clock_period_in_ns;
653
/* Adjust tEYE accordingly. */
654
tEYE += clock_period_in_ns;
657
* Decrease the ideal sample delay by one half cycle, to keep it
658
* in the middle of the eye.
660
ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
662
/* ...and one less period for the delay time. */
663
ideal_sample_delay_in_ns -= clock_period_in_ns;
665
/* Jam a negative ideal sample delay to zero. */
666
if (ideal_sample_delay_in_ns < 0)
667
ideal_sample_delay_in_ns = 0;
670
* We have a new ideal sample delay, so re-compute the quantized
673
sample_delay_factor =
675
ideal_sample_delay_in_ns << dll_delay_shift,
676
clock_period_in_ns, 0);
678
if (sample_delay_factor > nfc->max_sample_delay_factor)
679
sample_delay_factor = nfc->max_sample_delay_factor;
682
/* Control arrives here when we're ready to return our results. */
684
hw->data_setup_in_cycles = data_setup_in_cycles;
685
hw->data_hold_in_cycles = data_hold_in_cycles;
686
hw->address_setup_in_cycles = address_setup_in_cycles;
687
hw->use_half_periods = dll_use_half_periods;
688
hw->sample_delay_factor = sample_delay_factor;
690
/* Return success. */
695
void gpmi_begin(struct gpmi_nand_data *this)
697
struct resources *r = &this->resources;
698
struct timing_threshod *nfc = &timing_default_threshold;
699
unsigned char *gpmi_regs = r->gpmi_regs;
700
unsigned int clock_period_in_ns;
702
unsigned int dll_wait_time_in_us;
703
struct gpmi_nfc_hardware_timing hw;
706
/* Enable the clock. */
707
ret = clk_enable(r->clock);
709
pr_err("We failed in enable the clk\n");
713
/* set ready/busy timeout */
714
writel(0x500 << BP_GPMI_TIMING1_BUSY_TIMEOUT,
715
gpmi_regs + HW_GPMI_TIMING1);
717
/* Get the timing information we need. */
718
nfc->clock_frequency_in_hz = clk_get_rate(r->clock);
719
clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
721
gpmi_nfc_compute_hardware_timing(this, &hw);
723
/* Set up all the simple timing parameters. */
724
reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
725
BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
726
BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
728
writel(reg, gpmi_regs + HW_GPMI_TIMING0);
731
* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
733
writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
735
/* Clear out the DLL control fields. */
736
writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR);
737
writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
739
/* If no sample delay is called for, return immediately. */
740
if (!hw.sample_delay_factor)
743
/* Configure the HALF_PERIOD flag. */
744
if (hw.use_half_periods)
745
writel(BM_GPMI_CTRL1_HALF_PERIOD,
746
gpmi_regs + HW_GPMI_CTRL1_SET);
748
/* Set the delay factor. */
749
writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
750
gpmi_regs + HW_GPMI_CTRL1_SET);
752
/* Enable the DLL. */
753
writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
756
* After we enable the GPMI DLL, we have to wait 64 clock cycles before
757
* we can use the GPMI.
759
* Calculate the amount of time we need to wait, in microseconds.
761
dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
763
if (!dll_wait_time_in_us)
764
dll_wait_time_in_us = 1;
766
/* Wait for the DLL to settle. */
767
udelay(dll_wait_time_in_us);
773
void gpmi_end(struct gpmi_nand_data *this)
775
struct resources *r = &this->resources;
776
clk_disable(r->clock);
779
/* Clears a BCH interrupt. */
780
void gpmi_clear_bch(struct gpmi_nand_data *this)
782
struct resources *r = &this->resources;
783
writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
786
/* Returns the Ready/Busy status of the given chip. */
787
int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
789
struct resources *r = &this->resources;
793
if (GPMI_IS_MX23(this)) {
794
mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
795
reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
796
} else if (GPMI_IS_MX28(this)) {
797
mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
798
reg = readl(r->gpmi_regs + HW_GPMI_STAT);
800
pr_err("unknow arch.\n");
804
static inline void set_dma_type(struct gpmi_nand_data *this,
805
enum dma_ops_type type)
807
this->last_dma_type = this->dma_type;
808
this->dma_type = type;
811
int gpmi_send_command(struct gpmi_nand_data *this)
813
struct dma_chan *channel = get_dma_chan(this);
814
struct dma_async_tx_descriptor *desc;
815
struct scatterlist *sgl;
816
int chip = this->current_chip;
819
/* [1] send out the PIO words */
820
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
821
| BM_GPMI_CTRL0_WORD_LENGTH
822
| BF_GPMI_CTRL0_CS(chip, this)
823
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
824
| BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
825
| BM_GPMI_CTRL0_ADDRESS_INCREMENT
826
| BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
828
desc = channel->device->device_prep_slave_sg(channel,
829
(struct scatterlist *)pio,
830
ARRAY_SIZE(pio), DMA_NONE, 0);
832
pr_err("step 1 error\n");
836
/* [2] send out the COMMAND + ADDRESS string stored in @buffer */
837
sgl = &this->cmd_sgl;
839
sg_init_one(sgl, this->cmd_buffer, this->command_length);
840
dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
841
desc = channel->device->device_prep_slave_sg(channel,
842
sgl, 1, DMA_TO_DEVICE, 1);
844
pr_err("step 2 error\n");
848
/* [3] submit the DMA */
849
set_dma_type(this, DMA_FOR_COMMAND);
850
return start_dma_without_bch_irq(this, desc);
853
int gpmi_send_data(struct gpmi_nand_data *this)
855
struct dma_async_tx_descriptor *desc;
856
struct dma_chan *channel = get_dma_chan(this);
857
int chip = this->current_chip;
858
uint32_t command_mode;
863
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
864
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
866
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
867
| BM_GPMI_CTRL0_WORD_LENGTH
868
| BF_GPMI_CTRL0_CS(chip, this)
869
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
870
| BF_GPMI_CTRL0_ADDRESS(address)
871
| BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
873
desc = channel->device->device_prep_slave_sg(channel,
874
(struct scatterlist *)pio,
875
ARRAY_SIZE(pio), DMA_NONE, 0);
877
pr_err("step 1 error\n");
881
/* [2] send DMA request */
882
prepare_data_dma(this, DMA_TO_DEVICE);
883
desc = channel->device->device_prep_slave_sg(channel, &this->data_sgl,
884
1, DMA_TO_DEVICE, 1);
886
pr_err("step 2 error\n");
889
/* [3] submit the DMA */
890
set_dma_type(this, DMA_FOR_WRITE_DATA);
891
return start_dma_without_bch_irq(this, desc);
894
int gpmi_read_data(struct gpmi_nand_data *this)
896
struct dma_async_tx_descriptor *desc;
897
struct dma_chan *channel = get_dma_chan(this);
898
int chip = this->current_chip;
902
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
903
| BM_GPMI_CTRL0_WORD_LENGTH
904
| BF_GPMI_CTRL0_CS(chip, this)
905
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
906
| BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
907
| BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
909
desc = channel->device->device_prep_slave_sg(channel,
910
(struct scatterlist *)pio,
911
ARRAY_SIZE(pio), DMA_NONE, 0);
913
pr_err("step 1 error\n");
917
/* [2] : send DMA request */
918
prepare_data_dma(this, DMA_FROM_DEVICE);
919
desc = channel->device->device_prep_slave_sg(channel, &this->data_sgl,
920
1, DMA_FROM_DEVICE, 1);
922
pr_err("step 2 error\n");
926
/* [3] : submit the DMA */
927
set_dma_type(this, DMA_FOR_READ_DATA);
928
return start_dma_without_bch_irq(this, desc);
931
int gpmi_send_page(struct gpmi_nand_data *this,
932
dma_addr_t payload, dma_addr_t auxiliary)
934
struct bch_geometry *geo = &this->bch_geometry;
935
uint32_t command_mode;
937
uint32_t ecc_command;
938
uint32_t buffer_mask;
939
struct dma_async_tx_descriptor *desc;
940
struct dma_chan *channel = get_dma_chan(this);
941
int chip = this->current_chip;
944
/* A DMA descriptor that does an ECC page read. */
945
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
946
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
947
ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
948
buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
949
BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
951
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
952
| BM_GPMI_CTRL0_WORD_LENGTH
953
| BF_GPMI_CTRL0_CS(chip, this)
954
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
955
| BF_GPMI_CTRL0_ADDRESS(address)
956
| BF_GPMI_CTRL0_XFER_COUNT(0);
958
pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
959
| BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
960
| BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
961
pio[3] = geo->page_size;
965
desc = channel->device->device_prep_slave_sg(channel,
966
(struct scatterlist *)pio,
967
ARRAY_SIZE(pio), DMA_NONE, 0);
969
pr_err("step 2 error\n");
972
set_dma_type(this, DMA_FOR_WRITE_ECC_PAGE);
973
return start_dma_with_bch_irq(this, desc);
976
int gpmi_read_page(struct gpmi_nand_data *this,
977
dma_addr_t payload, dma_addr_t auxiliary)
979
struct bch_geometry *geo = &this->bch_geometry;
980
uint32_t command_mode;
982
uint32_t ecc_command;
983
uint32_t buffer_mask;
984
struct dma_async_tx_descriptor *desc;
985
struct dma_chan *channel = get_dma_chan(this);
986
int chip = this->current_chip;
989
/* [1] Wait for the chip to report ready. */
990
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
991
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
993
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
994
| BM_GPMI_CTRL0_WORD_LENGTH
995
| BF_GPMI_CTRL0_CS(chip, this)
996
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
997
| BF_GPMI_CTRL0_ADDRESS(address)
998
| BF_GPMI_CTRL0_XFER_COUNT(0);
1000
desc = channel->device->device_prep_slave_sg(channel,
1001
(struct scatterlist *)pio, 2, DMA_NONE, 0);
1003
pr_err("step 1 error\n");
1007
/* [2] Enable the BCH block and read. */
1008
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
1009
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1010
ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
1011
buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
1012
| BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
1014
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1015
| BM_GPMI_CTRL0_WORD_LENGTH
1016
| BF_GPMI_CTRL0_CS(chip, this)
1017
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1018
| BF_GPMI_CTRL0_ADDRESS(address)
1019
| BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1022
pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
1023
| BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
1024
| BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
1025
pio[3] = geo->page_size;
1028
desc = channel->device->device_prep_slave_sg(channel,
1029
(struct scatterlist *)pio,
1030
ARRAY_SIZE(pio), DMA_NONE, 1);
1032
pr_err("step 2 error\n");
1036
/* [3] Disable the BCH block */
1037
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1038
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1040
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1041
| BM_GPMI_CTRL0_WORD_LENGTH
1042
| BF_GPMI_CTRL0_CS(chip, this)
1043
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1044
| BF_GPMI_CTRL0_ADDRESS(address)
1045
| BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1047
desc = channel->device->device_prep_slave_sg(channel,
1048
(struct scatterlist *)pio, 2, DMA_NONE, 1);
1050
pr_err("step 3 error\n");
1054
/* [4] submit the DMA */
1055
set_dma_type(this, DMA_FOR_READ_ECC_PAGE);
1056
return start_dma_with_bch_irq(this, desc);
added
removed
drivers/mtd/nand/gpmi-nand/gpmi-lib.c
