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Viewing changes to arch/arm/plat-omap/include/plat/mcbsp.h

  • Committer: Package Import Robot
  • Author(s): Paolo Pisati, Paolo Pisati
  • Date: 2011-12-06 15:56:07 UTC
  • Revision ID: package-import@ubuntu.com-20111206155607-pcf44kv5fmhk564f
Tags: 3.2.0-1401.1
[ Paolo Pisati ]

* Rebased on top of Ubuntu-3.2.0-3.8
* Tilt-tracking @ ef2487af4bb15bdd0689631774b5a5e3a59f74e2
* Delete debian.ti-omap4/control, it shoudln't be tracked
* Fix architecture spelling (s/armel/armhf/)
* [Config] Update configs following 3.2 import
* [Config] Fix compilation: disable CODA and ARCH_OMAP3
* [Config] Fix compilation: disable Ethernet Faraday
* Update series to precise

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arch/arm/plat-omap/include/plat/mcbsp.h
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#ifndef __ASM_ARCH_OMAP_MCBSP_H
25
25
#define __ASM_ARCH_OMAP_MCBSP_H
26
26
 
27
 
#include <linux/completion.h>
28
27
#include <linux/spinlock.h>
29
 
 
30
 
#include <mach/hardware.h>
31
 
#include <plat/clock.h>
 
28
#include <linux/clk.h>
32
29
 
33
30
/* macro for building platform_device for McBSP ports */
34
31
#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)             \
35
32
static struct platform_device omap_mcbsp##port_nr = {   \
36
33
        .name   = "omap-mcbsp-dai",                     \
37
 
        .id     = OMAP_MCBSP##port_nr,                  \
 
34
        .id     = port_nr - 1,                  \
38
35
}
39
36
 
40
37
#define MCBSP_CONFIG_TYPE2      0x2
41
38
#define MCBSP_CONFIG_TYPE3      0x3
42
39
#define MCBSP_CONFIG_TYPE4      0x4
43
40
 
44
 
#define OMAP7XX_MCBSP1_BASE     0xfffb1000
45
 
#define OMAP7XX_MCBSP2_BASE     0xfffb1800
46
 
 
47
 
#define OMAP1510_MCBSP1_BASE    0xe1011800
48
 
#define OMAP1510_MCBSP2_BASE    0xfffb1000
49
 
#define OMAP1510_MCBSP3_BASE    0xe1017000
50
 
 
51
 
#define OMAP1610_MCBSP1_BASE    0xe1011800
52
 
#define OMAP1610_MCBSP2_BASE    0xfffb1000
53
 
#define OMAP1610_MCBSP3_BASE    0xe1017000
54
 
 
55
 
#ifdef CONFIG_ARCH_OMAP1
56
 
 
57
 
#define OMAP_MCBSP_REG_DRR2     0x00
58
 
#define OMAP_MCBSP_REG_DRR1     0x02
59
 
#define OMAP_MCBSP_REG_DXR2     0x04
60
 
#define OMAP_MCBSP_REG_DXR1     0x06
61
 
#define OMAP_MCBSP_REG_DRR      0x02
62
 
#define OMAP_MCBSP_REG_DXR      0x06
63
 
#define OMAP_MCBSP_REG_SPCR2    0x08
64
 
#define OMAP_MCBSP_REG_SPCR1    0x0a
65
 
#define OMAP_MCBSP_REG_RCR2     0x0c
66
 
#define OMAP_MCBSP_REG_RCR1     0x0e
67
 
#define OMAP_MCBSP_REG_XCR2     0x10
68
 
#define OMAP_MCBSP_REG_XCR1     0x12
69
 
#define OMAP_MCBSP_REG_SRGR2    0x14
70
 
#define OMAP_MCBSP_REG_SRGR1    0x16
71
 
#define OMAP_MCBSP_REG_MCR2     0x18
72
 
#define OMAP_MCBSP_REG_MCR1     0x1a
73
 
#define OMAP_MCBSP_REG_RCERA    0x1c
74
 
#define OMAP_MCBSP_REG_RCERB    0x1e
75
 
#define OMAP_MCBSP_REG_XCERA    0x20
76
 
#define OMAP_MCBSP_REG_XCERB    0x22
77
 
#define OMAP_MCBSP_REG_PCR0     0x24
78
 
#define OMAP_MCBSP_REG_RCERC    0x26
79
 
#define OMAP_MCBSP_REG_RCERD    0x28
80
 
#define OMAP_MCBSP_REG_XCERC    0x2A
81
 
#define OMAP_MCBSP_REG_XCERD    0x2C
82
 
#define OMAP_MCBSP_REG_RCERE    0x2E
83
 
#define OMAP_MCBSP_REG_RCERF    0x30
84
 
#define OMAP_MCBSP_REG_XCERE    0x32
85
 
#define OMAP_MCBSP_REG_XCERF    0x34
86
 
#define OMAP_MCBSP_REG_RCERG    0x36
87
 
#define OMAP_MCBSP_REG_RCERH    0x38
88
 
#define OMAP_MCBSP_REG_XCERG    0x3A
89
 
#define OMAP_MCBSP_REG_XCERH    0x3C
90
 
 
91
 
/* Dummy defines, these are not available on omap1 */
92
 
#define OMAP_MCBSP_REG_XCCR     0x00
93
 
#define OMAP_MCBSP_REG_RCCR     0x00
94
 
 
95
 
#else
96
 
 
97
 
#define OMAP_MCBSP_REG_DRR2     0x00
98
 
#define OMAP_MCBSP_REG_DRR1     0x04
99
 
#define OMAP_MCBSP_REG_DXR2     0x08
100
 
#define OMAP_MCBSP_REG_DXR1     0x0C
101
 
#define OMAP_MCBSP_REG_DRR      0x00
102
 
#define OMAP_MCBSP_REG_DXR      0x08
103
 
#define OMAP_MCBSP_REG_SPCR2    0x10
104
 
#define OMAP_MCBSP_REG_SPCR1    0x14
105
 
#define OMAP_MCBSP_REG_RCR2     0x18
106
 
#define OMAP_MCBSP_REG_RCR1     0x1C
107
 
#define OMAP_MCBSP_REG_XCR2     0x20
108
 
#define OMAP_MCBSP_REG_XCR1     0x24
109
 
#define OMAP_MCBSP_REG_SRGR2    0x28
110
 
#define OMAP_MCBSP_REG_SRGR1    0x2C
111
 
#define OMAP_MCBSP_REG_MCR2     0x30
112
 
#define OMAP_MCBSP_REG_MCR1     0x34
113
 
#define OMAP_MCBSP_REG_RCERA    0x38
114
 
#define OMAP_MCBSP_REG_RCERB    0x3C
115
 
#define OMAP_MCBSP_REG_XCERA    0x40
116
 
#define OMAP_MCBSP_REG_XCERB    0x44
117
 
#define OMAP_MCBSP_REG_PCR0     0x48
118
 
#define OMAP_MCBSP_REG_RCERC    0x4C
119
 
#define OMAP_MCBSP_REG_RCERD    0x50
120
 
#define OMAP_MCBSP_REG_XCERC    0x54
121
 
#define OMAP_MCBSP_REG_XCERD    0x58
122
 
#define OMAP_MCBSP_REG_RCERE    0x5C
123
 
#define OMAP_MCBSP_REG_RCERF    0x60
124
 
#define OMAP_MCBSP_REG_XCERE    0x64
125
 
#define OMAP_MCBSP_REG_XCERF    0x68
126
 
#define OMAP_MCBSP_REG_RCERG    0x6C
127
 
#define OMAP_MCBSP_REG_RCERH    0x70
128
 
#define OMAP_MCBSP_REG_XCERG    0x74
129
 
#define OMAP_MCBSP_REG_XCERH    0x78
130
 
#define OMAP_MCBSP_REG_SYSCON   0x8C
131
 
#define OMAP_MCBSP_REG_THRSH2   0x90
132
 
#define OMAP_MCBSP_REG_THRSH1   0x94
133
 
#define OMAP_MCBSP_REG_IRQST    0xA0
134
 
#define OMAP_MCBSP_REG_IRQEN    0xA4
135
 
#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
136
 
#define OMAP_MCBSP_REG_XCCR     0xAC
137
 
#define OMAP_MCBSP_REG_RCCR     0xB0
138
 
#define OMAP_MCBSP_REG_XBUFFSTAT        0xB4
139
 
#define OMAP_MCBSP_REG_RBUFFSTAT        0xB8
140
 
#define OMAP_MCBSP_REG_SSELCR   0xBC
141
 
 
 
41
/* McBSP register numbers. Register address offset = num * reg_step */
 
42
enum {
 
43
        /* Common registers */
 
44
        OMAP_MCBSP_REG_SPCR2 = 4,
 
45
        OMAP_MCBSP_REG_SPCR1,
 
46
        OMAP_MCBSP_REG_RCR2,
 
47
        OMAP_MCBSP_REG_RCR1,
 
48
        OMAP_MCBSP_REG_XCR2,
 
49
        OMAP_MCBSP_REG_XCR1,
 
50
        OMAP_MCBSP_REG_SRGR2,
 
51
        OMAP_MCBSP_REG_SRGR1,
 
52
        OMAP_MCBSP_REG_MCR2,
 
53
        OMAP_MCBSP_REG_MCR1,
 
54
        OMAP_MCBSP_REG_RCERA,
 
55
        OMAP_MCBSP_REG_RCERB,
 
56
        OMAP_MCBSP_REG_XCERA,
 
57
        OMAP_MCBSP_REG_XCERB,
 
58
        OMAP_MCBSP_REG_PCR0,
 
59
        OMAP_MCBSP_REG_RCERC,
 
60
        OMAP_MCBSP_REG_RCERD,
 
61
        OMAP_MCBSP_REG_XCERC,
 
62
        OMAP_MCBSP_REG_XCERD,
 
63
        OMAP_MCBSP_REG_RCERE,
 
64
        OMAP_MCBSP_REG_RCERF,
 
65
        OMAP_MCBSP_REG_XCERE,
 
66
        OMAP_MCBSP_REG_XCERF,
 
67
        OMAP_MCBSP_REG_RCERG,
 
68
        OMAP_MCBSP_REG_RCERH,
 
69
        OMAP_MCBSP_REG_XCERG,
 
70
        OMAP_MCBSP_REG_XCERH,
 
71
 
 
72
        /* OMAP1-OMAP2420 registers */
 
73
        OMAP_MCBSP_REG_DRR2 = 0,
 
74
        OMAP_MCBSP_REG_DRR1,
 
75
        OMAP_MCBSP_REG_DXR2,
 
76
        OMAP_MCBSP_REG_DXR1,
 
77
 
 
78
        /* OMAP2430 and onwards */
 
79
        OMAP_MCBSP_REG_DRR = 0,
 
80
        OMAP_MCBSP_REG_DXR = 2,
 
81
        OMAP_MCBSP_REG_SYSCON = 35,
 
82
        OMAP_MCBSP_REG_THRSH2,
 
83
        OMAP_MCBSP_REG_THRSH1,
 
84
        OMAP_MCBSP_REG_IRQST = 40,
 
85
        OMAP_MCBSP_REG_IRQEN,
 
86
        OMAP_MCBSP_REG_WAKEUPEN,
 
87
        OMAP_MCBSP_REG_XCCR,
 
88
        OMAP_MCBSP_REG_RCCR,
 
89
        OMAP_MCBSP_REG_XBUFFSTAT,
 
90
        OMAP_MCBSP_REG_RBUFFSTAT,
 
91
        OMAP_MCBSP_REG_SSELCR,
 
92
};
 
93
 
 
94
/* OMAP3 sidetone control registers */
142
95
#define OMAP_ST_REG_REV         0x00
143
96
#define OMAP_ST_REG_SYSCONFIG   0x10
144
97
#define OMAP_ST_REG_IRQSTATUS   0x18
147
100
#define OMAP_ST_REG_SFIRCR      0x28
148
101
#define OMAP_ST_REG_SSELCR      0x2C
149
102
 
150
 
#endif
151
 
 
152
103
/************************** McBSP SPCR1 bit definitions ***********************/
153
104
#define RRST                    0x0001
154
105
#define RRDY                    0x0002
333
284
};
334
285
 
335
286
typedef enum {
336
 
        OMAP_MCBSP1 = 0,
337
 
        OMAP_MCBSP2,
338
 
        OMAP_MCBSP3,
339
 
        OMAP_MCBSP4,
340
 
        OMAP_MCBSP5
341
 
} omap_mcbsp_id;
342
 
 
343
 
typedef int __bitwise omap_mcbsp_io_type_t;
344
 
#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
345
 
#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
346
 
 
347
 
typedef enum {
348
287
        OMAP_MCBSP_WORD_8 = 0,
349
288
        OMAP_MCBSP_WORD_12,
350
289
        OMAP_MCBSP_WORD_16,
353
292
        OMAP_MCBSP_WORD_32,
354
293
} omap_mcbsp_word_length;
355
294
 
356
 
typedef enum {
357
 
        OMAP_MCBSP_CLK_RISING = 0,
358
 
        OMAP_MCBSP_CLK_FALLING,
359
 
} omap_mcbsp_clk_polarity;
360
 
 
361
 
typedef enum {
362
 
        OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
363
 
        OMAP_MCBSP_FS_ACTIVE_LOW,
364
 
} omap_mcbsp_fs_polarity;
365
 
 
366
 
typedef enum {
367
 
        OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
368
 
        OMAP_MCBSP_CLK_STP_MODE_DELAY,
369
 
} omap_mcbsp_clk_stp_mode;
370
 
 
371
 
 
372
 
/******* SPI specific mode **********/
373
 
typedef enum {
374
 
        OMAP_MCBSP_SPI_MASTER = 0,
375
 
        OMAP_MCBSP_SPI_SLAVE,
376
 
} omap_mcbsp_spi_mode;
377
 
 
378
 
struct omap_mcbsp_spi_cfg {
379
 
        omap_mcbsp_spi_mode             spi_mode;
380
 
        omap_mcbsp_clk_polarity         rx_clock_polarity;
381
 
        omap_mcbsp_clk_polarity         tx_clock_polarity;
382
 
        omap_mcbsp_fs_polarity          fsx_polarity;
383
 
        u8                              clk_div;
384
 
        omap_mcbsp_clk_stp_mode         clk_stp_mode;
385
 
        omap_mcbsp_word_length          word_length;
386
 
};
387
 
 
388
295
/* Platform specific configuration */
389
296
struct omap_mcbsp_ops {
390
297
        void (*request)(unsigned int);
391
298
        void (*free)(unsigned int);
392
 
        int (*set_clks_src)(u8, u8);
393
299
};
394
300
 
395
301
struct omap_mcbsp_platform_data {
396
 
        unsigned long phys_base;
397
 
        u8 dma_rx_sync, dma_tx_sync;
398
 
        u16 rx_irq, tx_irq;
399
302
        struct omap_mcbsp_ops *ops;
400
 
#ifdef CONFIG_ARCH_OMAP3
401
 
        /* Sidetone block for McBSP 2 and 3 */
402
 
        unsigned long phys_base_st;
403
 
#endif
404
303
        u16 buffer_size;
405
 
        unsigned int mcbsp_config_type;
 
304
        u8 reg_size;
 
305
        u8 reg_step;
 
306
 
 
307
        /* McBSP platform and instance specific features */
 
308
        bool has_wakeup; /* Wakeup capability */
 
309
        bool has_ccr; /* Transceiver has configuration control registers */
 
310
        int (*enable_st_clock)(unsigned int, bool);
 
311
        int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
 
312
        int (*mux_signal)(struct device *dev, const char *signal, const char *src);
406
313
};
407
314
 
408
315
struct omap_mcbsp_st_data {
422
329
        void __iomem *io_base;
423
330
        u8 id;
424
331
        u8 free;
425
 
        omap_mcbsp_word_length rx_word_length;
426
 
        omap_mcbsp_word_length tx_word_length;
427
332
 
428
 
        omap_mcbsp_io_type_t io_type; /* IRQ or poll */
429
 
        /* IRQ based TX/RX */
430
333
        int rx_irq;
431
334
        int tx_irq;
432
335
 
433
336
        /* DMA stuff */
434
337
        u8 dma_rx_sync;
435
 
        short dma_rx_lch;
436
338
        u8 dma_tx_sync;
437
 
        short dma_tx_lch;
438
 
 
439
 
        /* Completion queues */
440
 
        struct completion tx_irq_completion;
441
 
        struct completion rx_irq_completion;
442
 
        struct completion tx_dma_completion;
443
 
        struct completion rx_dma_completion;
444
339
 
445
340
        /* Protect the field .free, while checking if the mcbsp is in use */
446
341
        spinlock_t lock;
447
342
        struct omap_mcbsp_platform_data *pdata;
448
343
        struct clk *fclk;
449
 
#ifdef CONFIG_ARCH_OMAP3
450
344
        struct omap_mcbsp_st_data *st_data;
451
345
        int dma_op_mode;
452
346
        u16 max_tx_thres;
453
347
        u16 max_rx_thres;
454
 
#endif
455
348
        void *reg_cache;
456
 
        unsigned int mcbsp_config_type;
 
349
        int reg_cache_size;
457
350
};
458
351
 
459
352
/**
465
358
};
466
359
 
467
360
extern struct omap_mcbsp **mcbsp_ptr;
468
 
extern int omap_mcbsp_count, omap_mcbsp_cache_size;
469
 
 
470
 
#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
471
 
#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 
361
extern int omap_mcbsp_count;
472
362
 
473
363
int omap_mcbsp_init(void);
474
 
void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
475
 
                        struct omap_mcbsp_platform_data *config, int size);
476
364
void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
477
 
#ifdef CONFIG_ARCH_OMAP3
478
365
void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
479
366
void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
480
367
u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
483
370
u16 omap_mcbsp_get_tx_delay(unsigned int id);
484
371
u16 omap_mcbsp_get_rx_delay(unsigned int id);
485
372
int omap_mcbsp_get_dma_op_mode(unsigned int id);
486
 
#else
487
 
static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
488
 
{ }
489
 
static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
490
 
{ }
491
 
static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
492
 
static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
493
 
static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
494
 
static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
495
 
static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
496
 
static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
497
 
#endif
498
373
int omap_mcbsp_request(unsigned int id);
499
374
void omap_mcbsp_free(unsigned int id);
500
375
void omap_mcbsp_start(unsigned int id, int tx, int rx);
501
376
void omap_mcbsp_stop(unsigned int id, int tx, int rx);
502
 
void omap_mcbsp_xmit_word(unsigned int id, u32 word);
503
 
u32 omap_mcbsp_recv_word(unsigned int id);
504
 
 
505
 
int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
506
 
int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
507
 
int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
508
 
int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
509
 
 
510
377
 
511
378
/* McBSP functional clock source changing function */
512
379
extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
513
 
/* SPI specific API */
514
 
void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
515
 
 
516
 
/* Polled read/write functions */
517
 
int omap_mcbsp_pollread(unsigned int id, u16 * buf);
518
 
int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
519
 
int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
520
380
 
521
381
/* McBSP signal muxing API */
522
382
void omap2_mcbsp1_mux_clkr_src(u8 mux);
525
385
int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
526
386
int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
527
387
 
528
 
#ifdef CONFIG_ARCH_OMAP3
529
388
/* Sidetone specific API */
530
389
int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
531
390
int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
532
391
int omap_st_enable(unsigned int id);
533
392
int omap_st_disable(unsigned int id);
534
393
int omap_st_is_enabled(unsigned int id);
535
 
#else
536
 
static inline int omap_st_set_chgain(unsigned int id, int channel,
537
 
                                     s16 chgain) { return 0; }
538
 
static inline int omap_st_get_chgain(unsigned int id, int channel,
539
 
                                     s16 *chgain) { return 0; }
540
 
static inline int omap_st_enable(unsigned int id) { return 0; }
541
 
static inline int omap_st_disable(unsigned int id) { return 0; }
542
 
static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
543
 
#endif
544
394
 
545
395
#endif