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/*******************************************************************************
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Intel PRO/1000 Linux driver
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Copyright(c) 1999 - 2011 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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* 80003ES2LAN Gigabit Ethernet Controller (Copper)
31
* 80003ES2LAN Gigabit Ethernet Controller (Serdes)
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#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
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#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
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#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
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#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
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#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
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#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
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#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
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#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
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#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
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#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
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#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
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#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
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#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
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#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
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#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
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#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
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/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
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#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
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#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
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#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
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#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
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#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
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/* PHY Specific Control Register 2 (Page 0, Register 26) */
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#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
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/* 1=Reverse Auto-Negotiation */
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/* MAC Specific Control Register (Page 2, Register 21) */
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/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
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#define GG82563_MSCR_TX_CLK_MASK 0x0007
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#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
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#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
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#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
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#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
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/* DSP Distance Register (Page 5, Register 26) */
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#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
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/* Kumeran Mode Control Register (Page 193, Register 16) */
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#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
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/* Max number of times Kumeran read/write should be validated */
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#define GG82563_MAX_KMRN_RETRY 0x5
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/* Power Management Control Register (Page 193, Register 20) */
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#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
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/* 1=Enable SERDES Electrical Idle */
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/* In-Band Control Register (Page 194, Register 18) */
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#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
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* A table for the GG82563 cable length where the range is defined
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* with a lower bound at "index" and the upper bound at
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static const u16 e1000_gg82563_cable_length_table[] = {
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0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
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#define GG82563_CABLE_LENGTH_TABLE_SIZE \
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ARRAY_SIZE(e1000_gg82563_cable_length_table)
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static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
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static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
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static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
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static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
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static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
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static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
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static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
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static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
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static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
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static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
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static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
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* e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
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* @hw: pointer to the HW structure
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static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
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struct e1000_phy_info *phy = &hw->phy;
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if (hw->phy.media_type != e1000_media_type_copper) {
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phy->type = e1000_phy_none;
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phy->ops.power_up = e1000_power_up_phy_copper;
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phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
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phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
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phy->reset_delay_us = 100;
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phy->type = e1000_phy_gg82563;
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/* This can only be done after all function pointers are setup. */
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ret_val = e1000e_get_phy_id(hw);
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if (phy->id != GG82563_E_PHY_ID)
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return -E1000_ERR_PHY;
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* e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
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* @hw: pointer to the HW structure
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static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = er32(EECD);
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nvm->opcode_bits = 8;
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switch (nvm->override) {
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case e1000_nvm_override_spi_large:
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nvm->address_bits = 16;
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case e1000_nvm_override_spi_small:
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nvm->address_bits = 8;
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nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
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nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
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nvm->type = e1000_nvm_eeprom_spi;
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size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
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E1000_EECD_SIZE_EX_SHIFT);
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* Added to a constant, "size" becomes the left-shift value
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* for setting word_size.
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size += NVM_WORD_SIZE_BASE_SHIFT;
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/* EEPROM access above 16k is unsupported */
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nvm->word_size = 1 << size;
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* e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
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* @hw: pointer to the HW structure
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static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
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struct e1000_hw *hw = &adapter->hw;
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struct e1000_mac_info *mac = &hw->mac;
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struct e1000_mac_operations *func = &mac->ops;
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switch (adapter->pdev->device) {
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case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
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hw->phy.media_type = e1000_media_type_internal_serdes;
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hw->phy.media_type = e1000_media_type_copper;
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/* Set mta register count */
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mac->mta_reg_count = 128;
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/* Set rar entry count */
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mac->rar_entry_count = E1000_RAR_ENTRIES;
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mac->has_fwsm = true;
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/* ARC supported; valid only if manageability features are enabled. */
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mac->arc_subsystem_valid =
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(er32(FWSM) & E1000_FWSM_MODE_MASK)
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/* Adaptive IFS not supported */
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mac->adaptive_ifs = false;
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switch (hw->phy.media_type) {
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case e1000_media_type_copper:
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func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
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func->check_for_link = e1000e_check_for_copper_link;
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case e1000_media_type_fiber:
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func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
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func->check_for_link = e1000e_check_for_fiber_link;
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case e1000_media_type_internal_serdes:
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func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
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func->check_for_link = e1000e_check_for_serdes_link;
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return -E1000_ERR_CONFIG;
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/* set lan id for port to determine which phy lock to use */
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hw->mac.ops.set_lan_id(hw);
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static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
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struct e1000_hw *hw = &adapter->hw;
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rc = e1000_init_mac_params_80003es2lan(adapter);
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rc = e1000_init_nvm_params_80003es2lan(hw);
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rc = e1000_init_phy_params_80003es2lan(hw);
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* e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
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* @hw: pointer to the HW structure
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* A wrapper to acquire access rights to the correct PHY.
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static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
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mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
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return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
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* e1000_release_phy_80003es2lan - Release rights to access PHY
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* @hw: pointer to the HW structure
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* A wrapper to release access rights to the correct PHY.
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static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
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mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
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e1000_release_swfw_sync_80003es2lan(hw, mask);
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* e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
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* @hw: pointer to the HW structure
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* Acquire the semaphore to access the Kumeran interface.
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static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
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mask = E1000_SWFW_CSR_SM;
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return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
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* e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
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* @hw: pointer to the HW structure
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* Release the semaphore used to access the Kumeran interface
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static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
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mask = E1000_SWFW_CSR_SM;
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e1000_release_swfw_sync_80003es2lan(hw, mask);
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* e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
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* @hw: pointer to the HW structure
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* Acquire the semaphore to access the EEPROM.
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static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
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ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
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ret_val = e1000e_acquire_nvm(hw);
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e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
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* e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
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* @hw: pointer to the HW structure
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* Release the semaphore used to access the EEPROM.
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static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
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e1000e_release_nvm(hw);
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e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
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* e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
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* @hw: pointer to the HW structure
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* @mask: specifies which semaphore to acquire
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* Acquire the SW/FW semaphore to access the PHY or NVM. The mask
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* will also specify which port we're acquiring the lock for.
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static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
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u32 fwmask = mask << 16;
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while (i < timeout) {
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if (e1000e_get_hw_semaphore(hw))
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return -E1000_ERR_SWFW_SYNC;
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swfw_sync = er32(SW_FW_SYNC);
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if (!(swfw_sync & (fwmask | swmask)))
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* Firmware currently using resource (fwmask)
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* or other software thread using resource (swmask)
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e1000e_put_hw_semaphore(hw);
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e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
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return -E1000_ERR_SWFW_SYNC;
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ew32(SW_FW_SYNC, swfw_sync);
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e1000e_put_hw_semaphore(hw);
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* e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
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* @hw: pointer to the HW structure
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* @mask: specifies which semaphore to acquire
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* Release the SW/FW semaphore used to access the PHY or NVM. The mask
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* will also specify which port we're releasing the lock for.
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static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
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while (e1000e_get_hw_semaphore(hw) != 0)
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swfw_sync = er32(SW_FW_SYNC);
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ew32(SW_FW_SYNC, swfw_sync);
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e1000e_put_hw_semaphore(hw);
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* e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
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* @hw: pointer to the HW structure
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* @offset: offset of the register to read
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* @data: pointer to the data returned from the operation
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* Read the GG82563 PHY register.
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static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
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u32 offset, u16 *data)
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ret_val = e1000_acquire_phy_80003es2lan(hw);
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/* Select Configuration Page */
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if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
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page_select = GG82563_PHY_PAGE_SELECT;
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* Use Alternative Page Select register to access
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* registers 30 and 31
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page_select = GG82563_PHY_PAGE_SELECT_ALT;
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temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
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ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
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e1000_release_phy_80003es2lan(hw);
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if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
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* The "ready" bit in the MDIC register may be incorrectly set
479
* before the device has completed the "Page Select" MDI
480
* transaction. So we wait 200us after each MDI command...
484
/* ...and verify the command was successful. */
485
ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
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if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
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ret_val = -E1000_ERR_PHY;
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e1000_release_phy_80003es2lan(hw);
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ret_val = e1000e_read_phy_reg_mdic(hw,
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MAX_PHY_REG_ADDRESS & offset,
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ret_val = e1000e_read_phy_reg_mdic(hw,
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MAX_PHY_REG_ADDRESS & offset,
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e1000_release_phy_80003es2lan(hw);
512
* e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
513
* @hw: pointer to the HW structure
514
* @offset: offset of the register to read
515
* @data: value to write to the register
517
* Write to the GG82563 PHY register.
519
static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
520
u32 offset, u16 data)
526
ret_val = e1000_acquire_phy_80003es2lan(hw);
530
/* Select Configuration Page */
531
if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
532
page_select = GG82563_PHY_PAGE_SELECT;
535
* Use Alternative Page Select register to access
536
* registers 30 and 31
538
page_select = GG82563_PHY_PAGE_SELECT_ALT;
541
temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
542
ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
544
e1000_release_phy_80003es2lan(hw);
548
if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
550
* The "ready" bit in the MDIC register may be incorrectly set
551
* before the device has completed the "Page Select" MDI
552
* transaction. So we wait 200us after each MDI command...
556
/* ...and verify the command was successful. */
557
ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
559
if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
560
e1000_release_phy_80003es2lan(hw);
561
return -E1000_ERR_PHY;
566
ret_val = e1000e_write_phy_reg_mdic(hw,
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MAX_PHY_REG_ADDRESS & offset,
572
ret_val = e1000e_write_phy_reg_mdic(hw,
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MAX_PHY_REG_ADDRESS & offset,
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e1000_release_phy_80003es2lan(hw);
583
* e1000_write_nvm_80003es2lan - Write to ESB2 NVM
584
* @hw: pointer to the HW structure
585
* @offset: offset of the register to read
586
* @words: number of words to write
587
* @data: buffer of data to write to the NVM
589
* Write "words" of data to the ESB2 NVM.
591
static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
592
u16 words, u16 *data)
594
return e1000e_write_nvm_spi(hw, offset, words, data);
598
* e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
599
* @hw: pointer to the HW structure
601
* Wait a specific amount of time for manageability processes to complete.
602
* This is a function pointer entry point called by the phy module.
604
static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
606
s32 timeout = PHY_CFG_TIMEOUT;
607
u32 mask = E1000_NVM_CFG_DONE_PORT_0;
609
if (hw->bus.func == 1)
610
mask = E1000_NVM_CFG_DONE_PORT_1;
613
if (er32(EEMNGCTL) & mask)
615
usleep_range(1000, 2000);
619
e_dbg("MNG configuration cycle has not completed.\n");
620
return -E1000_ERR_RESET;
627
* e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
628
* @hw: pointer to the HW structure
630
* Force the speed and duplex settings onto the PHY. This is a
631
* function pointer entry point called by the phy module.
633
static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
640
* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
641
* forced whenever speed and duplex are forced.
643
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
647
phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
648
ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
652
e_dbg("GG82563 PSCR: %X\n", phy_data);
654
ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
658
e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
660
/* Reset the phy to commit changes. */
661
phy_data |= MII_CR_RESET;
663
ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
669
if (hw->phy.autoneg_wait_to_complete) {
670
e_dbg("Waiting for forced speed/duplex link "
671
"on GG82563 phy.\n");
673
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
680
* We didn't get link.
681
* Reset the DSP and cross our fingers.
683
ret_val = e1000e_phy_reset_dsp(hw);
689
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
695
ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
700
* Resetting the phy means we need to verify the TX_CLK corresponds
701
* to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
703
phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
704
if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
705
phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
707
phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
710
* In addition, we must re-enable CRS on Tx for both half and full
713
phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
714
ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
720
* e1000_get_cable_length_80003es2lan - Set approximate cable length
721
* @hw: pointer to the HW structure
723
* Find the approximate cable length as measured by the GG82563 PHY.
724
* This is a function pointer entry point called by the phy module.
726
static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
728
struct e1000_phy_info *phy = &hw->phy;
732
ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
736
index = phy_data & GG82563_DSPD_CABLE_LENGTH;
738
if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
739
ret_val = -E1000_ERR_PHY;
743
phy->min_cable_length = e1000_gg82563_cable_length_table[index];
744
phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
746
phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
753
* e1000_get_link_up_info_80003es2lan - Report speed and duplex
754
* @hw: pointer to the HW structure
755
* @speed: pointer to speed buffer
756
* @duplex: pointer to duplex buffer
758
* Retrieve the current speed and duplex configuration.
760
static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
765
if (hw->phy.media_type == e1000_media_type_copper) {
766
ret_val = e1000e_get_speed_and_duplex_copper(hw,
769
hw->phy.ops.cfg_on_link_up(hw);
771
ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
780
* e1000_reset_hw_80003es2lan - Reset the ESB2 controller
781
* @hw: pointer to the HW structure
783
* Perform a global reset to the ESB2 controller.
785
static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
791
* Prevent the PCI-E bus from sticking if there is no TLP connection
792
* on the last TLP read/write transaction when MAC is reset.
794
ret_val = e1000e_disable_pcie_master(hw);
796
e_dbg("PCI-E Master disable polling has failed.\n");
798
e_dbg("Masking off all interrupts\n");
799
ew32(IMC, 0xffffffff);
802
ew32(TCTL, E1000_TCTL_PSP);
805
usleep_range(10000, 20000);
809
ret_val = e1000_acquire_phy_80003es2lan(hw);
810
e_dbg("Issuing a global reset to MAC\n");
811
ew32(CTRL, ctrl | E1000_CTRL_RST);
812
e1000_release_phy_80003es2lan(hw);
814
ret_val = e1000e_get_auto_rd_done(hw);
816
/* We don't want to continue accessing MAC registers. */
819
/* Clear any pending interrupt events. */
820
ew32(IMC, 0xffffffff);
823
ret_val = e1000_check_alt_mac_addr_generic(hw);
829
* e1000_init_hw_80003es2lan - Initialize the ESB2 controller
830
* @hw: pointer to the HW structure
832
* Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
834
static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
836
struct e1000_mac_info *mac = &hw->mac;
841
e1000_initialize_hw_bits_80003es2lan(hw);
843
/* Initialize identification LED */
844
ret_val = e1000e_id_led_init(hw);
846
e_dbg("Error initializing identification LED\n");
847
/* This is not fatal and we should not stop init due to this */
849
/* Disabling VLAN filtering */
850
e_dbg("Initializing the IEEE VLAN\n");
851
mac->ops.clear_vfta(hw);
853
/* Setup the receive address. */
854
e1000e_init_rx_addrs(hw, mac->rar_entry_count);
856
/* Zero out the Multicast HASH table */
857
e_dbg("Zeroing the MTA\n");
858
for (i = 0; i < mac->mta_reg_count; i++)
859
E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
861
/* Setup link and flow control */
862
ret_val = e1000e_setup_link(hw);
864
/* Set the transmit descriptor write-back policy */
865
reg_data = er32(TXDCTL(0));
866
reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
867
E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
868
ew32(TXDCTL(0), reg_data);
870
/* ...for both queues. */
871
reg_data = er32(TXDCTL(1));
872
reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
873
E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
874
ew32(TXDCTL(1), reg_data);
876
/* Enable retransmit on late collisions */
877
reg_data = er32(TCTL);
878
reg_data |= E1000_TCTL_RTLC;
879
ew32(TCTL, reg_data);
881
/* Configure Gigabit Carry Extend Padding */
882
reg_data = er32(TCTL_EXT);
883
reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
884
reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
885
ew32(TCTL_EXT, reg_data);
887
/* Configure Transmit Inter-Packet Gap */
888
reg_data = er32(TIPG);
889
reg_data &= ~E1000_TIPG_IPGT_MASK;
890
reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
891
ew32(TIPG, reg_data);
893
reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
894
reg_data &= ~0x00100000;
895
E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
897
/* default to true to enable the MDIC W/A */
898
hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
900
ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
901
E1000_KMRNCTRLSTA_OFFSET >>
902
E1000_KMRNCTRLSTA_OFFSET_SHIFT,
905
if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
906
E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
907
hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
911
* Clear all of the statistics registers (clear on read). It is
912
* important that we do this after we have tried to establish link
913
* because the symbol error count will increment wildly if there
916
e1000_clear_hw_cntrs_80003es2lan(hw);
922
* e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
923
* @hw: pointer to the HW structure
925
* Initializes required hardware-dependent bits needed for normal operation.
927
static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
931
/* Transmit Descriptor Control 0 */
932
reg = er32(TXDCTL(0));
934
ew32(TXDCTL(0), reg);
936
/* Transmit Descriptor Control 1 */
937
reg = er32(TXDCTL(1));
939
ew32(TXDCTL(1), reg);
941
/* Transmit Arbitration Control 0 */
943
reg &= ~(0xF << 27); /* 30:27 */
944
if (hw->phy.media_type != e1000_media_type_copper)
948
/* Transmit Arbitration Control 1 */
950
if (er32(TCTL) & E1000_TCTL_MULR)
958
* e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
959
* @hw: pointer to the HW structure
961
* Setup some GG82563 PHY registers for obtaining link
963
static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
965
struct e1000_phy_info *phy = &hw->phy;
970
ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
974
data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
975
/* Use 25MHz for both link down and 1000Base-T for Tx clock. */
976
data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
978
ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
984
* MDI/MDI-X = 0 (default)
985
* 0 - Auto for all speeds
988
* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
990
ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
994
data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
998
data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1001
data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1005
data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1011
* disable_polarity_correction = 0 (default)
1012
* Automatic Correction for Reversed Cable Polarity
1016
data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1017
if (phy->disable_polarity_correction)
1018
data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1020
ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1024
/* SW Reset the PHY so all changes take effect */
1025
ret_val = e1000e_commit_phy(hw);
1027
e_dbg("Error Resetting the PHY\n");
1031
/* Bypass Rx and Tx FIFO's */
1032
ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1033
E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1034
E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1035
E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1039
ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1040
E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1044
data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1045
ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1046
E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1051
ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1055
data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1056
ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1060
ctrl_ext = er32(CTRL_EXT);
1061
ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1062
ew32(CTRL_EXT, ctrl_ext);
1064
ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1069
* Do not init these registers when the HW is in IAMT mode, since the
1070
* firmware will have already initialized them. We only initialize
1071
* them if the HW is not in IAMT mode.
1073
if (!e1000e_check_mng_mode(hw)) {
1074
/* Enable Electrical Idle on the PHY */
1075
data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1076
ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1080
ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1084
data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1085
ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1091
* Workaround: Disable padding in Kumeran interface in the MAC
1092
* and in the PHY to avoid CRC errors.
1094
ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1098
data |= GG82563_ICR_DIS_PADDING;
1099
ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1107
* e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1108
* @hw: pointer to the HW structure
1110
* Essentially a wrapper for setting up all things "copper" related.
1111
* This is a function pointer entry point called by the mac module.
1113
static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1120
ctrl |= E1000_CTRL_SLU;
1121
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1125
* Set the mac to wait the maximum time between each
1126
* iteration and increase the max iterations when
1127
* polling the phy; this fixes erroneous timeouts at 10Mbps.
1129
ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1133
ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1138
ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1142
ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1143
E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1147
reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1148
ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1149
E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1154
ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1158
ret_val = e1000e_setup_copper_link(hw);
1164
* e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1165
* @hw: pointer to the HW structure
1166
* @duplex: current duplex setting
1168
* Configure the KMRN interface by applying last minute quirks for
1171
static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1177
if (hw->phy.media_type == e1000_media_type_copper) {
1178
ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1183
if (speed == SPEED_1000)
1184
ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1186
ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1193
* e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1194
* @hw: pointer to the HW structure
1195
* @duplex: current duplex setting
1197
* Configure the KMRN interface by applying last minute quirks for
1200
static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1205
u16 reg_data, reg_data2;
1207
reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1208
ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1209
E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1214
/* Configure Transmit Inter-Packet Gap */
1216
tipg &= ~E1000_TIPG_IPGT_MASK;
1217
tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1221
ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1225
ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1229
} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1231
if (duplex == HALF_DUPLEX)
1232
reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1234
reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1236
ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1242
* e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1243
* @hw: pointer to the HW structure
1245
* Configure the KMRN interface by applying last minute quirks for
1246
* gigabit operation.
1248
static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1251
u16 reg_data, reg_data2;
1255
reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1256
ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1257
E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1262
/* Configure Transmit Inter-Packet Gap */
1264
tipg &= ~E1000_TIPG_IPGT_MASK;
1265
tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1269
ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1273
ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1277
} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1279
reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1280
ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1286
* e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1287
* @hw: pointer to the HW structure
1288
* @offset: register offset to be read
1289
* @data: pointer to the read data
1291
* Acquire semaphore, then read the PHY register at offset
1292
* using the kumeran interface. The information retrieved is stored in data.
1293
* Release the semaphore before exiting.
1295
static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1301
ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1305
kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1306
E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1307
ew32(KMRNCTRLSTA, kmrnctrlsta);
1311
kmrnctrlsta = er32(KMRNCTRLSTA);
1312
*data = (u16)kmrnctrlsta;
1314
e1000_release_mac_csr_80003es2lan(hw);
1320
* e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1321
* @hw: pointer to the HW structure
1322
* @offset: register offset to write to
1323
* @data: data to write at register offset
1325
* Acquire semaphore, then write the data to PHY register
1326
* at the offset using the kumeran interface. Release semaphore
1329
static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1335
ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1339
kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1340
E1000_KMRNCTRLSTA_OFFSET) | data;
1341
ew32(KMRNCTRLSTA, kmrnctrlsta);
1345
e1000_release_mac_csr_80003es2lan(hw);
1351
* e1000_read_mac_addr_80003es2lan - Read device MAC address
1352
* @hw: pointer to the HW structure
1354
static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1359
* If there's an alternate MAC address place it in RAR0
1360
* so that it will override the Si installed default perm
1363
ret_val = e1000_check_alt_mac_addr_generic(hw);
1367
ret_val = e1000_read_mac_addr_generic(hw);
1374
* e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1375
* @hw: pointer to the HW structure
1377
* In the case of a PHY power down to save power, or to turn off link during a
1378
* driver unload, or wake on lan is not enabled, remove the link.
1380
static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1382
/* If the management interface is not enabled, then power down */
1383
if (!(hw->mac.ops.check_mng_mode(hw) ||
1384
hw->phy.ops.check_reset_block(hw)))
1385
e1000_power_down_phy_copper(hw);
1389
* e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1390
* @hw: pointer to the HW structure
1392
* Clears the hardware counters by reading the counter registers.
1394
static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1396
e1000e_clear_hw_cntrs_base(hw);
1434
static struct e1000_mac_operations es2_mac_ops = {
1435
.read_mac_addr = e1000_read_mac_addr_80003es2lan,
1436
.id_led_init = e1000e_id_led_init,
1437
.blink_led = e1000e_blink_led_generic,
1438
.check_mng_mode = e1000e_check_mng_mode_generic,
1439
/* check_for_link dependent on media type */
1440
.cleanup_led = e1000e_cleanup_led_generic,
1441
.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1442
.get_bus_info = e1000e_get_bus_info_pcie,
1443
.set_lan_id = e1000_set_lan_id_multi_port_pcie,
1444
.get_link_up_info = e1000_get_link_up_info_80003es2lan,
1445
.led_on = e1000e_led_on_generic,
1446
.led_off = e1000e_led_off_generic,
1447
.update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1448
.write_vfta = e1000_write_vfta_generic,
1449
.clear_vfta = e1000_clear_vfta_generic,
1450
.reset_hw = e1000_reset_hw_80003es2lan,
1451
.init_hw = e1000_init_hw_80003es2lan,
1452
.setup_link = e1000e_setup_link,
1453
/* setup_physical_interface dependent on media type */
1454
.setup_led = e1000e_setup_led_generic,
1457
static struct e1000_phy_operations es2_phy_ops = {
1458
.acquire = e1000_acquire_phy_80003es2lan,
1459
.check_polarity = e1000_check_polarity_m88,
1460
.check_reset_block = e1000e_check_reset_block_generic,
1461
.commit = e1000e_phy_sw_reset,
1462
.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1463
.get_cfg_done = e1000_get_cfg_done_80003es2lan,
1464
.get_cable_length = e1000_get_cable_length_80003es2lan,
1465
.get_info = e1000e_get_phy_info_m88,
1466
.read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1467
.release = e1000_release_phy_80003es2lan,
1468
.reset = e1000e_phy_hw_reset_generic,
1469
.set_d0_lplu_state = NULL,
1470
.set_d3_lplu_state = e1000e_set_d3_lplu_state,
1471
.write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1472
.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1475
static struct e1000_nvm_operations es2_nvm_ops = {
1476
.acquire = e1000_acquire_nvm_80003es2lan,
1477
.read = e1000e_read_nvm_eerd,
1478
.release = e1000_release_nvm_80003es2lan,
1479
.update = e1000e_update_nvm_checksum_generic,
1480
.valid_led_default = e1000e_valid_led_default,
1481
.validate = e1000e_validate_nvm_checksum_generic,
1482
.write = e1000_write_nvm_80003es2lan,
1485
struct e1000_info e1000_es2_info = {
1486
.mac = e1000_80003es2lan,
1487
.flags = FLAG_HAS_HW_VLAN_FILTER
1488
| FLAG_HAS_JUMBO_FRAMES
1490
| FLAG_APME_IN_CTRL3
1491
| FLAG_RX_CSUM_ENABLED
1492
| FLAG_HAS_CTRLEXT_ON_LOAD
1493
| FLAG_RX_NEEDS_RESTART /* errata */
1494
| FLAG_TARC_SET_BIT_ZERO /* errata */
1495
| FLAG_APME_CHECK_PORT_B
1496
| FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1497
| FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1498
.flags2 = FLAG2_DMA_BURST,
1500
.max_hw_frame_size = DEFAULT_JUMBO,
1501
.get_variants = e1000_get_variants_80003es2lan,
1502
.mac_ops = &es2_mac_ops,
1503
.phy_ops = &es2_phy_ops,
1504
.nvm_ops = &es2_nvm_ops,
added
removed
drivers/net/e1000e/es2lan.c
