149
* enum ddr_pwrst - DDR power states definition
150
* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
152
* @DDR_PWR_STATE_OFFLOWLAT:
153
* @DDR_PWR_STATE_OFFHIGHLAT:
156
DDR_PWR_STATE_UNCHANGED = 0x00,
157
DDR_PWR_STATE_ON = 0x01,
158
DDR_PWR_STATE_OFFLOWLAT = 0x02,
159
DDR_PWR_STATE_OFFHIGHLAT = 0x03
163
* enum arm_opp - ARM OPP states definition
165
* @ARM_NO_CHANGE: The ARM operating point is unchanged
166
* @ARM_100_OPP: The new ARM operating point is arm100opp
167
* @ARM_50_OPP: The new ARM operating point is arm50opp
168
* @ARM_MAX_OPP: Operating point is "max" (more than 100)
169
* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
170
* @ARM_EXTCLK: The new ARM operating point is armExtClk
174
ARM_NO_CHANGE = 0x01,
178
ARM_MAX_FREQ100OPP = 0x05,
183
* enum ape_opp - APE OPP states definition
185
* @APE_NO_CHANGE: The APE operating point is unchanged
186
* @APE_100_OPP: The new APE operating point is ape100opp
191
APE_NO_CHANGE = 0x01,
197
148
* enum hw_acc_state - State definition for hardware accelerator
198
149
* @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
199
150
* @HW_OFF: The hardware accelerator must be switched off
470
421
/* End of file previously known as prcmu-fw-defs_v1.h */
472
/* PRCMU Wakeup defines */
473
enum prcmu_wakeup_index {
474
PRCMU_WAKEUP_INDEX_RTC,
475
PRCMU_WAKEUP_INDEX_RTT0,
476
PRCMU_WAKEUP_INDEX_RTT1,
477
PRCMU_WAKEUP_INDEX_HSI0,
478
PRCMU_WAKEUP_INDEX_HSI1,
479
PRCMU_WAKEUP_INDEX_USB,
480
PRCMU_WAKEUP_INDEX_ABB,
481
PRCMU_WAKEUP_INDEX_ABB_FIFO,
482
PRCMU_WAKEUP_INDEX_ARM,
483
NUM_PRCMU_WAKEUP_INDICES
485
#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
487
/* PRCMU QoS APE OPP class */
488
#define PRCMU_QOS_APE_OPP 1
489
#define PRCMU_QOS_DDR_OPP 2
490
#define PRCMU_QOS_DEFAULT_VALUE -1
493
424
* enum hw_acc_dev - enum for hw accelerators
494
425
* @HW_ACC_SVAMMDSP: for SVAMMDSP
530
* Ids for all EPODs (power domains)
531
* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
532
* - EPOD_ID_SVAPIPE: power domain for SVA pipe
533
* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
534
* - EPOD_ID_SIAPIPE: power domain for SIA pipe
535
* - EPOD_ID_SGA: power domain for SGA
536
* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
537
* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
538
* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
539
* - NUM_EPOD_ID: number of power domains
541
#define EPOD_ID_SVAMMDSP 0
542
#define EPOD_ID_SVAPIPE 1
543
#define EPOD_ID_SIAMMDSP 2
544
#define EPOD_ID_SIAPIPE 3
545
#define EPOD_ID_SGA 4
546
#define EPOD_ID_B2R2_MCDE 5
547
#define EPOD_ID_ESRAM12 6
548
#define EPOD_ID_ESRAM34 7
549
#define NUM_EPOD_ID 8
552
* state definition for EPOD (power domain)
553
* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
554
* - EPOD_STATE_OFF: The EPOD is switched off
555
* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
557
* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
558
* - EPOD_STATE_ON: Same as above, but with clock enabled
560
#define EPOD_STATE_NO_CHANGE 0x00
561
#define EPOD_STATE_OFF 0x01
562
#define EPOD_STATE_RAMRET 0x02
563
#define EPOD_STATE_ON_CLK_OFF 0x03
564
#define EPOD_STATE_ON 0x04
569
#define PRCMU_CLKSRC_CLK38M 0x00
570
#define PRCMU_CLKSRC_ACLK 0x01
571
#define PRCMU_CLKSRC_SYSCLK 0x02
572
#define PRCMU_CLKSRC_LCDCLK 0x03
573
#define PRCMU_CLKSRC_SDMMCCLK 0x04
574
#define PRCMU_CLKSRC_TVCLK 0x05
575
#define PRCMU_CLKSRC_TIMCLK 0x06
576
#define PRCMU_CLKSRC_CLK009 0x07
577
/* These are only valid for CLKOUT1: */
578
#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
579
#define PRCMU_CLKSRC_I2CCLK 0x41
580
#define PRCMU_CLKSRC_MSP02CLK 0x42
581
#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
582
#define PRCMU_CLKSRC_HSIRXCLK 0x44
583
#define PRCMU_CLKSRC_HSITXCLK 0x45
584
#define PRCMU_CLKSRC_ARMCLKFIX 0x46
585
#define PRCMU_CLKSRC_HDMICLK 0x47
588
461
* Definitions for autonomous power management configuration.
624
* enum ddr_opp - DDR OPP states definition
625
* @DDR_100_OPP: The new DDR operating point is ddr100opp
626
* @DDR_50_OPP: The new DDR operating point is ddr50opp
627
* @DDR_25_OPP: The new DDR operating point is ddr25opp
668
PRCMU_NUM_REG_CLOCKS,
669
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
674
* Definitions for controlling ESRAM0 in deep sleep.
676
#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
677
#define ESRAM0_DEEP_SLEEP_STATE_RET 2
679
#ifdef CONFIG_MFD_DB8500_PRCMU
680
void __init prcmu_early_init(void);
681
int prcmu_set_display_clocks(void);
682
int prcmu_disable_dsipll(void);
683
int prcmu_enable_dsipll(void);
685
static inline void __init prcmu_early_init(void) {}
688
#ifdef CONFIG_MFD_DB8500_PRCMU
496
#ifdef CONFIG_MFD_DB8500_PRCMU
498
void db8500_prcmu_early_init(void);
690
499
int prcmu_set_rc_a2p(enum romcode_write);
691
500
enum romcode_read prcmu_get_rc_p2a(void);
692
501
enum ap_pwrst prcmu_get_xp70_current_state(void);
693
int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
695
void prcmu_enable_wakeups(u32 wakeups);
696
static inline void prcmu_disable_wakeups(void)
698
prcmu_enable_wakeups(0);
701
void prcmu_config_abb_event_readout(u32 abb_events);
702
void prcmu_get_abb_event_buffer(void __iomem **buf);
703
int prcmu_set_arm_opp(u8 opp);
704
int prcmu_get_arm_opp(void);
705
502
bool prcmu_has_arm_maxopp(void);
706
503
bool prcmu_is_u8400(void);
707
504
int prcmu_set_ape_opp(u8 opp);
710
507
int prcmu_release_usb_wakeup_state(void);
711
508
int prcmu_set_ddr_opp(u8 opp);
712
509
int prcmu_get_ddr_opp(void);
713
unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
714
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
715
510
/* NOTE! Use regulator framework instead */
716
511
int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
717
int prcmu_set_epod(u16 epod_id, u8 epod_state);
718
512
void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
719
513
struct prcmu_auto_pm_config *idle);
720
514
bool prcmu_is_auto_pm_enabled(void);
722
516
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
723
int prcmu_request_clock(u8 clock, bool enable);
724
517
int prcmu_set_clock_divider(u8 clock, u8 divider);
725
int prcmu_config_esram0_deep_sleep(u8 state);
726
518
int prcmu_config_hotdog(u8 threshold);
727
519
int prcmu_config_hotmon(u8 low, u8 high);
728
520
int prcmu_start_temp_sense(u16 cycles32k);
733
525
void prcmu_ac_wake_req(void);
734
526
void prcmu_ac_sleep_req(void);
735
void prcmu_system_reset(u16 reset_code);
736
527
void prcmu_modem_reset(void);
737
bool prcmu_is_ac_wake_requested(void);
738
528
void prcmu_enable_spi2(void);
739
529
void prcmu_disable_spi2(void);
531
int prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
532
int prcmu_enable_a9wdog(u8 id);
533
int prcmu_disable_a9wdog(u8 id);
534
int prcmu_kick_a9wdog(u8 id);
535
int prcmu_load_a9wdog(u8 id, u32 val);
537
void db8500_prcmu_system_reset(u16 reset_code);
538
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
539
void db8500_prcmu_enable_wakeups(u32 wakeups);
540
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
541
int db8500_prcmu_request_clock(u8 clock, bool enable);
542
int db8500_prcmu_set_display_clocks(void);
543
int db8500_prcmu_disable_dsipll(void);
544
int db8500_prcmu_enable_dsipll(void);
545
void db8500_prcmu_config_abb_event_readout(u32 abb_events);
546
void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
547
int db8500_prcmu_config_esram0_deep_sleep(u8 state);
548
u16 db8500_prcmu_get_reset_code(void);
549
bool db8500_prcmu_is_ac_wake_requested(void);
550
int db8500_prcmu_set_arm_opp(u8 opp);
551
int db8500_prcmu_get_arm_opp(void);
741
553
#else /* !CONFIG_MFD_DB8500_PRCMU */
555
static inline void db8500_prcmu_early_init(void) {}
743
557
static inline int prcmu_set_rc_a2p(enum romcode_write code)
755
569
return AP_EXECUTE;
758
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
764
static inline void prcmu_enable_wakeups(u32 wakeups) {}
766
static inline void prcmu_disable_wakeups(void) {}
768
static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
770
static inline int prcmu_set_arm_opp(u8 opp)
775
static inline int prcmu_get_arm_opp(void)
780
static bool prcmu_has_arm_maxopp(void)
572
static inline bool prcmu_has_arm_maxopp(void)
785
static bool prcmu_is_u8400(void)
577
static inline bool prcmu_is_u8400(void)
894
669
static inline void prcmu_ac_sleep_req(void) {}
896
static inline void prcmu_system_reset(u16 reset_code) {}
898
671
static inline void prcmu_modem_reset(void) {}
900
static inline bool prcmu_is_ac_wake_requested(void)
905
#ifndef CONFIG_UX500_SOC_DB5500
906
static inline int prcmu_set_display_clocks(void)
911
static inline int prcmu_disable_dsipll(void)
916
static inline int prcmu_enable_dsipll(void)
922
673
static inline int prcmu_enable_spi2(void)
683
static inline void db8500_prcmu_system_reset(u16 reset_code) {}
685
static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
691
static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
693
static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
698
static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
703
static inline int db8500_prcmu_set_display_clocks(void)
708
static inline int db8500_prcmu_disable_dsipll(void)
713
static inline int db8500_prcmu_enable_dsipll(void)
718
static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
723
static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
725
static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
727
static inline u16 db8500_prcmu_get_reset_code(void)
732
static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
737
static inline int prcmu_enable_a9wdog(u8 id)
742
static inline int prcmu_disable_a9wdog(u8 id)
747
static inline int prcmu_kick_a9wdog(u8 id)
752
static inline int prcmu_load_a9wdog(u8 id, u32 val)
757
static inline bool db8500_prcmu_is_ac_wake_requested(void)
762
static inline int db8500_prcmu_set_arm_opp(u8 opp)
767
static inline int db8500_prcmu_get_arm_opp(void)
932
772
#endif /* !CONFIG_MFD_DB8500_PRCMU */
934
#ifdef CONFIG_UX500_PRCMU_QOS_POWER
935
int prcmu_qos_requirement(int pm_qos_class);
936
int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
937
int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
938
void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
939
int prcmu_qos_add_notifier(int prcmu_qos_class,
940
struct notifier_block *notifier);
941
int prcmu_qos_remove_notifier(int prcmu_qos_class,
942
struct notifier_block *notifier);
944
static inline int prcmu_qos_requirement(int prcmu_qos_class)
949
static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
950
char *name, s32 value)
955
static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
956
char *name, s32 new_value)
961
static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
965
static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
966
struct notifier_block *notifier)
970
static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
971
struct notifier_block *notifier)
978
774
#endif /* __MFD_DB8500_PRCMU_H */