45
45
s32 _s13_to_s32(u32 data)
49
val = (data & 0x0FFF);
51
if ((data & BIT(12)) != 0)
49
val = (data & 0x0FFF);
51
if ((data & BIT(12)) != 0)
57
57
u32 _s32_to_s13(s32 data)
63
else if (data < -4096)
63
else if (data < -4096)
71
71
/****************************************************************************/
72
72
s32 _s4_to_s32(u32 data)
76
val = (data & 0x0007);
78
if ((data & BIT(3)) != 0)
76
val = (data & 0x0007);
78
if ((data & BIT(3)) != 0)
84
84
u32 _s32_to_s4(s32 data)
98
98
/****************************************************************************/
99
99
s32 _s5_to_s32(u32 data)
103
val = (data & 0x000F);
105
if ((data & BIT(4)) != 0)
103
val = (data & 0x000F);
105
if ((data & BIT(4)) != 0)
111
111
u32 _s32_to_s5(s32 data)
125
125
/****************************************************************************/
126
126
s32 _s6_to_s32(u32 data)
130
val = (data & 0x001F);
132
if ((data & BIT(5)) != 0)
130
val = (data & 0x001F);
132
if ((data & BIT(5)) != 0)
138
138
u32 _s32_to_s6(s32 data)
152
152
/****************************************************************************/
153
153
s32 _s9_to_s32(u32 data)
159
if ((data & BIT(8)) != 0)
159
if ((data & BIT(8)) != 0)
165
165
u32 _s32_to_s9(s32 data)
171
else if (data < -256)
171
else if (data < -256)
179
179
/****************************************************************************/
180
180
s32 _floor(s32 n)
190
190
/****************************************************************************/
196
196
u32 _sqrt(u32 sqsum)
200
int g0, g1, g2, g3, g4;
205
g4 = sqsum / 100000000;
206
g3 = (sqsum - g4*100000000) / 1000000;
207
g2 = (sqsum - g4*100000000 - g3*1000000) / 10000;
208
g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) / 100;
209
g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100);
214
while (((seed+1)*(step+1)) <= next) {
219
sq_rt = seed * 10000;
220
next = (next-(seed*step))*100 + g3;
223
seed = 2 * seed * 10;
224
while (((seed+1)*(step+1)) <= next) {
229
sq_rt = sq_rt + step * 1000;
230
next = (next - seed * step) * 100 + g2;
231
seed = (seed + step) * 10;
233
while (((seed+1)*(step+1)) <= next) {
238
sq_rt = sq_rt + step * 100;
239
next = (next - seed * step) * 100 + g1;
240
seed = (seed + step) * 10;
243
while (((seed+1)*(step+1)) <= next) {
248
sq_rt = sq_rt + step * 10;
249
next = (next - seed * step) * 100 + g0;
250
seed = (seed + step) * 10;
253
while (((seed+1)*(step+1)) <= next) {
258
sq_rt = sq_rt + step;
200
int g0, g1, g2, g3, g4;
205
g4 = sqsum / 100000000;
206
g3 = (sqsum - g4*100000000) / 1000000;
207
g2 = (sqsum - g4*100000000 - g3*1000000) / 10000;
208
g1 = (sqsum - g4*100000000 - g3*1000000 - g2*10000) / 100;
209
g0 = (sqsum - g4*100000000 - g3*1000000 - g2*10000 - g1*100);
214
while (((seed+1)*(step+1)) <= next) {
219
sq_rt = seed * 10000;
220
next = (next-(seed*step))*100 + g3;
223
seed = 2 * seed * 10;
224
while (((seed+1)*(step+1)) <= next) {
229
sq_rt = sq_rt + step * 1000;
230
next = (next - seed * step) * 100 + g2;
231
seed = (seed + step) * 10;
233
while (((seed+1)*(step+1)) <= next) {
238
sq_rt = sq_rt + step * 100;
239
next = (next - seed * step) * 100 + g1;
240
seed = (seed + step) * 10;
243
while (((seed+1)*(step+1)) <= next) {
248
sq_rt = sq_rt + step * 10;
249
next = (next - seed * step) * 100 + g0;
250
seed = (seed + step) * 10;
253
while (((seed+1)*(step+1)) <= next) {
258
sq_rt = sq_rt + step;
263
263
/****************************************************************************/
264
264
void _sin_cos(s32 angle, s32 *sin, s32 *cos)
266
s32 X, Y, TargetAngle, CurrAngle;
269
X = FIXED(AG_CONST); /* AG_CONST * cos(0) */
270
Y = 0; /* AG_CONST * sin(0) */
271
TargetAngle = abs(angle);
274
for (Step = 0; Step < 12; Step++) {
277
if (TargetAngle > CurrAngle) {
278
NewX = X - (Y >> Step);
281
CurrAngle += Angles[Step];
283
NewX = X + (Y >> Step);
284
Y = -(X >> Step) + Y;
286
CurrAngle -= Angles[Step];
266
s32 X, Y, TargetAngle, CurrAngle;
269
X = FIXED(AG_CONST); /* AG_CONST * cos(0) */
270
Y = 0; /* AG_CONST * sin(0) */
271
TargetAngle = abs(angle);
274
for (Step = 0; Step < 12; Step++) {
277
if (TargetAngle > CurrAngle) {
278
NewX = X - (Y >> Step);
281
CurrAngle += Angles[Step];
283
NewX = X + (Y >> Step);
284
Y = -(X >> Step) + Y;
286
CurrAngle -= Angles[Step];
299
299
static unsigned char hal_get_dxx_reg(struct hw_data *pHwData, u16 number, u32 * pValue)
338
338
/**********************************************/
339
339
void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency)
346
PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n"));
347
phy_init_rf(phw_data);
349
/* set calibration channel */
350
if ((RF_WB_242 == phw_data->phy_type) ||
346
PHY_DEBUG(("[CAL] -> [1]_rxadc_dc_offset_cancellation()\n"));
347
phy_init_rf(phw_data);
349
/* set calibration channel */
350
if ((RF_WB_242 == phw_data->phy_type) ||
351
351
(RF_WB_242_1 == phw_data->phy_type)) /* 20060619.5 Add */{
352
if ((frequency >= 2412) && (frequency <= 2484)) {
353
/* w89rf242 change frequency to 2390Mhz */
354
PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n"));
352
if ((frequency >= 2412) && (frequency <= 2484)) {
353
/* w89rf242 change frequency to 2390Mhz */
354
PHY_DEBUG(("[CAL] W89RF242/11G/Channel=2390Mhz\n"));
355
355
phy_set_rf_data(phw_data, 3, (3<<24)|0x025586);
455
455
phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
456
456
/* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
457
457
phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
458
/* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
458
/* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
459
459
phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
460
460
/* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
461
461
phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
577
577
phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
578
578
/* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
579
579
phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
580
/* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
580
/* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
581
581
phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
582
582
/* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
583
583
phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
974
974
phy_set_rf_data(phw_data, 11, (11<<24)|0x19BDD6); /* 20060612.1.a 0x1905D6); */
975
975
/* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
976
976
phy_set_rf_data(phw_data, 5, (5<<24)|0x24C60A); /* 0x24C60A (high temperature) */
977
/* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
977
/* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
978
978
phy_set_rf_data(phw_data, 6, (6<<24)|0x34880C); /* 20060612.1.a 0x06890C); */
979
979
/* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
980
980
phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
1154
1154
capture_time = 0;
1156
1156
for (capture_time = 0; capture_time < 10; capture_time++) {
1157
/* i. Set "calib_start" to 0x0 */
1158
reg_mode_ctrl &= ~MASK_CALIB_START;
1159
if (!hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl))/*20060718.1 modify */
1161
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1163
reg_mode_ctrl &= ~MASK_IQCAL_MODE;
1164
reg_mode_ctrl |= (MASK_CALIB_START|0x1);
1165
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1166
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1169
hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
1170
PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
1172
iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
1173
iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
1174
PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
1175
iqcal_tone_i, iqcal_tone_q));
1177
hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
1178
PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
1180
iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
1181
iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
1182
PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n",
1183
iqcal_image_i, iqcal_image_q));
1157
/* i. Set "calib_start" to 0x0 */
1158
reg_mode_ctrl &= ~MASK_CALIB_START;
1159
if (!hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl))/*20060718.1 modify */
1161
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1163
reg_mode_ctrl &= ~MASK_IQCAL_MODE;
1164
reg_mode_ctrl |= (MASK_CALIB_START|0x1);
1165
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
1166
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
1169
hw_get_dxx_reg(phw_data, REG_CALIB_READ1, &val);
1170
PHY_DEBUG(("[CAL] CALIB_READ1 = 0x%08X\n", val));
1172
iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
1173
iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
1174
PHY_DEBUG(("[CAL] ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
1175
iqcal_tone_i, iqcal_tone_q));
1177
hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
1178
PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
1180
iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
1181
iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
1182
PHY_DEBUG(("[CAL] ** iqcal_image_i = %d, iqcal_image_q = %d\n",
1183
iqcal_image_i, iqcal_image_q));
1184
1184
if (capture_time == 0)
1476
1476
/******************/
1477
1477
void phy_set_rf_data(struct hw_data *pHwData, u32 index, u32 value)
1481
switch (pHwData->phy_type) {
1483
case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
1484
ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1488
ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1492
ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1496
ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1499
case RF_AIROHA_2230:
1500
case RF_AIROHA_2230S: /* 20060420 Add this */
1501
ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(value, 20);
1504
case RF_AIROHA_7230:
1505
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff);
1509
case RF_WB_242_1:/* 20060619.5 Add */
1510
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(value, 24);
1481
switch (pHwData->phy_type) {
1483
case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
1484
ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1488
ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1492
ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1496
ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(value, 18);
1499
case RF_AIROHA_2230:
1500
case RF_AIROHA_2230S: /* 20060420 Add this */
1501
ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(value, 20);
1504
case RF_AIROHA_7230:
1505
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | (value&0xffffff);
1509
case RF_WB_242_1:/* 20060619.5 Add */
1510
ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(value, 24);
1514
1514
Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);