32
30
#define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04
33
31
#define OMAP3_VP_VLIMITTO_TIMEOUT_US 200
35
#define OMAP3430_VP1_VLIMITTO_VDDMIN 0x14
36
#define OMAP3430_VP1_VLIMITTO_VDDMAX 0x42
37
#define OMAP3430_VP2_VLIMITTO_VDDMIN 0x18
38
#define OMAP3430_VP2_VLIMITTO_VDDMAX 0x2c
40
#define OMAP3630_VP1_VLIMITTO_VDDMIN 0x18
41
#define OMAP3630_VP1_VLIMITTO_VDDMAX 0x3c
42
#define OMAP3630_VP2_VLIMITTO_VDDMIN 0x18
43
#define OMAP3630_VP2_VLIMITTO_VDDMAX 0x30
45
33
#define OMAP4_SRI2C_SLAVE_ADDR 0x12
46
34
#define OMAP4_VDD_MPU_SR_VOLT_REG 0x55
35
#define OMAP4_VDD_MPU_SR_CMD_REG 0x56
47
36
#define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B
37
#define OMAP4_VDD_IVA_SR_CMD_REG 0x5C
48
38
#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
50
#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
51
#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
52
#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
53
#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
55
#define OMAP4_VP_MPU_VLIMITTO_VDDMIN 0xA
56
#define OMAP4_VP_MPU_VLIMITTO_VDDMAX 0x39
57
#define OMAP4_VP_IVA_VLIMITTO_VDDMIN 0xA
58
#define OMAP4_VP_IVA_VLIMITTO_VDDMAX 0x2D
59
#define OMAP4_VP_CORE_VLIMITTO_VDDMIN 0xA
60
#define OMAP4_VP_CORE_VLIMITTO_VDDMAX 0x28
39
#define OMAP4_VDD_CORE_SR_CMD_REG 0x62
62
41
static bool is_offset_valid;
63
42
static u8 smps_offset;
110
91
if (smps_offset & 0x8)
111
return ((((vsel - 1) * 125) + 7000)) * 100;
92
return ((((vsel - 1) * 1266) + 70900)) * 10;
113
return ((((vsel - 1) * 125) + 6000)) * 100;
94
return ((((vsel - 1) * 1266) + 60770)) * 10;
116
97
static u8 twl6030_uv_to_vsel(unsigned long uv)
136
119
* hardcoding only for 1.35 V which is used for 1GH OPP for
122
if (uv > twl6030_vsel_to_uv(0x39)) {
125
pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
126
__func__, uv, twl6030_vsel_to_uv(0x39));
142
130
if (smps_offset & 0x8)
143
return DIV_ROUND_UP(uv - 700000, 12500) + 1;
131
return DIV_ROUND_UP(uv - 709000, 12660) + 1;
145
return DIV_ROUND_UP(uv - 600000, 12500) + 1;
133
return DIV_ROUND_UP(uv - 607700, 12660) + 1;
148
static struct omap_volt_pmic_info omap3_mpu_volt_info = {
136
static struct omap_voltdm_pmic omap3_mpu_pmic = {
149
137
.slew_rate = 4000,
150
138
.step_size = 12500,
151
139
.on_volt = 1200000,
160
148
.vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX,
161
149
.vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
162
150
.i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
163
.pmic_reg = OMAP3_VDD_MPU_SR_CONTROL_REG,
151
.volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG,
152
.i2c_high_speed = true,
164
153
.vsel_to_uv = twl4030_vsel_to_uv,
165
154
.uv_to_vsel = twl4030_uv_to_vsel,
168
static struct omap_volt_pmic_info omap3_core_volt_info = {
157
static struct omap_voltdm_pmic omap3_core_pmic = {
169
158
.slew_rate = 4000,
170
159
.step_size = 12500,
171
160
.on_volt = 1200000,
180
169
.vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX,
181
170
.vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
182
171
.i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
183
.pmic_reg = OMAP3_VDD_CORE_SR_CONTROL_REG,
172
.volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG,
173
.i2c_high_speed = true,
184
174
.vsel_to_uv = twl4030_vsel_to_uv,
185
175
.uv_to_vsel = twl4030_uv_to_vsel,
188
static struct omap_volt_pmic_info omap4_mpu_volt_info = {
178
static struct omap_voltdm_pmic omap4_mpu_pmic = {
189
179
.slew_rate = 4000,
192
.onlp_volt = 1350000,
182
.onlp_volt = 1375000,
195
185
.volt_setup_time = 0,
196
186
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
197
187
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
200
190
.vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
201
191
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
202
192
.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
203
.pmic_reg = OMAP4_VDD_MPU_SR_VOLT_REG,
193
.volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
194
.cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG,
195
.i2c_high_speed = true,
196
.i2c_scll_low = 0x28,
197
.i2c_scll_high = 0x2C,
198
.i2c_hscll_low = 0x0B,
199
.i2c_hscll_high = 0x00,
204
200
.vsel_to_uv = twl6030_vsel_to_uv,
205
201
.uv_to_vsel = twl6030_uv_to_vsel,
208
static struct omap_volt_pmic_info omap4_iva_volt_info = {
204
static struct omap_voltdm_pmic omap4_iva_pmic = {
209
205
.slew_rate = 4000,
212
.onlp_volt = 1100000,
208
.onlp_volt = 1188000,
215
211
.volt_setup_time = 0,
216
212
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
217
213
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
220
216
.vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
221
217
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
222
218
.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
223
.pmic_reg = OMAP4_VDD_IVA_SR_VOLT_REG,
219
.volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
220
.cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG,
221
.i2c_high_speed = true,
222
.i2c_scll_low = 0x28,
223
.i2c_scll_high = 0x2C,
224
.i2c_hscll_low = 0x0B,
225
.i2c_hscll_high = 0x00,
224
226
.vsel_to_uv = twl6030_vsel_to_uv,
225
227
.uv_to_vsel = twl6030_uv_to_vsel,
228
static struct omap_volt_pmic_info omap4_core_volt_info = {
230
static struct omap_voltdm_pmic omap443x_core_pmic = {
229
231
.slew_rate = 4000,
232
.onlp_volt = 1100000,
234
.onlp_volt = 1200000,
235
237
.volt_setup_time = 0,
236
238
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
237
239
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
240
242
.vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
241
243
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
242
244
.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
243
.pmic_reg = OMAP4_VDD_CORE_SR_VOLT_REG,
245
.i2c_high_speed = true,
246
.i2c_scll_low = 0x28,
247
.i2c_scll_high = 0x2C,
248
.i2c_hscll_low = 0x0B,
249
.i2c_hscll_high = 0x00,
250
.volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG,
251
.cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG,
244
252
.vsel_to_uv = twl6030_vsel_to_uv,
245
253
.uv_to_vsel = twl6030_uv_to_vsel,
248
int __init omap4_twl_init(void)
250
struct voltagedomain *voltdm;
252
if (!cpu_is_omap44xx())
255
voltdm = omap_voltage_domain_lookup("mpu");
256
omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info);
258
voltdm = omap_voltage_domain_lookup("iva");
259
omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info);
261
voltdm = omap_voltage_domain_lookup("core");
262
omap_voltage_register_pmic(voltdm, &omap4_core_volt_info);
267
int __init omap3_twl_init(void)
269
struct voltagedomain *voltdm;
271
if (!cpu_is_omap34xx())
274
if (cpu_is_omap3630()) {
275
omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
276
omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
277
omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
278
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
256
static int __init twl_set_sr(struct voltagedomain *voltdm)
282
261
* The smartreflex bit on twl4030 specifies if the setting of voltage
288
267
* voltage scaling will not function on TWL over I2C_SR.
290
269
if (!twl_sr_enable_autoinit)
291
omap3_twl_set_sr_bit(true);
293
voltdm = omap_voltage_domain_lookup("mpu");
294
omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
296
voltdm = omap_voltage_domain_lookup("core");
297
omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
270
r = omap3_twl_set_sr_bit(true);
274
static struct omap_revisions rev_list_3430[] = {
275
{ OMAP343X_CLASS, OMAP_REVISION_MASK_REV },
278
static struct omap_revisions rev_list_44xx[] = {
279
{ OMAP443X_CLASS, OMAP_REVISION_MASK_REV },
280
{ OMAP446X_CLASS, OMAP_REVISION_MASK_REV},
284
static __initdata struct omap_pmic_map omap_twl_map[] = {
287
.omap_revs = rev_list_3430,
288
.pmic_data = &omap3_mpu_pmic,
289
.special_action = twl_set_sr,
293
.omap_revs = rev_list_3430,
294
.pmic_data = &omap3_core_pmic,
298
.omap_revs = rev_list_44xx,
299
.pmic_data = &omap4_mpu_pmic,
303
.omap_revs = rev_list_44xx,
304
.pmic_data = &omap443x_core_pmic,
308
.omap_revs = rev_list_44xx,
309
.pmic_data = &omap4_iva_pmic,
312
{ .name = NULL, .pmic_data = NULL},
315
int __init omap_twl_init(void)
317
/* Reuse OMAP3430 values */
318
if (cpu_is_omap3630()) {
319
omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
320
omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
321
omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
322
omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
325
return omap_pmic_register_data(omap_twl_map);