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Viewing changes to arch/arm/mach-s5pc100/include/mach/regs-fb.h

  • Committer: Package Import Robot
  • Author(s): Paolo Pisati, Paolo Pisati
  • Date: 2011-12-06 15:56:07 UTC
  • Revision ID: package-import@ubuntu.com-20111206155607-pcf44kv5fmhk564f
Tags: 3.2.0-1401.1
[ Paolo Pisati ]

* Rebased on top of Ubuntu-3.2.0-3.8
* Tilt-tracking @ ef2487af4bb15bdd0689631774b5a5e3a59f74e2
* Delete debian.ti-omap4/control, it shoudln't be tracked
* Fix architecture spelling (s/armel/armhf/)
* [Config] Update configs following 3.2 import
* [Config] Fix compilation: disable CODA and ARCH_OMAP3
* [Config] Fix compilation: disable Ethernet Faraday
* Update series to precise

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arch/arm/mach-s5pc100/include/mach/regs-fb.h
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/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
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 *
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 * Copyright 2009 Samsung Electronics Co.
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 *   Pawel Osciak <p.osciak@samsung.com>
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 *
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 * Framebuffer register definitions for Samsung S5PC100.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License version 2 as
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 * published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_FB_H
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#define __ASM_ARCH_REGS_FB_H __FILE__
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#include <plat/regs-fb-v4.h>
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/* VP1 interface timing control */
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#define VP1CON0                                         (0x118)
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#define VP1_RATECON_EN                                  (1 << 31)
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#define VP1_CLKRATE_MASK                                (0xff)
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#define VP1CON1                                         (0x11c)
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#define VP1_VTREGCON_EN                                 (1 << 31)
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#define VP1_VBPD_MASK                                   (0xfff)
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#define VP1_VBPD_SHIFT                                  (16)
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#define WPALCON_H                                       (0x19c)
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#define WPALCON_L                                       (0x1a0)
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/* Palette control for WPAL0 and WPAL1 is the same as in S3C64xx, but
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 * different for WPAL2-4
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 */
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/* In WPALCON_L (aka WPALCON) */
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#define WPALCON_W1PAL_32BPP_A888                        (0x7 << 3)
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#define WPALCON_W0PAL_32BPP_A888                        (0x7 << 0)
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/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
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 * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
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 */
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#define WPALCON_L_WxPAL_L_MASK                          (0x1)
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#define WPALCON_L_W2PAL_L_SHIFT                         (6)
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#define WPALCON_L_W3PAL_L_SHIFT                         (7)
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#define WPALCON_L_W4PAL_L_SHIFT                         (8)
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#define WPALCON_L_WxPAL_H_MASK                          (0x3)
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#define WPALCON_H_W2PAL_H_SHIFT                         (9)
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#define WPALCON_H_W3PAL_H_SHIFT                         (13)
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#define WPALCON_H_W4PAL_H_SHIFT                         (17)
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/* Per-window alpha value registers */
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/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
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 * for windows 1-4 alpha values consist of two parts, the 4 low bits are
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 * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
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 * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
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 */
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#define VIDWxALPHA0(_win)                               (0x200 + (_win * 8))
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#define VIDWxALPHA1(_win)                               (0x204 + (_win * 8))
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/* Only for window 0 in VIDW0ALPHAx. */
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#define VIDW0ALPHAx_R(_x)                               ((_x) << 16)
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#define VIDW0ALPHAx_R_MASK                              (0xff << 16)
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#define VIDW0ALPHAx_R_SHIFT                             (16)
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#define VIDW0ALPHAx_G(_x)                               ((_x) << 8)
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#define VIDW0ALPHAx_G_MASK                              (0xff << 8)
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#define VIDW0ALPHAx_G_SHIFT                             (8)
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#define VIDW0ALPHAx_B(_x)                               ((_x) << 0)
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#define VIDW0ALPHAx_B_MASK                              (0xff << 0)
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#define VIDW0ALPHAx_B_SHIFT                             (0)
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/* Low 4 bits of alpha0-1 for windows 1-4 */
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#define VIDW14ALPHAx_R_L(_x)                            ((_x) << 16)
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#define VIDW14ALPHAx_R_L_MASK                           (0xf << 16)
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#define VIDW14ALPHAx_R_L_SHIFT                          (16)
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#define VIDW14ALPHAx_G_L(_x)                            ((_x) << 8)
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#define VIDW14ALPHAx_G_L_MASK                           (0xf << 8)
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#define VIDW14ALPHAx_G_L_SHIFT                          (8)
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#define VIDW14ALPHAx_B_L(_x)                            ((_x) << 0)
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#define VIDW14ALPHAx_B_L_MASK                           (0xf << 0)
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#define VIDW14ALPHAx_B_L_SHIFT                          (0)
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/* Per-window blending equation control registers */
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#define BLENDEQx(_win)                                  (0x244 + ((_win) * 4))
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#define BLENDEQ1                                        (0x244)
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#define BLENDEQ2                                        (0x248)
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#define BLENDEQ3                                        (0x24c)
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#define BLENDEQ4                                        (0x250)
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#define BLENDEQx_Q_FUNC(_x)                             ((_x) << 18)
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#define BLENDEQx_Q_FUNC_MASK                            (0xf << 18)
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#define BLENDEQx_P_FUNC(_x)                             ((_x) << 12)
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#define BLENDEQx_P_FUNC_MASK                            (0xf << 12)
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#define BLENDEQx_B_FUNC(_x)                             ((_x) << 6)
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#define BLENDEQx_B_FUNC_MASK                            (0xf << 6)
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#define BLENDEQx_A_FUNC(_x)                             ((_x) << 0)
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#define BLENDEQx_A_FUNC_MASK                            (0xf << 0)
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#define BLENDCON                                        (0x260)
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#define BLENDCON_8BIT_ALPHA                             (1 << 0)
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#endif /* __ASM_ARCH_REGS_FB_H */
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