65
65
/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
66
66
#define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17))
68
74
/* command register values to disable interrupts and halt the HC */
69
75
/* start/stop HC execution - do not write unless HC is halted*/
70
76
#define XHCI_CMD_RUN (1 << 0)