29
29
#define ULONG_SIZE 8
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30
#define FUNC(name) GLUE(.,name)
32
#define GET_SHADOW_VCPU(reg) \
33
addi reg, r13, PACA_KVM_SVCPU
35
#define DISABLE_INTERRUPTS \
41
32
#elif defined(CONFIG_PPC_BOOK3S_32)
43
34
#define ULONG_SIZE 4
44
35
#define FUNC(name) name
46
#define GET_SHADOW_VCPU(reg) \
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lwz reg, (THREAD + THREAD_KVM_SVCPU)(r2)
49
#define DISABLE_INTERRUPTS \
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rlwinm r0,r0,0,17,15; \
54
37
#endif /* CONFIG_PPC_BOOK3S_XX */
107
90
/* Load non-volatile guest state from the vcpu */
108
91
VCPU_LOAD_NVGPRS(r4)
112
/* Save R1/R2 in the PACA */
113
PPC_STL r1, SVCPU_HOST_R1(r5)
114
PPC_STL r2, SVCPU_HOST_R2(r5)
116
/* XXX swap in/out on load? */
117
PPC_LL r3, VCPU_HIGHMEM_HANDLER(r4)
118
PPC_STL r3, SVCPU_VMHANDLER(r5)
120
93
kvm_start_lightweight:
122
PPC_LL r10, VCPU_SHADOW_MSR(r4) /* r10 = vcpu->arch.shadow_msr */
126
95
#ifdef CONFIG_PPC_BOOK3S_64
127
/* Some guests may need to have dcbz set to 32 byte length.
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* Usually we ensure that by patching the guest's instructions
130
* to trap on dcbz and emulate it in the hypervisor.
132
* If we can, we should tell the CPU to use 32 byte dcbz though,
133
* because that's a lot faster.
136
96
PPC_LL r3, VCPU_HFLAGS(r4)
137
rldicl. r3, r3, 0, 63 /* CR = ((r3 & 1) == 0) */
141
ori r3, r3, 0x80 /* XXX HID5_dcbz32 = 0x80 */
97
rldicl r3, r3, 0, 63 /* r3 &= 1 */
98
stb r3, HSTATE_RESTORE_HID5(r13)
146
99
#endif /* CONFIG_PPC_BOOK3S_64 */
148
PPC_LL r6, VCPU_RMCALL(r4)
151
PPC_LL r3, VCPU_TRAMPOLINE_ENTER(r4)
152
LOAD_REG_IMMEDIATE(r4, MSR_KERNEL & ~(MSR_IR | MSR_DR))
101
PPC_LL r4, VCPU_SHADOW_MSR(r4) /* get shadow_msr */
154
103
/* Jump to segment patching handler and into our guest */
104
bl FUNC(kvmppc_entry_trampoline)
158
108
* This is the handler in module memory. It gets jumped at from the
178
128
PPC_LL r7, GPR4(r1)
180
#ifdef CONFIG_PPC_BOOK3S_64
182
PPC_LL r5, VCPU_HFLAGS(r7)
183
rldicl. r5, r5, 0, 63 /* CR = ((r5 & 1) == 0) */
193
#endif /* CONFIG_PPC_BOOK3S_64 */
195
130
PPC_STL r14, VCPU_GPR(r14)(r7)
196
131
PPC_STL r15, VCPU_GPR(r15)(r7)
197
132
PPC_STL r16, VCPU_GPR(r16)(r7)
211
146
PPC_STL r30, VCPU_GPR(r30)(r7)
212
147
PPC_STL r31, VCPU_GPR(r31)(r7)
214
/* Restore host msr -> SRR1 */
215
PPC_LL r6, VCPU_HOST_MSR(r7)
218
* For some interrupts, we need to call the real Linux
219
* handler, so it can do work for us. This has to happen
220
* as if the interrupt arrived from the kernel though,
221
* so let's fake it here where most state is restored.
223
* Call Linux for hardware interrupts/decrementer
224
* r3 = address of interrupt handler (exit reason)
227
cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
228
beq call_linux_handler
229
cmpwi r12, BOOK3S_INTERRUPT_DECREMENTER
230
beq call_linux_handler
231
cmpwi r12, BOOK3S_INTERRUPT_PERFMON
232
beq call_linux_handler
242
* If we land here we need to jump back to the handler we
245
* We have a page that we can access from real mode, so let's
246
* jump back to that and use it as a trampoline to get back into the
249
* R3 still contains the exit code,
250
* R5 VCPU_HOST_RETIP and
254
/* Restore host IP -> SRR0 */
255
PPC_LL r5, VCPU_HOST_RETIP(r7)
257
/* XXX Better move to a safe function?
258
* What if we get an HTAB flush in between mtsrr0 and mtsrr1? */
262
PPC_LL r4, VCPU_TRAMPOLINE_LOWMEM(r7)
264
LOAD_REG_IMMEDIATE(r3, MSR_KERNEL & ~(MSR_IR | MSR_DR))
269
.global kvm_return_point
272
/* Jump back to lightweight entry if we're supposed to */
273
/* go back into the guest */
275
149
/* Pass the exit number as 3rd argument to kvmppc_handle_exit */