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/***************************************************************************
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* Copyright (C) 2006-2010 by Marin Mitov *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include <linux/module.h>
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#include <linux/version.h>
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#include <linux/stringify.h>
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#include <linux/delay.h>
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#include <linux/kthread.h>
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#include <linux/slab.h>
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#include <media/v4l2-dev.h>
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#include <media/v4l2-ioctl.h>
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#include <media/videobuf2-dma-contig.h>
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#include "dt3155v4l.h"
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#define DT3155_VENDOR_ID 0x8086
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#define DT3155_DEVICE_ID 0x1223
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/* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */
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#define DT3155_CHUNK_SIZE (1U << 22)
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#define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN)
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#define DT3155_BUF_SIZE (768 * 576)
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#ifdef CONFIG_DT3155_STREAMING
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#define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING
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#define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE
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/* global initializers (for all boards) */
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#ifdef CONFIG_DT3155_CCIR
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static const u8 csr2_init = VT_50HZ;
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#define DT3155_CURRENT_NORM V4L2_STD_625_50
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static const unsigned int img_width = 768;
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static const unsigned int img_height = 576;
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static const unsigned int frames_per_sec = 25;
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static const struct v4l2_fmtdesc frame_std[] = {
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.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
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.description = "CCIR/50Hz 8 bits gray",
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.pixelformat = V4L2_PIX_FMT_GREY,
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static const u8 csr2_init = VT_60HZ;
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#define DT3155_CURRENT_NORM V4L2_STD_525_60
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static const unsigned int img_width = 640;
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static const unsigned int img_height = 480;
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static const unsigned int frames_per_sec = 30;
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static const struct v4l2_fmtdesc frame_std[] = {
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.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
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.description = "RS-170/60Hz 8 bits gray",
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.pixelformat = V4L2_PIX_FMT_GREY,
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#define NUM_OF_FORMATS ARRAY_SIZE(frame_std)
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static u8 config_init = ACQ_MODE_EVEN;
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* read_i2c_reg - reads an internal i2c register
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* @addr: dt3155 mmio base address
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* @index: index (internal address) of register to read
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* @data: pointer to byte the read data will be placed in
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* returns: zero on success or error code
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* This function starts reading the specified (by index) register
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* and busy waits for the process to finish. The result is placed
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* in a byte pointed by data.
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read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
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iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2);
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udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
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if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
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return -EIO; /* error: NEW_CYCLE not cleared */
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tmp = ioread32(addr + IIC_CSR1);
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if (tmp & DIRECT_ABORT) {
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/* reset DIRECT_ABORT bit */
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iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
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return -EIO; /* error: DIRECT_ABORT set */
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* write_i2c_reg - writes to an internal i2c register
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* @addr: dt3155 mmio base address
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* @index: index (internal address) of register to read
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* @data: data to be written
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* returns: zero on success or error code
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* This function starts writting the specified (by index) register
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* and busy waits for the process to finish.
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write_i2c_reg(void __iomem *addr, u8 index, u8 data)
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iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
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udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
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if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
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return -EIO; /* error: NEW_CYCLE not cleared */
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if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
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/* reset DIRECT_ABORT bit */
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iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
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return -EIO; /* error: DIRECT_ABORT set */
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* write_i2c_reg_nowait - writes to an internal i2c register
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* @addr: dt3155 mmio base address
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* @index: index (internal address) of register to read
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* @data: data to be written
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* This function starts writting the specified (by index) register
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static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
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iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
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* wait_i2c_reg - waits the read/write to finish
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* @addr: dt3155 mmio base address
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* returns: zero on success or error code
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* This function waits reading/writting to finish.
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static int wait_i2c_reg(void __iomem *addr)
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if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
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udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
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if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
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return -EIO; /* error: NEW_CYCLE not cleared */
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if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
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/* reset DIRECT_ABORT bit */
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iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
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return -EIO; /* error: DIRECT_ABORT set */
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dt3155_start_acq(struct dt3155_priv *pd)
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struct vb2_buffer *vb = pd->curr_buf;
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dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
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iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
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iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START);
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iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE);
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iowrite32(img_width, pd->regs + ODD_DMA_STRIDE);
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/* enable interrupts, clear all irq flags */
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iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
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FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
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iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
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FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
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wait_i2c_reg(pd->regs);
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write_i2c_reg(pd->regs, CONFIG, pd->config);
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write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
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write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
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/* start the board */
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write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
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return 0; /* success */
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* driver-specific callbacks (vb2_ops)
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dt3155_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
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unsigned int *num_planes, unsigned long sizes[],
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struct dt3155_priv *pd = vb2_get_drv_priv(q);
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if (*num_buffers == 0)
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sizes[0] = img_width * img_height;
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if (pd->q->alloc_ctx[0])
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ret = vb2_dma_contig_init_ctx(&pd->pdev->dev);
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pd->q->alloc_ctx[0] = ret;
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dt3155_wait_prepare(struct vb2_queue *q)
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struct dt3155_priv *pd = vb2_get_drv_priv(q);
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mutex_unlock(pd->vdev->lock);
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dt3155_wait_finish(struct vb2_queue *q)
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struct dt3155_priv *pd = vb2_get_drv_priv(q);
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mutex_lock(pd->vdev->lock);
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dt3155_buf_prepare(struct vb2_buffer *vb)
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vb2_set_plane_payload(vb, 0, img_width * img_height);
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dt3155_start_streaming(struct vb2_queue *q)
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dt3155_stop_streaming(struct vb2_queue *q)
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struct dt3155_priv *pd = vb2_get_drv_priv(q);
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struct vb2_buffer *vb;
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spin_lock_irq(&pd->lock);
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while (!list_empty(&pd->dmaq)) {
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vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
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list_del(&vb->done_entry);
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vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
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spin_unlock_irq(&pd->lock);
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msleep(45); /* irq hendler will stop the hardware */
288
dt3155_buf_queue(struct vb2_buffer *vb)
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struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
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/* pd->q->streaming = 1 when dt3155_buf_queue() is invoked */
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spin_lock_irq(&pd->lock);
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list_add_tail(&vb->done_entry, &pd->dmaq);
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dt3155_start_acq(pd);
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spin_unlock_irq(&pd->lock);
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* end driver-specific callbacks
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const struct vb2_ops q_ops = {
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.queue_setup = dt3155_queue_setup,
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.wait_prepare = dt3155_wait_prepare,
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.wait_finish = dt3155_wait_finish,
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.buf_prepare = dt3155_buf_prepare,
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.start_streaming = dt3155_start_streaming,
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.stop_streaming = dt3155_stop_streaming,
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.buf_queue = dt3155_buf_queue,
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dt3155_irq_handler_even(int irq, void *dev_id)
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struct dt3155_priv *ipd = dev_id;
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struct vb2_buffer *ivb;
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tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
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return IRQ_NONE; /* not our irq */
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if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
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iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
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ipd->regs + INT_CSR);
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return IRQ_HANDLED; /* start of field irq */
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if ((tmp & FLD_START) && (tmp & FLD_END_ODD))
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ipd->stats.start_before_end++;
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/* check for corrupted fields */
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/* write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); */
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/* write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); */
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tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
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ipd->stats.corrupted_fields++;
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iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
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FLD_DN_ODD | FLD_DN_EVEN |
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CAP_CONT_EVEN | CAP_CONT_ODD,
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spin_lock(&ipd->lock);
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do_gettimeofday(&ipd->curr_buf->v4l2_buf.timestamp);
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ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1;
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vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE);
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if (!ipd->q->streaming || list_empty(&ipd->dmaq))
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ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
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list_del(&ivb->done_entry);
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dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
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iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
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iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START);
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iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE);
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iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE);
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/* enable interrupts, clear all irq flags */
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iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
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FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
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spin_unlock(&ipd->lock);
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ipd->curr_buf = NULL;
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write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2);
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iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
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FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1);
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/* disable interrupts, clear all irq flags */
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iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
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spin_unlock(&ipd->lock);
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dt3155_open(struct file *filp)
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struct dt3155_priv *pd = video_drvdata(filp);
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pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL);
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goto err_alloc_queue;
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pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
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pd->q->io_modes = VB2_READ | VB2_MMAP;
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pd->q->mem_ops = &vb2_dma_contig_memops;
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pd->q->drv_priv = pd;
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vb2_queue_init(pd->q); /* cannot fail */
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INIT_LIST_HEAD(&pd->dmaq);
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spin_lock_init(&pd->lock);
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/* disable all irqs, clear all irq flags */
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iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
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ret = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
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IRQF_SHARED, DT3155_NAME, pd);
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goto err_request_irq;
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return 0; /* success */
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dt3155_release(struct file *filp)
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struct dt3155_priv *pd = video_drvdata(filp);
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BUG_ON(pd->users < 0);
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vb2_queue_release(pd->q);
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free_irq(pd->pdev->irq, pd);
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if (pd->q->alloc_ctx[0])
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vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]);
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dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff)
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struct dt3155_priv *pd = video_drvdata(filp);
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return vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK);
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dt3155_poll(struct file *filp, struct poll_table_struct *polltbl)
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struct dt3155_priv *pd = video_drvdata(filp);
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return vb2_poll(pd->q, filp, polltbl);
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dt3155_mmap(struct file *filp, struct vm_area_struct *vma)
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struct dt3155_priv *pd = video_drvdata(filp);
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return vb2_mmap(pd->q, vma);
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static const struct v4l2_file_operations dt3155_fops = {
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.owner = THIS_MODULE,
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.release = dt3155_release,
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.unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
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dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type)
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struct dt3155_priv *pd = video_drvdata(filp);
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return vb2_streamon(pd->q, type);
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dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type)
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struct dt3155_priv *pd = video_drvdata(filp);
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return vb2_streamoff(pd->q, type);
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dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap)
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struct dt3155_priv *pd = video_drvdata(filp);
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strcpy(cap->driver, DT3155_NAME);
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strcpy(cap->card, DT3155_NAME " frame grabber");
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sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
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KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT);
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cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
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DT3155_CAPTURE_METHOD;
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dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f)
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if (f->index >= NUM_OF_FORMATS)
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*f = frame_std[f->index];
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dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
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if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
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f->fmt.pix.width = img_width;
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f->fmt.pix.height = img_height;
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f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
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f->fmt.pix.field = V4L2_FIELD_NONE;
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f->fmt.pix.bytesperline = f->fmt.pix.width;
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f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
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f->fmt.pix.colorspace = 0;
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dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
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if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
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if (f->fmt.pix.width == img_width &&
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f->fmt.pix.height == img_height &&
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f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY &&
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f->fmt.pix.field == V4L2_FIELD_NONE &&
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f->fmt.pix.bytesperline == f->fmt.pix.width &&
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f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height)
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dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
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return dt3155_ioc_g_fmt_vid_cap(filp, p, f);
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dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b)
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struct dt3155_priv *pd = video_drvdata(filp);
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return vb2_reqbufs(pd->q, b);
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dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b)
564
struct dt3155_priv *pd = video_drvdata(filp);
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return vb2_querybuf(pd->q, b);
570
dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b)
572
struct dt3155_priv *pd = video_drvdata(filp);
574
return vb2_qbuf(pd->q, b);
578
dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b)
580
struct dt3155_priv *pd = video_drvdata(filp);
582
return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK);
586
dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm)
588
*norm = DT3155_CURRENT_NORM;
593
dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm)
595
*norm = DT3155_CURRENT_NORM;
600
dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id *norm)
602
if (*norm & DT3155_CURRENT_NORM)
608
dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input)
612
strcpy(input->name, "Coax in");
613
input->type = V4L2_INPUT_TYPE_CAMERA;
615
* FIXME: input->std = 0 according to v4l2 API
616
* VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD
617
* should return -EINVAL
619
input->std = DT3155_CURRENT_NORM;
620
input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */
625
dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i)
632
dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i)
640
dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
642
if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
644
parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
645
parms->parm.capture.capturemode = 0;
646
parms->parm.capture.timeperframe.numerator = 1001;
647
parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
648
parms->parm.capture.extendedmode = 0;
649
parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
654
dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
656
if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
658
parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
659
parms->parm.capture.capturemode = 0;
660
parms->parm.capture.timeperframe.numerator = 1001;
661
parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
662
parms->parm.capture.extendedmode = 0;
663
parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
667
static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
668
.vidioc_streamon = dt3155_ioc_streamon,
669
.vidioc_streamoff = dt3155_ioc_streamoff,
670
.vidioc_querycap = dt3155_ioc_querycap,
672
.vidioc_g_priority = dt3155_ioc_g_priority,
673
.vidioc_s_priority = dt3155_ioc_s_priority,
675
.vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap,
676
.vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap,
677
.vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap,
678
.vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap,
679
.vidioc_reqbufs = dt3155_ioc_reqbufs,
680
.vidioc_querybuf = dt3155_ioc_querybuf,
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.vidioc_qbuf = dt3155_ioc_qbuf,
682
.vidioc_dqbuf = dt3155_ioc_dqbuf,
683
.vidioc_querystd = dt3155_ioc_querystd,
684
.vidioc_g_std = dt3155_ioc_g_std,
685
.vidioc_s_std = dt3155_ioc_s_std,
686
.vidioc_enum_input = dt3155_ioc_enum_input,
687
.vidioc_g_input = dt3155_ioc_g_input,
688
.vidioc_s_input = dt3155_ioc_s_input,
690
.vidioc_queryctrl = dt3155_ioc_queryctrl,
691
.vidioc_g_ctrl = dt3155_ioc_g_ctrl,
692
.vidioc_s_ctrl = dt3155_ioc_s_ctrl,
693
.vidioc_querymenu = dt3155_ioc_querymenu,
694
.vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls,
695
.vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls,
697
.vidioc_g_parm = dt3155_ioc_g_parm,
698
.vidioc_s_parm = dt3155_ioc_s_parm,
700
.vidioc_cropcap = dt3155_ioc_cropcap,
701
.vidioc_g_crop = dt3155_ioc_g_crop,
702
.vidioc_s_crop = dt3155_ioc_s_crop,
703
.vidioc_enum_framesizes = dt3155_ioc_enum_framesizes,
704
.vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals,
709
dt3155_init_board(struct pci_dev *pdev)
711
struct dt3155_priv *pd = pci_get_drvdata(pdev);
717
pci_set_master(pdev); /* dt3155 needs it */
719
/* resetting the adapter */
720
iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN,
725
/* initializing adaper registers */
726
iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
728
iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
729
iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
730
iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
731
iowrite32(0x00000103, pd->regs + XFER_MODE);
732
iowrite32(0, pd->regs + RETRY_WAIT_CNT);
733
iowrite32(0, pd->regs + INT_CSR);
734
iowrite32(1, pd->regs + EVEN_FLD_MASK);
735
iowrite32(1, pd->regs + ODD_FLD_MASK);
736
iowrite32(0, pd->regs + MASK_LENGTH);
737
iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
738
iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
741
/* verifying that we have a DT3155 board (not just a SAA7116 chip) */
742
read_i2c_reg(pd->regs, DT_ID, &tmp);
743
if (tmp != DT3155_ID)
746
/* initialize AD LUT */
747
write_i2c_reg(pd->regs, AD_ADDR, 0);
748
for (i = 0; i < 256; i++)
749
write_i2c_reg(pd->regs, AD_LUT, i);
751
/* initialize ADC references */
752
/* FIXME: pos_ref & neg_ref depend on VT_50HZ */
753
write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
754
write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
755
write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
756
write_i2c_reg(pd->regs, AD_CMD, 34);
757
write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
758
write_i2c_reg(pd->regs, AD_CMD, 0);
760
/* initialize PM LUT */
761
write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
762
for (i = 0; i < 256; i++) {
763
write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
764
write_i2c_reg(pd->regs, PM_LUT_DATA, i);
766
write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
767
for (i = 0; i < 256; i++) {
768
write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
769
write_i2c_reg(pd->regs, PM_LUT_DATA, i);
771
write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
773
/* select chanel 1 for input and set sync level */
774
write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
775
write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
777
/* allocate memory, and initialize the DMA machine */
778
buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma,
782
iowrite32(buf_dma, pd->regs + EVEN_DMA_START);
783
iowrite32(buf_dma, pd->regs + ODD_DMA_START);
784
iowrite32(0, pd->regs + EVEN_DMA_STRIDE);
785
iowrite32(0, pd->regs + ODD_DMA_STRIDE);
787
/* Perform a pseudo even field acquire */
788
iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1);
789
write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL);
790
write_i2c_reg(pd->regs, CONFIG, pd->config);
791
write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL);
792
write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL);
794
read_i2c_reg(pd->regs, CSR2, &tmp);
795
write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
796
write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
797
write_i2c_reg(pd->regs, CSR2, pd->csr2);
798
iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1);
800
/* deallocate memory */
801
dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma);
807
static struct video_device dt3155_vdev = {
809
.fops = &dt3155_fops,
810
.ioctl_ops = &dt3155_ioctl_ops,
812
.release = video_device_release,
813
.tvnorms = DT3155_CURRENT_NORM,
814
.current_norm = DT3155_CURRENT_NORM,
817
/* same as in drivers/base/dma-coherent.c */
818
struct dma_coherent_mem {
820
dma_addr_t device_base;
823
unsigned long *bitmap;
827
dt3155_alloc_coherent(struct device *dev, size_t size, int flags)
829
struct dma_coherent_mem *mem;
831
int pages = size >> PAGE_SHIFT;
832
int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
834
if ((flags & DMA_MEMORY_MAP) == 0)
841
mem = kzalloc(sizeof(*mem), GFP_KERNEL);
844
mem->virt_base = dma_alloc_coherent(dev, size, &dev_base,
847
goto err_alloc_coherent;
848
mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
852
/* coherent_dma_mask is already set to 32 bits */
853
mem->device_base = dev_base;
857
return DMA_MEMORY_MAP;
860
dma_free_coherent(dev, size, mem->virt_base, dev_base);
867
static void __devexit
868
dt3155_free_coherent(struct device *dev)
870
struct dma_coherent_mem *mem = dev->dma_mem;
875
dma_free_coherent(dev, mem->size << PAGE_SHIFT,
876
mem->virt_base, mem->device_base);
882
dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
885
struct dt3155_priv *pd;
887
err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
890
err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
893
pd = kzalloc(sizeof(*pd), GFP_KERNEL);
896
pd->vdev = video_device_alloc();
898
goto err_video_device_alloc;
899
*pd->vdev = dt3155_vdev;
900
pci_set_drvdata(pdev, pd); /* for use in dt3155_remove() */
901
video_set_drvdata(pd->vdev, pd); /* for use in video_fops */
904
INIT_LIST_HEAD(&pd->dmaq);
905
mutex_init(&pd->mux);
906
pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */
907
spin_lock_init(&pd->lock);
908
pd->csr2 = csr2_init;
909
pd->config = config_init;
910
err = pci_enable_device(pdev);
913
err = pci_request_region(pdev, 0, pci_name(pdev));
916
pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
920
err = dt3155_init_board(pdev);
923
err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1);
926
if (dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE,
928
dev_info(&pdev->dev, "preallocated 8 buffers\n");
929
dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev->minor);
930
return 0; /* success */
933
pci_iounmap(pdev, pd->regs);
935
pci_release_region(pdev, 0);
937
pci_disable_device(pdev);
939
video_device_release(pd->vdev);
940
err_video_device_alloc:
945
static void __devexit
946
dt3155_remove(struct pci_dev *pdev)
948
struct dt3155_priv *pd = pci_get_drvdata(pdev);
950
dt3155_free_coherent(&pdev->dev);
951
video_unregister_device(pd->vdev);
952
pci_iounmap(pdev, pd->regs);
953
pci_release_region(pdev, 0);
954
pci_disable_device(pdev);
956
* video_device_release() is invoked automatically
957
* see: struct video_device dt3155_vdev
962
static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
963
{ PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) },
964
{ 0, /* zero marks the end */ },
966
MODULE_DEVICE_TABLE(pci, pci_ids);
968
static struct pci_driver pci_driver = {
971
.probe = dt3155_probe,
972
.remove = __devexit_p(dt3155_remove),
976
dt3155_init_module(void)
978
return pci_register_driver(&pci_driver);
982
dt3155_exit_module(void)
984
pci_unregister_driver(&pci_driver);
987
module_init(dt3155_init_module);
988
module_exit(dt3155_exit_module);
990
MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
991
MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
992
MODULE_VERSION(DT3155_VERSION);
993
MODULE_LICENSE("GPL");