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* Freescale eSPI controller driver.
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* Copyright 2010 Freescale Semiconductor, Inc.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/spi/spi.h>
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#include <linux/platform_device.h>
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#include <linux/fsl_devices.h>
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#include <linux/of_platform.h>
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#include <linux/of_spi.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <sysdev/fsl_soc.h>
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#include "spi-fsl-lib.h"
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/* eSPI Controller registers */
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__be32 mode; /* 0x000 - eSPI mode register */
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__be32 event; /* 0x004 - eSPI event register */
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__be32 mask; /* 0x008 - eSPI mask register */
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__be32 command; /* 0x00c - eSPI command register */
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__be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
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__be32 receive; /* 0x014 - eSPI receive FIFO access register*/
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u8 res[8]; /* 0x018 - 0x01c reserved */
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__be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
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struct fsl_espi_transfer {
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unsigned actual_length;
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/* eSPI Controller mode register definitions */
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#define SPMODE_ENABLE (1 << 31)
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#define SPMODE_LOOP (1 << 30)
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#define SPMODE_TXTHR(x) ((x) << 8)
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#define SPMODE_RXTHR(x) ((x) << 0)
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/* eSPI Controller CS mode register definitions */
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#define CSMODE_CI_INACTIVEHIGH (1 << 31)
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#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
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#define CSMODE_REV (1 << 29)
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#define CSMODE_DIV16 (1 << 28)
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#define CSMODE_PM(x) ((x) << 24)
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#define CSMODE_POL_1 (1 << 20)
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#define CSMODE_LEN(x) ((x) << 16)
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#define CSMODE_BEF(x) ((x) << 12)
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#define CSMODE_AFT(x) ((x) << 8)
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#define CSMODE_CG(x) ((x) << 3)
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/* Default mode/csmode for eSPI controller */
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#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
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#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
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| CSMODE_AFT(0) | CSMODE_CG(1))
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/* SPIE register values */
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#define SPIE_NE 0x00000200 /* Not empty */
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#define SPIE_NF 0x00000100 /* Not full */
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/* SPIM register values */
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#define SPIM_NE 0x00000200 /* Not empty */
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#define SPIM_NF 0x00000100 /* Not full */
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#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
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#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
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/* SPCOM register values */
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#define SPCOM_CS(x) ((x) << 30)
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#define SPCOM_TRANLEN(x) ((x) << 0)
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#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
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static void fsl_espi_change_mode(struct spi_device *spi)
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struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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struct fsl_espi_reg *reg_base = mspi->reg_base;
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__be32 __iomem *mode = ®_base->csmode[spi->chip_select];
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__be32 __iomem *espi_mode = ®_base->mode;
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/* Turn off IRQs locally to minimize time that SPI is disabled. */
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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tmp = mpc8xxx_spi_read_reg(espi_mode);
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mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
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mpc8xxx_spi_write_reg(mode, cs->hw_mode);
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mpc8xxx_spi_write_reg(espi_mode, tmp);
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local_irq_restore(flags);
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static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
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const u32 *tx = mpc8xxx_spi->tx;
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data = *tx++ << mpc8xxx_spi->tx_shift;
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data_l = data & 0xffff;
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data_h = (data >> 16) & 0xffff;
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data = data_h | data_l;
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mpc8xxx_spi->tx = tx;
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static int fsl_espi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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int bits_per_word = 0;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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bits_per_word = t->bits_per_word;
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/* spi_transfer level calls that work per-word */
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bits_per_word = spi->bits_per_word;
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/* Make sure its a bit width we support [4..16] */
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if ((bits_per_word < 4) || (bits_per_word > 16))
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hz = spi->max_speed_hz;
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cs->get_rx = mpc8xxx_spi_rx_buf_u32;
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cs->get_tx = mpc8xxx_spi_tx_buf_u32;
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if (bits_per_word <= 8) {
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cs->rx_shift = 8 - bits_per_word;
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} else if (bits_per_word <= 16) {
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cs->rx_shift = 16 - bits_per_word;
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if (spi->mode & SPI_LSB_FIRST)
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cs->get_tx = fsl_espi_tx_buf_lsb;
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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bits_per_word = bits_per_word - 1;
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
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cs->hw_mode |= CSMODE_LEN(bits_per_word);
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if ((mpc8xxx_spi->spibrg / hz) > 64) {
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cs->hw_mode |= CSMODE_DIV16;
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pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
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WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
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"Will use %d Hz instead.\n", dev_name(&spi->dev),
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hz, mpc8xxx_spi->spibrg / 1024);
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pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
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cs->hw_mode |= CSMODE_PM(pm);
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fsl_espi_change_mode(spi);
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static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
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struct fsl_espi_reg *reg_base = mspi->reg_base;
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mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
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word = mspi->get_tx(mspi);
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mpc8xxx_spi_write_reg(®_base->transmit, word);
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static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
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unsigned int len = t->len;
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bits_per_word = spi->bits_per_word;
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if (t->bits_per_word)
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bits_per_word = t->bits_per_word;
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mpc8xxx_spi->len = t->len;
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len = roundup(len, 4) / 4;
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mpc8xxx_spi->tx = t->tx_buf;
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mpc8xxx_spi->rx = t->rx_buf;
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INIT_COMPLETION(mpc8xxx_spi->done);
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/* Set SPCOM[CS] and SPCOM[TRANLEN] field */
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if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
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dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
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" beyond the SPCOM[TRANLEN] field\n", t->len);
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mpc8xxx_spi_write_reg(®_base->command,
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(SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
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ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
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wait_for_completion(&mpc8xxx_spi->done);
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/* disable rx ints */
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mpc8xxx_spi_write_reg(®_base->mask, 0);
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return mpc8xxx_spi->count;
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static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
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cmd[1] = (u8)(addr >> 16);
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cmd[2] = (u8)(addr >> 8);
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cmd[3] = (u8)(addr >> 0);
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static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
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return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
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static void fsl_espi_do_trans(struct spi_message *m,
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struct fsl_espi_transfer *tr)
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struct spi_device *spi = m->spi;
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struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
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struct fsl_espi_transfer *espi_trans = tr;
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struct spi_message message;
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struct spi_transfer *t, *first, trans;
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spi_message_init(&message);
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memset(&trans, 0, sizeof(trans));
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first = list_first_entry(&m->transfers, struct spi_transfer,
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if ((first->bits_per_word != t->bits_per_word) ||
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(first->speed_hz != t->speed_hz)) {
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espi_trans->status = -EINVAL;
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dev_err(mspi->dev, "bits_per_word/speed_hz should be"
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" same for the same SPI transfer\n");
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trans.speed_hz = t->speed_hz;
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trans.bits_per_word = t->bits_per_word;
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trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
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trans.len = espi_trans->len;
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trans.tx_buf = espi_trans->tx_buf;
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trans.rx_buf = espi_trans->rx_buf;
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spi_message_add_tail(&trans, &message);
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list_for_each_entry(t, &message.transfers, transfer_list) {
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if (t->bits_per_word || t->speed_hz) {
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status = fsl_espi_setup_transfer(spi, t);
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status = fsl_espi_bufs(spi, t);
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udelay(t->delay_usecs);
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espi_trans->status = status;
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fsl_espi_setup_transfer(spi, NULL);
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static void fsl_espi_cmd_trans(struct spi_message *m,
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struct fsl_espi_transfer *trans, u8 *rx_buff)
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struct spi_transfer *t;
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struct fsl_espi_transfer *espi_trans = trans;
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local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
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espi_trans->status = -ENOMEM;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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memcpy(local_buf + i, t->tx_buf, t->len);
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espi_trans->tx_buf = local_buf;
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espi_trans->rx_buf = local_buf + espi_trans->n_tx;
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fsl_espi_do_trans(m, espi_trans);
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espi_trans->actual_length = espi_trans->len;
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static void fsl_espi_rw_trans(struct spi_message *m,
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struct fsl_espi_transfer *trans, u8 *rx_buff)
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struct fsl_espi_transfer *espi_trans = trans;
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unsigned int n_tx = espi_trans->n_tx;
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unsigned int n_rx = espi_trans->n_rx;
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struct spi_transfer *t;
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u8 *rx_buf = rx_buff;
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unsigned int trans_len;
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local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
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espi_trans->status = -ENOMEM;
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for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
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trans_len = n_rx - pos;
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if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
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trans_len = SPCOM_TRANLEN_MAX - n_tx;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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memcpy(local_buf + i, t->tx_buf, t->len);
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addr = fsl_espi_cmd2addr(local_buf);
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fsl_espi_addr2cmd(addr, local_buf);
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espi_trans->n_tx = n_tx;
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espi_trans->n_rx = trans_len;
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espi_trans->len = trans_len + n_tx;
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espi_trans->tx_buf = local_buf;
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espi_trans->rx_buf = local_buf + n_tx;
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fsl_espi_do_trans(m, espi_trans);
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memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
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espi_trans->actual_length += espi_trans->len - n_tx;
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espi_trans->actual_length += espi_trans->len;
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static void fsl_espi_do_one_msg(struct spi_message *m)
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struct spi_transfer *t;
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unsigned int n_tx = 0;
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unsigned int n_rx = 0;
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struct fsl_espi_transfer espi_trans;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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espi_trans.n_tx = n_tx;
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espi_trans.n_rx = n_rx;
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espi_trans.len = n_tx + n_rx;
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espi_trans.actual_length = 0;
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espi_trans.status = 0;
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fsl_espi_cmd_trans(m, &espi_trans, NULL);
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fsl_espi_rw_trans(m, &espi_trans, rx_buf);
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m->actual_length = espi_trans.actual_length;
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m->status = espi_trans.status;
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m->complete(m->context);
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static int fsl_espi_setup(struct spi_device *spi)
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struct mpc8xxx_spi *mpc8xxx_spi;
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struct fsl_espi_reg *reg_base;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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if (!spi->max_speed_hz)
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cs = kzalloc(sizeof *cs, GFP_KERNEL);
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spi->controller_state = cs;
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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reg_base = mpc8xxx_spi->reg_base;
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hw_mode = cs->hw_mode; /* Save original settings */
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cs->hw_mode = mpc8xxx_spi_read_reg(
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®_base->csmode[spi->chip_select]);
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
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if (spi->mode & SPI_CPHA)
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cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
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if (spi->mode & SPI_CPOL)
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cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
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if (!(spi->mode & SPI_LSB_FIRST))
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cs->hw_mode |= CSMODE_REV;
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/* Handle the loop mode */
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loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
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loop_mode &= ~SPMODE_LOOP;
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if (spi->mode & SPI_LOOP)
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loop_mode |= SPMODE_LOOP;
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mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
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retval = fsl_espi_setup_transfer(spi, NULL);
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cs->hw_mode = hw_mode; /* Restore settings */
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void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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struct fsl_espi_reg *reg_base = mspi->reg_base;
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/* We need handle RX first */
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if (events & SPIE_NE) {
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/* Spin until RX is done */
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while (SPIE_RXCNT(events) < min(4, mspi->len)) {
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events = mpc8xxx_spi_read_reg(®_base->event);
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if (mspi->len >= 4) {
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rx_data = mpc8xxx_spi_read_reg(®_base->receive);
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rx_data_8 = in_8((u8 *)®_base->receive);
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rx_data |= (rx_data_8 << (tmp * 8));
531
rx_data <<= (4 - mspi->len) * 8;
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mspi->get_rx(rx_data, mspi);
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if (!(events & SPIE_NF)) {
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/* spin until TX is done */
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ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
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®_base->event)) & SPIE_NF) == 0, 1000, 0);
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dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
552
/* Clear the events */
553
mpc8xxx_spi_write_reg(®_base->event, events);
557
u32 word = mspi->get_tx(mspi);
559
mpc8xxx_spi_write_reg(®_base->transmit, word);
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complete(&mspi->done);
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static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
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struct mpc8xxx_spi *mspi = context_data;
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struct fsl_espi_reg *reg_base = mspi->reg_base;
569
irqreturn_t ret = IRQ_NONE;
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/* Get interrupt events(tx/rx) */
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events = mpc8xxx_spi_read_reg(®_base->event);
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dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
579
fsl_espi_cpu_irq(mspi, events);
584
static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
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iounmap(mspi->reg_base);
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static struct spi_master * __devinit fsl_espi_probe(struct device *dev,
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struct resource *mem, unsigned int irq)
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struct fsl_spi_platform_data *pdata = dev->platform_data;
593
struct spi_master *master;
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struct mpc8xxx_spi *mpc8xxx_spi;
595
struct fsl_espi_reg *reg_base;
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master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
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dev_set_drvdata(dev, master);
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ret = mpc8xxx_spi_probe(dev, mem, irq);
611
master->setup = fsl_espi_setup;
613
mpc8xxx_spi = spi_master_get_devdata(master);
614
mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
615
mpc8xxx_spi->spi_remove = fsl_espi_remove;
617
mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
618
if (!mpc8xxx_spi->reg_base) {
623
reg_base = mpc8xxx_spi->reg_base;
625
/* Register for SPI Interrupt */
626
ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
627
0, "fsl_espi", mpc8xxx_spi);
631
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
632
mpc8xxx_spi->rx_shift = 16;
633
mpc8xxx_spi->tx_shift = 24;
636
/* SPI controller initializations */
637
mpc8xxx_spi_write_reg(®_base->mode, 0);
638
mpc8xxx_spi_write_reg(®_base->mask, 0);
639
mpc8xxx_spi_write_reg(®_base->command, 0);
640
mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
642
/* Init eSPI CS mode register */
643
for (i = 0; i < pdata->max_chipselect; i++)
644
mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
646
/* Enable SPI interface */
647
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
649
mpc8xxx_spi_write_reg(®_base->mode, regval);
651
ret = spi_register_master(master);
655
dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
660
free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
662
iounmap(mpc8xxx_spi->reg_base);
664
spi_master_put(master);
669
static int of_fsl_espi_get_chipselects(struct device *dev)
671
struct device_node *np = dev->of_node;
672
struct fsl_spi_platform_data *pdata = dev->platform_data;
676
prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
677
if (!prop || len < sizeof(*prop)) {
678
dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
682
pdata->max_chipselect = *prop;
683
pdata->cs_control = NULL;
688
static int __devinit of_fsl_espi_probe(struct platform_device *ofdev)
690
struct device *dev = &ofdev->dev;
691
struct device_node *np = ofdev->dev.of_node;
692
struct spi_master *master;
697
ret = of_mpc8xxx_spi_probe(ofdev);
701
ret = of_fsl_espi_get_chipselects(dev);
705
ret = of_address_to_resource(np, 0, &mem);
709
ret = of_irq_to_resource(np, 0, &irq);
715
master = fsl_espi_probe(dev, &mem, irq.start);
716
if (IS_ERR(master)) {
717
ret = PTR_ERR(master);
727
static int __devexit of_fsl_espi_remove(struct platform_device *dev)
729
return mpc8xxx_spi_remove(&dev->dev);
732
static const struct of_device_id of_fsl_espi_match[] = {
733
{ .compatible = "fsl,mpc8536-espi" },
736
MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
738
static struct platform_driver fsl_espi_driver = {
741
.owner = THIS_MODULE,
742
.of_match_table = of_fsl_espi_match,
744
.probe = of_fsl_espi_probe,
745
.remove = __devexit_p(of_fsl_espi_remove),
747
module_platform_driver(fsl_espi_driver);
749
MODULE_AUTHOR("Mingkai Hu");
750
MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
751
MODULE_LICENSE("GPL");