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/*******************************************************************************
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STMMAC Ethernet Driver -- MDIO bus implementation
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Provides Bus interface for MII registers
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Carl Shaw <carl.shaw@st.com>
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Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/slab.h>
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#define MII_BUSY 0x00000001
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#define MII_WRITE 0x00000002
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* @bus: points to the mii_bus structure
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* @phyaddr: MII addr reg bits 15-11
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* @phyreg: MII addr reg bits 10-6
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* Description: it reads data from the MII register from within the phy device.
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* For the 7111 GMAC, we must set the bit 0 in the MII address register while
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* accessing the PHY registers.
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* Fortunately, it seems this has no drawback for the 7109 MAC.
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static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
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((phyreg << 6) & (0x000007C0)));
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regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
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do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
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writel(regValue, priv->ioaddr + mii_address);
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do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
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/* Read the data from the MII data register */
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data = (int)readl(priv->ioaddr + mii_data);
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* @bus: points to the mii_bus structure
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* @phyaddr: MII addr reg bits 15-11
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* @phyreg: MII addr reg bits 10-6
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* Description: it writes the data into the MII register from within the device.
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static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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(((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
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value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
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/* Wait until any existing MII operation is complete */
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do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
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/* Set the MII address register to write */
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writel(phydata, priv->ioaddr + mii_data);
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writel(value, priv->ioaddr + mii_address);
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/* Wait until any existing MII operation is complete */
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do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
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* @bus: points to the mii_bus structure
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* Description: reset the MII bus
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static int stmmac_mdio_reset(struct mii_bus *bus)
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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if (priv->phy_reset) {
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pr_debug("stmmac_mdio_reset: calling phy_reset\n");
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priv->phy_reset(priv->plat->bsp_priv);
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/* This is a workaround for problems with the STE101P PHY.
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* It doesn't complete its reset until at least one clock cycle
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* on MDC, so perform a dummy mdio read.
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writel(0, priv->ioaddr + mii_address);
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* stmmac_mdio_register
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* @ndev: net device structure
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* Description: it registers the MII bus
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int stmmac_mdio_register(struct net_device *ndev)
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struct mii_bus *new_bus;
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struct stmmac_priv *priv = netdev_priv(ndev);
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new_bus = mdiobus_alloc();
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irqlist = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
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if (irqlist == NULL) {
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goto irqlist_alloc_fail;
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/* Assign IRQ to phy at address phy_addr */
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if (priv->phy_addr != -1)
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irqlist[priv->phy_addr] = priv->phy_irq;
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new_bus->name = "STMMAC MII Bus";
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new_bus->read = &stmmac_mdio_read;
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new_bus->write = &stmmac_mdio_write;
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new_bus->reset = &stmmac_mdio_reset;
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snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
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new_bus->priv = ndev;
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new_bus->irq = irqlist;
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new_bus->phy_mask = priv->phy_mask;
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new_bus->parent = priv->device;
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err = mdiobus_register(new_bus);
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pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
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goto bus_register_fail;
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for (addr = 0; addr < 32; addr++) {
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struct phy_device *phydev = new_bus->phy_map[addr];
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if (priv->phy_addr == -1) {
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priv->phy_addr = addr;
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phydev->irq = priv->phy_irq;
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irqlist[addr] = priv->phy_irq;
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pr_info("%s: PHY ID %08x at %d IRQ %d (%s)%s\n",
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ndev->name, phydev->phy_id, addr,
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phydev->irq, dev_name(&phydev->dev),
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(addr == priv->phy_addr) ? " active" : "");
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pr_warning("%s: No PHY found\n", ndev->name);
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* stmmac_mdio_unregister
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* @ndev: net device structure
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* Description: it unregisters the MII bus
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int stmmac_mdio_unregister(struct net_device *ndev)
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struct stmmac_priv *priv = netdev_priv(ndev);
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mdiobus_unregister(priv->mii);
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priv->mii->priv = NULL;