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//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file defines the MachineRegisterInfo class.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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/// MachineRegisterInfo - Keep track of information for virtual and physical
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/// registers, including vreg register classes, use/def chains for registers,
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class MachineRegisterInfo {
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virtual void anchor();
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virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
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virtual ~Delegate() {}
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const MachineFunction *MF;
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Delegate *TheDelegate;
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/// IsSSA - True when the machine function is in SSA form and virtual
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/// registers have a single def.
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/// TracksLiveness - True while register liveness is being tracked accurately.
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/// Basic block live-in lists, kill flags, and implicit defs may not be
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/// accurate when after this flag is cleared.
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/// True if subregister liveness is tracked.
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bool TracksSubRegLiveness;
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/// VRegInfo - Information we keep for each virtual register.
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/// Each element in this list contains the register class of the vreg and the
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/// start of the use/def list for the register.
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IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
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VirtReg2IndexFunctor> VRegInfo;
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/// RegAllocHints - This vector records register allocation hints for virtual
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/// registers. For each virtual register, it keeps a register and hint type
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/// pair making up the allocation hint. Hint type is target specific except
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/// for the value 0 which means the second value of the pair is the preferred
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/// register for allocation. For example, if the hint is <0, 1024>, it means
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/// the allocator should prefer the physical register allocated to the virtual
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/// register of the hint.
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IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
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/// PhysRegUseDefLists - This is an array of the head of the use/def list for
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/// physical registers.
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std::vector<MachineOperand *> PhysRegUseDefLists;
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/// getRegUseDefListHead - Return the head pointer for the register use/def
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/// list for the specified virtual or physical register.
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MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
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if (TargetRegisterInfo::isVirtualRegister(RegNo))
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return VRegInfo[RegNo].second;
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return PhysRegUseDefLists[RegNo];
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MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
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if (TargetRegisterInfo::isVirtualRegister(RegNo))
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return VRegInfo[RegNo].second;
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return PhysRegUseDefLists[RegNo];
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/// Get the next element in the use-def chain.
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static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
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assert(MO && MO->isReg() && "This is not a register operand!");
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return MO->Contents.Reg.Next;
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/// UsedPhysRegMask - Additional used physregs including aliases.
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/// This bit vector represents all the registers clobbered by function calls.
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BitVector UsedPhysRegMask;
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/// ReservedRegs - This is a bit vector of reserved registers. The target
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/// may change its mind about which registers should be reserved. This
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/// vector is the frozen set of reserved registers when register allocation
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BitVector ReservedRegs;
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/// Keep track of the physical registers that are live in to the function.
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/// Live in values are typically arguments in registers. LiveIn values are
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/// allowed to have virtual registers associated with them, stored in the
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std::vector<std::pair<unsigned, unsigned> > LiveIns;
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MachineRegisterInfo(const MachineRegisterInfo&) = delete;
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void operator=(const MachineRegisterInfo&) = delete;
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explicit MachineRegisterInfo(const MachineFunction *MF);
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const TargetRegisterInfo *getTargetRegisterInfo() const {
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return MF->getSubtarget().getRegisterInfo();
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void resetDelegate(Delegate *delegate) {
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// Ensure another delegate does not take over unless the current
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// delegate first unattaches itself. If we ever need to multicast
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// notifications, we will need to change to using a list.
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assert(TheDelegate == delegate &&
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"Only the current delegate can perform reset!");
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TheDelegate = nullptr;
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void setDelegate(Delegate *delegate) {
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assert(delegate && !TheDelegate &&
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"Attempted to set delegate to null, or to change it without "
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"first resetting it!");
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TheDelegate = delegate;
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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// isSSA - Returns true when the machine function is in SSA form. Early
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// passes require the machine function to be in SSA form where every virtual
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// register has a single defining instruction.
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// The TwoAddressInstructionPass and PHIElimination passes take the machine
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// function out of SSA form when they introduce multiple defs per virtual
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bool isSSA() const { return IsSSA; }
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// leaveSSA - Indicates that the machine function is no longer in SSA form.
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void leaveSSA() { IsSSA = false; }
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/// tracksLiveness - Returns true when tracking register liveness accurately.
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/// While this flag is true, register liveness information in basic block
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/// live-in lists and machine instruction operands is accurate. This means it
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/// can be used to change the code in ways that affect the values in
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/// registers, for example by the register scavenger.
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/// When this flag is false, liveness is no longer reliable.
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bool tracksLiveness() const { return TracksLiveness; }
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/// invalidateLiveness - Indicates that register liveness is no longer being
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/// tracked accurately.
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/// This should be called by late passes that invalidate the liveness
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void invalidateLiveness() { TracksLiveness = false; }
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/// Returns true if liveness for register class @p RC should be tracked at
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/// the subregister level.
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bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
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return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
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bool shouldTrackSubRegLiveness(unsigned VReg) const {
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assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
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return shouldTrackSubRegLiveness(*getRegClass(VReg));
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bool subRegLivenessEnabled() const {
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return TracksSubRegLiveness;
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void enableSubRegLiveness(bool Enable = true) {
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TracksSubRegLiveness = Enable;
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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// Strictly for use by MachineInstr.cpp.
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void addRegOperandToUseList(MachineOperand *MO);
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// Strictly for use by MachineInstr.cpp.
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void removeRegOperandFromUseList(MachineOperand *MO);
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// Strictly for use by MachineInstr.cpp.
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void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
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/// Verify the sanity of the use list for Reg.
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void verifyUseList(unsigned Reg) const;
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/// Verify the use list of all registers.
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void verifyUseLists() const;
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/// reg_begin/reg_end - Provide iteration support to walk over all definitions
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/// and uses of a register within the MachineFunction that corresponds to this
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/// MachineRegisterInfo object.
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template<bool Uses, bool Defs, bool SkipDebug,
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bool ByOperand, bool ByInstr, bool ByBundle>
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class defusechain_iterator;
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template<bool Uses, bool Defs, bool SkipDebug,
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bool ByOperand, bool ByInstr, bool ByBundle>
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class defusechain_instr_iterator;
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// Make it a friend so it can access getNextOperandForReg().
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template<bool, bool, bool, bool, bool, bool>
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friend class defusechain_iterator;
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template<bool, bool, bool, bool, bool, bool>
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friend class defusechain_instr_iterator;
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/// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
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typedef defusechain_iterator<true,true,false,true,false,false>
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reg_iterator reg_begin(unsigned RegNo) const {
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return reg_iterator(getRegUseDefListHead(RegNo));
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static reg_iterator reg_end() { return reg_iterator(nullptr); }
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inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
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return iterator_range<reg_iterator>(reg_begin(Reg), reg_end());
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/// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
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/// of the specified register, stepping by MachineInstr.
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typedef defusechain_instr_iterator<true,true,false,false,true,false>
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reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
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return reg_instr_iterator(getRegUseDefListHead(RegNo));
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static reg_instr_iterator reg_instr_end() {
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return reg_instr_iterator(nullptr);
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inline iterator_range<reg_instr_iterator>
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reg_instructions(unsigned Reg) const {
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return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg),
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/// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
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/// of the specified register, stepping by bundle.
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typedef defusechain_instr_iterator<true,true,false,false,false,true>
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reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
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return reg_bundle_iterator(getRegUseDefListHead(RegNo));
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static reg_bundle_iterator reg_bundle_end() {
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return reg_bundle_iterator(nullptr);
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inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
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return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg),
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/// reg_empty - Return true if there are no instructions using or defining the
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/// specified register (it may be live-in).
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bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
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/// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
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/// of the specified register, skipping those marked as Debug.
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typedef defusechain_iterator<true,true,true,true,false,false>
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reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
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return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
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static reg_nodbg_iterator reg_nodbg_end() {
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return reg_nodbg_iterator(nullptr);
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inline iterator_range<reg_nodbg_iterator>
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reg_nodbg_operands(unsigned Reg) const {
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return iterator_range<reg_nodbg_iterator>(reg_nodbg_begin(Reg),
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/// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
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/// all defs and uses of the specified register, stepping by MachineInstr,
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/// skipping those marked as Debug.
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typedef defusechain_instr_iterator<true,true,true,false,true,false>
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reg_instr_nodbg_iterator;
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reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
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return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
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static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
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return reg_instr_nodbg_iterator(nullptr);
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inline iterator_range<reg_instr_nodbg_iterator>
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reg_nodbg_instructions(unsigned Reg) const {
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return iterator_range<reg_instr_nodbg_iterator>(reg_instr_nodbg_begin(Reg),
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reg_instr_nodbg_end());
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/// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
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/// all defs and uses of the specified register, stepping by bundle,
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/// skipping those marked as Debug.
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typedef defusechain_instr_iterator<true,true,true,false,false,true>
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reg_bundle_nodbg_iterator;
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reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
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return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
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static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
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return reg_bundle_nodbg_iterator(nullptr);
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inline iterator_range<reg_bundle_nodbg_iterator>
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reg_nodbg_bundles(unsigned Reg) const {
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return iterator_range<reg_bundle_nodbg_iterator>(reg_bundle_nodbg_begin(Reg),
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reg_bundle_nodbg_end());
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/// reg_nodbg_empty - Return true if the only instructions using or defining
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/// Reg are Debug instructions.
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bool reg_nodbg_empty(unsigned RegNo) const {
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return reg_nodbg_begin(RegNo) == reg_nodbg_end();
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/// def_iterator/def_begin/def_end - Walk all defs of the specified register.
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typedef defusechain_iterator<false,true,false,true,false,false>
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def_iterator def_begin(unsigned RegNo) const {
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return def_iterator(getRegUseDefListHead(RegNo));
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static def_iterator def_end() { return def_iterator(nullptr); }
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inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
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return iterator_range<def_iterator>(def_begin(Reg), def_end());
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/// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
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/// specified register, stepping by MachineInst.
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typedef defusechain_instr_iterator<false,true,false,false,true,false>
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def_instr_iterator def_instr_begin(unsigned RegNo) const {
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return def_instr_iterator(getRegUseDefListHead(RegNo));
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static def_instr_iterator def_instr_end() {
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return def_instr_iterator(nullptr);
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inline iterator_range<def_instr_iterator>
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def_instructions(unsigned Reg) const {
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return iterator_range<def_instr_iterator>(def_instr_begin(Reg),
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/// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
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/// specified register, stepping by bundle.
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typedef defusechain_instr_iterator<false,true,false,false,false,true>
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def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
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return def_bundle_iterator(getRegUseDefListHead(RegNo));
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static def_bundle_iterator def_bundle_end() {
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return def_bundle_iterator(nullptr);
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inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
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return iterator_range<def_bundle_iterator>(def_bundle_begin(Reg),
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/// def_empty - Return true if there are no instructions defining the
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/// specified register (it may be live-in).
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bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
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/// hasOneDef - Return true if there is exactly one instruction defining the
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/// specified register.
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bool hasOneDef(unsigned RegNo) const {
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def_iterator DI = def_begin(RegNo);
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return ++DI == def_end();
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/// use_iterator/use_begin/use_end - Walk all uses of the specified register.
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typedef defusechain_iterator<true,false,false,true,false,false>
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use_iterator use_begin(unsigned RegNo) const {
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return use_iterator(getRegUseDefListHead(RegNo));
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static use_iterator use_end() { return use_iterator(nullptr); }
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inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
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return iterator_range<use_iterator>(use_begin(Reg), use_end());
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/// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
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/// specified register, stepping by MachineInstr.
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typedef defusechain_instr_iterator<true,false,false,false,true,false>
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use_instr_iterator use_instr_begin(unsigned RegNo) const {
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return use_instr_iterator(getRegUseDefListHead(RegNo));
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static use_instr_iterator use_instr_end() {
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return use_instr_iterator(nullptr);
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inline iterator_range<use_instr_iterator>
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use_instructions(unsigned Reg) const {
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return iterator_range<use_instr_iterator>(use_instr_begin(Reg),
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/// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
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/// specified register, stepping by bundle.
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typedef defusechain_instr_iterator<true,false,false,false,false,true>
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use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
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return use_bundle_iterator(getRegUseDefListHead(RegNo));
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static use_bundle_iterator use_bundle_end() {
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return use_bundle_iterator(nullptr);
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inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
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return iterator_range<use_bundle_iterator>(use_bundle_begin(Reg),
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/// use_empty - Return true if there are no instructions using the specified
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bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
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/// hasOneUse - Return true if there is exactly one instruction using the
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/// specified register.
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bool hasOneUse(unsigned RegNo) const {
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use_iterator UI = use_begin(RegNo);
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return ++UI == use_end();
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/// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
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/// specified register, skipping those marked as Debug.
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typedef defusechain_iterator<true,false,true,true,false,false>
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use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
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return use_nodbg_iterator(getRegUseDefListHead(RegNo));
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static use_nodbg_iterator use_nodbg_end() {
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return use_nodbg_iterator(nullptr);
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inline iterator_range<use_nodbg_iterator>
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use_nodbg_operands(unsigned Reg) const {
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return iterator_range<use_nodbg_iterator>(use_nodbg_begin(Reg),
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/// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
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/// all uses of the specified register, stepping by MachineInstr, skipping
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/// those marked as Debug.
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typedef defusechain_instr_iterator<true,false,true,false,true,false>
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use_instr_nodbg_iterator;
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use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
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return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
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static use_instr_nodbg_iterator use_instr_nodbg_end() {
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return use_instr_nodbg_iterator(nullptr);
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inline iterator_range<use_instr_nodbg_iterator>
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use_nodbg_instructions(unsigned Reg) const {
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return iterator_range<use_instr_nodbg_iterator>(use_instr_nodbg_begin(Reg),
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use_instr_nodbg_end());
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/// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
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/// all uses of the specified register, stepping by bundle, skipping
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/// those marked as Debug.
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typedef defusechain_instr_iterator<true,false,true,false,false,true>
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use_bundle_nodbg_iterator;
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use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
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return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
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static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
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return use_bundle_nodbg_iterator(nullptr);
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inline iterator_range<use_bundle_nodbg_iterator>
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use_nodbg_bundles(unsigned Reg) const {
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return iterator_range<use_bundle_nodbg_iterator>(use_bundle_nodbg_begin(Reg),
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use_bundle_nodbg_end());
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/// use_nodbg_empty - Return true if there are no non-Debug instructions
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/// using the specified register.
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bool use_nodbg_empty(unsigned RegNo) const {
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return use_nodbg_begin(RegNo) == use_nodbg_end();
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/// hasOneNonDBGUse - Return true if there is exactly one non-Debug
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/// instruction using the specified register.
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bool hasOneNonDBGUse(unsigned RegNo) const;
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/// replaceRegWith - Replace all instances of FromReg with ToReg in the
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/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
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/// except that it also changes any definitions of the register as well.
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/// Note that it is usually necessary to first constrain ToReg's register
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/// class to match the FromReg constraints using:
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/// constrainRegClass(ToReg, getRegClass(FromReg))
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/// That function will return NULL if the virtual registers have incompatible
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/// Note that if ToReg is a physical register the function will replace and
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/// apply sub registers to ToReg in order to obtain a final/proper physical
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void replaceRegWith(unsigned FromReg, unsigned ToReg);
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/// getVRegDef - Return the machine instr that defines the specified virtual
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/// register or null if none is found. This assumes that the code is in SSA
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/// form, so there should only be one definition.
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MachineInstr *getVRegDef(unsigned Reg) const;
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/// getUniqueVRegDef - Return the unique machine instr that defines the
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/// specified virtual register or null if none is found. If there are
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/// multiple definitions or no definition, return null.
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MachineInstr *getUniqueVRegDef(unsigned Reg) const;
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/// clearKillFlags - Iterate over all the uses of the given register and
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/// clear the kill flag from the MachineOperand. This function is used by
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/// optimization passes which extend register lifetimes and need only
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/// preserve conservative kill flag information.
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void clearKillFlags(unsigned Reg) const;
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void dumpUses(unsigned RegNo) const;
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/// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
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/// throughout the function. It is safe to move instructions that read such
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bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
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/// Get an iterator over the pressure sets affected by the given physical or
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/// virtual register. If RegUnit is physical, it must be a register unit (from
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/// MCRegUnitIterator).
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PSetIterator getPressureSets(unsigned RegUnit) const;
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//===--------------------------------------------------------------------===//
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// Virtual Register Info
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//===--------------------------------------------------------------------===//
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/// getRegClass - Return the register class of the specified virtual register.
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const TargetRegisterClass *getRegClass(unsigned Reg) const {
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return VRegInfo[Reg].first;
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/// setRegClass - Set the register class of the specified virtual register.
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void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
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/// constrainRegClass - Constrain the register class of the specified virtual
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/// register to be a common subclass of RC and the current register class,
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/// but only if the new class has at least MinNumRegs registers. Return the
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/// new register class, or NULL if no such class exists.
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/// This should only be used when the constraint is known to be trivial, like
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/// GR32 -> GR32_NOSP. Beware of increasing register pressure.
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const TargetRegisterClass *constrainRegClass(unsigned Reg,
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const TargetRegisterClass *RC,
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unsigned MinNumRegs = 0);
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/// recomputeRegClass - Try to find a legal super-class of Reg's register
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/// class that still satisfies the constraints from the instructions using
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/// Reg. Returns true if Reg was upgraded.
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/// This method can be used after constraints have been removed from a
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/// virtual register, for example after removing instructions or splitting
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bool recomputeRegClass(unsigned Reg);
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/// createVirtualRegister - Create and return a new virtual register in the
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/// function with the specified register class.
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unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
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/// getNumVirtRegs - Return the number of virtual registers created.
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unsigned getNumVirtRegs() const { return VRegInfo.size(); }
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/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
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void clearVirtRegs();
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/// setRegAllocationHint - Specify a register allocation hint for the
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/// specified virtual register.
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void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
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assert(TargetRegisterInfo::isVirtualRegister(VReg));
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RegAllocHints[VReg].first = Type;
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RegAllocHints[VReg].second = PrefReg;
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/// getRegAllocationHint - Return the register allocation hint for the
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/// specified virtual register.
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std::pair<unsigned, unsigned>
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getRegAllocationHint(unsigned VReg) const {
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assert(TargetRegisterInfo::isVirtualRegister(VReg));
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return RegAllocHints[VReg];
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/// getSimpleHint - Return the preferred register allocation hint, or 0 if a
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/// standard simple hint (Type == 0) is not set.
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unsigned getSimpleHint(unsigned VReg) const {
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assert(TargetRegisterInfo::isVirtualRegister(VReg));
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std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
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return Hint.first ? 0 : Hint.second;
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/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
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/// specified register as undefined which causes the DBG_VALUE to be
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/// deleted during LiveDebugVariables analysis.
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void markUsesInDebugValueAsUndef(unsigned Reg) const;
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/// Return true if the specified register is modified in this function.
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/// This checks that no defining machine operands exist for the register or
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/// any of its aliases. Definitions found on functions marked noreturn are
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bool isPhysRegModified(unsigned PhysReg) const;
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/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
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/// This corresponds to the bit mask attached to register mask operands.
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void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
647
UsedPhysRegMask.setBitsNotInMask(RegMask);
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//===--------------------------------------------------------------------===//
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// Reserved Register Info
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//===--------------------------------------------------------------------===//
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// The set of reserved registers must be invariant during register
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// allocation. For example, the target cannot suddenly decide it needs a
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// frame pointer when the register allocator has already used the frame
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// pointer register for something else.
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// These methods can be used by target hooks like hasFP() to avoid changing
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// the reserved register set during register allocation.
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/// freezeReservedRegs - Called by the register allocator to freeze the set
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/// of reserved registers before allocation begins.
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void freezeReservedRegs(const MachineFunction&);
666
/// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
667
/// to ensure the set of reserved registers stays constant.
668
bool reservedRegsFrozen() const {
669
return !ReservedRegs.empty();
672
/// canReserveReg - Returns true if PhysReg can be used as a reserved
673
/// register. Any register can be reserved before freezeReservedRegs() is
675
bool canReserveReg(unsigned PhysReg) const {
676
return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
679
/// getReservedRegs - Returns a reference to the frozen set of reserved
680
/// registers. This method should always be preferred to calling
681
/// TRI::getReservedRegs() when possible.
682
const BitVector &getReservedRegs() const {
683
assert(reservedRegsFrozen() &&
684
"Reserved registers haven't been frozen yet. "
685
"Use TRI::getReservedRegs().");
689
/// isReserved - Returns true when PhysReg is a reserved register.
691
/// Reserved registers may belong to an allocatable register class, but the
692
/// target has explicitly requested that they are not used.
694
bool isReserved(unsigned PhysReg) const {
695
return getReservedRegs().test(PhysReg);
698
/// isAllocatable - Returns true when PhysReg belongs to an allocatable
699
/// register class and it hasn't been reserved.
701
/// Allocatable registers may show up in the allocation order of some virtual
702
/// register, so a register allocator needs to track its liveness and
704
bool isAllocatable(unsigned PhysReg) const {
705
return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
706
!isReserved(PhysReg);
709
//===--------------------------------------------------------------------===//
711
//===--------------------------------------------------------------------===//
713
/// addLiveIn - Add the specified register as a live-in. Note that it
714
/// is an error to add the same register to the same set more than once.
715
void addLiveIn(unsigned Reg, unsigned vreg = 0) {
716
LiveIns.push_back(std::make_pair(Reg, vreg));
719
// Iteration support for the live-ins set. It's kept in sorted order
720
// by register number.
721
typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
723
livein_iterator livein_begin() const { return LiveIns.begin(); }
724
livein_iterator livein_end() const { return LiveIns.end(); }
725
bool livein_empty() const { return LiveIns.empty(); }
727
bool isLiveIn(unsigned Reg) const;
729
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
730
/// corresponding live-in physical register.
731
unsigned getLiveInPhysReg(unsigned VReg) const;
733
/// getLiveInVirtReg - If PReg is a live-in physical register, return the
734
/// corresponding live-in physical register.
735
unsigned getLiveInVirtReg(unsigned PReg) const;
737
/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
738
/// into the given entry block.
739
void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
740
const TargetRegisterInfo &TRI,
741
const TargetInstrInfo &TII);
743
/// Returns a mask covering all bits that can appear in lane masks of
744
/// subregisters of the virtual register @p Reg.
745
unsigned getMaxLaneMaskForVReg(unsigned Reg) const;
747
/// defusechain_iterator - This class provides iterator support for machine
748
/// operands in the function that use or define a specific register. If
749
/// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
750
/// returns defs. If neither are true then you are silly and it always
751
/// returns end(). If SkipDebug is true it skips uses marked Debug
752
/// when incrementing.
753
template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
754
bool ByOperand, bool ByInstr, bool ByBundle>
755
class defusechain_iterator
756
: public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
758
explicit defusechain_iterator(MachineOperand *op) : Op(op) {
759
// If the first node isn't one we're interested in, advance to one that
760
// we are interested in.
762
if ((!ReturnUses && op->isUse()) ||
763
(!ReturnDefs && op->isDef()) ||
764
(SkipDebug && op->isDebug()))
768
friend class MachineRegisterInfo;
771
assert(Op && "Cannot increment end iterator!");
772
Op = getNextOperandForReg(Op);
774
// All defs come before the uses, so stop def_iterator early.
780
assert(!Op->isDebug() && "Can't have debug defs");
783
// If this is an operand we don't care about, skip it.
784
while (Op && ((!ReturnDefs && Op->isDef()) ||
785
(SkipDebug && Op->isDebug())))
786
Op = getNextOperandForReg(Op);
790
typedef std::iterator<std::forward_iterator_tag,
791
MachineInstr, ptrdiff_t>::reference reference;
792
typedef std::iterator<std::forward_iterator_tag,
793
MachineInstr, ptrdiff_t>::pointer pointer;
795
defusechain_iterator() : Op(nullptr) {}
797
bool operator==(const defusechain_iterator &x) const {
800
bool operator!=(const defusechain_iterator &x) const {
801
return !operator==(x);
804
/// atEnd - return true if this iterator is equal to reg_end() on the value.
805
bool atEnd() const { return Op == nullptr; }
807
// Iterator traversal: forward iteration only
808
defusechain_iterator &operator++() { // Preincrement
809
assert(Op && "Cannot increment end iterator!");
813
MachineInstr *P = Op->getParent();
816
} while (Op && Op->getParent() == P);
817
} else if (ByBundle) {
818
MachineInstr *P = getBundleStart(Op->getParent());
821
} while (Op && getBundleStart(Op->getParent()) == P);
826
defusechain_iterator operator++(int) { // Postincrement
827
defusechain_iterator tmp = *this; ++*this; return tmp;
830
/// getOperandNo - Return the operand # of this MachineOperand in its
832
unsigned getOperandNo() const {
833
assert(Op && "Cannot dereference end iterator!");
834
return Op - &Op->getParent()->getOperand(0);
837
// Retrieve a reference to the current operand.
838
MachineOperand &operator*() const {
839
assert(Op && "Cannot dereference end iterator!");
843
MachineOperand *operator->() const {
844
assert(Op && "Cannot dereference end iterator!");
849
/// defusechain_iterator - This class provides iterator support for machine
850
/// operands in the function that use or define a specific register. If
851
/// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
852
/// returns defs. If neither are true then you are silly and it always
853
/// returns end(). If SkipDebug is true it skips uses marked Debug
854
/// when incrementing.
855
template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
856
bool ByOperand, bool ByInstr, bool ByBundle>
857
class defusechain_instr_iterator
858
: public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
860
explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
861
// If the first node isn't one we're interested in, advance to one that
862
// we are interested in.
864
if ((!ReturnUses && op->isUse()) ||
865
(!ReturnDefs && op->isDef()) ||
866
(SkipDebug && op->isDebug()))
870
friend class MachineRegisterInfo;
873
assert(Op && "Cannot increment end iterator!");
874
Op = getNextOperandForReg(Op);
876
// All defs come before the uses, so stop def_iterator early.
882
assert(!Op->isDebug() && "Can't have debug defs");
885
// If this is an operand we don't care about, skip it.
886
while (Op && ((!ReturnDefs && Op->isDef()) ||
887
(SkipDebug && Op->isDebug())))
888
Op = getNextOperandForReg(Op);
892
typedef std::iterator<std::forward_iterator_tag,
893
MachineInstr, ptrdiff_t>::reference reference;
894
typedef std::iterator<std::forward_iterator_tag,
895
MachineInstr, ptrdiff_t>::pointer pointer;
897
defusechain_instr_iterator() : Op(nullptr) {}
899
bool operator==(const defusechain_instr_iterator &x) const {
902
bool operator!=(const defusechain_instr_iterator &x) const {
903
return !operator==(x);
906
/// atEnd - return true if this iterator is equal to reg_end() on the value.
907
bool atEnd() const { return Op == nullptr; }
909
// Iterator traversal: forward iteration only
910
defusechain_instr_iterator &operator++() { // Preincrement
911
assert(Op && "Cannot increment end iterator!");
915
MachineInstr *P = Op->getParent();
918
} while (Op && Op->getParent() == P);
919
} else if (ByBundle) {
920
MachineInstr *P = getBundleStart(Op->getParent());
923
} while (Op && getBundleStart(Op->getParent()) == P);
928
defusechain_instr_iterator operator++(int) { // Postincrement
929
defusechain_instr_iterator tmp = *this; ++*this; return tmp;
932
// Retrieve a reference to the current operand.
933
MachineInstr &operator*() const {
934
assert(Op && "Cannot dereference end iterator!");
935
if (ByBundle) return *(getBundleStart(Op->getParent()));
936
return *Op->getParent();
939
MachineInstr *operator->() const {
940
assert(Op && "Cannot dereference end iterator!");
941
if (ByBundle) return getBundleStart(Op->getParent());
942
return Op->getParent();
947
/// Iterate over the pressure sets affected by the given physical or virtual
948
/// register. If Reg is physical, it must be a register unit (from
949
/// MCRegUnitIterator).
954
PSetIterator(): PSet(nullptr), Weight(0) {}
955
PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
956
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
957
if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
958
const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
959
PSet = TRI->getRegClassPressureSets(RC);
960
Weight = TRI->getRegClassWeight(RC).RegWeight;
963
PSet = TRI->getRegUnitPressureSets(RegUnit);
964
Weight = TRI->getRegUnitWeight(RegUnit);
969
bool isValid() const { return PSet; }
971
unsigned getWeight() const { return Weight; }
973
unsigned operator*() const { return *PSet; }
976
assert(isValid() && "Invalid PSetIterator.");
983
inline PSetIterator MachineRegisterInfo::
984
getPressureSets(unsigned RegUnit) const {
985
return PSetIterator(RegUnit, this);
988
} // End llvm namespace