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//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file describes Mips MSA ASE instructions.
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//===----------------------------------------------------------------------===//
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def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
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def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
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SDTCisVT<3, OtherVT>]>;
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def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
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SDTCisVT<3, OtherVT>]>;
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def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
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SDTCisInt<1>, SDTCisVec<1>,
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SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
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def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
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SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
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def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
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def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
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SDTCisVT<2, i32>, SDTCisSameAs<0, 3>,
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def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
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def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
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def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
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def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
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def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
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def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
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def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
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def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
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def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
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def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
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def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
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def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
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def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
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def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
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def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
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def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
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SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
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def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
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SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
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def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
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def immZExt6Ptr : ImmLeaf<iPTR, [{return isUInt<6>(Imm);}]>;
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// The immediate of an LSA instruction needs special handling
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// as the encoded value should be subtracted by one.
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def uimm2LSAAsmOperand : AsmOperandClass {
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let ParserMethod = "parseLSAImm";
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let RenderMethod = "addImmOperands";
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def LSAImm : Operand<i32> {
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let PrintMethod = "printUnsignedImm";
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let EncoderMethod = "getLSAImmEncoding";
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let DecoderMethod = "DecodeLSAImm";
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let ParserMatchClass = uimm2LSAAsmOperand;
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def uimm4 : Operand<i32> {
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let PrintMethod = "printUnsignedImm8";
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def uimm4_ptr : Operand<iPTR> {
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let PrintMethod = "printUnsignedImm8";
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def uimm6_ptr : Operand<iPTR> {
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let PrintMethod = "printUnsignedImm8";
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def uimm8 : Operand<i32> {
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let PrintMethod = "printUnsignedImm8";
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def simm5 : Operand<i32>;
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def vsplat_uimm1 : Operand<vAny> {
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let PrintMethod = "printUnsignedImm8";
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def vsplat_uimm2 : Operand<vAny> {
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let PrintMethod = "printUnsignedImm8";
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def vsplat_uimm3 : Operand<vAny> {
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let PrintMethod = "printUnsignedImm8";
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def vsplat_uimm4 : Operand<vAny> {
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let PrintMethod = "printUnsignedImm8";
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def vsplat_uimm5 : Operand<vAny> {
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let PrintMethod = "printUnsignedImm8";
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def vsplat_uimm6 : Operand<vAny> {
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let PrintMethod = "printUnsignedImm8";
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def vsplat_uimm8 : Operand<vAny> {
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let PrintMethod = "printUnsignedImm8";
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def vsplat_simm5 : Operand<vAny>;
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def vsplat_simm10 : Operand<vAny>;
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def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
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def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractSExt node:$vec, node:$idx, i8)>;
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def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractSExt node:$vec, node:$idx, i16)>;
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def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractSExt node:$vec, node:$idx, i32)>;
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def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractSExt node:$vec, node:$idx, i64)>;
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def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractZExt node:$vec, node:$idx, i8)>;
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def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractZExt node:$vec, node:$idx, i16)>;
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def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractZExt node:$vec, node:$idx, i32)>;
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def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
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(MipsVExtractZExt node:$vec, node:$idx, i64)>;
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def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
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(v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
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def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
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(v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
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def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
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(v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
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def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
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(v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
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def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
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(v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
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def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
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(v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
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def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
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(v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
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def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
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(v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
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class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
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PatFrag<(ops node:$lhs, node:$rhs),
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(ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
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// ISD::SETFALSE cannot occur
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def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
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def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
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def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
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def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
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def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
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def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
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def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
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def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
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def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
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def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
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def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
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def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
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def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
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def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
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def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
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def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
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def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
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def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
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def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
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def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
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def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
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def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
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def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
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def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
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def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
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def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
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def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
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def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
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// ISD::SETTRUE cannot occur
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// ISD::SETFALSE2 cannot occur
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// ISD::SETTRUE2 cannot occur
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class vsetcc_type<ValueType ResTy, CondCode CC> :
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PatFrag<(ops node:$lhs, node:$rhs),
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(ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
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def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
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def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
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def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
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def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
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def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
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def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
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def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
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def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
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def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
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def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
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def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
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def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
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def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
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def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
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def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
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def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
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def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
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def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
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def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
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def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
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def vsplati8 : PatFrag<(ops node:$e0),
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(v16i8 (build_vector node:$e0, node:$e0,
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node:$e0, node:$e0))>;
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def vsplati16 : PatFrag<(ops node:$e0),
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(v8i16 (build_vector node:$e0, node:$e0,
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node:$e0, node:$e0))>;
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def vsplati32 : PatFrag<(ops node:$e0),
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(v4i32 (build_vector node:$e0, node:$e0,
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node:$e0, node:$e0))>;
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def vsplati64 : PatFrag<(ops node:$e0),
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(v2i64 (build_vector node:$e0, node:$e0))>;
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def vsplatf32 : PatFrag<(ops node:$e0),
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(v4f32 (build_vector node:$e0, node:$e0,
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node:$e0, node:$e0))>;
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def vsplatf64 : PatFrag<(ops node:$e0),
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(v2f64 (build_vector node:$e0, node:$e0))>;
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def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
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(MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
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def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
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(MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
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def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
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(MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
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def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
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(MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>;
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class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
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SDNodeXForm xform = NOOP_SDNodeXForm>
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: PatLeaf<frag, pred, xform> {
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Operand OpClass = opclass;
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class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
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list<SDNode> roots = [],
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list<SDNodeProperty> props = []> :
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ComplexPattern<ty, numops, fn, roots, props> {
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Operand OpClass = opclass;
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def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
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[build_vector, bitconvert]>;
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def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
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[build_vector, bitconvert]>;
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def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
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[build_vector, bitconvert]>;
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def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
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[build_vector, bitconvert]>;
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def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
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[build_vector, bitconvert]>;
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def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
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[build_vector, bitconvert]>;
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def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
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[build_vector, bitconvert]>;
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def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
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[build_vector, bitconvert]>;
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def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
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[build_vector, bitconvert]>;
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def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
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[build_vector, bitconvert]>;
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def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
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[build_vector, bitconvert]>;
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def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
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[build_vector, bitconvert]>;
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def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
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[build_vector, bitconvert]>;
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def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
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[build_vector, bitconvert]>;
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def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
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[build_vector, bitconvert]>;
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def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
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[build_vector, bitconvert]>;
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// Any build_vector that is a constant splat with a value that is an exact
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def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
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[build_vector, bitconvert]>;
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// Any build_vector that is a constant splat with a value that is the bitwise
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// inverse of an exact power of 2
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def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
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[build_vector, bitconvert]>;
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// Any build_vector that is a constant splat with only a consecutive sequence
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// of left-most bits set.
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def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
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[build_vector, bitconvert]>;
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// Any build_vector that is a constant splat with only a consecutive sequence
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// of right-most bits set.
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def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
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[build_vector, bitconvert]>;
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// Any build_vector that is a constant splat with a value that equals 1
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// FIXME: These should be a ComplexPattern but we can't use them because the
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// ISel generator requires the uses to have a name, but providing a name
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// causes other errors ("used in pattern but not operand list")
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def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
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EVT EltTy = N->getValueType(0).getVectorElementType();
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return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
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Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
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def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
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SDNode *BV = N->getOperand(0).getNode();
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EVT EltTy = N->getValueType(0).getVectorElementType();
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return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
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Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
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def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
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(and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
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def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
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(and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
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def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
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(and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
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def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
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(and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
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(bitconvert (v4i32 immAllOnesV))))>;
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def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
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(xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
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def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
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(xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
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def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
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(xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
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def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
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(xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
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def vbset_b : PatFrag<(ops node:$ws, node:$wt),
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(or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
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def vbset_h : PatFrag<(ops node:$ws, node:$wt),
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(or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
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def vbset_w : PatFrag<(ops node:$ws, node:$wt),
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(or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
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def vbset_d : PatFrag<(ops node:$ws, node:$wt),
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(or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
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def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
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(fsub node:$wd, (fmul node:$ws, node:$wt))>;
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def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
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(add node:$wd, (mul node:$ws, node:$wt))>;
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def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
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(sub node:$wd, (mul node:$ws, node:$wt))>;
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def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
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(fmul node:$ws, (fexp2 node:$wt))>;
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def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
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def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
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// Instruction encoding.
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class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
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class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
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class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
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class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
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class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
448
class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
449
class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
450
class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
452
class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
453
class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
454
class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
455
class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
457
class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
458
class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
459
class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
460
class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
462
class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
463
class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
464
class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
465
class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
467
class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
468
class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
469
class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
470
class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
472
class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
474
class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
476
class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
477
class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
478
class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
479
class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
481
class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
482
class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
483
class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
484
class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
486
class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
487
class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
488
class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
489
class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
491
class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
492
class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
493
class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
494
class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
496
class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
497
class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
498
class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
499
class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
501
class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
502
class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
503
class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
504
class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
506
class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
507
class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
508
class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
509
class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
511
class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
512
class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
513
class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
514
class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
516
class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
517
class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
518
class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
519
class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
521
class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
522
class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
523
class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
524
class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
526
class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
527
class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
528
class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
529
class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
531
class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
532
class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
533
class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
534
class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
536
class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
538
class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
540
class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
542
class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
544
class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
545
class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
546
class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
547
class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
549
class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
550
class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
551
class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
552
class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
554
class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
555
class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
556
class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
557
class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
559
class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
561
class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
563
class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
565
class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
566
class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
567
class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
568
class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
570
class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
571
class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
572
class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
573
class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
575
class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
576
class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
577
class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
578
class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
580
class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
582
class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
583
class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
584
class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
585
class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
587
class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
588
class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
589
class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
590
class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
592
class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
594
class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
595
class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
596
class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
597
class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
599
class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
600
class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
601
class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
602
class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
604
class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
605
class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
606
class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
607
class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
609
class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
610
class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
611
class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
612
class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
614
class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
615
class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
616
class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
617
class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
619
class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
620
class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
621
class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
622
class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
624
class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
625
class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
626
class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
627
class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
629
class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
630
class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
631
class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
632
class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
634
class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
635
class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
636
class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
637
class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
639
class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
640
class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
641
class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
642
class COPY_U_D_ENC : MSA_ELM_COPY_D_FMT<0b0011, 0b011001>;
644
class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
646
class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
647
class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
648
class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
649
class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
651
class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
652
class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
653
class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
654
class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
656
class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
657
class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
658
class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
660
class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
661
class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
662
class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
664
class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
665
class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
666
class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
668
class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
669
class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
670
class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
672
class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
673
class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
674
class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
676
class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
677
class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
678
class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
680
class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
681
class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
683
class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
684
class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
686
class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
687
class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
689
class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
690
class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
692
class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
693
class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
695
class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
696
class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
698
class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
699
class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
701
class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
702
class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
704
class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
705
class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
707
class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
708
class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
710
class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
711
class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
713
class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
714
class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
716
class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
717
class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
719
class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
720
class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
722
class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
723
class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
725
class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
726
class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
728
class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
729
class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
731
class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
732
class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
734
class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
735
class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
737
class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
738
class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
740
class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
741
class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
743
class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
744
class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
746
class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
747
class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
748
class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
749
class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>;
751
class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
752
class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
754
class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
755
class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
757
class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
758
class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
760
class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
761
class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
763
class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
764
class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
766
class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
767
class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
769
class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
770
class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
772
class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
773
class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
775
class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
776
class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
778
class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
779
class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
781
class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
782
class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
784
class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
785
class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
787
class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
788
class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
790
class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
791
class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
793
class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
794
class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
796
class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
797
class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
799
class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
800
class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
802
class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
803
class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
805
class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
806
class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
808
class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
809
class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
811
class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
812
class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
814
class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
815
class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
817
class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
818
class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
820
class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
821
class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
823
class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
824
class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
826
class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
827
class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
829
class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
830
class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
832
class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
833
class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
835
class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
836
class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
838
class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
839
class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
840
class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
842
class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
843
class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
844
class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
846
class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
847
class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
848
class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
850
class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
851
class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
852
class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
854
class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
855
class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
856
class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
857
class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
859
class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
860
class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
861
class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
862
class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
864
class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
865
class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
866
class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
867
class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
869
class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
870
class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
871
class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
872
class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
874
class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
875
class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
876
class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
877
class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
879
class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
880
class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
881
class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
882
class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
884
class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
885
class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
886
class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
887
class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
889
class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>;
890
class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>;
891
class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>;
892
class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>;
894
class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
895
class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>;
897
class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
898
class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
900
class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
901
class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
903
class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
904
class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
905
class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
906
class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
908
class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
909
class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
910
class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
911
class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
913
class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
914
class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
915
class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
916
class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
918
class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
919
class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
920
class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
921
class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
923
class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
924
class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
925
class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
926
class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
928
class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
929
class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
930
class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
931
class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
933
class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
934
class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
935
class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
936
class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
938
class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
939
class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
940
class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
941
class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
943
class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
944
class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
945
class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
946
class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
948
class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
949
class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
950
class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
951
class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
953
class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
954
class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
955
class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
956
class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
958
class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
959
class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
960
class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
961
class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
963
class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
964
class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
965
class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
966
class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
968
class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
970
class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
971
class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
973
class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
974
class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
976
class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
977
class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
978
class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
979
class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
981
class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
982
class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
984
class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
985
class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
987
class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
988
class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
989
class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
990
class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
992
class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
993
class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
994
class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
995
class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
997
class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
998
class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
999
class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
1000
class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
1002
class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
1004
class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
1006
class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
1008
class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
1010
class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
1011
class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
1012
class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
1013
class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
1015
class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
1016
class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
1017
class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
1018
class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
1020
class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
1021
class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
1022
class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
1023
class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
1025
class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
1026
class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
1027
class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
1028
class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
1030
class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
1031
class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
1032
class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
1033
class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
1035
class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
1036
class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
1037
class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
1039
class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
1040
class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
1041
class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
1042
class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
1044
class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
1045
class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
1046
class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
1047
class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
1049
class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
1050
class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
1051
class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
1052
class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1054
class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
1055
class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
1056
class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
1057
class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
1059
class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
1060
class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
1061
class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
1062
class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
1064
class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1065
class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1066
class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1067
class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
1069
class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
1070
class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
1071
class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
1072
class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1074
class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
1075
class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
1076
class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
1077
class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
1079
class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
1080
class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
1081
class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
1082
class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
1084
class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
1085
class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
1086
class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
1087
class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
1089
class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
1090
class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
1091
class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
1092
class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1094
class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
1095
class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
1096
class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
1097
class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
1099
class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
1100
class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
1101
class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
1102
class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
1104
class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
1105
class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1106
class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1107
class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1109
class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
1110
class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
1111
class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
1112
class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
1114
class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1115
class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1116
class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1117
class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1119
class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1120
class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1121
class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1122
class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1124
class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1125
class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1126
class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1127
class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1129
class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1130
class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1131
class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1132
class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1134
class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1135
class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1136
class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1137
class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1139
class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1140
class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1141
class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1142
class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1144
class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1145
class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1146
class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1147
class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1149
class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1151
class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1153
// Instruction desc.
1154
class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1155
ComplexPattern Imm, RegisterOperand ROWD,
1156
RegisterOperand ROWS = ROWD,
1157
InstrItinClass itin = NoItinerary> {
1158
dag OutOperandList = (outs ROWD:$wd);
1159
dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1160
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1161
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1162
InstrItinClass Itinerary = itin;
1165
class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1166
ComplexPattern Imm, RegisterOperand ROWD,
1167
RegisterOperand ROWS = ROWD,
1168
InstrItinClass itin = NoItinerary> {
1169
dag OutOperandList = (outs ROWD:$wd);
1170
dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1171
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1172
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1173
InstrItinClass Itinerary = itin;
1176
class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1177
ComplexPattern Imm, RegisterOperand ROWD,
1178
RegisterOperand ROWS = ROWD,
1179
InstrItinClass itin = NoItinerary> {
1180
dag OutOperandList = (outs ROWD:$wd);
1181
dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1182
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1183
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1184
InstrItinClass Itinerary = itin;
1187
class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1188
ComplexPattern Imm, RegisterOperand ROWD,
1189
RegisterOperand ROWS = ROWD,
1190
InstrItinClass itin = NoItinerary> {
1191
dag OutOperandList = (outs ROWD:$wd);
1192
dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1193
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1194
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1195
InstrItinClass Itinerary = itin;
1198
// This class is deprecated and will be removed soon.
1199
class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1200
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1201
InstrItinClass itin = NoItinerary> {
1202
dag OutOperandList = (outs ROWD:$wd);
1203
dag InOperandList = (ins ROWS:$ws, uimm3:$m);
1204
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1205
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
1206
InstrItinClass Itinerary = itin;
1209
// This class is deprecated and will be removed soon.
1210
class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1211
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1212
InstrItinClass itin = NoItinerary> {
1213
dag OutOperandList = (outs ROWD:$wd);
1214
dag InOperandList = (ins ROWS:$ws, uimm4:$m);
1215
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1216
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
1217
InstrItinClass Itinerary = itin;
1220
// This class is deprecated and will be removed soon.
1221
class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1222
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1223
InstrItinClass itin = NoItinerary> {
1224
dag OutOperandList = (outs ROWD:$wd);
1225
dag InOperandList = (ins ROWS:$ws, uimm5:$m);
1226
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1227
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
1228
InstrItinClass Itinerary = itin;
1231
// This class is deprecated and will be removed soon.
1232
class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1233
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1234
InstrItinClass itin = NoItinerary> {
1235
dag OutOperandList = (outs ROWD:$wd);
1236
dag InOperandList = (ins ROWS:$ws, uimm6:$m);
1237
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1238
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
1239
InstrItinClass Itinerary = itin;
1242
class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1243
ComplexPattern Mask, RegisterOperand ROWD,
1244
RegisterOperand ROWS = ROWD,
1245
InstrItinClass itin = NoItinerary> {
1246
dag OutOperandList = (outs ROWD:$wd);
1247
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m);
1248
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1249
// Note that binsxi and vselect treat the condition operand the opposite
1250
// way to each other.
1251
// (vselect cond, if_set, if_clear)
1252
// (BSEL_V cond, if_clear, if_set)
1253
list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws),
1255
InstrItinClass Itinerary = itin;
1256
string Constraints = "$wd = $wd_in";
1259
class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1260
RegisterOperand ROWD,
1261
RegisterOperand ROWS = ROWD,
1262
InstrItinClass itin = NoItinerary> :
1263
MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>;
1265
class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1266
RegisterOperand ROWD,
1267
RegisterOperand ROWS = ROWD,
1268
InstrItinClass itin = NoItinerary> :
1269
MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>;
1271
class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1272
SplatComplexPattern SplatImm,
1273
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1274
InstrItinClass itin = NoItinerary> {
1275
dag OutOperandList = (outs ROWD:$wd);
1276
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1277
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1278
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1279
InstrItinClass Itinerary = itin;
1282
class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1283
ValueType VecTy, RegisterOperand ROD,
1284
RegisterOperand ROWS,
1285
InstrItinClass itin = NoItinerary> {
1286
dag OutOperandList = (outs ROD:$rd);
1287
dag InOperandList = (ins ROWS:$ws, uimm4_ptr:$n);
1288
string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1289
list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4Ptr:$n))];
1290
InstrItinClass Itinerary = itin;
1293
class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1294
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1295
InstrItinClass itin = NoItinerary> {
1296
dag OutOperandList = (outs ROWD:$wd);
1297
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, uimm4:$n);
1298
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1299
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1301
string Constraints = "$wd = $wd_in";
1302
InstrItinClass Itinerary = itin;
1305
class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1306
RegisterClass RCD, RegisterClass RCWS> :
1307
MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4_ptr:$n),
1308
[(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4Ptr:$n))]> {
1309
bit usesCustomInserter = 1;
1312
class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1313
SplatComplexPattern SplatImm, RegisterOperand ROWD,
1314
RegisterOperand ROWS = ROWD,
1315
InstrItinClass itin = NoItinerary> {
1316
dag OutOperandList = (outs ROWD:$wd);
1317
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1318
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1319
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1320
InstrItinClass Itinerary = itin;
1323
class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1324
SplatComplexPattern SplatImm, RegisterOperand ROWD,
1325
RegisterOperand ROWS = ROWD,
1326
InstrItinClass itin = NoItinerary> {
1327
dag OutOperandList = (outs ROWD:$wd);
1328
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1329
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1330
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1331
InstrItinClass Itinerary = itin;
1334
class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1335
RegisterOperand ROWS = ROWD,
1336
InstrItinClass itin = NoItinerary> {
1337
dag OutOperandList = (outs ROWD:$wd);
1338
dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1339
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1340
list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
1341
InstrItinClass Itinerary = itin;
1344
class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1345
InstrItinClass itin = NoItinerary> {
1346
dag OutOperandList = (outs ROWD:$wd);
1347
dag InOperandList = (ins vsplat_simm10:$s10);
1348
string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1349
// LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1350
list<dag> Pattern = [];
1351
bit hasSideEffects = 0;
1352
InstrItinClass Itinerary = itin;
1355
class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1356
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1357
InstrItinClass itin = NoItinerary> {
1358
dag OutOperandList = (outs ROWD:$wd);
1359
dag InOperandList = (ins ROWS:$ws);
1360
string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1361
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1362
InstrItinClass Itinerary = itin;
1365
class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1366
SDPatternOperator OpNode, RegisterOperand ROWD,
1367
RegisterOperand ROS = ROWD,
1368
InstrItinClass itin = NoItinerary> {
1369
dag OutOperandList = (outs ROWD:$wd);
1370
dag InOperandList = (ins ROS:$rs);
1371
string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1372
list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1373
InstrItinClass Itinerary = itin;
1376
class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
1377
RegisterClass RCWD, RegisterClass RCWS = RCWD> :
1378
MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1379
[(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1380
let usesCustomInserter = 1;
1383
class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1384
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1385
InstrItinClass itin = NoItinerary> {
1386
dag OutOperandList = (outs ROWD:$wd);
1387
dag InOperandList = (ins ROWS:$ws);
1388
string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1389
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1390
InstrItinClass Itinerary = itin;
1393
class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1394
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1395
RegisterOperand ROWT = ROWD,
1396
InstrItinClass itin = NoItinerary> {
1397
dag OutOperandList = (outs ROWD:$wd);
1398
dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1399
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1400
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1401
InstrItinClass Itinerary = itin;
1404
class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1405
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1406
RegisterOperand ROWT = ROWD,
1407
InstrItinClass itin = NoItinerary> {
1408
dag OutOperandList = (outs ROWD:$wd);
1409
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1410
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1411
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1413
string Constraints = "$wd = $wd_in";
1414
InstrItinClass Itinerary = itin;
1417
class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1418
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1419
InstrItinClass itin = NoItinerary> {
1420
dag OutOperandList = (outs ROWD:$wd);
1421
dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
1422
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1423
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
1424
InstrItinClass Itinerary = itin;
1427
class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1428
RegisterOperand ROWS = ROWD,
1429
RegisterOperand ROWT = ROWD,
1430
InstrItinClass itin = NoItinerary> {
1431
dag OutOperandList = (outs ROWD:$wd);
1432
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1433
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1434
list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1436
string Constraints = "$wd = $wd_in";
1437
InstrItinClass Itinerary = itin;
1440
class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1441
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1442
InstrItinClass itin = NoItinerary> {
1443
dag OutOperandList = (outs ROWD:$wd);
1444
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
1445
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1446
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1448
InstrItinClass Itinerary = itin;
1449
string Constraints = "$wd = $wd_in";
1452
class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1453
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1454
RegisterOperand ROWT = ROWD,
1455
InstrItinClass itin = NoItinerary> {
1456
dag OutOperandList = (outs ROWD:$wd);
1457
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1458
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1459
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1461
InstrItinClass Itinerary = itin;
1462
string Constraints = "$wd = $wd_in";
1465
class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1466
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1467
RegisterOperand ROWT = ROWD,
1468
InstrItinClass itin = NoItinerary> :
1469
MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1471
class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1472
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1473
RegisterOperand ROWT = ROWD,
1474
InstrItinClass itin = NoItinerary> :
1475
MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1477
class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1478
dag OutOperandList = (outs);
1479
dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1480
string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1481
list<dag> Pattern = [];
1482
InstrItinClass Itinerary = IIBranch;
1484
bit isTerminator = 1;
1485
bit hasDelaySlot = 1;
1486
list<Register> Defs = [AT];
1489
class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1490
RegisterOperand ROWD, RegisterOperand ROS,
1491
InstrItinClass itin = NoItinerary> {
1492
dag OutOperandList = (outs ROWD:$wd);
1493
dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6_ptr:$n);
1494
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1495
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1498
InstrItinClass Itinerary = itin;
1499
string Constraints = "$wd = $wd_in";
1502
class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1503
RegisterOperand ROWD, RegisterOperand ROFS> :
1504
MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6_ptr:$n, ROFS:$fs),
1505
[(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1506
immZExt6Ptr:$n))]> {
1507
bit usesCustomInserter = 1;
1508
string Constraints = "$wd = $wd_in";
1511
class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1512
RegisterOperand ROWD, RegisterOperand ROFS,
1513
RegisterOperand ROIdx> :
1514
MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs),
1515
[(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1517
bit usesCustomInserter = 1;
1518
string Constraints = "$wd = $wd_in";
1521
class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1522
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1523
InstrItinClass itin = NoItinerary> {
1524
dag OutOperandList = (outs ROWD:$wd);
1525
dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws, uimmz:$n2);
1526
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
1527
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1531
InstrItinClass Itinerary = itin;
1532
string Constraints = "$wd = $wd_in";
1535
class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1536
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1537
RegisterOperand ROWT = ROWD,
1538
InstrItinClass itin = NoItinerary> {
1539
dag OutOperandList = (outs ROWD:$wd);
1540
dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1541
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1542
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1543
InstrItinClass Itinerary = itin;
1546
class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1547
RegisterOperand ROWD,
1548
RegisterOperand ROWS = ROWD,
1549
InstrItinClass itin = NoItinerary> {
1550
dag OutOperandList = (outs ROWD:$wd);
1551
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1552
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1553
list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1555
InstrItinClass Itinerary = itin;
1558
class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1559
RegisterOperand ROWS = ROWD,
1560
RegisterOperand ROWT = ROWD> :
1561
MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1562
[(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1564
class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1566
class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1568
class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1570
class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1573
class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1574
MSA128BOpnd>, IsCommutable;
1575
class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1576
MSA128HOpnd>, IsCommutable;
1577
class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1578
MSA128WOpnd>, IsCommutable;
1579
class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1580
MSA128DOpnd>, IsCommutable;
1582
class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1583
MSA128BOpnd>, IsCommutable;
1584
class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1585
MSA128HOpnd>, IsCommutable;
1586
class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1587
MSA128WOpnd>, IsCommutable;
1588
class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1589
MSA128DOpnd>, IsCommutable;
1591
class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1592
MSA128BOpnd>, IsCommutable;
1593
class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1594
MSA128HOpnd>, IsCommutable;
1595
class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1596
MSA128WOpnd>, IsCommutable;
1597
class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1598
MSA128DOpnd>, IsCommutable;
1600
class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1601
class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1602
class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1603
class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1605
class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1607
class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1609
class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1611
class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1614
class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1615
class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1616
class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1617
class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1619
class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1622
class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1624
class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1626
class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1628
class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1631
class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1633
class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1635
class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1637
class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1640
class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1642
class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1644
class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1646
class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1649
class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1651
class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1653
class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1655
class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1658
class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1659
MSA128BOpnd>, IsCommutable;
1660
class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1661
MSA128HOpnd>, IsCommutable;
1662
class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1663
MSA128WOpnd>, IsCommutable;
1664
class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1665
MSA128DOpnd>, IsCommutable;
1667
class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1668
MSA128BOpnd>, IsCommutable;
1669
class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1670
MSA128HOpnd>, IsCommutable;
1671
class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1672
MSA128WOpnd>, IsCommutable;
1673
class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1674
MSA128DOpnd>, IsCommutable;
1676
class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1677
class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1678
class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1679
class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
1681
class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1683
class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1685
class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1687
class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1690
class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1692
class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1694
class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1696
class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1699
class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>;
1700
class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>;
1701
class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>;
1702
class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>;
1704
class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1706
class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1708
class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1710
class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1713
class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>;
1714
class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>;
1715
class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>;
1716
class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>;
1719
dag OutOperandList = (outs MSA128BOpnd:$wd);
1720
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1722
string AsmString = "bmnz.v\t$wd, $ws, $wt";
1723
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1725
MSA128BOpnd:$wd_in))];
1726
InstrItinClass Itinerary = NoItinerary;
1727
string Constraints = "$wd = $wd_in";
1730
class BMNZI_B_DESC {
1731
dag OutOperandList = (outs MSA128BOpnd:$wd);
1732
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1734
string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1735
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1737
MSA128BOpnd:$wd_in))];
1738
InstrItinClass Itinerary = NoItinerary;
1739
string Constraints = "$wd = $wd_in";
1743
dag OutOperandList = (outs MSA128BOpnd:$wd);
1744
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1746
string AsmString = "bmz.v\t$wd, $ws, $wt";
1747
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1750
InstrItinClass Itinerary = NoItinerary;
1751
string Constraints = "$wd = $wd_in";
1755
dag OutOperandList = (outs MSA128BOpnd:$wd);
1756
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1758
string AsmString = "bmzi.b\t$wd, $ws, $u8";
1759
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1762
InstrItinClass Itinerary = NoItinerary;
1763
string Constraints = "$wd = $wd_in";
1766
class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
1767
class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
1768
class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
1769
class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
1771
class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
1773
class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
1775
class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
1777
class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
1780
class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1781
class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1782
class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1783
class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1785
class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1788
dag OutOperandList = (outs MSA128BOpnd:$wd);
1789
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1791
string AsmString = "bsel.v\t$wd, $ws, $wt";
1792
// Note that vselect and BSEL_V treat the condition operand the opposite way
1794
// (vselect cond, if_set, if_clear)
1795
// (BSEL_V cond, if_clear, if_set)
1796
list<dag> Pattern = [(set MSA128BOpnd:$wd,
1797
(vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt,
1799
InstrItinClass Itinerary = NoItinerary;
1800
string Constraints = "$wd = $wd_in";
1803
class BSELI_B_DESC {
1804
dag OutOperandList = (outs MSA128BOpnd:$wd);
1805
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1807
string AsmString = "bseli.b\t$wd, $ws, $u8";
1808
// Note that vselect and BSEL_V treat the condition operand the opposite way
1810
// (vselect cond, if_set, if_clear)
1811
// (BSEL_V cond, if_clear, if_set)
1812
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1815
InstrItinClass Itinerary = NoItinerary;
1816
string Constraints = "$wd = $wd_in";
1819
class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
1820
class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
1821
class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
1822
class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
1824
class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1826
class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1828
class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1830
class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1833
class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1834
class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1835
class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1836
class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1838
class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1840
class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1842
class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1844
class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1846
class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1849
class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1851
class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1853
class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1855
class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1859
dag OutOperandList = (outs GPR32Opnd:$rd);
1860
dag InOperandList = (ins MSA128CROpnd:$cs);
1861
string AsmString = "cfcmsa\t$rd, $cs";
1862
InstrItinClass Itinerary = NoItinerary;
1863
bit hasSideEffects = 1;
1866
class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1867
class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1868
class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1869
class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1871
class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1872
class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1873
class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1874
class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1876
class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1877
vsplati8_simm5, MSA128BOpnd>;
1878
class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1879
vsplati16_simm5, MSA128HOpnd>;
1880
class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1881
vsplati32_simm5, MSA128WOpnd>;
1882
class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1883
vsplati64_simm5, MSA128DOpnd>;
1885
class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1886
vsplati8_uimm5, MSA128BOpnd>;
1887
class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1888
vsplati16_uimm5, MSA128HOpnd>;
1889
class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1890
vsplati32_uimm5, MSA128WOpnd>;
1891
class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1892
vsplati64_uimm5, MSA128DOpnd>;
1894
class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1895
class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1896
class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1897
class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1899
class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1900
class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1901
class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1902
class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1904
class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1905
vsplati8_simm5, MSA128BOpnd>;
1906
class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1907
vsplati16_simm5, MSA128HOpnd>;
1908
class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1909
vsplati32_simm5, MSA128WOpnd>;
1910
class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1911
vsplati64_simm5, MSA128DOpnd>;
1913
class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1914
vsplati8_uimm5, MSA128BOpnd>;
1915
class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1916
vsplati16_uimm5, MSA128HOpnd>;
1917
class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1918
vsplati32_uimm5, MSA128WOpnd>;
1919
class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1920
vsplati64_uimm5, MSA128DOpnd>;
1922
class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
1923
GPR32Opnd, MSA128BOpnd>;
1924
class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1925
GPR32Opnd, MSA128HOpnd>;
1926
class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1927
GPR32Opnd, MSA128WOpnd>;
1928
class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
1929
GPR64Opnd, MSA128DOpnd>;
1931
class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
1932
GPR32Opnd, MSA128BOpnd>;
1933
class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1934
GPR32Opnd, MSA128HOpnd>;
1935
class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1936
GPR32Opnd, MSA128WOpnd>;
1937
class COPY_U_D_DESC : MSA_COPY_DESC_BASE<"copy_u.d", vextract_zext_i64, v2i64,
1938
GPR64Opnd, MSA128DOpnd>;
1940
class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
1942
class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
1946
dag OutOperandList = (outs);
1947
dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1948
string AsmString = "ctcmsa\t$cd, $rs";
1949
InstrItinClass Itinerary = NoItinerary;
1950
bit hasSideEffects = 1;
1953
class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1954
class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1955
class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1956
class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1958
class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1959
class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1960
class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1961
class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1963
class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1964
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1966
class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1967
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1969
class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1970
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1973
class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1974
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1976
class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1977
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1979
class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1980
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1983
class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1984
MSA128HOpnd, MSA128BOpnd,
1985
MSA128BOpnd>, IsCommutable;
1986
class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1987
MSA128WOpnd, MSA128HOpnd,
1988
MSA128HOpnd>, IsCommutable;
1989
class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1990
MSA128DOpnd, MSA128WOpnd,
1991
MSA128WOpnd>, IsCommutable;
1993
class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1994
MSA128HOpnd, MSA128BOpnd,
1995
MSA128BOpnd>, IsCommutable;
1996
class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1997
MSA128WOpnd, MSA128HOpnd,
1998
MSA128HOpnd>, IsCommutable;
1999
class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
2000
MSA128DOpnd, MSA128WOpnd,
2001
MSA128WOpnd>, IsCommutable;
2003
class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
2004
MSA128HOpnd, MSA128BOpnd,
2006
class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
2007
MSA128WOpnd, MSA128HOpnd,
2009
class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
2010
MSA128DOpnd, MSA128WOpnd,
2013
class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
2014
MSA128HOpnd, MSA128BOpnd,
2016
class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
2017
MSA128WOpnd, MSA128HOpnd,
2019
class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
2020
MSA128DOpnd, MSA128WOpnd,
2023
class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
2025
class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
2028
class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
2030
class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
2033
class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
2035
class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
2038
class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
2040
class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
2043
class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
2044
class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
2046
class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
2047
class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
2049
class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
2051
class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
2054
class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
2056
class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
2059
class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
2061
class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
2064
class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
2066
class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
2069
class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
2071
class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
2074
class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
2076
class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
2079
class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
2081
class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
2084
class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
2085
class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
2087
class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
2088
MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2089
class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
2090
MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2092
// The fexp2.df instruction multiplies the first operand by 2 to the power of
2093
// the second operand. We therefore need a pseudo-insn in order to invent the
2094
// 1.0 when we only need to match ISD::FEXP2.
2095
class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
2096
class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
2097
let usesCustomInserter = 1 in {
2098
class FEXP2_W_1_PSEUDO_DESC :
2099
MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
2100
[(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
2101
class FEXP2_D_1_PSEUDO_DESC :
2102
MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
2103
[(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
2106
class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
2107
MSA128WOpnd, MSA128HOpnd>;
2108
class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
2109
MSA128DOpnd, MSA128WOpnd>;
2111
class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
2112
MSA128WOpnd, MSA128HOpnd>;
2113
class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
2114
MSA128DOpnd, MSA128WOpnd>;
2116
class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2117
class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2119
class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2120
class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2122
class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2123
MSA128WOpnd, MSA128HOpnd>;
2124
class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2125
MSA128DOpnd, MSA128WOpnd>;
2127
class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2128
MSA128WOpnd, MSA128HOpnd>;
2129
class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2130
MSA128DOpnd, MSA128WOpnd>;
2132
class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2133
MSA128BOpnd, GPR32Opnd>;
2134
class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2135
MSA128HOpnd, GPR32Opnd>;
2136
class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2137
MSA128WOpnd, GPR32Opnd>;
2138
class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
2139
MSA128DOpnd, GPR64Opnd>;
2141
class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
2143
class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
2146
class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2147
class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2149
class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2150
class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2152
class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2153
class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2155
class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2157
class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2160
class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2161
class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2163
class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2165
class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2168
class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
2169
class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
2171
class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2172
class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2174
class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2175
class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2177
class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2178
class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2180
class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2182
class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2185
class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2186
class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2188
class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2189
class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2191
class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2192
class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2194
class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2195
class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2197
class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2198
class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2200
class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2201
class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2203
class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2204
class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2206
class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2207
class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2209
class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2211
class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2214
class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2216
class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2219
class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2221
class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2224
class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2226
class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2229
class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2231
class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2234
class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2236
class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2239
class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2241
class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2244
class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2245
MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2246
class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2247
MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2249
class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2251
class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2254
class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2256
class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2259
class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2260
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2261
class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2262
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2263
class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2264
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2266
class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2267
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2268
class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2269
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2270
class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2271
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2273
class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2274
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2275
class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2276
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2277
class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2278
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2280
class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2281
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2282
class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2283
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2284
class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2285
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2287
class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2288
class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2289
class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2290
class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2292
class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2293
class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2294
class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2295
class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2297
class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2298
class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2299
class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2300
class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2302
class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2303
class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2304
class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2305
class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2307
class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
2308
MSA128BOpnd, GPR32Opnd>;
2309
class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
2310
MSA128HOpnd, GPR32Opnd>;
2311
class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
2312
MSA128WOpnd, GPR32Opnd>;
2313
class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64,
2314
MSA128DOpnd, GPR64Opnd>;
2316
class INSERT_B_VIDX_PSEUDO_DESC :
2317
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>;
2318
class INSERT_H_VIDX_PSEUDO_DESC :
2319
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>;
2320
class INSERT_W_VIDX_PSEUDO_DESC :
2321
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>;
2322
class INSERT_D_VIDX_PSEUDO_DESC :
2323
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;
2325
class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2326
MSA128WOpnd, FGR32Opnd>;
2327
class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2328
MSA128DOpnd, FGR64Opnd>;
2330
class INSERT_FW_VIDX_PSEUDO_DESC :
2331
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>;
2332
class INSERT_FD_VIDX_PSEUDO_DESC :
2333
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>;
2335
class INSERT_B_VIDX64_PSEUDO_DESC :
2336
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>;
2337
class INSERT_H_VIDX64_PSEUDO_DESC :
2338
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>;
2339
class INSERT_W_VIDX64_PSEUDO_DESC :
2340
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>;
2341
class INSERT_D_VIDX64_PSEUDO_DESC :
2342
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
2344
class INSERT_FW_VIDX64_PSEUDO_DESC :
2345
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
2346
class INSERT_FD_VIDX64_PSEUDO_DESC :
2347
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
2349
class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8,
2351
class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16,
2353
class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32,
2355
class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64,
2358
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2359
ValueType TyNode, RegisterOperand ROWD,
2360
Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
2361
InstrItinClass itin = NoItinerary> {
2362
dag OutOperandList = (outs ROWD:$wd);
2363
dag InOperandList = (ins MemOpnd:$addr);
2364
string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2365
list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2366
InstrItinClass Itinerary = itin;
2367
string DecoderMethod = "DecodeMSA128Mem";
2370
class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2371
class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2372
class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2373
class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2375
class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2376
class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2377
class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2378
class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2380
class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD,
2381
RegisterOperand RORS = RORD, RegisterOperand RORT = RORD,
2382
InstrItinClass itin = NoItinerary > {
2383
dag OutOperandList = (outs RORD:$rd);
2384
dag InOperandList = (ins RORS:$rs, RORT:$rt, LSAImm:$sa);
2385
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa");
2386
list<dag> Pattern = [(set RORD:$rd, (add RORT:$rt,
2388
immZExt2Lsa:$sa)))];
2389
InstrItinClass Itinerary = itin;
2392
class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd>;
2393
class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd>;
2395
class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2397
class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2400
class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2402
class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2405
class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2406
class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2407
class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2408
class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2410
class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2411
class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2412
class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2413
class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2415
class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
2416
class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
2417
class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
2418
class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
2420
class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
2421
class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
2422
class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
2423
class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
2425
class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
2427
class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
2429
class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
2431
class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
2434
class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
2436
class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
2438
class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
2440
class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
2443
class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2444
class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2445
class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2446
class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2448
class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
2449
class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
2450
class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
2451
class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
2453
class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
2454
class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
2455
class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
2456
class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
2458
class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
2460
class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
2462
class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
2464
class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
2467
class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
2469
class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
2471
class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
2473
class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
2476
class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2477
class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2478
class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2479
class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2481
class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2482
class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2483
class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2484
class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2487
dag OutOperandList = (outs MSA128BOpnd:$wd);
2488
dag InOperandList = (ins MSA128BOpnd:$ws);
2489
string AsmString = "move.v\t$wd, $ws";
2490
list<dag> Pattern = [];
2491
InstrItinClass Itinerary = NoItinerary;
2494
class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2496
class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2499
class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2501
class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2504
class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2505
class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2506
class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2507
class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2509
class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2511
class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2514
class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2516
class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2519
class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2520
class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2521
class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2522
class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2524
class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2525
class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2526
class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2527
class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2529
class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2530
class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2531
class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2532
class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2534
class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2535
class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2536
class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2537
class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2539
class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2542
class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2543
class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2544
class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2545
class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2547
class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2549
class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2550
class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2551
class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2552
class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2554
class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2555
class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2556
class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2557
class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2559
class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2560
class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2561
class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2562
class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2564
class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
2566
class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
2568
class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
2570
class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
2573
class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
2575
class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
2577
class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
2579
class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
2582
class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2583
class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2584
class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2586
class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2587
class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2588
class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2589
class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2591
class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
2593
class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
2595
class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
2597
class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
2600
class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2601
class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2602
class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2603
class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2605
class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2607
class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2609
class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2611
class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2614
class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2616
class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2618
class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2620
class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2623
class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2625
class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2627
class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2629
class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2632
class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2633
class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2634
class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2635
class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2637
class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2639
class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2641
class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2643
class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2646
class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2647
class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2648
class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2649
class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2651
class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b,
2653
class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h,
2655
class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w,
2657
class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d,
2660
class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2661
class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2662
class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2663
class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2665
class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2667
class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2669
class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2671
class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2674
class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2675
class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2676
class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2677
class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2679
class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b,
2681
class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h,
2683
class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w,
2685
class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d,
2688
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2689
ValueType TyNode, RegisterOperand ROWD,
2690
Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
2691
InstrItinClass itin = NoItinerary> {
2692
dag OutOperandList = (outs);
2693
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2694
string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2695
list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2696
InstrItinClass Itinerary = itin;
2697
string DecoderMethod = "DecodeMSA128Mem";
2700
class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2701
class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2702
class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2703
class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2705
class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2707
class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2709
class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2711
class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2714
class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2716
class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2718
class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2720
class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2723
class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2725
class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2727
class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2729
class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2732
class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2734
class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2736
class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2738
class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2741
class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2742
class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2743
class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2744
class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2746
class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2748
class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2750
class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2752
class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2755
class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2756
class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2757
class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2758
class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2760
class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2761
class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2762
class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2763
class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2765
class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2768
// Instruction defs.
2769
def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2770
def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2771
def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2772
def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2774
def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2775
def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2776
def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2777
def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2779
def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2780
def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2781
def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2782
def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2784
def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2785
def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2786
def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2787
def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2789
def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2790
def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2791
def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2792
def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2794
def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2795
def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2796
def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2797
def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2799
def AND_V : AND_V_ENC, AND_V_DESC;
2800
def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2801
PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2804
def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2805
PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2808
def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2809
PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2813
def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2815
def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2816
def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2817
def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2818
def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2820
def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2821
def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2822
def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2823
def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2825
def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2826
def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2827
def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2828
def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2830
def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2831
def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2832
def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2833
def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2835
def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2836
def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2837
def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2838
def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2840
def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2841
def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2842
def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2843
def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2845
def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2846
def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2847
def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2848
def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2850
def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2851
def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2852
def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2853
def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2855
def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2856
def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2857
def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2858
def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2860
def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2861
def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2862
def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2863
def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2865
def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2866
def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2867
def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2868
def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2870
def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2871
def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2872
def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2873
def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2875
def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2877
def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2879
def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2881
def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2883
def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2884
def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2885
def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2886
def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2888
def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2889
def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2890
def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2891
def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2893
def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2894
def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2895
def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2896
def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2898
def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2900
def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2902
class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2903
MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2904
[(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>,
2905
// Note that vselect and BSEL_V treat the condition operand the opposite way
2907
// (vselect cond, if_set, if_clear)
2908
// (BSEL_V cond, if_clear, if_set)
2909
PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2910
MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2911
let Constraints = "$wd_in = $wd";
2914
def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2915
def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2916
def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2917
def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2918
def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2920
def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2922
def BSET_B : BSET_B_ENC, BSET_B_DESC;
2923
def BSET_H : BSET_H_ENC, BSET_H_DESC;
2924
def BSET_W : BSET_W_ENC, BSET_W_DESC;
2925
def BSET_D : BSET_D_ENC, BSET_D_DESC;
2927
def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2928
def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2929
def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2930
def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2932
def BZ_B : BZ_B_ENC, BZ_B_DESC;
2933
def BZ_H : BZ_H_ENC, BZ_H_DESC;
2934
def BZ_W : BZ_W_ENC, BZ_W_DESC;
2935
def BZ_D : BZ_D_ENC, BZ_D_DESC;
2937
def BZ_V : BZ_V_ENC, BZ_V_DESC;
2939
def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2940
def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2941
def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2942
def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2944
def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2945
def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2946
def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2947
def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2949
def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2951
def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2952
def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2953
def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2954
def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2956
def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2957
def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2958
def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2959
def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2961
def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2962
def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2963
def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2964
def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2966
def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2967
def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2968
def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2969
def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2971
def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2972
def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2973
def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2974
def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2976
def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2977
def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2978
def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2979
def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2981
def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2982
def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2983
def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2984
def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2986
def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2987
def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2988
def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2989
def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2991
def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2992
def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2993
def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2994
def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC;
2996
def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2997
def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2998
def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
2999
def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC;
3001
def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
3002
def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
3004
def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
3006
def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
3007
def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
3008
def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
3009
def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
3011
def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
3012
def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
3013
def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
3014
def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
3016
def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
3017
def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
3018
def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
3020
def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
3021
def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
3022
def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
3024
def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
3025
def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
3026
def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
3028
def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
3029
def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
3030
def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
3032
def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
3033
def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
3034
def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
3036
def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
3037
def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
3038
def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
3040
def FADD_W : FADD_W_ENC, FADD_W_DESC;
3041
def FADD_D : FADD_D_ENC, FADD_D_DESC;
3043
def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
3044
def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
3046
def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
3047
def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
3049
def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
3050
def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
3052
def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
3053
def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
3055
def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
3056
def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
3058
def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
3059
def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
3061
def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
3062
def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
3064
def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
3065
def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
3067
def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
3068
def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
3070
def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
3071
def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
3073
def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
3074
def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
3076
def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
3077
def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
3079
def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
3080
def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
3082
def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
3083
def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
3085
def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
3086
def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
3087
def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
3088
def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
3090
def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
3091
def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
3093
def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
3094
def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
3096
def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
3097
def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
3099
def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
3100
def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
3102
def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
3103
def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
3105
def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
3106
def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
3108
def FILL_B : FILL_B_ENC, FILL_B_DESC;
3109
def FILL_H : FILL_H_ENC, FILL_H_DESC;
3110
def FILL_W : FILL_W_ENC, FILL_W_DESC;
3111
def FILL_D : FILL_D_ENC, FILL_D_DESC;
3112
def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3113
def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3115
def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3116
def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3118
def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3119
def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3121
def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3122
def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3124
def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3125
def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3127
def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3128
def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3130
def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3131
def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3133
def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3134
def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3136
def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3137
def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3139
def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3140
def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3142
def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3143
def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3145
def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3146
def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3148
def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3149
def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3151
def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3152
def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3154
def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3155
def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3157
def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3158
def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3160
def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3161
def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3163
def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3164
def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3166
def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3167
def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3169
def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3170
def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3172
def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3173
def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3175
def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3176
def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3178
def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3179
def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3181
def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3182
def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3184
def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3185
def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3187
def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3188
def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3190
def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3191
def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3193
def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3194
def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3196
def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3197
def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3199
def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3200
def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3202
def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3203
def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3204
def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3206
def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3207
def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3208
def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3210
def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3211
def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3212
def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3214
def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3215
def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3216
def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3218
def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3219
def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3220
def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3221
def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3223
def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3224
def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3225
def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3226
def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3228
def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3229
def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3230
def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3231
def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3233
def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3234
def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3235
def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3236
def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3238
def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3239
def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3240
def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3241
def INSERT_D : INSERT_D_ENC, INSERT_D_DESC;
3243
// INSERT_FW_PSEUDO defined after INSVE_W
3244
// INSERT_FD_PSEUDO defined after INSVE_D
3246
// There is a fourth operand that is not present in the encoding. Use a
3247
// custom decoder to get a chance to add it.
3248
let DecoderMethod = "DecodeINSVE_DF" in {
3249
def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3250
def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3251
def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3252
def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3255
def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3256
def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3258
def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
3259
def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
3260
def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
3261
def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
3262
def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
3263
def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
3265
def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC;
3266
def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC;
3267
def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC;
3268
def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC;
3269
def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC;
3270
def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC;
3272
def LD_B: LD_B_ENC, LD_B_DESC;
3273
def LD_H: LD_H_ENC, LD_H_DESC;
3274
def LD_W: LD_W_ENC, LD_W_DESC;
3275
def LD_D: LD_D_ENC, LD_D_DESC;
3277
def LDI_B : LDI_B_ENC, LDI_B_DESC;
3278
def LDI_H : LDI_H_ENC, LDI_H_DESC;
3279
def LDI_W : LDI_W_ENC, LDI_W_DESC;
3280
def LDI_D : LDI_D_ENC, LDI_D_DESC;
3282
def LSA : LSA_ENC, LSA_DESC;
3283
def DLSA : DLSA_ENC, DLSA_DESC;
3285
def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3286
def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3288
def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3289
def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3291
def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3292
def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3293
def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3294
def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3296
def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3297
def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3298
def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3299
def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3301
def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3302
def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3303
def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3304
def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3306
def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3307
def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3308
def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3309
def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3311
def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3312
def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3313
def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3314
def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3316
def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3317
def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3318
def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3319
def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3321
def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3322
def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3323
def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3324
def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3326
def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3327
def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3328
def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3329
def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3331
def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3332
def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3333
def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3334
def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3336
def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3337
def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3338
def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3339
def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3341
def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3342
def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3343
def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3344
def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3346
def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3347
def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3348
def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3349
def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3351
def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3352
def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3353
def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3354
def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3356
def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3358
def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3359
def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3361
def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3362
def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3364
def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3365
def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3366
def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3367
def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3369
def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3370
def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3372
def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3373
def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3375
def MULV_B : MULV_B_ENC, MULV_B_DESC;
3376
def MULV_H : MULV_H_ENC, MULV_H_DESC;
3377
def MULV_W : MULV_W_ENC, MULV_W_DESC;
3378
def MULV_D : MULV_D_ENC, MULV_D_DESC;
3380
def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3381
def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3382
def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3383
def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3385
def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3386
def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3387
def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3388
def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3390
def NOR_V : NOR_V_ENC, NOR_V_DESC;
3391
def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3392
PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3395
def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3396
PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3399
def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3400
PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3404
def NORI_B : NORI_B_ENC, NORI_B_DESC;
3406
def OR_V : OR_V_ENC, OR_V_DESC;
3407
def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3408
PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3411
def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3412
PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3415
def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3416
PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3420
def ORI_B : ORI_B_ENC, ORI_B_DESC;
3422
def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3423
def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3424
def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3425
def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3427
def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3428
def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3429
def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3430
def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3432
def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3433
def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3434
def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3435
def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3437
def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3438
def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3439
def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3440
def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3442
def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3443
def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3444
def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3445
def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3447
def SHF_B : SHF_B_ENC, SHF_B_DESC;
3448
def SHF_H : SHF_H_ENC, SHF_H_DESC;
3449
def SHF_W : SHF_W_ENC, SHF_W_DESC;
3451
def SLD_B : SLD_B_ENC, SLD_B_DESC;
3452
def SLD_H : SLD_H_ENC, SLD_H_DESC;
3453
def SLD_W : SLD_W_ENC, SLD_W_DESC;
3454
def SLD_D : SLD_D_ENC, SLD_D_DESC;
3456
def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3457
def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3458
def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3459
def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3461
def SLL_B : SLL_B_ENC, SLL_B_DESC;
3462
def SLL_H : SLL_H_ENC, SLL_H_DESC;
3463
def SLL_W : SLL_W_ENC, SLL_W_DESC;
3464
def SLL_D : SLL_D_ENC, SLL_D_DESC;
3466
def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3467
def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3468
def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3469
def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3471
def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3472
def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3473
def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3474
def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3476
def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3477
def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3478
def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3479
def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3481
def SRA_B : SRA_B_ENC, SRA_B_DESC;
3482
def SRA_H : SRA_H_ENC, SRA_H_DESC;
3483
def SRA_W : SRA_W_ENC, SRA_W_DESC;
3484
def SRA_D : SRA_D_ENC, SRA_D_DESC;
3486
def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3487
def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3488
def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3489
def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3491
def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3492
def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3493
def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3494
def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3496
def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3497
def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3498
def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3499
def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3501
def SRL_B : SRL_B_ENC, SRL_B_DESC;
3502
def SRL_H : SRL_H_ENC, SRL_H_DESC;
3503
def SRL_W : SRL_W_ENC, SRL_W_DESC;
3504
def SRL_D : SRL_D_ENC, SRL_D_DESC;
3506
def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3507
def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3508
def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3509
def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3511
def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3512
def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3513
def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3514
def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3516
def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3517
def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3518
def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3519
def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3521
def ST_B: ST_B_ENC, ST_B_DESC;
3522
def ST_H: ST_H_ENC, ST_H_DESC;
3523
def ST_W: ST_W_ENC, ST_W_DESC;
3524
def ST_D: ST_D_ENC, ST_D_DESC;
3526
def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3527
def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3528
def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3529
def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3531
def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3532
def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3533
def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3534
def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3536
def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3537
def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3538
def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3539
def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3541
def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3542
def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3543
def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3544
def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3546
def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3547
def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3548
def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3549
def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3551
def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3552
def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3553
def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3554
def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3556
def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3557
def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3558
def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3559
def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3561
def XOR_V : XOR_V_ENC, XOR_V_DESC;
3562
def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3563
PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3566
def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3567
PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3570
def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3571
PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3575
def XORI_B : XORI_B_ENC, XORI_B_DESC;
3578
class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3579
Pat<pattern, result>, Requires<pred>;
3581
def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3582
(COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3584
def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>;
3585
def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>;
3586
def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>;
3588
def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr),
3589
(ST_H MSA128H:$ws, addrimm10:$addr)>;
3590
def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr),
3591
(ST_W MSA128W:$ws, addrimm10:$addr)>;
3592
def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr),
3593
(ST_D MSA128D:$ws, addrimm10:$addr)>;
3595
class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3596
RegisterOperand ROWS = ROWD,
3597
InstrItinClass itin = NoItinerary> :
3598
MSAPseudo<(outs ROWD:$wd),
3600
[(set ROWD:$wd, (fabs ROWS:$ws))]> {
3601
InstrItinClass Itinerary = itin;
3603
def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3604
PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3606
def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3607
PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3610
class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3611
RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3612
MSAPat<(DstVT (bitconvert SrcVT:$src)),
3613
(COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3615
// These are endian-independent because the element size doesnt change
3616
def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3617
def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3618
def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3619
def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3620
def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3621
def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3623
// Little endian bitcasts are always no-ops
3624
def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3625
def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3626
def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3627
def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3628
def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3629
def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3631
def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3632
def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3633
def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3634
def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3635
def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3637
def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3638
def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3639
def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3640
def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3641
def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3643
def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3644
def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3645
def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3646
def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3647
def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3649
def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3650
def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3651
def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3652
def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3653
def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3655
def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3656
def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3657
def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3658
def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3659
def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3661
// Big endian bitcasts expand to shuffle instructions.
3662
// This is because bitcast is defined to be a store/load sequence and the
3663
// vector store/load instructions are mixed-endian with respect to the vector
3664
// as a whole (little endian with respect to element order, but big endian
3667
class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3668
RegisterClass DstRC, MSAInst Insn,
3669
RegisterClass ViaRC> :
3670
MSAPat<(DstVT (bitconvert SrcVT:$src)),
3671
(COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3675
class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3676
RegisterClass DstRC, MSAInst Insn,
3677
RegisterClass ViaRC> :
3678
MSAPat<(DstVT (bitconvert SrcVT:$src)),
3679
(COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3683
class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3684
RegisterClass DstRC> :
3685
MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3687
class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3688
RegisterClass DstRC> :
3689
MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3691
class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3692
RegisterClass DstRC> :
3693
MSAPat<(DstVT (bitconvert SrcVT:$src)),
3697
(SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3702
class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3703
RegisterClass DstRC> :
3704
MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3706
class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3707
RegisterClass DstRC> :
3708
MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3710
class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3711
RegisterClass DstRC> :
3712
MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3714
def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3715
def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3716
def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3717
def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3718
def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3719
def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3721
def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3722
def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3723
def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3724
def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3725
def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3727
def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3728
def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3729
def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3730
def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3731
def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3733
def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3734
def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3735
def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3736
def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3737
def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3739
def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3740
def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3741
def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3742
def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3743
def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3745
def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3746
def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3747
def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3748
def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3749
def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3751
def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3752
def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3753
def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3754
def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3755
def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3757
// Pseudos used to implement BNZ.df, and BZ.df
3759
class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3761
InstrItinClass itin = NoItinerary> :
3762
MipsPseudo<(outs GPR32:$dst),
3764
[(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3765
bit usesCustomInserter = 1;
3768
def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
3769
MSA128B, NoItinerary>;
3770
def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
3771
MSA128H, NoItinerary>;
3772
def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
3773
MSA128W, NoItinerary>;
3774
def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
3775
MSA128D, NoItinerary>;
3776
def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
3777
MSA128B, NoItinerary>;
3779
def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
3780
MSA128B, NoItinerary>;
3781
def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
3782
MSA128H, NoItinerary>;
3783
def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
3784
MSA128W, NoItinerary>;
3785
def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
3786
MSA128D, NoItinerary>;
3787
def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
3788
MSA128B, NoItinerary>;
3790
// Vector extraction with variable index
3791
def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
3792
(SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3796
def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
3797
(SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3801
def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
3802
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3806
def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
3807
(COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3810
GPR64), [HasMSA, IsGP64bit]>;
3812
def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
3813
(SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3817
def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
3818
(SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3822
def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
3823
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3827
def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
3828
(COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3831
GPR64), [HasMSA, IsGP64bit]>;
3833
def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
3834
(f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
3837
def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
3838
(f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
3842
// Vector extraction with variable index (N64 ABI)
3844
(i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)),
3845
(SRA (COPY_TO_REGCLASS
3846
(i32 (EXTRACT_SUBREG
3849
(i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3854
(i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)),
3855
(SRA (COPY_TO_REGCLASS
3856
(i32 (EXTRACT_SUBREG
3859
(i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3864
(i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)),
3866
(i32 (EXTRACT_SUBREG
3869
(i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3873
(i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)),
3875
(i64 (EXTRACT_SUBREG
3877
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3879
GPR64), [HasMSA, IsGP64bit]>;
3882
(i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)),
3883
(SRL (COPY_TO_REGCLASS
3884
(i32 (EXTRACT_SUBREG
3887
(i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3892
(i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)),
3893
(SRL (COPY_TO_REGCLASS
3894
(i32 (EXTRACT_SUBREG
3897
(i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3902
(i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)),
3904
(i32 (EXTRACT_SUBREG
3906
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3910
(i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)),
3912
(i64 (EXTRACT_SUBREG
3914
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3917
[HasMSA, IsGP64bit]>;
3920
(f32 (vector_extract v4f32:$ws, i64:$idx)),
3921
(f32 (EXTRACT_SUBREG
3923
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3926
(f64 (vector_extract v2f64:$ws, i64:$idx)),
3927
(f64 (EXTRACT_SUBREG
3929
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),