1
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math %s -o - \
7
; Disable this optimization unless we know one of them is zero.
8
define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
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; CHECK: vldr [[S0:s[0-9]+]],
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; CHECK: vldr [[S1:s[0-9]+]],
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; CHECK: vcmpe.f32 [[S1]], [[S0]]
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; CHECK: vmrs APSR_nzcv, fpscr
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%0 = load float, float* %a
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%1 = load float, float* %b
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%2 = fcmp une float %0, %1
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br i1 %2, label %bb1, label %bb2
30
; If one side is zero, the other size sign bit is masked off to allow
32
define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
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; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
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; CHECK: bfc [[REG2]], #31, #1
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; CHECK: cmp [[REG1]], #0
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; CHECK: cmpeq [[REG2]], #0
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; CHECK-NOT: vcmpe.f32
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%0 = load double, double* %a
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%1 = fcmp oeq double %0, 0.000000e+00
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br i1 %1, label %bb1, label %bb2
57
define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
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; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
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; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
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; CHECK: tst [[REG3]], [[REG4]]
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; CHECK-NOT: vcmpe.f32
67
%0 = load float, float* %a
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%1 = fcmp oeq float %0, 0.000000e+00
69
br i1 %1, label %bb1, label %bb2