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//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This implements the TargetLowering class.
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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/// NOTE: The TargetMachine owns TLOF.
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TargetLowering::TargetLowering(const TargetMachine &tm)
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: TargetLoweringBase(tm) {}
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const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
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/// Check whether a given call node is in tail position within its function. If
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/// so, it sets Chain to the input chain of the tail call.
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bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
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SDValue &Chain) const {
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const Function *F = DAG.getMachineFunction().getFunction();
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// Conservatively require the attributes of the call to match those of
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// the return. Ignore noalias because it doesn't affect the call sequence.
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AttributeSet CallerAttrs = F->getAttributes();
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if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
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.removeAttribute(Attribute::NoAlias).hasAttributes())
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// It's not safe to eliminate the sign / zero extension of the return value.
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if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
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CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
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// Check if the only use is a function return node.
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return isUsedByReturnOnly(Node, Chain);
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/// \brief Set CallLoweringInfo attribute flags based on a call instruction
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/// and called function attributes.
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void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
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isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
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isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
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isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
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isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
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isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
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isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
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isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
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isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
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Alignment = CS->getParamAlignment(AttrIdx);
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/// Generate a libcall taking the given operands as arguments and returning a
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/// result of type RetVT.
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std::pair<SDValue, SDValue>
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TargetLowering::makeLibCall(SelectionDAG &DAG,
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RTLIB::Libcall LC, EVT RetVT,
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const SDValue *Ops, unsigned NumOps,
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bool isSigned, SDLoc dl,
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bool isReturnValueUsed) const {
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TargetLowering::ArgListTy Args;
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TargetLowering::ArgListEntry Entry;
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for (unsigned i = 0; i != NumOps; ++i) {
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Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
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Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
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Entry.isZExt = !shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
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Args.push_back(Entry);
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if (LC == RTLIB::UNKNOWN_LIBCALL)
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report_fatal_error("Unsupported library call operation!");
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SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
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getPointerTy(DAG.getDataLayout()));
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Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
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TargetLowering::CallLoweringInfo CLI(DAG);
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bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
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CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
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.setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
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.setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
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.setSExtResult(signExtend).setZExtResult(!signExtend);
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return LowerCallTo(CLI);
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/// SoftenSetCCOperands - Soften the operands of a comparison. This code is
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/// shared among BR_CC, SELECT_CC, and SETCC handlers.
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void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
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SDValue &NewLHS, SDValue &NewRHS,
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ISD::CondCode &CCCode,
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assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
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&& "Unsupported setcc type!");
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// Expand into one or more soft-fp libcall(s).
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RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
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LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
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(VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
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LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
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(VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
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LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
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(VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
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LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
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(VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
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LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
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(VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
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LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
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(VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
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LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
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(VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
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LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
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(VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
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LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
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(VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
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// SETONE = SETOLT | SETOGT
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LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
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(VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
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LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
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(VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
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LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
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(VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
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LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
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(VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
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LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
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(VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
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LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
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(VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
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default: llvm_unreachable("Do not know how to soften this setcc!");
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// Use the target specific return value for comparions lib calls.
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EVT RetVT = getCmpLibcallReturnType();
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SDValue Ops[2] = { NewLHS, NewRHS };
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NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
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NewRHS = DAG.getConstant(0, dl, RetVT);
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CCCode = getCmpLibcallCC(LC1);
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if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
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SDValue Tmp = DAG.getNode(
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getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
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NewLHS, NewRHS, DAG.getCondCode(CCCode));
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NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
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NewLHS = DAG.getNode(
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getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT),
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NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
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NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
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/// getJumpTableEncoding - Return the entry encoding for a jump table in the
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/// current function. The returned value is a member of the
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/// MachineJumpTableInfo::JTEntryKind enum.
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unsigned TargetLowering::getJumpTableEncoding() const {
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// In non-pic modes, just use the address of a block.
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
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return MachineJumpTableInfo::EK_BlockAddress;
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// In PIC mode, if the target supports a GPRel32 directive, use it.
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if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
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return MachineJumpTableInfo::EK_GPRel32BlockAddress;
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// Otherwise, use a label difference.
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return MachineJumpTableInfo::EK_LabelDifference32;
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SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
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SelectionDAG &DAG) const {
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// If our PIC model is GP relative, use the global offset table as the base.
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unsigned JTEncoding = getJumpTableEncoding();
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if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
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(JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
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return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(DAG.getDataLayout()));
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/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
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/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
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TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
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unsigned JTI,MCContext &Ctx) const{
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// The normal PIC reloc base is the label at the start of the jump table.
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return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
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TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
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// Assume that everything is safe in static mode.
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if (getTargetMachine().getRelocationModel() == Reloc::Static)
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// In dynamic-no-pic mode, assume that known defined values are safe.
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if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
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GA && GA->getGlobal()->isStrongDefinitionForLinker())
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// Otherwise assume nothing is safe.
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//===----------------------------------------------------------------------===//
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// Optimization Methods
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//===----------------------------------------------------------------------===//
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/// ShrinkDemandedConstant - Check to see if the specified operand of the
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/// specified instruction is a constant integer. If so, check to see if there
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/// are any bits set in the constant that are not demanded. If so, shrink the
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/// constant and return true.
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bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
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const APInt &Demanded) {
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// FIXME: ISD::SELECT, ISD::SELECT_CC
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switch (Op.getOpcode()) {
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
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if (!C) return false;
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if (Op.getOpcode() == ISD::XOR &&
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(C->getAPIntValue() | (~Demanded)).isAllOnesValue())
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// if we can expand it to have all bits set, do it
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if (C->getAPIntValue().intersects(~Demanded)) {
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EVT VT = Op.getValueType();
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SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
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DAG.getConstant(Demanded &
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return CombineTo(Op, New);
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/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
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/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
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/// cast, but it could be generalized for targets with other types of
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/// implicit widening casts.
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TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
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const APInt &Demanded,
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assert(Op.getNumOperands() == 2 &&
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"ShrinkDemandedOp only supports binary operators!");
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assert(Op.getNode()->getNumValues() == 1 &&
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"ShrinkDemandedOp only supports nodes with one result!");
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// Early return, as this function cannot handle vector types.
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if (Op.getValueType().isVector())
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// Don't do this if the node has another user, which may require the
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if (!Op.getNode()->hasOneUse())
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// Search for the smallest integer type with free casts to and from
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// Op's type. For expedience, just check power-of-2 integer types.
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
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unsigned SmallVTBits = DemandedSize;
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if (!isPowerOf2_32(SmallVTBits))
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SmallVTBits = NextPowerOf2(SmallVTBits);
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for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
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EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
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if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
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TLI.isZExtFree(SmallVT, Op.getValueType())) {
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// We found a type with free casts.
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SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
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DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
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Op.getNode()->getOperand(0)),
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DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
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Op.getNode()->getOperand(1)));
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bool NeedZext = DemandedSize > SmallVTBits;
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SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
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dl, Op.getValueType(), X);
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return CombineTo(Op, Z);
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/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
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/// DemandedMask bits of the result of Op are ever used downstream. If we can
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/// use this information to simplify Op, create a new simplified DAG node and
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/// return true, returning the original and new nodes in Old and New. Otherwise,
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/// analyze the expression and return a mask of KnownOne and KnownZero bits for
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/// the expression (used to simplify the caller). The KnownZero/One bits may
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/// only be accurate for those bits in the DemandedMask.
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bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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const APInt &DemandedMask,
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TargetLoweringOpt &TLO,
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unsigned Depth) const {
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unsigned BitWidth = DemandedMask.getBitWidth();
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assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
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"Mask size mismatches value type size!");
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APInt NewMask = DemandedMask;
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auto &DL = TLO.DAG.getDataLayout();
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// Don't know anything.
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KnownZero = KnownOne = APInt(BitWidth, 0);
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// Other users may use these bits.
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if (!Op.getNode()->hasOneUse()) {
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// If not at the root, Just compute the KnownZero/KnownOne bits to
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// simplify things downstream.
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TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
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// If this is the root being simplified, allow it to have multiple uses,
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// just set the NewMask to all bits.
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NewMask = APInt::getAllOnesValue(BitWidth);
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} else if (DemandedMask == 0) {
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// Not demanding any bits from Op.
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if (Op.getOpcode() != ISD::UNDEF)
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return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
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} else if (Depth == 6) { // Limit search depth.
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APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
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switch (Op.getOpcode()) {
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// We know all of the bits for a constant!
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KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
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KnownZero = ~KnownOne;
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return false; // Don't fall through, will infinitely loop.
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// If the RHS is a constant, check to see if the LHS would be zero without
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// using the bits from the RHS. Below, we use knowledge about the RHS to
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// simplify the LHS, here we're using information from the LHS to simplify
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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APInt LHSZero, LHSOne;
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// Do not increment Depth here; that can cause an infinite loop.
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TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
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// If the LHS already has zeros where RHSC does, this and is dead.
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if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(0));
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// If any of the set bits in the RHS are known zero on the LHS, shrink
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if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
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if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
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KnownOne, TLO, Depth+1))
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
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KnownZero2, KnownOne2, TLO, Depth+1))
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assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
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// If all of the demanded bits are known one on one side, return the other.
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// These bits cannot contribute to the result of the 'and'.
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if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(0));
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if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(1));
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// If all of the demanded bits in the inputs are known zeros, return zero.
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if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
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return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.getValueType()));
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// If the RHS is a constant, see if we can simplify it.
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if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
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// If the operation can be done in a smaller type, do so.
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if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
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// Output known-1 bits are only known if set in both the LHS & RHS.
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KnownOne &= KnownOne2;
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// Output known-0 are known to be clear if zero in either the LHS | RHS.
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KnownZero |= KnownZero2;
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if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
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KnownOne, TLO, Depth+1))
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
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KnownZero2, KnownOne2, TLO, Depth+1))
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assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
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// If all of the demanded bits are known zero on one side, return the other.
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// These bits cannot contribute to the result of the 'or'.
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if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(0));
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if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(1));
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// If all of the potentially set bits on one side are known to be set on
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// the other side, just use the 'other' side.
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if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(0));
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if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
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return TLO.CombineTo(Op, Op.getOperand(1));
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// If the RHS is a constant, see if we can simplify it.
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if (TLO.ShrinkDemandedConstant(Op, NewMask))
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// If the operation can be done in a smaller type, do so.
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if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
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// Output known-0 bits are only known if clear in both the LHS & RHS.
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KnownZero &= KnownZero2;
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// Output known-1 are known to be set if set in either the LHS | RHS.
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KnownOne |= KnownOne2;
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if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
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KnownOne, TLO, Depth+1))
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
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KnownOne2, TLO, Depth+1))
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assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
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// If all of the demanded bits are known zero on one side, return the other.
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// These bits cannot contribute to the result of the 'xor'.
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if ((KnownZero & NewMask) == NewMask)
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return TLO.CombineTo(Op, Op.getOperand(0));
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if ((KnownZero2 & NewMask) == NewMask)
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return TLO.CombineTo(Op, Op.getOperand(1));
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// If the operation can be done in a smaller type, do so.
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if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
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// If all of the unknown bits are known to be zero on one side or the other
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// (but not both) turn this into an *inclusive* or.
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// e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
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if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
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// Output known-0 bits are known if clear or set in both the LHS & RHS.
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KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
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// Output known-1 are known to be set if set in only one of the LHS, RHS.
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KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
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// If all of the demanded bits on one side are known, and all of the set
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// bits on that side are also known to be set on the other side, turn this
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// into an AND, as we know the bits will be cleared.
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// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
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// NB: it is okay if more bits are known than are requested
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if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
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if (KnownOne == KnownOne2) { // set bits are the same on both sides
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EVT VT = Op.getValueType();
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SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT);
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return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
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Op.getOperand(0), ANDC));
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// If the RHS is a constant, see if we can simplify it.
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// for XOR, we prefer to force bits to 1 if they will make a -1.
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// if we can't force bits, try to shrink constant
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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APInt Expanded = C->getAPIntValue() | (~NewMask);
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// if we can expand it to have all bits set, do it
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if (Expanded.isAllOnesValue()) {
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if (Expanded != C->getAPIntValue()) {
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EVT VT = Op.getValueType();
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SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
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TLO.DAG.getConstant(Expanded, dl, VT));
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return TLO.CombineTo(Op, New);
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// if it already has all the bits set, nothing to change
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// but don't shrink either!
563
} else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
568
KnownZero = KnownZeroOut;
569
KnownOne = KnownOneOut;
572
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
573
KnownOne, TLO, Depth+1))
575
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
576
KnownOne2, TLO, Depth+1))
578
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
579
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
581
// If the operands are constants, see if we can simplify them.
582
if (TLO.ShrinkDemandedConstant(Op, NewMask))
585
// Only known if known in both the LHS and RHS.
586
KnownOne &= KnownOne2;
587
KnownZero &= KnownZero2;
590
if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
591
KnownOne, TLO, Depth+1))
593
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
594
KnownOne2, TLO, Depth+1))
596
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
597
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
599
// If the operands are constants, see if we can simplify them.
600
if (TLO.ShrinkDemandedConstant(Op, NewMask))
603
// Only known if known in both the LHS and RHS.
604
KnownOne &= KnownOne2;
605
KnownZero &= KnownZero2;
608
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
609
unsigned ShAmt = SA->getZExtValue();
610
SDValue InOp = Op.getOperand(0);
612
// If the shift count is an invalid immediate, don't do anything.
613
if (ShAmt >= BitWidth)
616
// If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
617
// single shift. We can do this if the bottom bits (which are shifted
618
// out) are never demanded.
619
if (InOp.getOpcode() == ISD::SRL &&
620
isa<ConstantSDNode>(InOp.getOperand(1))) {
621
if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
622
unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
623
unsigned Opc = ISD::SHL;
631
TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
632
EVT VT = Op.getValueType();
633
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
634
InOp.getOperand(0), NewSA));
638
if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
639
KnownZero, KnownOne, TLO, Depth+1))
642
// Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
643
// are not demanded. This will likely allow the anyext to be folded away.
644
if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
645
SDValue InnerOp = InOp.getNode()->getOperand(0);
646
EVT InnerVT = InnerOp.getValueType();
647
unsigned InnerBits = InnerVT.getSizeInBits();
648
if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
649
isTypeDesirableForOp(ISD::SHL, InnerVT)) {
650
EVT ShTy = getShiftAmountTy(InnerVT, DL);
651
if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
654
TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
655
TLO.DAG.getConstant(ShAmt, dl, ShTy));
658
TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
661
// Repeat the SHL optimization above in cases where an extension
662
// intervenes: (shl (anyext (shr x, c1)), c2) to
663
// (shl (anyext x), c2-c1). This requires that the bottom c1 bits
664
// aren't demanded (as above) and that the shifted upper c1 bits of
665
// x aren't demanded.
666
if (InOp.hasOneUse() &&
667
InnerOp.getOpcode() == ISD::SRL &&
668
InnerOp.hasOneUse() &&
669
isa<ConstantSDNode>(InnerOp.getOperand(1))) {
670
uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
672
if (InnerShAmt < ShAmt &&
673
InnerShAmt < InnerBits &&
674
NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
675
NewMask.trunc(ShAmt) == 0) {
677
TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
678
Op.getOperand(1).getValueType());
679
EVT VT = Op.getValueType();
680
SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
681
InnerOp.getOperand(0));
682
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
688
KnownZero <<= SA->getZExtValue();
689
KnownOne <<= SA->getZExtValue();
690
// low bits known zero.
691
KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
695
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
696
EVT VT = Op.getValueType();
697
unsigned ShAmt = SA->getZExtValue();
698
unsigned VTSize = VT.getSizeInBits();
699
SDValue InOp = Op.getOperand(0);
701
// If the shift count is an invalid immediate, don't do anything.
702
if (ShAmt >= BitWidth)
705
APInt InDemandedMask = (NewMask << ShAmt);
707
// If the shift is exact, then it does demand the low bits (and knows that
709
if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
710
InDemandedMask |= APInt::getLowBitsSet(BitWidth, ShAmt);
712
// If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
713
// single shift. We can do this if the top bits (which are shifted out)
714
// are never demanded.
715
if (InOp.getOpcode() == ISD::SHL &&
716
isa<ConstantSDNode>(InOp.getOperand(1))) {
717
if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
718
unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
719
unsigned Opc = ISD::SRL;
727
TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
728
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
729
InOp.getOperand(0), NewSA));
733
// Compute the new bits that are at the top now.
734
if (SimplifyDemandedBits(InOp, InDemandedMask,
735
KnownZero, KnownOne, TLO, Depth+1))
737
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
738
KnownZero = KnownZero.lshr(ShAmt);
739
KnownOne = KnownOne.lshr(ShAmt);
741
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
742
KnownZero |= HighBits; // High bits known zero.
746
// If this is an arithmetic shift right and only the low-bit is set, we can
747
// always convert this into a logical shr, even if the shift amount is
748
// variable. The low bit of the shift cannot be an input sign bit unless
749
// the shift amount is >= the size of the datatype, which is undefined.
751
return TLO.CombineTo(Op,
752
TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
753
Op.getOperand(0), Op.getOperand(1)));
755
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
756
EVT VT = Op.getValueType();
757
unsigned ShAmt = SA->getZExtValue();
759
// If the shift count is an invalid immediate, don't do anything.
760
if (ShAmt >= BitWidth)
763
APInt InDemandedMask = (NewMask << ShAmt);
765
// If the shift is exact, then it does demand the low bits (and knows that
767
if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
768
InDemandedMask |= APInt::getLowBitsSet(BitWidth, ShAmt);
770
// If any of the demanded bits are produced by the sign extension, we also
771
// demand the input sign bit.
772
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
773
if (HighBits.intersects(NewMask))
774
InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
776
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
777
KnownZero, KnownOne, TLO, Depth+1))
779
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
780
KnownZero = KnownZero.lshr(ShAmt);
781
KnownOne = KnownOne.lshr(ShAmt);
783
// Handle the sign bit, adjusted to where it is now in the mask.
784
APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
786
// If the input sign bit is known to be zero, or if none of the top bits
787
// are demanded, turn this into an unsigned shift right.
788
if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
790
Flags.setExact(cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact());
791
return TLO.CombineTo(Op,
792
TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0),
793
Op.getOperand(1), &Flags));
796
int Log2 = NewMask.exactLogBase2();
798
// The bit must come from the sign.
800
TLO.DAG.getConstant(BitWidth - 1 - Log2, dl,
801
Op.getOperand(1).getValueType());
802
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
803
Op.getOperand(0), NewSA));
806
if (KnownOne.intersects(SignBit))
807
// New bits are known one.
808
KnownOne |= HighBits;
811
case ISD::SIGN_EXTEND_INREG: {
812
EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
814
APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
815
// If we only care about the highest bit, don't bother shifting right.
816
if (MsbMask == NewMask) {
817
unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
818
SDValue InOp = Op.getOperand(0);
819
unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits();
820
bool AlreadySignExtended =
821
TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1;
822
// However if the input is already sign extended we expect the sign
823
// extension to be dropped altogether later and do not simplify.
824
if (!AlreadySignExtended) {
825
// Compute the correct shift amount type, which must be getShiftAmountTy
826
// for scalar types after legalization.
827
EVT ShiftAmtTy = Op.getValueType();
828
if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
829
ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL);
831
SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl,
833
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
834
Op.getValueType(), InOp,
839
// Sign extension. Compute the demanded bits in the result that are not
840
// present in the input.
842
APInt::getHighBitsSet(BitWidth,
843
BitWidth - ExVT.getScalarType().getSizeInBits());
845
// If none of the extended bits are demanded, eliminate the sextinreg.
846
if ((NewBits & NewMask) == 0)
847
return TLO.CombineTo(Op, Op.getOperand(0));
850
APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
851
APInt InputDemandedBits =
852
APInt::getLowBitsSet(BitWidth,
853
ExVT.getScalarType().getSizeInBits()) &
856
// Since the sign extended bits are demanded, we know that the sign
858
InputDemandedBits |= InSignBit;
860
if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
861
KnownZero, KnownOne, TLO, Depth+1))
863
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
865
// If the sign bit of the input is known set or clear, then we know the
866
// top bits of the result.
868
// If the input sign bit is known zero, convert this into a zero extension.
869
if (KnownZero.intersects(InSignBit))
870
return TLO.CombineTo(Op,
871
TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
873
if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
875
KnownZero &= ~NewBits;
876
} else { // Input sign bit unknown
877
KnownZero &= ~NewBits;
878
KnownOne &= ~NewBits;
882
case ISD::BUILD_PAIR: {
883
EVT HalfVT = Op.getOperand(0).getValueType();
884
unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
886
APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
887
APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
889
APInt KnownZeroLo, KnownOneLo;
890
APInt KnownZeroHi, KnownOneHi;
892
if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
893
KnownOneLo, TLO, Depth + 1))
896
if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
897
KnownOneHi, TLO, Depth + 1))
900
KnownZero = KnownZeroLo.zext(BitWidth) |
901
KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
903
KnownOne = KnownOneLo.zext(BitWidth) |
904
KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
907
case ISD::ZERO_EXTEND: {
908
unsigned OperandBitWidth =
909
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
910
APInt InMask = NewMask.trunc(OperandBitWidth);
912
// If none of the top bits are demanded, convert this into an any_extend.
914
APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
915
if (!NewBits.intersects(NewMask))
916
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
920
if (SimplifyDemandedBits(Op.getOperand(0), InMask,
921
KnownZero, KnownOne, TLO, Depth+1))
923
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
924
KnownZero = KnownZero.zext(BitWidth);
925
KnownOne = KnownOne.zext(BitWidth);
926
KnownZero |= NewBits;
929
case ISD::SIGN_EXTEND: {
930
EVT InVT = Op.getOperand(0).getValueType();
931
unsigned InBits = InVT.getScalarType().getSizeInBits();
932
APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
933
APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
934
APInt NewBits = ~InMask & NewMask;
936
// If none of the top bits are demanded, convert this into an any_extend.
938
return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
942
// Since some of the sign extended bits are demanded, we know that the sign
944
APInt InDemandedBits = InMask & NewMask;
945
InDemandedBits |= InSignBit;
946
InDemandedBits = InDemandedBits.trunc(InBits);
948
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
949
KnownOne, TLO, Depth+1))
951
KnownZero = KnownZero.zext(BitWidth);
952
KnownOne = KnownOne.zext(BitWidth);
954
// If the sign bit is known zero, convert this to a zero extend.
955
if (KnownZero.intersects(InSignBit))
956
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
960
// If the sign bit is known one, the top bits match.
961
if (KnownOne.intersects(InSignBit)) {
963
assert((KnownZero & NewBits) == 0);
964
} else { // Otherwise, top bits aren't known.
965
assert((KnownOne & NewBits) == 0);
966
assert((KnownZero & NewBits) == 0);
970
case ISD::ANY_EXTEND: {
971
unsigned OperandBitWidth =
972
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
973
APInt InMask = NewMask.trunc(OperandBitWidth);
974
if (SimplifyDemandedBits(Op.getOperand(0), InMask,
975
KnownZero, KnownOne, TLO, Depth+1))
977
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
978
KnownZero = KnownZero.zext(BitWidth);
979
KnownOne = KnownOne.zext(BitWidth);
982
case ISD::TRUNCATE: {
983
// Simplify the input, using demanded bit information, and compute the known
984
// zero/one bits live out.
985
unsigned OperandBitWidth =
986
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
987
APInt TruncMask = NewMask.zext(OperandBitWidth);
988
if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
989
KnownZero, KnownOne, TLO, Depth+1))
991
KnownZero = KnownZero.trunc(BitWidth);
992
KnownOne = KnownOne.trunc(BitWidth);
994
// If the input is only used by this truncate, see if we can shrink it based
995
// on the known demanded bits.
996
if (Op.getOperand(0).getNode()->hasOneUse()) {
997
SDValue In = Op.getOperand(0);
998
switch (In.getOpcode()) {
1001
// Shrink SRL by a constant if none of the high bits shifted in are
1003
if (TLO.LegalTypes() &&
1004
!isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1005
// Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1008
ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1011
SDValue Shift = In.getOperand(1);
1012
if (TLO.LegalTypes()) {
1013
uint64_t ShVal = ShAmt->getZExtValue();
1014
Shift = TLO.DAG.getConstant(ShVal, dl,
1015
getShiftAmountTy(Op.getValueType(), DL));
1018
APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1019
OperandBitWidth - BitWidth);
1020
HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1022
if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1023
// None of the shifted in bits are needed. Add a truncate of the
1024
// shift input, then shift it.
1025
SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1028
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1037
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1040
case ISD::AssertZext: {
1041
// AssertZext demands all of the high bits, plus any of the low bits
1042
// demanded by its users.
1043
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1044
APInt InMask = APInt::getLowBitsSet(BitWidth,
1045
VT.getSizeInBits());
1046
if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1047
KnownZero, KnownOne, TLO, Depth+1))
1049
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1051
KnownZero |= ~InMask & NewMask;
1055
// If this is an FP->Int bitcast and if the sign bit is the only
1056
// thing demanded, turn this into a FGETSIGN.
1057
if (!TLO.LegalOperations() &&
1058
!Op.getValueType().isVector() &&
1059
!Op.getOperand(0).getValueType().isVector() &&
1060
NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1061
Op.getOperand(0).getValueType().isFloatingPoint()) {
1062
bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1063
bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1064
if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1065
EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1066
// Make a FGETSIGN + SHL to move the sign bit into the appropriate
1067
// place. We expect the SHL to be eliminated by other optimizations.
1068
SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1069
unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1070
if (!OpVTLegal && OpVTSizeInBits > 32)
1071
Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1072
unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1073
SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, Op.getValueType());
1074
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1083
// Add, Sub, and Mul don't demand any bits in positions beyond that
1084
// of the highest bit demanded of them.
1085
APInt LoMask = APInt::getLowBitsSet(BitWidth,
1086
BitWidth - NewMask.countLeadingZeros());
1087
if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1088
KnownOne2, TLO, Depth+1))
1090
if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1091
KnownOne2, TLO, Depth+1))
1093
// See if the operation should be performed at a smaller bit width.
1094
if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1099
// Just use computeKnownBits to compute output bits.
1100
TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1104
// If we know the value of all of the demanded bits, return this as a
1106
if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
1107
// Avoid folding to a constant if any OpaqueConstant is involved.
1108
const SDNode *N = Op.getNode();
1109
for (SDNodeIterator I = SDNodeIterator::begin(N),
1110
E = SDNodeIterator::end(N); I != E; ++I) {
1112
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
1116
return TLO.CombineTo(Op,
1117
TLO.DAG.getConstant(KnownOne, dl, Op.getValueType()));
1123
/// computeKnownBitsForTargetNode - Determine which of the bits specified
1124
/// in Mask are known to be either zero or one and return them in the
1125
/// KnownZero/KnownOne bitsets.
1126
void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1129
const SelectionDAG &DAG,
1130
unsigned Depth) const {
1131
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1132
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1133
Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1134
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1135
"Should use MaskedValueIsZero if you don't know whether Op"
1136
" is a target node!");
1137
KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1140
/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1141
/// targets that want to expose additional information about sign bits to the
1143
unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1144
const SelectionDAG &,
1145
unsigned Depth) const {
1146
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1147
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1148
Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1149
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1150
"Should use ComputeNumSignBits if you don't know whether Op"
1151
" is a target node!");
1155
/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1156
/// one bit set. This differs from computeKnownBits in that it doesn't need to
1157
/// determine which bit is set.
1159
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1160
// A left-shift of a constant one will have exactly one bit set, because
1161
// shifting the bit off the end is undefined.
1162
if (Val.getOpcode() == ISD::SHL)
1163
if (ConstantSDNode *C =
1164
dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1165
if (C->getAPIntValue() == 1)
1168
// Similarly, a right-shift of a constant sign-bit will have exactly
1170
if (Val.getOpcode() == ISD::SRL)
1171
if (ConstantSDNode *C =
1172
dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1173
if (C->getAPIntValue().isSignBit())
1176
// More could be done here, though the above checks are enough
1177
// to handle some common cases.
1179
// Fall back to computeKnownBits to catch other known cases.
1180
EVT OpVT = Val.getValueType();
1181
unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1182
APInt KnownZero, KnownOne;
1183
DAG.computeKnownBits(Val, KnownZero, KnownOne);
1184
return (KnownZero.countPopulation() == BitWidth - 1) &&
1185
(KnownOne.countPopulation() == 1);
1188
bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1192
const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1194
const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1198
BitVector UndefElements;
1199
CN = BV->getConstantSplatNode(&UndefElements);
1200
// Only interested in constant splats, and we don't try to handle undef
1201
// elements in identifying boolean constants.
1202
if (!CN || UndefElements.none())
1206
switch (getBooleanContents(N->getValueType(0))) {
1207
case UndefinedBooleanContent:
1208
return CN->getAPIntValue()[0];
1209
case ZeroOrOneBooleanContent:
1211
case ZeroOrNegativeOneBooleanContent:
1212
return CN->isAllOnesValue();
1215
llvm_unreachable("Invalid boolean contents");
1218
bool TargetLowering::isConstFalseVal(const SDNode *N) const {
1222
const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1224
const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1228
BitVector UndefElements;
1229
CN = BV->getConstantSplatNode(&UndefElements);
1230
// Only interested in constant splats, and we don't try to handle undef
1231
// elements in identifying boolean constants.
1232
if (!CN || UndefElements.none())
1236
if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
1237
return !CN->getAPIntValue()[0];
1239
return CN->isNullValue();
1242
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
1243
/// and cc. If it is unable to simplify it, return a null SDValue.
1245
TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1246
ISD::CondCode Cond, bool foldBooleans,
1247
DAGCombinerInfo &DCI, SDLoc dl) const {
1248
SelectionDAG &DAG = DCI.DAG;
1250
// These setcc operations always fold.
1254
case ISD::SETFALSE2: return DAG.getConstant(0, dl, VT);
1256
case ISD::SETTRUE2: {
1257
TargetLowering::BooleanContent Cnt =
1258
getBooleanContents(N0->getValueType(0));
1259
return DAG.getConstant(
1260
Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, dl,
1265
// Ensure that the constant occurs on the RHS, and fold constant
1267
ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1268
if (isa<ConstantSDNode>(N0.getNode()) &&
1269
(DCI.isBeforeLegalizeOps() ||
1270
isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1271
return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1273
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1274
const APInt &C1 = N1C->getAPIntValue();
1276
// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1277
// equality comparison, then we're just comparing whether X itself is
1279
if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1280
N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1281
N0.getOperand(1).getOpcode() == ISD::Constant) {
1283
= cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1284
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1285
ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1286
if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1287
// (srl (ctlz x), 5) == 0 -> X != 0
1288
// (srl (ctlz x), 5) != 1 -> X != 0
1291
// (srl (ctlz x), 5) != 0 -> X == 0
1292
// (srl (ctlz x), 5) == 1 -> X == 0
1295
SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
1296
return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1302
// Look through truncs that don't change the value of a ctpop.
1303
if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1304
CTPOP = N0.getOperand(0);
1306
if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1307
(N0 == CTPOP || N0.getValueType().getSizeInBits() >
1308
Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1309
EVT CTVT = CTPOP.getValueType();
1310
SDValue CTOp = CTPOP.getOperand(0);
1312
// (ctpop x) u< 2 -> (x & x-1) == 0
1313
// (ctpop x) u> 1 -> (x & x-1) != 0
1314
if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1315
SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1316
DAG.getConstant(1, dl, CTVT));
1317
SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1318
ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1319
return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
1322
// TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1325
// (zext x) == C --> x == (trunc C)
1326
// (sext x) == C --> x == (trunc C)
1327
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1328
DCI.isBeforeLegalize() && N0->hasOneUse()) {
1329
unsigned MinBits = N0.getValueSizeInBits();
1331
bool Signed = false;
1332
if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1334
MinBits = N0->getOperand(0).getValueSizeInBits();
1335
PreExt = N0->getOperand(0);
1336
} else if (N0->getOpcode() == ISD::AND) {
1337
// DAGCombine turns costly ZExts into ANDs
1338
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1339
if ((C->getAPIntValue()+1).isPowerOf2()) {
1340
MinBits = C->getAPIntValue().countTrailingOnes();
1341
PreExt = N0->getOperand(0);
1343
} else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
1345
MinBits = N0->getOperand(0).getValueSizeInBits();
1346
PreExt = N0->getOperand(0);
1348
} else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1349
// ZEXTLOAD / SEXTLOAD
1350
if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1351
MinBits = LN0->getMemoryVT().getSizeInBits();
1353
} else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
1355
MinBits = LN0->getMemoryVT().getSizeInBits();
1360
// Figure out how many bits we need to preserve this constant.
1361
unsigned ReqdBits = Signed ?
1362
C1.getBitWidth() - C1.getNumSignBits() + 1 :
1365
// Make sure we're not losing bits from the constant.
1367
MinBits < C1.getBitWidth() &&
1368
MinBits >= ReqdBits) {
1369
EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1370
if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1371
// Will get folded away.
1372
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
1373
SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
1374
return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1379
// If the LHS is '(and load, const)', the RHS is 0,
1380
// the test is for equality or unsigned, and all 1 bits of the const are
1381
// in the same partial word, see if we can shorten the load.
1382
if (DCI.isBeforeLegalize() &&
1383
!ISD::isSignedIntSetCC(Cond) &&
1384
N0.getOpcode() == ISD::AND && C1 == 0 &&
1385
N0.getNode()->hasOneUse() &&
1386
isa<LoadSDNode>(N0.getOperand(0)) &&
1387
N0.getOperand(0).getNode()->hasOneUse() &&
1388
isa<ConstantSDNode>(N0.getOperand(1))) {
1389
LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1391
unsigned bestWidth = 0, bestOffset = 0;
1392
if (!Lod->isVolatile() && Lod->isUnindexed()) {
1393
unsigned origWidth = N0.getValueType().getSizeInBits();
1394
unsigned maskWidth = origWidth;
1395
// We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1396
// 8 bits, but have to be careful...
1397
if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1398
origWidth = Lod->getMemoryVT().getSizeInBits();
1400
cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1401
for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1402
APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1403
for (unsigned offset=0; offset<origWidth/width; offset++) {
1404
if ((newMask & Mask) == Mask) {
1405
if (!DAG.getDataLayout().isLittleEndian())
1406
bestOffset = (origWidth/width - offset - 1) * (width/8);
1408
bestOffset = (uint64_t)offset * (width/8);
1409
bestMask = Mask.lshr(offset * (width/8) * 8);
1413
newMask = newMask << width;
1418
EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1419
if (newVT.isRound()) {
1420
EVT PtrType = Lod->getOperand(1).getValueType();
1421
SDValue Ptr = Lod->getBasePtr();
1422
if (bestOffset != 0)
1423
Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1424
DAG.getConstant(bestOffset, dl, PtrType));
1425
unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1426
SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1427
Lod->getPointerInfo().getWithOffset(bestOffset),
1428
false, false, false, NewAlign);
1429
return DAG.getSetCC(dl, VT,
1430
DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1431
DAG.getConstant(bestMask.trunc(bestWidth),
1433
DAG.getConstant(0LL, dl, newVT), Cond);
1438
// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1439
if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1440
unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1442
// If the comparison constant has bits in the upper part, the
1443
// zero-extended value could never match.
1444
if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1445
C1.getBitWidth() - InSize))) {
1449
case ISD::SETEQ: return DAG.getConstant(0, dl, VT);
1452
case ISD::SETNE: return DAG.getConstant(1, dl, VT);
1455
// True if the sign bit of C1 is set.
1456
return DAG.getConstant(C1.isNegative(), dl, VT);
1459
// True if the sign bit of C1 isn't set.
1460
return DAG.getConstant(C1.isNonNegative(), dl, VT);
1466
// Otherwise, we can perform the comparison with the low bits.
1474
EVT newVT = N0.getOperand(0).getValueType();
1475
if (DCI.isBeforeLegalizeOps() ||
1476
(isOperationLegal(ISD::SETCC, newVT) &&
1477
getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1479
getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), newVT);
1480
SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
1482
SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1484
return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1489
break; // todo, be more careful with signed comparisons
1491
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1492
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1493
EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1494
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1495
EVT ExtDstTy = N0.getValueType();
1496
unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1498
// If the constant doesn't fit into the number of bits for the source of
1499
// the sign extension, it is impossible for both sides to be equal.
1500
if (C1.getMinSignedBits() > ExtSrcTyBits)
1501
return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
1504
EVT Op0Ty = N0.getOperand(0).getValueType();
1505
if (Op0Ty == ExtSrcTy) {
1506
ZextOp = N0.getOperand(0);
1508
APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1509
ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1510
DAG.getConstant(Imm, dl, Op0Ty));
1512
if (!DCI.isCalledByLegalizer())
1513
DCI.AddToWorklist(ZextOp.getNode());
1514
// Otherwise, make this a use of a zext.
1515
return DAG.getSetCC(dl, VT, ZextOp,
1516
DAG.getConstant(C1 & APInt::getLowBitsSet(
1521
} else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1522
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1523
// SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1524
if (N0.getOpcode() == ISD::SETCC &&
1525
isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1526
bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1528
return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1529
// Invert the condition.
1530
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1531
CC = ISD::getSetCCInverse(CC,
1532
N0.getOperand(0).getValueType().isInteger());
1533
if (DCI.isBeforeLegalizeOps() ||
1534
isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1535
return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1538
if ((N0.getOpcode() == ISD::XOR ||
1539
(N0.getOpcode() == ISD::AND &&
1540
N0.getOperand(0).getOpcode() == ISD::XOR &&
1541
N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1542
isa<ConstantSDNode>(N0.getOperand(1)) &&
1543
cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1544
// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1545
// can only do this if the top bits are known zero.
1546
unsigned BitWidth = N0.getValueSizeInBits();
1547
if (DAG.MaskedValueIsZero(N0,
1548
APInt::getHighBitsSet(BitWidth,
1550
// Okay, get the un-inverted input value.
1552
if (N0.getOpcode() == ISD::XOR)
1553
Val = N0.getOperand(0);
1555
assert(N0.getOpcode() == ISD::AND &&
1556
N0.getOperand(0).getOpcode() == ISD::XOR);
1557
// ((X^1)&1)^1 -> X & 1
1558
Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1559
N0.getOperand(0).getOperand(0),
1563
return DAG.getSetCC(dl, VT, Val, N1,
1564
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1566
} else if (N1C->getAPIntValue() == 1 &&
1568
getBooleanContents(N0->getValueType(0)) ==
1569
ZeroOrOneBooleanContent)) {
1571
if (Op0.getOpcode() == ISD::TRUNCATE)
1572
Op0 = Op0.getOperand(0);
1574
if ((Op0.getOpcode() == ISD::XOR) &&
1575
Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1576
Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1577
// (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1578
Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1579
return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1582
if (Op0.getOpcode() == ISD::AND &&
1583
isa<ConstantSDNode>(Op0.getOperand(1)) &&
1584
cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1585
// If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1586
if (Op0.getValueType().bitsGT(VT))
1587
Op0 = DAG.getNode(ISD::AND, dl, VT,
1588
DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1589
DAG.getConstant(1, dl, VT));
1590
else if (Op0.getValueType().bitsLT(VT))
1591
Op0 = DAG.getNode(ISD::AND, dl, VT,
1592
DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1593
DAG.getConstant(1, dl, VT));
1595
return DAG.getSetCC(dl, VT, Op0,
1596
DAG.getConstant(0, dl, Op0.getValueType()),
1597
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1599
if (Op0.getOpcode() == ISD::AssertZext &&
1600
cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1601
return DAG.getSetCC(dl, VT, Op0,
1602
DAG.getConstant(0, dl, Op0.getValueType()),
1603
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1607
APInt MinVal, MaxVal;
1608
unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1609
if (ISD::isSignedIntSetCC(Cond)) {
1610
MinVal = APInt::getSignedMinValue(OperandBitSize);
1611
MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1613
MinVal = APInt::getMinValue(OperandBitSize);
1614
MaxVal = APInt::getMaxValue(OperandBitSize);
1617
// Canonicalize GE/LE comparisons to use GT/LT comparisons.
1618
if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1619
if (C1 == MinVal) return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1620
// X >= C0 --> X > (C0 - 1)
1622
ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1623
if ((DCI.isBeforeLegalizeOps() ||
1624
isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1625
(!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1626
isLegalICmpImmediate(C.getSExtValue())))) {
1627
return DAG.getSetCC(dl, VT, N0,
1628
DAG.getConstant(C, dl, N1.getValueType()),
1633
if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1634
if (C1 == MaxVal) return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1635
// X <= C0 --> X < (C0 + 1)
1637
ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1638
if ((DCI.isBeforeLegalizeOps() ||
1639
isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1640
(!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1641
isLegalICmpImmediate(C.getSExtValue())))) {
1642
return DAG.getSetCC(dl, VT, N0,
1643
DAG.getConstant(C, dl, N1.getValueType()),
1648
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1649
return DAG.getConstant(0, dl, VT); // X < MIN --> false
1650
if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1651
return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1652
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1653
return DAG.getConstant(0, dl, VT); // X > MAX --> false
1654
if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1655
return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1657
// Canonicalize setgt X, Min --> setne X, Min
1658
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1659
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1660
// Canonicalize setlt X, Max --> setne X, Max
1661
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1662
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1664
// If we have setult X, 1, turn it into seteq X, 0
1665
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1666
return DAG.getSetCC(dl, VT, N0,
1667
DAG.getConstant(MinVal, dl, N0.getValueType()),
1669
// If we have setugt X, Max-1, turn it into seteq X, Max
1670
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1671
return DAG.getSetCC(dl, VT, N0,
1672
DAG.getConstant(MaxVal, dl, N0.getValueType()),
1675
// If we have "setcc X, C0", check to see if we can shrink the immediate
1678
// SETUGT X, SINTMAX -> SETLT X, 0
1679
if (Cond == ISD::SETUGT &&
1680
C1 == APInt::getSignedMaxValue(OperandBitSize))
1681
return DAG.getSetCC(dl, VT, N0,
1682
DAG.getConstant(0, dl, N1.getValueType()),
1685
// SETULT X, SINTMIN -> SETGT X, -1
1686
if (Cond == ISD::SETULT &&
1687
C1 == APInt::getSignedMinValue(OperandBitSize)) {
1688
SDValue ConstMinusOne =
1689
DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
1691
return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1694
// Fold bit comparisons when we can.
1695
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1696
(VT == N0.getValueType() ||
1697
(isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1698
N0.getOpcode() == ISD::AND) {
1699
auto &DL = DAG.getDataLayout();
1700
if (ConstantSDNode *AndRHS =
1701
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1702
EVT ShiftTy = DCI.isBeforeLegalize()
1704
: getShiftAmountTy(N0.getValueType(), DL);
1705
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1706
// Perform the xform if the AND RHS is a single bit.
1707
if (AndRHS->getAPIntValue().isPowerOf2()) {
1708
return DAG.getNode(ISD::TRUNCATE, dl, VT,
1709
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1710
DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl,
1713
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1714
// (X & 8) == 8 --> (X & 8) >> 3
1715
// Perform the xform if C1 is a single bit.
1716
if (C1.isPowerOf2()) {
1717
return DAG.getNode(ISD::TRUNCATE, dl, VT,
1718
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1719
DAG.getConstant(C1.logBase2(), dl,
1726
if (C1.getMinSignedBits() <= 64 &&
1727
!isLegalICmpImmediate(C1.getSExtValue())) {
1728
// (X & -256) == 256 -> (X >> 8) == 1
1729
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1730
N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1731
if (ConstantSDNode *AndRHS =
1732
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1733
const APInt &AndRHSC = AndRHS->getAPIntValue();
1734
if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1735
unsigned ShiftBits = AndRHSC.countTrailingZeros();
1736
auto &DL = DAG.getDataLayout();
1737
EVT ShiftTy = DCI.isBeforeLegalize()
1739
: getShiftAmountTy(N0.getValueType(), DL);
1740
EVT CmpTy = N0.getValueType();
1741
SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1742
DAG.getConstant(ShiftBits, dl,
1744
SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
1745
return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1748
} else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1749
Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1750
bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1751
// X < 0x100000000 -> (X >> 32) < 1
1752
// X >= 0x100000000 -> (X >> 32) >= 1
1753
// X <= 0x0ffffffff -> (X >> 32) < 1
1754
// X > 0x0ffffffff -> (X >> 32) >= 1
1757
ISD::CondCode NewCond = Cond;
1759
ShiftBits = C1.countTrailingOnes();
1761
NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1763
ShiftBits = C1.countTrailingZeros();
1765
NewC = NewC.lshr(ShiftBits);
1766
if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
1767
isLegalICmpImmediate(NewC.getSExtValue())) {
1768
auto &DL = DAG.getDataLayout();
1769
EVT ShiftTy = DCI.isBeforeLegalize()
1771
: getShiftAmountTy(N0.getValueType(), DL);
1772
EVT CmpTy = N0.getValueType();
1773
SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1774
DAG.getConstant(ShiftBits, dl, ShiftTy));
1775
SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);
1776
return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1782
if (isa<ConstantFPSDNode>(N0.getNode())) {
1783
// Constant fold or commute setcc.
1784
SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1785
if (O.getNode()) return O;
1786
} else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1787
// If the RHS of an FP comparison is a constant, simplify it away in
1789
if (CFP->getValueAPF().isNaN()) {
1790
// If an operand is known to be a nan, we can fold it.
1791
switch (ISD::getUnorderedFlavor(Cond)) {
1792
default: llvm_unreachable("Unknown flavor!");
1793
case 0: // Known false.
1794
return DAG.getConstant(0, dl, VT);
1795
case 1: // Known true.
1796
return DAG.getConstant(1, dl, VT);
1797
case 2: // Undefined.
1798
return DAG.getUNDEF(VT);
1802
// Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1803
// constant if knowing that the operand is non-nan is enough. We prefer to
1804
// have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1806
if (Cond == ISD::SETO || Cond == ISD::SETUO)
1807
return DAG.getSetCC(dl, VT, N0, N0, Cond);
1809
// If the condition is not legal, see if we can find an equivalent one
1811
if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1812
// If the comparison was an awkward floating-point == or != and one of
1813
// the comparison operands is infinity or negative infinity, convert the
1814
// condition to a less-awkward <= or >=.
1815
if (CFP->getValueAPF().isInfinity()) {
1816
if (CFP->getValueAPF().isNegative()) {
1817
if (Cond == ISD::SETOEQ &&
1818
isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1819
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1820
if (Cond == ISD::SETUEQ &&
1821
isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1822
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1823
if (Cond == ISD::SETUNE &&
1824
isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1825
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1826
if (Cond == ISD::SETONE &&
1827
isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1828
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1830
if (Cond == ISD::SETOEQ &&
1831
isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1832
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1833
if (Cond == ISD::SETUEQ &&
1834
isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1835
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1836
if (Cond == ISD::SETUNE &&
1837
isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1838
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1839
if (Cond == ISD::SETONE &&
1840
isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1841
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1848
// The sext(setcc()) => setcc() optimization relies on the appropriate
1849
// constant being emitted.
1851
switch (getBooleanContents(N0.getValueType())) {
1852
case UndefinedBooleanContent:
1853
case ZeroOrOneBooleanContent:
1854
EqVal = ISD::isTrueWhenEqual(Cond);
1856
case ZeroOrNegativeOneBooleanContent:
1857
EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1861
// We can always fold X == X for integer setcc's.
1862
if (N0.getValueType().isInteger()) {
1863
return DAG.getConstant(EqVal, dl, VT);
1865
unsigned UOF = ISD::getUnorderedFlavor(Cond);
1866
if (UOF == 2) // FP operators that are undefined on NaNs.
1867
return DAG.getConstant(EqVal, dl, VT);
1868
if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1869
return DAG.getConstant(EqVal, dl, VT);
1870
// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1871
// if it is not already.
1872
ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1873
if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1874
getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1875
return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1878
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1879
N0.getValueType().isInteger()) {
1880
if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1881
N0.getOpcode() == ISD::XOR) {
1882
// Simplify (X+Y) == (X+Z) --> Y == Z
1883
if (N0.getOpcode() == N1.getOpcode()) {
1884
if (N0.getOperand(0) == N1.getOperand(0))
1885
return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1886
if (N0.getOperand(1) == N1.getOperand(1))
1887
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1888
if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1889
// If X op Y == Y op X, try other combinations.
1890
if (N0.getOperand(0) == N1.getOperand(1))
1891
return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1893
if (N0.getOperand(1) == N1.getOperand(0))
1894
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1899
// If RHS is a legal immediate value for a compare instruction, we need
1900
// to be careful about increasing register pressure needlessly.
1901
bool LegalRHSImm = false;
1903
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1904
if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1905
// Turn (X+C1) == C2 --> X == C2-C1
1906
if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1907
return DAG.getSetCC(dl, VT, N0.getOperand(0),
1908
DAG.getConstant(RHSC->getAPIntValue()-
1909
LHSR->getAPIntValue(),
1910
dl, N0.getValueType()), Cond);
1913
// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1914
if (N0.getOpcode() == ISD::XOR)
1915
// If we know that all of the inverted bits are zero, don't bother
1916
// performing the inversion.
1917
if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1919
DAG.getSetCC(dl, VT, N0.getOperand(0),
1920
DAG.getConstant(LHSR->getAPIntValue() ^
1921
RHSC->getAPIntValue(),
1922
dl, N0.getValueType()),
1926
// Turn (C1-X) == C2 --> X == C1-C2
1927
if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1928
if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1930
DAG.getSetCC(dl, VT, N0.getOperand(1),
1931
DAG.getConstant(SUBC->getAPIntValue() -
1932
RHSC->getAPIntValue(),
1933
dl, N0.getValueType()),
1938
// Could RHSC fold directly into a compare?
1939
if (RHSC->getValueType(0).getSizeInBits() <= 64)
1940
LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1943
// Simplify (X+Z) == X --> Z == 0
1944
// Don't do this if X is an immediate that can fold into a cmp
1945
// instruction and X+Z has other uses. It could be an induction variable
1946
// chain, and the transform would increase register pressure.
1947
if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1948
if (N0.getOperand(0) == N1)
1949
return DAG.getSetCC(dl, VT, N0.getOperand(1),
1950
DAG.getConstant(0, dl, N0.getValueType()), Cond);
1951
if (N0.getOperand(1) == N1) {
1952
if (DAG.isCommutativeBinOp(N0.getOpcode()))
1953
return DAG.getSetCC(dl, VT, N0.getOperand(0),
1954
DAG.getConstant(0, dl, N0.getValueType()),
1956
if (N0.getNode()->hasOneUse()) {
1957
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1958
auto &DL = DAG.getDataLayout();
1959
// (Z-X) == X --> Z == X<<1
1960
SDValue SH = DAG.getNode(
1961
ISD::SHL, dl, N1.getValueType(), N1,
1962
DAG.getConstant(1, dl,
1963
getShiftAmountTy(N1.getValueType(), DL)));
1964
if (!DCI.isCalledByLegalizer())
1965
DCI.AddToWorklist(SH.getNode());
1966
return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1972
if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1973
N1.getOpcode() == ISD::XOR) {
1974
// Simplify X == (X+Z) --> Z == 0
1975
if (N1.getOperand(0) == N0)
1976
return DAG.getSetCC(dl, VT, N1.getOperand(1),
1977
DAG.getConstant(0, dl, N1.getValueType()), Cond);
1978
if (N1.getOperand(1) == N0) {
1979
if (DAG.isCommutativeBinOp(N1.getOpcode()))
1980
return DAG.getSetCC(dl, VT, N1.getOperand(0),
1981
DAG.getConstant(0, dl, N1.getValueType()), Cond);
1982
if (N1.getNode()->hasOneUse()) {
1983
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1984
auto &DL = DAG.getDataLayout();
1985
// X == (Z-X) --> X<<1 == Z
1986
SDValue SH = DAG.getNode(
1987
ISD::SHL, dl, N1.getValueType(), N0,
1988
DAG.getConstant(1, dl, getShiftAmountTy(N0.getValueType(), DL)));
1989
if (!DCI.isCalledByLegalizer())
1990
DCI.AddToWorklist(SH.getNode());
1991
return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1996
// Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1997
// Note that where y is variable and is known to have at most
1998
// one bit set (for example, if it is z&1) we cannot do this;
1999
// the expressions are not equivalent when y==0.
2000
if (N0.getOpcode() == ISD::AND)
2001
if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2002
if (ValueHasExactlyOneBitSet(N1, DAG)) {
2003
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2004
if (DCI.isBeforeLegalizeOps() ||
2005
isCondCodeLegal(Cond, N0.getSimpleValueType())) {
2006
SDValue Zero = DAG.getConstant(0, dl, N1.getValueType());
2007
return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2011
if (N1.getOpcode() == ISD::AND)
2012
if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2013
if (ValueHasExactlyOneBitSet(N0, DAG)) {
2014
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2015
if (DCI.isBeforeLegalizeOps() ||
2016
isCondCodeLegal(Cond, N1.getSimpleValueType())) {
2017
SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
2018
return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2024
// Fold away ALL boolean setcc's.
2026
if (N0.getValueType() == MVT::i1 && foldBooleans) {
2028
default: llvm_unreachable("Unknown integer setcc!");
2029
case ISD::SETEQ: // X == Y -> ~(X^Y)
2030
Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2031
N0 = DAG.getNOT(dl, Temp, MVT::i1);
2032
if (!DCI.isCalledByLegalizer())
2033
DCI.AddToWorklist(Temp.getNode());
2035
case ISD::SETNE: // X != Y --> (X^Y)
2036
N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2038
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2039
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2040
Temp = DAG.getNOT(dl, N0, MVT::i1);
2041
N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2042
if (!DCI.isCalledByLegalizer())
2043
DCI.AddToWorklist(Temp.getNode());
2045
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2046
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2047
Temp = DAG.getNOT(dl, N1, MVT::i1);
2048
N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2049
if (!DCI.isCalledByLegalizer())
2050
DCI.AddToWorklist(Temp.getNode());
2052
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2053
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2054
Temp = DAG.getNOT(dl, N0, MVT::i1);
2055
N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2056
if (!DCI.isCalledByLegalizer())
2057
DCI.AddToWorklist(Temp.getNode());
2059
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2060
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2061
Temp = DAG.getNOT(dl, N1, MVT::i1);
2062
N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2065
if (VT != MVT::i1) {
2066
if (!DCI.isCalledByLegalizer())
2067
DCI.AddToWorklist(N0.getNode());
2068
// FIXME: If running after legalize, we probably can't do this.
2069
N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2074
// Could not fold it.
2078
/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2079
/// node is a GlobalAddress + offset.
2080
bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2081
int64_t &Offset) const {
2082
if (isa<GlobalAddressSDNode>(N)) {
2083
GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2084
GA = GASD->getGlobal();
2085
Offset += GASD->getOffset();
2089
if (N->getOpcode() == ISD::ADD) {
2090
SDValue N1 = N->getOperand(0);
2091
SDValue N2 = N->getOperand(1);
2092
if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2093
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2095
Offset += V->getSExtValue();
2098
} else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2099
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2101
Offset += V->getSExtValue();
2111
SDValue TargetLowering::
2112
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2113
// Default implementation: no optimization.
2117
//===----------------------------------------------------------------------===//
2118
// Inline Assembler Implementation Methods
2119
//===----------------------------------------------------------------------===//
2121
TargetLowering::ConstraintType
2122
TargetLowering::getConstraintType(StringRef Constraint) const {
2123
unsigned S = Constraint.size();
2126
switch (Constraint[0]) {
2128
case 'r': return C_RegisterClass;
2130
case 'o': // offsetable
2131
case 'V': // not offsetable
2133
case 'i': // Simple Integer or Relocatable Constant
2134
case 'n': // Simple Integer
2135
case 'E': // Floating Point Constant
2136
case 'F': // Floating Point Constant
2137
case 's': // Relocatable Constant
2138
case 'p': // Address.
2139
case 'X': // Allow ANY value.
2140
case 'I': // Target registers.
2154
if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2155
if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
2162
/// LowerXConstraint - try to replace an X constraint, which matches anything,
2163
/// with another that has more specific requirements based on the type of the
2164
/// corresponding operand.
2165
const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2166
if (ConstraintVT.isInteger())
2168
if (ConstraintVT.isFloatingPoint())
2169
return "f"; // works for many targets
2173
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2174
/// vector. If it is invalid, don't add anything to Ops.
2175
void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2176
std::string &Constraint,
2177
std::vector<SDValue> &Ops,
2178
SelectionDAG &DAG) const {
2180
if (Constraint.length() > 1) return;
2182
char ConstraintLetter = Constraint[0];
2183
switch (ConstraintLetter) {
2185
case 'X': // Allows any operand; labels (basic block) use this.
2186
if (Op.getOpcode() == ISD::BasicBlock) {
2191
case 'i': // Simple Integer or Relocatable Constant
2192
case 'n': // Simple Integer
2193
case 's': { // Relocatable Constant
2194
// These operands are interested in values of the form (GV+C), where C may
2195
// be folded in as an offset of GV, or it may be explicitly added. Also, it
2196
// is possible and fine if either GV or C are missing.
2197
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2198
GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2200
// If we have "(add GV, C)", pull out GV/C
2201
if (Op.getOpcode() == ISD::ADD) {
2202
C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2203
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2205
C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2206
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2209
C = nullptr, GA = nullptr;
2212
// If we find a valid operand, map to the TargetXXX version so that the
2213
// value itself doesn't get selected.
2214
if (GA) { // Either &GV or &GV+C
2215
if (ConstraintLetter != 'n') {
2216
int64_t Offs = GA->getOffset();
2217
if (C) Offs += C->getZExtValue();
2218
Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2219
C ? SDLoc(C) : SDLoc(),
2220
Op.getValueType(), Offs));
2224
if (C) { // just C, no GV.
2225
// Simple constants are not allowed for 's'.
2226
if (ConstraintLetter != 's') {
2227
// gcc prints these as sign extended. Sign extend value to 64 bits
2228
// now; without this it would get ZExt'd later in
2229
// ScheduleDAGSDNodes::EmitNode, which is very generic.
2230
Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2231
SDLoc(C), MVT::i64));
2240
std::pair<unsigned, const TargetRegisterClass *>
2241
TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
2242
StringRef Constraint,
2244
if (Constraint.empty() || Constraint[0] != '{')
2245
return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2246
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2248
// Remove the braces from around the name.
2249
StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2251
std::pair<unsigned, const TargetRegisterClass*> R =
2252
std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2254
// Figure out which register class contains this reg.
2255
for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2256
E = RI->regclass_end(); RCI != E; ++RCI) {
2257
const TargetRegisterClass *RC = *RCI;
2259
// If none of the value types for this register class are valid, we
2260
// can't use it. For example, 64-bit reg classes on 32-bit targets.
2264
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2266
if (RegName.equals_lower(RI->getName(*I))) {
2267
std::pair<unsigned, const TargetRegisterClass*> S =
2268
std::make_pair(*I, RC);
2270
// If this register class has the requested value type, return it,
2271
// otherwise keep searching and return the first class found
2272
// if no other is found which explicitly has the requested type.
2273
if (RC->hasType(VT))
2284
//===----------------------------------------------------------------------===//
2285
// Constraint Selection.
2287
/// isMatchingInputConstraint - Return true of this is an input operand that is
2288
/// a matching constraint like "4".
2289
bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2290
assert(!ConstraintCode.empty() && "No known constraint!");
2291
return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2294
/// getMatchedOperand - If this is an input matching constraint, this method
2295
/// returns the output operand it matches.
2296
unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2297
assert(!ConstraintCode.empty() && "No known constraint!");
2298
return atoi(ConstraintCode.c_str());
2302
/// ParseConstraints - Split up the constraint string from the inline
2303
/// assembly value into the specific constraints and their prefixes,
2304
/// and also tie in the associated operand values.
2305
/// If this returns an empty vector, and if the constraint string itself
2306
/// isn't empty, there was an error parsing.
2307
TargetLowering::AsmOperandInfoVector
2308
TargetLowering::ParseConstraints(const DataLayout &DL,
2309
const TargetRegisterInfo *TRI,
2310
ImmutableCallSite CS) const {
2311
/// ConstraintOperands - Information about all of the constraints.
2312
AsmOperandInfoVector ConstraintOperands;
2313
const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2314
unsigned maCount = 0; // Largest number of multiple alternative constraints.
2316
// Do a prepass over the constraints, canonicalizing them, and building up the
2317
// ConstraintOperands list.
2318
unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2319
unsigned ResNo = 0; // ResNo - The result number of the next output.
2321
for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
2322
ConstraintOperands.emplace_back(std::move(CI));
2323
AsmOperandInfo &OpInfo = ConstraintOperands.back();
2325
// Update multiple alternative constraint count.
2326
if (OpInfo.multipleAlternatives.size() > maCount)
2327
maCount = OpInfo.multipleAlternatives.size();
2329
OpInfo.ConstraintVT = MVT::Other;
2331
// Compute the value type for each operand.
2332
switch (OpInfo.Type) {
2333
case InlineAsm::isOutput:
2334
// Indirect outputs just consume an argument.
2335
if (OpInfo.isIndirect) {
2336
OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2340
// The return value of the call is this value. As such, there is no
2341
// corresponding argument.
2342
assert(!CS.getType()->isVoidTy() &&
2344
if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2345
OpInfo.ConstraintVT =
2346
getSimpleValueType(DL, STy->getElementType(ResNo));
2348
assert(ResNo == 0 && "Asm only has one result!");
2349
OpInfo.ConstraintVT = getSimpleValueType(DL, CS.getType());
2353
case InlineAsm::isInput:
2354
OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2356
case InlineAsm::isClobber:
2361
if (OpInfo.CallOperandVal) {
2362
llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2363
if (OpInfo.isIndirect) {
2364
llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2366
report_fatal_error("Indirect operand for inline asm not a pointer!");
2367
OpTy = PtrTy->getElementType();
2370
// Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2371
if (StructType *STy = dyn_cast<StructType>(OpTy))
2372
if (STy->getNumElements() == 1)
2373
OpTy = STy->getElementType(0);
2375
// If OpTy is not a single value, it may be a struct/union that we
2376
// can tile with integers.
2377
if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2378
unsigned BitSize = DL.getTypeSizeInBits(OpTy);
2387
OpInfo.ConstraintVT =
2388
MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2391
} else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2392
unsigned PtrSize = DL.getPointerSizeInBits(PT->getAddressSpace());
2393
OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2395
OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2400
// If we have multiple alternative constraints, select the best alternative.
2401
if (!ConstraintOperands.empty()) {
2403
unsigned bestMAIndex = 0;
2404
int bestWeight = -1;
2405
// weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2408
// Compute the sums of the weights for each alternative, keeping track
2409
// of the best (highest weight) one so far.
2410
for (maIndex = 0; maIndex < maCount; ++maIndex) {
2412
for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2413
cIndex != eIndex; ++cIndex) {
2414
AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2415
if (OpInfo.Type == InlineAsm::isClobber)
2418
// If this is an output operand with a matching input operand,
2419
// look up the matching input. If their types mismatch, e.g. one
2420
// is an integer, the other is floating point, or their sizes are
2421
// different, flag it as an maCantMatch.
2422
if (OpInfo.hasMatchingInput()) {
2423
AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2424
if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2425
if ((OpInfo.ConstraintVT.isInteger() !=
2426
Input.ConstraintVT.isInteger()) ||
2427
(OpInfo.ConstraintVT.getSizeInBits() !=
2428
Input.ConstraintVT.getSizeInBits())) {
2429
weightSum = -1; // Can't match.
2434
weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2439
weightSum += weight;
2442
if (weightSum > bestWeight) {
2443
bestWeight = weightSum;
2444
bestMAIndex = maIndex;
2448
// Now select chosen alternative in each constraint.
2449
for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2450
cIndex != eIndex; ++cIndex) {
2451
AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2452
if (cInfo.Type == InlineAsm::isClobber)
2454
cInfo.selectAlternative(bestMAIndex);
2459
// Check and hook up tied operands, choose constraint code to use.
2460
for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2461
cIndex != eIndex; ++cIndex) {
2462
AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2464
// If this is an output operand with a matching input operand, look up the
2465
// matching input. If their types mismatch, e.g. one is an integer, the
2466
// other is floating point, or their sizes are different, flag it as an
2468
if (OpInfo.hasMatchingInput()) {
2469
AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2471
if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2472
std::pair<unsigned, const TargetRegisterClass *> MatchRC =
2473
getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
2474
OpInfo.ConstraintVT);
2475
std::pair<unsigned, const TargetRegisterClass *> InputRC =
2476
getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
2477
Input.ConstraintVT);
2478
if ((OpInfo.ConstraintVT.isInteger() !=
2479
Input.ConstraintVT.isInteger()) ||
2480
(MatchRC.second != InputRC.second)) {
2481
report_fatal_error("Unsupported asm: input constraint"
2482
" with a matching output constraint of"
2483
" incompatible type!");
2490
return ConstraintOperands;
2494
/// getConstraintGenerality - Return an integer indicating how general CT
2496
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2498
case TargetLowering::C_Other:
2499
case TargetLowering::C_Unknown:
2501
case TargetLowering::C_Register:
2503
case TargetLowering::C_RegisterClass:
2505
case TargetLowering::C_Memory:
2508
llvm_unreachable("Invalid constraint type");
2511
/// Examine constraint type and operand type and determine a weight value.
2512
/// This object must already have been set up with the operand type
2513
/// and the current alternative constraint selected.
2514
TargetLowering::ConstraintWeight
2515
TargetLowering::getMultipleConstraintMatchWeight(
2516
AsmOperandInfo &info, int maIndex) const {
2517
InlineAsm::ConstraintCodeVector *rCodes;
2518
if (maIndex >= (int)info.multipleAlternatives.size())
2519
rCodes = &info.Codes;
2521
rCodes = &info.multipleAlternatives[maIndex].Codes;
2522
ConstraintWeight BestWeight = CW_Invalid;
2524
// Loop over the options, keeping track of the most general one.
2525
for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2526
ConstraintWeight weight =
2527
getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2528
if (weight > BestWeight)
2529
BestWeight = weight;
2535
/// Examine constraint type and operand type and determine a weight value.
2536
/// This object must already have been set up with the operand type
2537
/// and the current alternative constraint selected.
2538
TargetLowering::ConstraintWeight
2539
TargetLowering::getSingleConstraintMatchWeight(
2540
AsmOperandInfo &info, const char *constraint) const {
2541
ConstraintWeight weight = CW_Invalid;
2542
Value *CallOperandVal = info.CallOperandVal;
2543
// If we don't have a value, we can't do a match,
2544
// but allow it at the lowest weight.
2545
if (!CallOperandVal)
2547
// Look at the constraint type.
2548
switch (*constraint) {
2549
case 'i': // immediate integer.
2550
case 'n': // immediate integer with a known value.
2551
if (isa<ConstantInt>(CallOperandVal))
2552
weight = CW_Constant;
2554
case 's': // non-explicit intregal immediate.
2555
if (isa<GlobalValue>(CallOperandVal))
2556
weight = CW_Constant;
2558
case 'E': // immediate float if host format.
2559
case 'F': // immediate float.
2560
if (isa<ConstantFP>(CallOperandVal))
2561
weight = CW_Constant;
2563
case '<': // memory operand with autodecrement.
2564
case '>': // memory operand with autoincrement.
2565
case 'm': // memory operand.
2566
case 'o': // offsettable memory operand
2567
case 'V': // non-offsettable memory operand
2570
case 'r': // general register.
2571
case 'g': // general register, memory operand or immediate integer.
2572
// note: Clang converts "g" to "imr".
2573
if (CallOperandVal->getType()->isIntegerTy())
2574
weight = CW_Register;
2576
case 'X': // any operand.
2578
weight = CW_Default;
2584
/// ChooseConstraint - If there are multiple different constraints that we
2585
/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2586
/// This is somewhat tricky: constraints fall into four classes:
2587
/// Other -> immediates and magic values
2588
/// Register -> one specific register
2589
/// RegisterClass -> a group of regs
2590
/// Memory -> memory
2591
/// Ideally, we would pick the most specific constraint possible: if we have
2592
/// something that fits into a register, we would pick it. The problem here
2593
/// is that if we have something that could either be in a register or in
2594
/// memory that use of the register could cause selection of *other*
2595
/// operands to fail: they might only succeed if we pick memory. Because of
2596
/// this the heuristic we use is:
2598
/// 1) If there is an 'other' constraint, and if the operand is valid for
2599
/// that constraint, use it. This makes us take advantage of 'i'
2600
/// constraints when available.
2601
/// 2) Otherwise, pick the most general constraint present. This prefers
2602
/// 'm' over 'r', for example.
2604
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2605
const TargetLowering &TLI,
2606
SDValue Op, SelectionDAG *DAG) {
2607
assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2608
unsigned BestIdx = 0;
2609
TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2610
int BestGenerality = -1;
2612
// Loop over the options, keeping track of the most general one.
2613
for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2614
TargetLowering::ConstraintType CType =
2615
TLI.getConstraintType(OpInfo.Codes[i]);
2617
// If this is an 'other' constraint, see if the operand is valid for it.
2618
// For example, on X86 we might have an 'rI' constraint. If the operand
2619
// is an integer in the range [0..31] we want to use I (saving a load
2620
// of a register), otherwise we must use 'r'.
2621
if (CType == TargetLowering::C_Other && Op.getNode()) {
2622
assert(OpInfo.Codes[i].size() == 1 &&
2623
"Unhandled multi-letter 'other' constraint");
2624
std::vector<SDValue> ResultOps;
2625
TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2627
if (!ResultOps.empty()) {
2634
// Things with matching constraints can only be registers, per gcc
2635
// documentation. This mainly affects "g" constraints.
2636
if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2639
// This constraint letter is more general than the previous one, use it.
2640
int Generality = getConstraintGenerality(CType);
2641
if (Generality > BestGenerality) {
2644
BestGenerality = Generality;
2648
OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2649
OpInfo.ConstraintType = BestType;
2652
/// ComputeConstraintToUse - Determines the constraint code and constraint
2653
/// type to use for the specific AsmOperandInfo, setting
2654
/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2655
void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2657
SelectionDAG *DAG) const {
2658
assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2660
// Single-letter constraints ('r') are very common.
2661
if (OpInfo.Codes.size() == 1) {
2662
OpInfo.ConstraintCode = OpInfo.Codes[0];
2663
OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2665
ChooseConstraint(OpInfo, *this, Op, DAG);
2668
// 'X' matches anything.
2669
if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2670
// Labels and constants are handled elsewhere ('X' is the only thing
2671
// that matches labels). For Functions, the type here is the type of
2672
// the result, which is not what we want to look at; leave them alone.
2673
Value *v = OpInfo.CallOperandVal;
2674
if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2675
OpInfo.CallOperandVal = v;
2679
// Otherwise, try to resolve it to something we know about by looking at
2680
// the actual operand type.
2681
if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2682
OpInfo.ConstraintCode = Repl;
2683
OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2688
/// \brief Given an exact SDIV by a constant, create a multiplication
2689
/// with the multiplicative inverse of the constant.
2690
static SDValue BuildExactSDIV(const TargetLowering &TLI, SDValue Op1, APInt d,
2691
SDLoc dl, SelectionDAG &DAG,
2692
std::vector<SDNode *> &Created) {
2693
assert(d != 0 && "Division by zero!");
2695
// Shift the value upfront if it is even, so the LSB is one.
2696
unsigned ShAmt = d.countTrailingZeros();
2698
// TODO: For UDIV use SRL instead of SRA.
2700
DAG.getConstant(ShAmt, dl, TLI.getShiftAmountTy(Op1.getValueType(),
2701
DAG.getDataLayout()));
2703
Flags.setExact(true);
2704
Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, &Flags);
2705
Created.push_back(Op1.getNode());
2709
// Calculate the multiplicative inverse, using Newton's method.
2711
while ((t = d*xn) != 1)
2712
xn *= APInt(d.getBitWidth(), 2) - t;
2714
SDValue Op2 = DAG.getConstant(xn, dl, Op1.getValueType());
2715
SDValue Mul = DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2716
Created.push_back(Mul.getNode());
2720
/// \brief Given an ISD::SDIV node expressing a divide by constant,
2721
/// return a DAG expression to select that will generate the same value by
2722
/// multiplying by a magic number.
2723
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2724
SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
2725
SelectionDAG &DAG, bool IsAfterLegalization,
2726
std::vector<SDNode *> *Created) const {
2727
assert(Created && "No vector to hold sdiv ops.");
2729
EVT VT = N->getValueType(0);
2732
// Check to see if we can do this.
2733
// FIXME: We should be more aggressive here.
2734
if (!isTypeLegal(VT))
2737
// If the sdiv has an 'exact' bit we can use a simpler lowering.
2738
if (cast<BinaryWithFlagsSDNode>(N)->Flags.hasExact())
2739
return BuildExactSDIV(*this, N->getOperand(0), Divisor, dl, DAG, *Created);
2741
APInt::ms magics = Divisor.magic();
2743
// Multiply the numerator (operand 0) by the magic value
2744
// FIXME: We should support doing a MUL in a wider type
2746
if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2747
isOperationLegalOrCustom(ISD::MULHS, VT))
2748
Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2749
DAG.getConstant(magics.m, dl, VT));
2750
else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2751
isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2752
Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2754
DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2756
return SDValue(); // No mulhs or equvialent
2757
// If d > 0 and m < 0, add the numerator
2758
if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2759
Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2760
Created->push_back(Q.getNode());
2762
// If d < 0 and m > 0, subtract the numerator.
2763
if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2764
Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2765
Created->push_back(Q.getNode());
2767
auto &DL = DAG.getDataLayout();
2768
// Shift right algebraic if shift value is nonzero
2771
ISD::SRA, dl, VT, Q,
2772
DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL)));
2773
Created->push_back(Q.getNode());
2775
// Extract the sign bit and add it to the quotient
2777
DAG.getNode(ISD::SRL, dl, VT, Q,
2778
DAG.getConstant(VT.getScalarSizeInBits() - 1, dl,
2779
getShiftAmountTy(Q.getValueType(), DL)));
2780
Created->push_back(T.getNode());
2781
return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2784
/// \brief Given an ISD::UDIV node expressing a divide by constant,
2785
/// return a DAG expression to select that will generate the same value by
2786
/// multiplying by a magic number.
2787
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2788
SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
2789
SelectionDAG &DAG, bool IsAfterLegalization,
2790
std::vector<SDNode *> *Created) const {
2791
assert(Created && "No vector to hold udiv ops.");
2793
EVT VT = N->getValueType(0);
2795
auto &DL = DAG.getDataLayout();
2797
// Check to see if we can do this.
2798
// FIXME: We should be more aggressive here.
2799
if (!isTypeLegal(VT))
2802
// FIXME: We should use a narrower constant when the upper
2803
// bits are known to be zero.
2804
APInt::mu magics = Divisor.magicu();
2806
SDValue Q = N->getOperand(0);
2808
// If the divisor is even, we can avoid using the expensive fixup by shifting
2809
// the divided value upfront.
2810
if (magics.a != 0 && !Divisor[0]) {
2811
unsigned Shift = Divisor.countTrailingZeros();
2813
ISD::SRL, dl, VT, Q,
2814
DAG.getConstant(Shift, dl, getShiftAmountTy(Q.getValueType(), DL)));
2815
Created->push_back(Q.getNode());
2817
// Get magic number for the shifted divisor.
2818
magics = Divisor.lshr(Shift).magicu(Shift);
2819
assert(magics.a == 0 && "Should use cheap fixup now");
2822
// Multiply the numerator (operand 0) by the magic value
2823
// FIXME: We should support doing a MUL in a wider type
2824
if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2825
isOperationLegalOrCustom(ISD::MULHU, VT))
2826
Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT));
2827
else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2828
isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2829
Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2830
DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2832
return SDValue(); // No mulhu or equvialent
2834
Created->push_back(Q.getNode());
2836
if (magics.a == 0) {
2837
assert(magics.s < Divisor.getBitWidth() &&
2838
"We shouldn't generate an undefined shift!");
2840
ISD::SRL, dl, VT, Q,
2841
DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL)));
2843
SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2844
Created->push_back(NPQ.getNode());
2846
ISD::SRL, dl, VT, NPQ,
2847
DAG.getConstant(1, dl, getShiftAmountTy(NPQ.getValueType(), DL)));
2848
Created->push_back(NPQ.getNode());
2849
NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2850
Created->push_back(NPQ.getNode());
2852
ISD::SRL, dl, VT, NPQ,
2853
DAG.getConstant(magics.s - 1, dl,
2854
getShiftAmountTy(NPQ.getValueType(), DL)));
2858
bool TargetLowering::
2859
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2860
if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2861
DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2862
"be a constant integer");
2869
//===----------------------------------------------------------------------===//
2870
// Legalization Utilities
2871
//===----------------------------------------------------------------------===//
2873
bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2874
SelectionDAG &DAG, SDValue LL, SDValue LH,
2875
SDValue RL, SDValue RH) const {
2876
EVT VT = N->getValueType(0);
2879
bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2880
bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2881
bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2882
bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2883
if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2884
unsigned OuterBitSize = VT.getSizeInBits();
2885
unsigned InnerBitSize = HiLoVT.getSizeInBits();
2886
unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2887
unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2889
// LL, LH, RL, and RH must be either all NULL or all set to a value.
2890
assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2891
(!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2893
if (!LL.getNode() && !RL.getNode() &&
2894
isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2895
LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2896
RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2902
APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2903
if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2904
DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2905
// The inputs are both zero-extended.
2907
// We can emit a umul_lohi.
2908
Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2910
Hi = SDValue(Lo.getNode(), 1);
2914
// We can emit a mulhu+mul.
2915
Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2916
Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2920
if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2921
// The input values are both sign-extended.
2923
// We can emit a smul_lohi.
2924
Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2926
Hi = SDValue(Lo.getNode(), 1);
2930
// We can emit a mulhs+mul.
2931
Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2932
Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2937
if (!LH.getNode() && !RH.getNode() &&
2938
isOperationLegalOrCustom(ISD::SRL, VT) &&
2939
isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2940
auto &DL = DAG.getDataLayout();
2941
unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2942
SDValue Shift = DAG.getConstant(ShiftAmt, dl, getShiftAmountTy(VT, DL));
2943
LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2944
LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2945
RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2946
RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2953
// Lo,Hi = umul LHS, RHS.
2954
SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2955
DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2957
Hi = UMulLOHI.getValue(1);
2958
RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2959
LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2960
Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2961
Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2965
Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2966
Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2967
RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2968
LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2969
Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2970
Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2977
bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
2978
SelectionDAG &DAG) const {
2979
EVT VT = Node->getOperand(0).getValueType();
2980
EVT NVT = Node->getValueType(0);
2981
SDLoc dl(SDValue(Node, 0));
2983
// FIXME: Only f32 to i64 conversions are supported.
2984
if (VT != MVT::f32 || NVT != MVT::i64)
2987
// Expand f32 -> i64 conversion
2988
// This algorithm comes from compiler-rt's implementation of fixsfdi:
2989
// https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2990
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2991
VT.getSizeInBits());
2992
SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
2993
SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
2994
SDValue Bias = DAG.getConstant(127, dl, IntVT);
2995
SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl,
2997
SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT);
2998
SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
3000
SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
3002
auto &DL = DAG.getDataLayout();
3003
SDValue ExponentBits = DAG.getNode(
3004
ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
3005
DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT, DL)));
3006
SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
3008
SDValue Sign = DAG.getNode(
3009
ISD::SRA, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
3010
DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT, DL)));
3011
Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
3013
SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
3014
DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
3015
DAG.getConstant(0x00800000, dl, IntVT));
3017
R = DAG.getZExtOrTrunc(R, dl, NVT);
3019
R = DAG.getSelectCC(
3020
dl, Exponent, ExponentLoBit,
3021
DAG.getNode(ISD::SHL, dl, NVT, R,
3023
DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
3024
dl, getShiftAmountTy(IntVT, DL))),
3025
DAG.getNode(ISD::SRL, dl, NVT, R,
3027
DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
3028
dl, getShiftAmountTy(IntVT, DL))),
3031
SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
3032
DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
3035
Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT),
3036
DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT);
added
removed
lib/CodeGen/SelectionDAG/TargetLowering.cpp
