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//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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/// \brief Custom DAG lowering for SI
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//===----------------------------------------------------------------------===//
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#define _USE_MATH_DEFINES
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#include "SIISelLowering.h"
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#include "AMDGPUIntrinsicInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/Function.h"
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#include "llvm/ADT/SmallString.h"
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SITargetLowering::SITargetLowering(TargetMachine &TM,
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const AMDGPUSubtarget &STI)
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: AMDGPUTargetLowering(TM, STI) {
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addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
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addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
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addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
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addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
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addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
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addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
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addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
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addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
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addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
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addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
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addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
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addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
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addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
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addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
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addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
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computeRegisterProperties(STI.getRegisterInfo());
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
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setOperationAction(ISD::ADD, MVT::i32, Legal);
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setOperationAction(ISD::ADDC, MVT::i32, Legal);
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setOperationAction(ISD::ADDE, MVT::i32, Legal);
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setOperationAction(ISD::SUBC, MVT::i32, Legal);
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setOperationAction(ISD::SUBE, MVT::i32, Legal);
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setOperationAction(ISD::FSIN, MVT::f32, Custom);
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setOperationAction(ISD::FCOS, MVT::f32, Custom);
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setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
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// We need to custom lower vector stores from local memory
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setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
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setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
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setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
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setOperationAction(ISD::STORE, MVT::v8i32, Custom);
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setOperationAction(ISD::STORE, MVT::v16i32, Custom);
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setOperationAction(ISD::STORE, MVT::i1, Custom);
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setOperationAction(ISD::STORE, MVT::v4i32, Custom);
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setOperationAction(ISD::SELECT, MVT::i64, Custom);
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setOperationAction(ISD::SELECT, MVT::f64, Promote);
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AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
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setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
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setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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for (MVT VT : MVT::integer_valuetypes()) {
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
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for (MVT VT : MVT::integer_vector_valuetypes()) {
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand);
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for (MVT VT : MVT::fp_valuetypes())
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
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setTruncStoreAction(MVT::i64, MVT::i32, Expand);
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setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
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setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
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setOperationAction(ISD::LOAD, MVT::i1, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
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// These should use UDIVREM, so set them to expand
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setOperationAction(ISD::UDIV, MVT::i64, Expand);
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
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setOperationAction(ISD::SELECT, MVT::i1, Promote);
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// We only support LOAD/STORE and vector manipulation ops for vectors
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// with > 4 elements.
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for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32}) {
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for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
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case ISD::BUILD_VECTOR:
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case ISD::EXTRACT_VECTOR_ELT:
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case ISD::INSERT_VECTOR_ELT:
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case ISD::INSERT_SUBVECTOR:
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case ISD::EXTRACT_SUBVECTOR:
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case ISD::CONCAT_VECTORS:
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setOperationAction(Op, VT, Custom);
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setOperationAction(Op, VT, Expand);
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if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
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setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
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setOperationAction(ISD::FCEIL, MVT::f64, Legal);
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setOperationAction(ISD::FRINT, MVT::f64, Legal);
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setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
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setOperationAction(ISD::FDIV, MVT::f32, Custom);
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setOperationAction(ISD::FDIV, MVT::f64, Custom);
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setTargetDAGCombine(ISD::FADD);
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setTargetDAGCombine(ISD::FSUB);
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setTargetDAGCombine(ISD::FMINNUM);
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setTargetDAGCombine(ISD::FMAXNUM);
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setTargetDAGCombine(ISD::SMIN);
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setTargetDAGCombine(ISD::SMAX);
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setTargetDAGCombine(ISD::UMIN);
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setTargetDAGCombine(ISD::UMAX);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::SETCC);
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::UINT_TO_FP);
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// All memory operations. Some folding on the pointer operand is done to help
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// matching the constant offsets in the addressing modes.
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setTargetDAGCombine(ISD::LOAD);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::ATOMIC_LOAD);
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setTargetDAGCombine(ISD::ATOMIC_STORE);
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setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
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setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
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setTargetDAGCombine(ISD::ATOMIC_SWAP);
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setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
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setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
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setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
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setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
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setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
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setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
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setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
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setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
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setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
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setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
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setSchedulingPreference(Sched::RegPressure);
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//===----------------------------------------------------------------------===//
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// TargetLowering queries
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//===----------------------------------------------------------------------===//
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bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
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// SI has some legal vector types, but no legal vector operations. Say no
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// shuffles are legal in order to prefer scalarizing some vector operations.
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bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
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// Flat instructions do not have offsets, and only have the register
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return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
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bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
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const AddrMode &AM, Type *Ty,
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// No global is ever allowed as a base.
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case AMDGPUAS::GLOBAL_ADDRESS:
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if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
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// Assume the we will use FLAT for all global memory accesses
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// FIXME: This assumption is currently wrong. On VI we still use
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// MUBUF instructions for the r + i addressing mode. As currently
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// implemented, the MUBUF instructions only work on buffer < 4GB.
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// It may be possible to support > 4GB buffers with MUBUF instructions,
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// by setting the stride value in the resource descriptor which would
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// increase the size limit to (stride * 4GB). However, this is risky,
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// because it has never been validated.
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return isLegalFlatAddressingMode(AM);
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case AMDGPUAS::PRIVATE_ADDRESS:
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case AMDGPUAS::CONSTANT_ADDRESS: // XXX - Should we assume SMRD instructions?
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case AMDGPUAS::UNKNOWN_ADDRESS_SPACE: {
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// MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
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// additionally can do r + r + i with addr64. 32-bit has more addressing
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// mode options. Depending on the resource constant, it can also do
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// (i64 r0) + (i32 r1) * (i14 i).
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// SMRD instructions have an 8-bit, dword offset.
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// Assume nonunifom access, since the address space isn't enough to know
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// what instruction we will use, and since we don't know if this is a load
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// or store and scalar stores are only available on VI.
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// We also know if we are doing an extload, we can't do a scalar load.
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// Private arrays end up using a scratch buffer most of the time, so also
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// assume those use MUBUF instructions. Scratch loads / stores are currently
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// implemented as mubuf instructions with offen bit set, so slightly
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// different than the normal addr64.
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if (!isUInt<12>(AM.BaseOffs))
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// FIXME: Since we can split immediate into soffset and immediate offset,
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// would it make sense to allow any immediate?
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case 0: // r + i or just i, depending on HasBaseReg.
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return true; // We have r + r or r + i.
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// Allow 2 * r as r + r
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// Or 2 * r + i is allowed as r + r + i.
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default: // Don't allow n * r
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case AMDGPUAS::LOCAL_ADDRESS:
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case AMDGPUAS::REGION_ADDRESS: {
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// Basic, single offset DS instructions allow a 16-bit unsigned immediate
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// XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
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// an 8-bit dword offset but we don't know the alignment here.
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if (!isUInt<16>(AM.BaseOffs))
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if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
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if (AM.Scale == 1 && AM.HasBaseReg)
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case AMDGPUAS::FLAT_ADDRESS:
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return isLegalFlatAddressingMode(AM);
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llvm_unreachable("unhandled address space");
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bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
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bool *IsFast) const {
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// TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
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// which isn't a simple VT.
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if (!VT.isSimple() || VT == MVT::Other)
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// TODO - CI+ supports unaligned memory accesses, but this requires driver
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// XXX - The only mention I see of this in the ISA manual is for LDS direct
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// reads the "byte address and must be dword aligned". Is it also true for the
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// normal loads and stores?
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if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS) {
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// ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
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// aligned, 8 byte access in a single operation using ds_read2/write2_b32
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// with adjacent offsets.
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return Align % 4 == 0;
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// Smaller than dword value must be aligned.
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// FIXME: This should be allowed on CI+
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if (VT.bitsLT(MVT::i32))
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// 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
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// byte-address are ignored, thus forcing Dword alignment.
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// This applies to private, global, and constant memory.
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return VT.bitsGT(MVT::i32) && Align % 4 == 0;
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EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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unsigned SrcAlign, bool IsMemset,
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MachineFunction &MF) const {
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// FIXME: Should account for address space here.
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// The default fallback uses the private pointer size as a guess for a type to
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// use. Make sure we switch these to 64-bit accesses.
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if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
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if (Size >= 8 && DstAlign >= 4)
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TargetLoweringBase::LegalizeTypeAction
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SITargetLowering::getPreferredVectorAction(EVT VT) const {
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if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
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return TypeSplitVector;
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return TargetLoweringBase::getPreferredVectorAction(VT);
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bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
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return TII->isInlineConstant(Imm);
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static EVT toIntegerVT(EVT VT) {
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return VT.changeVectorElementTypeToInteger();
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return MVT::getIntegerVT(VT.getSizeInBits());
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SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
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SDLoc SL, SDValue Chain,
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unsigned Offset, bool Signed) const {
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const DataLayout &DL = DAG.getDataLayout();
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MachineFunction &MF = DAG.getMachineFunction();
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const SIRegisterInfo *TRI =
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static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
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unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
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Type *Ty = VT.getTypeForEVT(*DAG.getContext());
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MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
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MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
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PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
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SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
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MRI.getLiveInVirtReg(InputPtrReg), PtrVT);
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SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
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DAG.getConstant(Offset, SL, PtrVT));
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SDValue PtrOffset = DAG.getUNDEF(PtrVT);
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MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
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unsigned Align = DL.getABITypeAlignment(Ty);
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if (VT != MemVT && VT.isFloatingPoint()) {
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// Do an integer load and convert.
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// FIXME: This is mostly because load legalization after type legalization
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// doesn't handle FP extloads.
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assert(VT.getScalarType() == MVT::f32 &&
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MemVT.getScalarType() == MVT::f16);
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EVT IVT = toIntegerVT(VT);
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EVT MemIVT = toIntegerVT(MemVT);
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SDValue Load = DAG.getLoad(ISD::UNINDEXED, ISD::ZEXTLOAD,
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IVT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemIVT,
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true, // isNonTemporal
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DAG.getNode(ISD::FP16_TO_FP, SL, VT, Load),
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return DAG.getMergeValues(Ops, SL);
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ISD::LoadExtType ExtTy = Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
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return DAG.getLoad(ISD::UNINDEXED, ExtTy,
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VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
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true, // isNonTemporal
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SDValue SITargetLowering::LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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const SIRegisterInfo *TRI =
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static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
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MachineFunction &MF = DAG.getMachineFunction();
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FunctionType *FType = MF.getFunction()->getFunctionType();
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SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
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assert(CallConv == CallingConv::C);
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SmallVector<ISD::InputArg, 16> Splits;
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BitVector Skipped(Ins.size());
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for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
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const ISD::InputArg &Arg = Ins[i];
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// First check if it's a PS input addr
509
if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
510
!Arg.Flags.isByVal()) {
512
assert((PSInputNum <= 15) && "Too many PS inputs!");
515
// We can savely skip PS inputs
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Info->PSInputAddr |= 1 << PSInputNum++;
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// Second split vertices into their elements
525
if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
526
ISD::InputArg NewArg = Arg;
527
NewArg.Flags.setSplit();
528
NewArg.VT = Arg.VT.getVectorElementType();
530
// We REALLY want the ORIGINAL number of vertex elements here, e.g. a
531
// three or five element vertex only needs three or five registers,
532
// NOT four or eigth.
533
Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
534
unsigned NumElements = ParamType->getVectorNumElements();
536
for (unsigned j = 0; j != NumElements; ++j) {
537
Splits.push_back(NewArg);
538
NewArg.PartOffset += NewArg.VT.getStoreSize();
541
} else if (Info->getShaderType() != ShaderType::COMPUTE) {
542
Splits.push_back(Arg);
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SmallVector<CCValAssign, 16> ArgLocs;
547
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
550
// At least one interpolation mode must be enabled or else the GPU will hang.
551
if (Info->getShaderType() == ShaderType::PIXEL &&
552
(Info->PSInputAddr & 0x7F) == 0) {
553
Info->PSInputAddr |= 1;
554
CCInfo.AllocateReg(AMDGPU::VGPR0);
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CCInfo.AllocateReg(AMDGPU::VGPR1);
558
// The pointer to the list of arguments is stored in SGPR0, SGPR1
559
// The pointer to the scratch buffer is stored in SGPR2, SGPR3
560
if (Info->getShaderType() == ShaderType::COMPUTE) {
561
if (Subtarget->isAmdHsaOS())
562
Info->NumUserSGPRs = 2; // FIXME: Need to support scratch buffers.
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Info->NumUserSGPRs = 4;
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unsigned InputPtrReg =
567
TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
568
unsigned InputPtrRegLo =
569
TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 0);
570
unsigned InputPtrRegHi =
571
TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1);
573
unsigned ScratchPtrReg =
574
TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
575
unsigned ScratchPtrRegLo =
576
TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0);
577
unsigned ScratchPtrRegHi =
578
TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1);
580
CCInfo.AllocateReg(InputPtrRegLo);
581
CCInfo.AllocateReg(InputPtrRegHi);
582
CCInfo.AllocateReg(ScratchPtrRegLo);
583
CCInfo.AllocateReg(ScratchPtrRegHi);
584
MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
585
MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass);
588
if (Info->getShaderType() == ShaderType::COMPUTE) {
589
getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
593
AnalyzeFormalArguments(CCInfo, Splits);
595
SmallVector<SDValue, 16> Chains;
597
for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
599
const ISD::InputArg &Arg = Ins[i];
601
InVals.push_back(DAG.getUNDEF(Arg.VT));
605
CCValAssign &VA = ArgLocs[ArgIdx++];
606
MVT VT = VA.getLocVT();
610
EVT MemVT = Splits[i].VT;
611
const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
612
VA.getLocMemOffset();
613
// The first 36 bytes of the input buffer contains information about
614
// thread group and global sizes.
615
SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain,
616
Offset, Ins[i].Flags.isSExt());
617
Chains.push_back(Arg.getValue(1));
619
const PointerType *ParamTy =
620
dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
621
if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
622
ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
623
// On SI local pointers are just offsets into LDS, so they are always
624
// less than 16-bits. On CI and newer they could potentially be
625
// real pointers, so we can't guarantee their size.
626
Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
627
DAG.getValueType(MVT::i16));
630
InVals.push_back(Arg);
631
Info->ABIArgOffset = Offset + MemVT.getStoreSize();
634
assert(VA.isRegLoc() && "Parameter must be in a register!");
636
unsigned Reg = VA.getLocReg();
638
if (VT == MVT::i64) {
639
// For now assume it is a pointer
640
Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
641
&AMDGPU::SReg_64RegClass);
642
Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
643
SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
644
InVals.push_back(Copy);
648
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
650
Reg = MF.addLiveIn(Reg, RC);
651
SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
653
if (Arg.VT.isVector()) {
655
// Build a vector from the registers
656
Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
657
unsigned NumElements = ParamType->getVectorNumElements();
659
SmallVector<SDValue, 4> Regs;
661
for (unsigned j = 1; j != NumElements; ++j) {
662
Reg = ArgLocs[ArgIdx++].getLocReg();
663
Reg = MF.addLiveIn(Reg, RC);
665
SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
666
Regs.push_back(Copy);
669
// Fill up the missing vector elements
670
NumElements = Arg.VT.getVectorNumElements() - NumElements;
671
Regs.append(NumElements, DAG.getUNDEF(VT));
673
InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
677
InVals.push_back(Val);
680
if (Info->getShaderType() != ShaderType::COMPUTE) {
681
unsigned ScratchIdx = CCInfo.getFirstUnallocated(ArrayRef<MCPhysReg>(
682
AMDGPU::SGPR_32RegClass.begin(), AMDGPU::SGPR_32RegClass.getNumRegs()));
683
Info->ScratchOffsetReg = AMDGPU::SGPR_32RegClass.getRegister(ScratchIdx);
689
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
692
MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
693
MachineInstr * MI, MachineBasicBlock * BB) const {
695
MachineBasicBlock::iterator I = *MI;
696
const SIInstrInfo *TII =
697
static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
699
switch (MI->getOpcode()) {
701
return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
704
case AMDGPU::SI_RegisterStorePseudo: {
705
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
706
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
707
MachineInstrBuilder MIB =
708
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
710
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
711
MIB.addOperand(MI->getOperand(i));
713
MI->eraseFromParent();
720
bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
721
// This currently forces unfolding various combinations of fsub into fma with
722
// free fneg'd operands. As long as we have fast FMA (controlled by
723
// isFMAFasterThanFMulAndFAdd), we should perform these.
725
// When fma is quarter rate, for f64 where add / sub are at best half rate,
726
// most of these combines appear to be cycle neutral but save on instruction
727
// count / code size.
731
EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
733
if (!VT.isVector()) {
736
return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
739
MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
743
// Answering this is somewhat tricky and depends on the specific device which
744
// have different rates for fma or all f64 operations.
746
// v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
747
// regardless of which device (although the number of cycles differs between
748
// devices), so it is always profitable for f64.
750
// v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
751
// only on full rate devices. Normally, we should prefer selecting v_mad_f32
752
// which we can always do even without fused FP ops since it returns the same
753
// result as the separate operations and since it is always full
754
// rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
755
// however does not support denormals, so we do report fma as faster if we have
756
// a fast fma device and require denormals.
758
bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
759
VT = VT.getScalarType();
764
switch (VT.getSimpleVT().SimpleTy) {
766
// This is as fast on some subtargets. However, we always have full rate f32
767
// mad available which returns the same result as the separate operations
768
// which we should prefer over fma. We can't use this if we want to support
769
// denormals, so only report this in these cases.
770
return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();
780
//===----------------------------------------------------------------------===//
781
// Custom DAG Lowering Operations
782
//===----------------------------------------------------------------------===//
784
SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
785
switch (Op.getOpcode()) {
786
default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
787
case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
788
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
790
SDValue Result = LowerLOAD(Op, DAG);
791
assert((!Result.getNode() ||
792
Result.getNode()->getNumValues() == 2) &&
793
"Load should return a value and a chain");
799
return LowerTrig(Op, DAG);
800
case ISD::SELECT: return LowerSELECT(Op, DAG);
801
case ISD::FDIV: return LowerFDIV(Op, DAG);
802
case ISD::STORE: return LowerSTORE(Op, DAG);
803
case ISD::GlobalAddress: {
804
MachineFunction &MF = DAG.getMachineFunction();
805
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
806
return LowerGlobalAddress(MFI, Op, DAG);
808
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
809
case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
814
/// \brief Helper function for LowerBRCOND
815
static SDNode *findUser(SDValue Value, unsigned Opcode) {
817
SDNode *Parent = Value.getNode();
818
for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
821
if (I.getUse().get() != Value)
824
if (I->getOpcode() == Opcode)
830
SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
833
FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
834
unsigned FrameIndex = FINode->getIndex();
836
// A FrameIndex node represents a 32-bit offset into scratch memory. If
837
// the high bit of a frame index offset were to be set, this would mean
838
// that it represented an offset of ~2GB * 64 = ~128GB from the start of the
839
// scratch buffer, with 64 being the number of threads per wave.
841
// If we know the machine uses less than 128GB of scratch, then we can
842
// amrk the high bit of the FrameIndex node as known zero,
843
// which is important, because it means in most situations we can
844
// prove that values derived from FrameIndex nodes are non-negative.
845
// This enables us to take advantage of more addressing modes when
846
// accessing scratch buffers, since for scratch reads/writes, the register
847
// offset must always be positive.
849
SDValue TFI = DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
850
if (Subtarget->enableHugeScratchBuffer())
853
return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI,
854
DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 31)));
857
/// This transforms the control flow intrinsics to get the branch destination as
858
/// last parameter, also switches branch target with BR if the need arise
859
SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
860
SelectionDAG &DAG) const {
864
SDNode *Intr = BRCOND.getOperand(1).getNode();
865
SDValue Target = BRCOND.getOperand(2);
866
SDNode *BR = nullptr;
868
if (Intr->getOpcode() == ISD::SETCC) {
869
// As long as we negate the condition everything is fine
870
SDNode *SetCC = Intr;
871
assert(SetCC->getConstantOperandVal(1) == 1);
872
assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
874
Intr = SetCC->getOperand(0).getNode();
877
// Get the target from BR if we don't negate the condition
878
BR = findUser(BRCOND, ISD::BR);
879
Target = BR->getOperand(1);
882
assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
884
// Build the result and
885
ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
887
// operands of the new intrinsic call
888
SmallVector<SDValue, 4> Ops;
889
Ops.push_back(BRCOND.getOperand(0));
890
Ops.append(Intr->op_begin() + 1, Intr->op_end());
891
Ops.push_back(Target);
893
// build the new intrinsic call
894
SDNode *Result = DAG.getNode(
895
Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
896
DAG.getVTList(Res), Ops).getNode();
899
// Give the branch instruction our target
904
SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
905
DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
906
BR = NewBR.getNode();
909
SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
911
// Copy the intrinsic results to registers
912
for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
913
SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
917
Chain = DAG.getCopyToReg(
919
CopyToReg->getOperand(1),
920
SDValue(Result, i - 1),
923
DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
926
// Remove the old intrinsic from the chain
927
DAG.ReplaceAllUsesOfValueWith(
928
SDValue(Intr, Intr->getNumValues() - 1),
929
Intr->getOperand(0));
934
SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
936
SelectionDAG &DAG) const {
937
GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
939
if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
940
return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
943
const GlobalValue *GV = GSD->getGlobal();
944
MVT PtrVT = getPointerTy(DAG.getDataLayout(), GSD->getAddressSpace());
946
SDValue Ptr = DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT);
947
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
949
SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
950
DAG.getConstant(0, DL, MVT::i32));
951
SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
952
DAG.getConstant(1, DL, MVT::i32));
954
SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue),
956
SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue),
957
PtrHi, DAG.getConstant(0, DL, MVT::i32),
958
SDValue(Lo.getNode(), 1));
959
return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
962
SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
964
// We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
965
// so we will end up with redundant moves to m0.
967
// We can't use S_MOV_B32, because there is no way to specify m0 as the
968
// destination register.
970
// We have to use them both. Machine cse will combine all the S_MOV_B32
971
// instructions and the register coalescer eliminate the extra copies.
972
SDNode *M0 = DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, V.getValueType(), V);
973
return DAG.getCopyToReg(Chain, DL, DAG.getRegister(AMDGPU::M0, MVT::i32),
974
SDValue(M0, 0), SDValue()); // Glue
975
// A Null SDValue creates
979
SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
980
SelectionDAG &DAG) const {
981
MachineFunction &MF = DAG.getMachineFunction();
982
auto MFI = MF.getInfo<SIMachineFunctionInfo>();
983
const SIRegisterInfo *TRI =
984
static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
986
EVT VT = Op.getValueType();
988
unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
990
switch (IntrinsicID) {
991
case Intrinsic::r600_read_ngroups_x:
992
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
993
SI::KernelInputOffsets::NGROUPS_X, false);
994
case Intrinsic::r600_read_ngroups_y:
995
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
996
SI::KernelInputOffsets::NGROUPS_Y, false);
997
case Intrinsic::r600_read_ngroups_z:
998
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
999
SI::KernelInputOffsets::NGROUPS_Z, false);
1000
case Intrinsic::r600_read_global_size_x:
1001
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1002
SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
1003
case Intrinsic::r600_read_global_size_y:
1004
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1005
SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
1006
case Intrinsic::r600_read_global_size_z:
1007
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1008
SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
1009
case Intrinsic::r600_read_local_size_x:
1010
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1011
SI::KernelInputOffsets::LOCAL_SIZE_X, false);
1012
case Intrinsic::r600_read_local_size_y:
1013
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1014
SI::KernelInputOffsets::LOCAL_SIZE_Y, false);
1015
case Intrinsic::r600_read_local_size_z:
1016
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1017
SI::KernelInputOffsets::LOCAL_SIZE_Z, false);
1019
case Intrinsic::AMDGPU_read_workdim:
1020
return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1021
getImplicitParameterOffset(MFI, GRID_DIM), false);
1023
case Intrinsic::r600_read_tgid_x:
1024
return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1025
TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_X), VT);
1026
case Intrinsic::r600_read_tgid_y:
1027
return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1028
TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Y), VT);
1029
case Intrinsic::r600_read_tgid_z:
1030
return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1031
TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Z), VT);
1032
case Intrinsic::r600_read_tidig_x:
1033
return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1034
TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_X), VT);
1035
case Intrinsic::r600_read_tidig_y:
1036
return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1037
TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Y), VT);
1038
case Intrinsic::r600_read_tidig_z:
1039
return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1040
TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Z), VT);
1041
case AMDGPUIntrinsic::SI_load_const: {
1047
MachineMemOperand *MMO = MF.getMachineMemOperand(
1048
MachinePointerInfo(),
1049
MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
1050
VT.getStoreSize(), 4);
1051
return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
1052
Op->getVTList(), Ops, VT, MMO);
1054
case AMDGPUIntrinsic::SI_sample:
1055
return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
1056
case AMDGPUIntrinsic::SI_sampleb:
1057
return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
1058
case AMDGPUIntrinsic::SI_sampled:
1059
return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
1060
case AMDGPUIntrinsic::SI_samplel:
1061
return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
1062
case AMDGPUIntrinsic::SI_vs_load_input:
1063
return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
1068
case AMDGPUIntrinsic::AMDGPU_fract:
1069
case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
1070
return DAG.getNode(ISD::FSUB, DL, VT, Op.getOperand(1),
1071
DAG.getNode(ISD::FFLOOR, DL, VT, Op.getOperand(1)));
1072
case AMDGPUIntrinsic::SI_fs_constant: {
1073
SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1074
SDValue Glue = M0.getValue(1);
1075
return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
1076
DAG.getConstant(2, DL, MVT::i32), // P0
1077
Op.getOperand(1), Op.getOperand(2), Glue);
1079
case AMDGPUIntrinsic::SI_fs_interp: {
1080
SDValue IJ = Op.getOperand(4);
1081
SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1082
DAG.getConstant(0, DL, MVT::i32));
1083
SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1084
DAG.getConstant(1, DL, MVT::i32));
1085
SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1086
SDValue Glue = M0.getValue(1);
1087
SDValue P1 = DAG.getNode(AMDGPUISD::INTERP_P1, DL,
1088
DAG.getVTList(MVT::f32, MVT::Glue),
1089
I, Op.getOperand(1), Op.getOperand(2), Glue);
1090
Glue = SDValue(P1.getNode(), 1);
1091
return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, P1, J,
1092
Op.getOperand(1), Op.getOperand(2), Glue);
1095
return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1099
SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1100
SelectionDAG &DAG) const {
1101
MachineFunction &MF = DAG.getMachineFunction();
1103
SDValue Chain = Op.getOperand(0);
1104
unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1106
switch (IntrinsicID) {
1107
case AMDGPUIntrinsic::SI_sendmsg: {
1108
Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
1109
SDValue Glue = Chain.getValue(1);
1110
return DAG.getNode(AMDGPUISD::SENDMSG, DL, MVT::Other, Chain,
1111
Op.getOperand(2), Glue);
1113
case AMDGPUIntrinsic::SI_tbuffer_store: {
1131
EVT VT = Op.getOperand(3).getValueType();
1133
MachineMemOperand *MMO = MF.getMachineMemOperand(
1134
MachinePointerInfo(),
1135
MachineMemOperand::MOStore,
1136
VT.getStoreSize(), 4);
1137
return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
1138
Op->getVTList(), Ops, VT, MMO);
1145
SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1147
LoadSDNode *Load = cast<LoadSDNode>(Op);
1149
if (Op.getValueType().isVector()) {
1150
assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
1151
"Custom lowering for non-i32 vectors hasn't been implemented.");
1152
unsigned NumElements = Op.getValueType().getVectorNumElements();
1153
assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
1154
switch (Load->getAddressSpace()) {
1156
case AMDGPUAS::GLOBAL_ADDRESS:
1157
case AMDGPUAS::PRIVATE_ADDRESS:
1158
// v4 loads are supported for private and global memory.
1159
if (NumElements <= 4)
1162
case AMDGPUAS::LOCAL_ADDRESS:
1163
return ScalarizeVectorLoad(Op, DAG);
1167
return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1170
SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
1172
SelectionDAG &DAG) const {
1173
return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
1179
SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1180
if (Op.getValueType() != MVT::i64)
1184
SDValue Cond = Op.getOperand(0);
1186
SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1187
SDValue One = DAG.getConstant(1, DL, MVT::i32);
1189
SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1190
SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1192
SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1193
SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1195
SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1197
SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1198
SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1200
SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1202
SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1203
return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1206
// Catch division cases where we can use shortcuts with rcp and rsq
1208
SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1210
SDValue LHS = Op.getOperand(0);
1211
SDValue RHS = Op.getOperand(1);
1212
EVT VT = Op.getValueType();
1213
bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1215
if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1216
if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1217
CLHS->isExactlyValue(1.0)) {
1218
// v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1219
// the CI documentation has a worst case error of 1 ulp.
1220
// OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1221
// use it as long as we aren't trying to use denormals.
1223
// 1.0 / sqrt(x) -> rsq(x)
1225
// XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1226
// error seems really high at 2^29 ULP.
1227
if (RHS.getOpcode() == ISD::FSQRT)
1228
return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1230
// 1.0 / x -> rcp(x)
1231
return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1236
// Turn into multiply by the reciprocal.
1237
// x / y -> x * (1.0 / y)
1238
SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1239
return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip);
1245
SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1246
SDValue FastLowered = LowerFastFDIV(Op, DAG);
1247
if (FastLowered.getNode())
1250
// This uses v_rcp_f32 which does not handle denormals. Let this hit a
1251
// selection error for now rather than do something incorrect.
1252
if (Subtarget->hasFP32Denormals())
1256
SDValue LHS = Op.getOperand(0);
1257
SDValue RHS = Op.getOperand(1);
1259
SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1261
const APFloat K0Val(BitsToFloat(0x6f800000));
1262
const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
1264
const APFloat K1Val(BitsToFloat(0x2f800000));
1265
const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
1267
const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
1270
getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
1272
SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1274
SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1276
r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1278
SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1280
SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1282
return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1285
SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1286
if (DAG.getTarget().Options.UnsafeFPMath)
1287
return LowerFastFDIV(Op, DAG);
1290
SDValue X = Op.getOperand(0);
1291
SDValue Y = Op.getOperand(1);
1293
const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1295
SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
1297
SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
1299
SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
1301
SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
1303
SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
1305
SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
1307
SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
1309
SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
1311
SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
1312
SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
1314
SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
1315
NegDivScale0, Mul, DivScale1);
1319
if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1320
// Workaround a hardware bug on SI where the condition output from div_scale
1323
const SDValue Hi = DAG.getConstant(1, SL, MVT::i32);
1325
// Figure out if the scale to use for div_fmas.
1326
SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1327
SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
1328
SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
1329
SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
1331
SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
1332
SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
1335
= DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
1337
= DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
1339
SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
1340
SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
1341
Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
1343
Scale = DivScale1.getValue(1);
1346
SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
1347
Fma4, Fma3, Mul, Scale);
1349
return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
1352
SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1353
EVT VT = Op.getValueType();
1356
return LowerFDIV32(Op, DAG);
1359
return LowerFDIV64(Op, DAG);
1361
llvm_unreachable("Unexpected type for fdiv");
1364
SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1366
StoreSDNode *Store = cast<StoreSDNode>(Op);
1367
EVT VT = Store->getMemoryVT();
1369
// These stores are legal.
1370
if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1371
if (VT.isVector() && VT.getVectorNumElements() > 4)
1372
return ScalarizeVectorStore(Op, DAG);
1376
SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1380
if (VT.isVector() && VT.getVectorNumElements() >= 8)
1381
return ScalarizeVectorStore(Op, DAG);
1384
return DAG.getTruncStore(Store->getChain(), DL,
1385
DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1386
Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1391
SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1393
EVT VT = Op.getValueType();
1394
SDValue Arg = Op.getOperand(0);
1395
SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
1396
DAG.getNode(ISD::FMUL, DL, VT, Arg,
1397
DAG.getConstantFP(0.5/M_PI, DL,
1400
switch (Op.getOpcode()) {
1402
return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1404
return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1406
llvm_unreachable("Wrong trig opcode");
1410
//===----------------------------------------------------------------------===//
1411
// Custom DAG optimizations
1412
//===----------------------------------------------------------------------===//
1414
SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1415
DAGCombinerInfo &DCI) const {
1416
EVT VT = N->getValueType(0);
1417
EVT ScalarVT = VT.getScalarType();
1418
if (ScalarVT != MVT::f32)
1421
SelectionDAG &DAG = DCI.DAG;
1424
SDValue Src = N->getOperand(0);
1425
EVT SrcVT = Src.getValueType();
1427
// TODO: We could try to match extracting the higher bytes, which would be
1428
// easier if i8 vectors weren't promoted to i32 vectors, particularly after
1429
// types are legalized. v4i8 -> v4f32 is probably the only case to worry
1430
// about in practice.
1431
if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1432
if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1433
SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1434
DCI.AddToWorklist(Cvt.getNode());
1439
// We are primarily trying to catch operations on illegal vector types
1440
// before they are expanded.
1441
// For scalars, we can use the more flexible method of checking masked bits
1442
// after legalization.
1443
if (!DCI.isBeforeLegalize() ||
1444
!SrcVT.isVector() ||
1445
SrcVT.getVectorElementType() != MVT::i8) {
1449
assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1451
// Weird sized vectors are a pain to handle, but we know 3 is really the same
1453
unsigned NElts = SrcVT.getVectorNumElements();
1454
if (!SrcVT.isSimple() && NElts != 3)
1457
// Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1458
// prevent a mess from expanding to v4i32 and repacking.
1459
if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1460
EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1461
EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1462
EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1463
LoadSDNode *Load = cast<LoadSDNode>(Src);
1465
unsigned AS = Load->getAddressSpace();
1466
unsigned Align = Load->getAlignment();
1467
Type *Ty = LoadVT.getTypeForEVT(*DAG.getContext());
1468
unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
1470
// Don't try to replace the load if we have to expand it due to alignment
1471
// problems. Otherwise we will end up scalarizing the load, and trying to
1472
// repack into the vector for no real reason.
1473
if (Align < ABIAlignment &&
1474
!allowsMisalignedMemoryAccesses(LoadVT, AS, Align, nullptr)) {
1478
SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1482
Load->getMemOperand());
1484
// Make sure successors of the original load stay after it by updating
1485
// them to use the new Chain.
1486
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1488
SmallVector<SDValue, 4> Elts;
1489
if (RegVT.isVector())
1490
DAG.ExtractVectorElements(NewLoad, Elts);
1492
Elts.push_back(NewLoad);
1494
SmallVector<SDValue, 4> Ops;
1496
unsigned EltIdx = 0;
1497
for (SDValue Elt : Elts) {
1498
unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1499
for (unsigned I = 0; I < ComponentsInElt; ++I) {
1500
unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1501
SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1502
DCI.AddToWorklist(Cvt.getNode());
1509
assert(Ops.size() == NElts);
1511
return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1517
/// \brief Return true if the given offset Size in bytes can be folded into
1518
/// the immediate offsets of a memory instruction for the given address space.
1519
static bool canFoldOffset(unsigned OffsetSize, unsigned AS,
1520
const AMDGPUSubtarget &STI) {
1522
case AMDGPUAS::GLOBAL_ADDRESS: {
1523
// MUBUF instructions a 12-bit offset in bytes.
1524
return isUInt<12>(OffsetSize);
1526
case AMDGPUAS::CONSTANT_ADDRESS: {
1527
// SMRD instructions have an 8-bit offset in dwords on SI and
1528
// a 20-bit offset in bytes on VI.
1529
if (STI.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1530
return isUInt<20>(OffsetSize);
1532
return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1534
case AMDGPUAS::LOCAL_ADDRESS:
1535
case AMDGPUAS::REGION_ADDRESS: {
1536
// The single offset versions have a 16-bit offset in bytes.
1537
return isUInt<16>(OffsetSize);
1539
case AMDGPUAS::PRIVATE_ADDRESS:
1540
// Indirect register addressing does not use any offsets.
1546
// (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
1548
// This is a variant of
1549
// (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
1551
// The normal DAG combiner will do this, but only if the add has one use since
1552
// that would increase the number of instructions.
1554
// This prevents us from seeing a constant offset that can be folded into a
1555
// memory instruction's addressing mode. If we know the resulting add offset of
1556
// a pointer can be folded into an addressing offset, we can replace the pointer
1557
// operand with the add of new constant offset. This eliminates one of the uses,
1558
// and may allow the remaining use to also be simplified.
1560
SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1562
DAGCombinerInfo &DCI) const {
1563
SDValue N0 = N->getOperand(0);
1564
SDValue N1 = N->getOperand(1);
1566
if (N0.getOpcode() != ISD::ADD)
1569
const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
1573
const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1577
// If the resulting offset is too large, we can't fold it into the addressing
1579
APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
1580
if (!canFoldOffset(Offset.getZExtValue(), AddrSpace, *Subtarget))
1583
SelectionDAG &DAG = DCI.DAG;
1585
EVT VT = N->getValueType(0);
1587
SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
1588
SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
1590
return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
1593
SDValue SITargetLowering::performAndCombine(SDNode *N,
1594
DAGCombinerInfo &DCI) const {
1595
if (DCI.isBeforeLegalize())
1598
SelectionDAG &DAG = DCI.DAG;
1600
// (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
1601
// fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
1602
SDValue LHS = N->getOperand(0);
1603
SDValue RHS = N->getOperand(1);
1605
if (LHS.getOpcode() == ISD::SETCC &&
1606
RHS.getOpcode() == ISD::SETCC) {
1607
ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
1608
ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
1610
SDValue X = LHS.getOperand(0);
1611
SDValue Y = RHS.getOperand(0);
1612
if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
1615
if (LCC == ISD::SETO) {
1616
if (X != LHS.getOperand(1))
1619
if (RCC == ISD::SETUNE) {
1620
const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
1621
if (!C1 || !C1->isInfinity() || C1->isNegative())
1624
const uint32_t Mask = SIInstrFlags::N_NORMAL |
1625
SIInstrFlags::N_SUBNORMAL |
1626
SIInstrFlags::N_ZERO |
1627
SIInstrFlags::P_ZERO |
1628
SIInstrFlags::P_SUBNORMAL |
1629
SIInstrFlags::P_NORMAL;
1631
static_assert(((~(SIInstrFlags::S_NAN |
1632
SIInstrFlags::Q_NAN |
1633
SIInstrFlags::N_INFINITY |
1634
SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
1638
return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1639
X, DAG.getConstant(Mask, DL, MVT::i32));
1647
SDValue SITargetLowering::performOrCombine(SDNode *N,
1648
DAGCombinerInfo &DCI) const {
1649
SelectionDAG &DAG = DCI.DAG;
1650
SDValue LHS = N->getOperand(0);
1651
SDValue RHS = N->getOperand(1);
1653
// or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
1654
if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
1655
RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
1656
SDValue Src = LHS.getOperand(0);
1657
if (Src != RHS.getOperand(0))
1660
const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
1661
const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
1665
// Only 10 bits are used.
1666
static const uint32_t MaxMask = 0x3ff;
1668
uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
1670
return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1671
Src, DAG.getConstant(NewMask, DL, MVT::i32));
1677
SDValue SITargetLowering::performClassCombine(SDNode *N,
1678
DAGCombinerInfo &DCI) const {
1679
SelectionDAG &DAG = DCI.DAG;
1680
SDValue Mask = N->getOperand(1);
1682
// fp_class x, 0 -> false
1683
if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
1684
if (CMask->isNullValue())
1685
return DAG.getConstant(0, SDLoc(N), MVT::i1);
1691
static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
1694
return AMDGPUISD::FMAX3;
1696
return AMDGPUISD::SMAX3;
1698
return AMDGPUISD::UMAX3;
1700
return AMDGPUISD::FMIN3;
1702
return AMDGPUISD::SMIN3;
1704
return AMDGPUISD::UMIN3;
1706
llvm_unreachable("Not a min/max opcode");
1710
SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
1711
DAGCombinerInfo &DCI) const {
1712
SelectionDAG &DAG = DCI.DAG;
1714
unsigned Opc = N->getOpcode();
1715
SDValue Op0 = N->getOperand(0);
1716
SDValue Op1 = N->getOperand(1);
1718
// Only do this if the inner op has one use since this will just increases
1719
// register pressure for no benefit.
1721
// max(max(a, b), c)
1722
if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
1724
return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1732
// max(a, max(b, c))
1733
if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
1735
return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1746
SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1747
DAGCombinerInfo &DCI) const {
1748
SelectionDAG &DAG = DCI.DAG;
1751
SDValue LHS = N->getOperand(0);
1752
SDValue RHS = N->getOperand(1);
1753
EVT VT = LHS.getValueType();
1755
if (VT != MVT::f32 && VT != MVT::f64)
1758
// Match isinf pattern
1759
// (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
1760
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1761
if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
1762
const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
1766
const APFloat &APF = CRHS->getValueAPF();
1767
if (APF.isInfinity() && !APF.isNegative()) {
1768
unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
1769
return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0),
1770
DAG.getConstant(Mask, SL, MVT::i32));
1777
SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1778
DAGCombinerInfo &DCI) const {
1779
SelectionDAG &DAG = DCI.DAG;
1782
switch (N->getOpcode()) {
1784
return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1786
return performSetCCCombine(N, DCI);
1787
case ISD::FMAXNUM: // TODO: What about fmax_legacy?
1793
if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
1794
N->getValueType(0) != MVT::f64 &&
1795
getTargetMachine().getOptLevel() > CodeGenOpt::None)
1796
return performMin3Max3Combine(N, DCI);
1800
case AMDGPUISD::CVT_F32_UBYTE0:
1801
case AMDGPUISD::CVT_F32_UBYTE1:
1802
case AMDGPUISD::CVT_F32_UBYTE2:
1803
case AMDGPUISD::CVT_F32_UBYTE3: {
1804
unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1806
SDValue Src = N->getOperand(0);
1807
APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1809
APInt KnownZero, KnownOne;
1810
TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1811
!DCI.isBeforeLegalizeOps());
1812
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1813
if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1814
TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1815
DCI.CommitTargetLoweringOpt(TLO);
1821
case ISD::UINT_TO_FP: {
1822
return performUCharToFloatCombine(N, DCI);
1825
if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1828
EVT VT = N->getValueType(0);
1832
// Only do this if we are not trying to support denormals. v_mad_f32 does
1833
// not support denormals ever.
1834
if (Subtarget->hasFP32Denormals())
1837
SDValue LHS = N->getOperand(0);
1838
SDValue RHS = N->getOperand(1);
1840
// These should really be instruction patterns, but writing patterns with
1841
// source modiifiers is a pain.
1843
// fadd (fadd (a, a), b) -> mad 2.0, a, b
1844
if (LHS.getOpcode() == ISD::FADD) {
1845
SDValue A = LHS.getOperand(0);
1846
if (A == LHS.getOperand(1)) {
1847
const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
1848
return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
1852
// fadd (b, fadd (a, a)) -> mad 2.0, a, b
1853
if (RHS.getOpcode() == ISD::FADD) {
1854
SDValue A = RHS.getOperand(0);
1855
if (A == RHS.getOperand(1)) {
1856
const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
1857
return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
1864
if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1867
EVT VT = N->getValueType(0);
1869
// Try to get the fneg to fold into the source modifier. This undoes generic
1870
// DAG combines and folds them into the mad.
1872
// Only do this if we are not trying to support denormals. v_mad_f32 does
1873
// not support denormals ever.
1874
if (VT == MVT::f32 &&
1875
!Subtarget->hasFP32Denormals()) {
1876
SDValue LHS = N->getOperand(0);
1877
SDValue RHS = N->getOperand(1);
1878
if (LHS.getOpcode() == ISD::FADD) {
1879
// (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
1881
SDValue A = LHS.getOperand(0);
1882
if (A == LHS.getOperand(1)) {
1883
const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
1884
SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
1886
return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
1890
if (RHS.getOpcode() == ISD::FADD) {
1891
// (fsub c, (fadd a, a)) -> mad -2.0, a, c
1893
SDValue A = RHS.getOperand(0);
1894
if (A == RHS.getOperand(1)) {
1895
const SDValue NegTwo = DAG.getConstantFP(-2.0, DL, MVT::f32);
1896
return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
1908
case ISD::ATOMIC_LOAD:
1909
case ISD::ATOMIC_STORE:
1910
case ISD::ATOMIC_CMP_SWAP:
1911
case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
1912
case ISD::ATOMIC_SWAP:
1913
case ISD::ATOMIC_LOAD_ADD:
1914
case ISD::ATOMIC_LOAD_SUB:
1915
case ISD::ATOMIC_LOAD_AND:
1916
case ISD::ATOMIC_LOAD_OR:
1917
case ISD::ATOMIC_LOAD_XOR:
1918
case ISD::ATOMIC_LOAD_NAND:
1919
case ISD::ATOMIC_LOAD_MIN:
1920
case ISD::ATOMIC_LOAD_MAX:
1921
case ISD::ATOMIC_LOAD_UMIN:
1922
case ISD::ATOMIC_LOAD_UMAX: { // TODO: Target mem intrinsics.
1923
if (DCI.isBeforeLegalize())
1926
MemSDNode *MemNode = cast<MemSDNode>(N);
1927
SDValue Ptr = MemNode->getBasePtr();
1929
// TODO: We could also do this for multiplies.
1930
unsigned AS = MemNode->getAddressSpace();
1931
if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
1932
SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
1934
SmallVector<SDValue, 8> NewOps(MemNode->op_begin(), MemNode->op_end());
1936
NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
1937
return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
1943
return performAndCombine(N, DCI);
1945
return performOrCombine(N, DCI);
1946
case AMDGPUISD::FP_CLASS:
1947
return performClassCombine(N, DCI);
1949
return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1952
/// \brief Analyze the possible immediate value Op
1954
/// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1955
/// and the immediate value if it's a literal immediate
1956
int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1958
const SIInstrInfo *TII =
1959
static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1961
if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1962
if (TII->isInlineConstant(Node->getAPIntValue()))
1965
uint64_t Val = Node->getZExtValue();
1966
return isUInt<32>(Val) ? Val : -1;
1969
if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1970
if (TII->isInlineConstant(Node->getValueAPF().bitcastToAPInt()))
1973
if (Node->getValueType(0) == MVT::f32)
1974
return FloatToBits(Node->getValueAPF().convertToFloat());
1982
/// \brief Helper function for adjustWritemask
1983
static unsigned SubIdx2Lane(unsigned Idx) {
1986
case AMDGPU::sub0: return 0;
1987
case AMDGPU::sub1: return 1;
1988
case AMDGPU::sub2: return 2;
1989
case AMDGPU::sub3: return 3;
1993
/// \brief Adjust the writemask of MIMG instructions
1994
void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1995
SelectionDAG &DAG) const {
1996
SDNode *Users[4] = { };
1998
unsigned OldDmask = Node->getConstantOperandVal(0);
1999
unsigned NewDmask = 0;
2001
// Try to figure out the used register components
2002
for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
2005
// Abort if we can't understand the usage
2006
if (!I->isMachineOpcode() ||
2007
I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
2010
// Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
2011
// Note that subregs are packed, i.e. Lane==0 is the first bit set
2012
// in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
2014
Lane = SubIdx2Lane(I->getConstantOperandVal(1));
2016
// Set which texture component corresponds to the lane.
2018
for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
2020
Comp = countTrailingZeros(Dmask);
2021
Dmask &= ~(1 << Comp);
2024
// Abort if we have more than one user per component
2029
NewDmask |= 1 << Comp;
2032
// Abort if there's no change
2033
if (NewDmask == OldDmask)
2036
// Adjust the writemask in the node
2037
std::vector<SDValue> Ops;
2038
Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
2039
Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end());
2040
Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
2042
// If we only got one lane, replace it with a copy
2043
// (if NewDmask has only one bit set...)
2044
if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
2045
SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, SDLoc(),
2047
SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
2048
SDLoc(), Users[Lane]->getValueType(0),
2049
SDValue(Node, 0), RC);
2050
DAG.ReplaceAllUsesWith(Users[Lane], Copy);
2054
// Update the users of the node with the new indices
2055
for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
2057
SDNode *User = Users[i];
2061
SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
2062
DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
2066
case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
2067
case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
2068
case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
2073
static bool isFrameIndexOp(SDValue Op) {
2074
if (Op.getOpcode() == ISD::AssertZext)
2075
Op = Op.getOperand(0);
2077
return isa<FrameIndexSDNode>(Op);
2080
/// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
2081
/// with frame index operands.
2082
/// LLVM assumes that inputs are to these instructions are registers.
2083
void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
2084
SelectionDAG &DAG) const {
2086
SmallVector<SDValue, 8> Ops;
2087
for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
2088
if (!isFrameIndexOp(Node->getOperand(i))) {
2089
Ops.push_back(Node->getOperand(i));
2094
Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
2095
Node->getOperand(i).getValueType(),
2096
Node->getOperand(i)), 0));
2099
DAG.UpdateNodeOperands(Node, Ops);
2102
/// \brief Fold the instructions after selecting them.
2103
SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
2104
SelectionDAG &DAG) const {
2105
const SIInstrInfo *TII =
2106
static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2108
if (TII->isMIMG(Node->getMachineOpcode()))
2109
adjustWritemask(Node, DAG);
2111
if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG ||
2112
Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) {
2113
legalizeTargetIndependentNode(Node, DAG);
2119
/// \brief Assign the register class depending on the number of
2120
/// bits set in the writemask
2121
void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
2122
SDNode *Node) const {
2123
const SIInstrInfo *TII =
2124
static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2126
MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2127
TII->legalizeOperands(MI);
2129
if (TII->isMIMG(MI->getOpcode())) {
2130
unsigned VReg = MI->getOperand(0).getReg();
2131
unsigned Writemask = MI->getOperand(1).getImm();
2132
unsigned BitsSet = 0;
2133
for (unsigned i = 0; i < 4; ++i)
2134
BitsSet += Writemask & (1 << i) ? 1 : 0;
2136
const TargetRegisterClass *RC;
2139
case 1: RC = &AMDGPU::VGPR_32RegClass; break;
2140
case 2: RC = &AMDGPU::VReg_64RegClass; break;
2141
case 3: RC = &AMDGPU::VReg_96RegClass; break;
2144
unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
2145
MI->setDesc(TII->get(NewOpcode));
2146
MRI.setRegClass(VReg, RC);
2150
// Replace unused atomics with the no return version.
2151
int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI->getOpcode());
2152
if (NoRetAtomicOp != -1) {
2153
if (!Node->hasAnyUseOfValue(0)) {
2154
MI->setDesc(TII->get(NoRetAtomicOp));
2155
MI->RemoveOperand(0);
2162
static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) {
2163
SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32);
2164
return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
2167
MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
2169
SDValue Ptr) const {
2170
const SIInstrInfo *TII =
2171
static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2173
// XXX - Workaround for moveToVALU not handling different register class
2174
// inserts for REG_SEQUENCE.
2176
// Build the half of the subregister with the constants.
2177
const SDValue Ops0[] = {
2178
DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32),
2179
buildSMovImm32(DAG, DL, 0),
2180
DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2181
buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
2182
DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
2185
SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
2186
MVT::v2i32, Ops0), 0);
2188
// Combine the constants and the pointer.
2189
const SDValue Ops1[] = {
2190
DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2192
DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
2194
DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32)
2197
return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
2199
const SDValue Ops[] = {
2200
DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
2202
DAG.getTargetConstant(AMDGPU::sub0_sub1, MVT::i32),
2203
buildSMovImm32(DAG, DL, 0),
2204
DAG.getTargetConstant(AMDGPU::sub2, MVT::i32),
2205
buildSMovImm32(DAG, DL, TII->getDefaultRsrcFormat() >> 32),
2206
DAG.getTargetConstant(AMDGPU::sub3, MVT::i32)
2209
return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2214
/// \brief Return a resource descriptor with the 'Add TID' bit enabled
2215
/// The TID (Thread ID) is multipled by the stride value (bits [61:48]
2216
/// of the resource descriptor) to create an offset, which is added to the
2217
/// resource ponter.
2218
MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
2221
uint32_t RsrcDword1,
2222
uint64_t RsrcDword2And3) const {
2223
SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
2224
SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
2226
PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
2227
DAG.getConstant(RsrcDword1, DL, MVT::i32)),
2231
SDValue DataLo = buildSMovImm32(DAG, DL,
2232
RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
2233
SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
2235
const SDValue Ops[] = {
2236
DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2238
DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2240
DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
2242
DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32),
2244
DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32)
2247
return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2250
MachineSDNode *SITargetLowering::buildScratchRSRC(SelectionDAG &DAG,
2252
SDValue Ptr) const {
2253
const SIInstrInfo *TII =
2254
static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2255
uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE |
2258
return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
2261
SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2262
const TargetRegisterClass *RC,
2263
unsigned Reg, EVT VT) const {
2264
SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
2266
return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
2267
cast<RegisterSDNode>(VReg)->getReg(), VT);
2270
//===----------------------------------------------------------------------===//
2271
// SI Inline Assembly Support
2272
//===----------------------------------------------------------------------===//
2274
std::pair<unsigned, const TargetRegisterClass *>
2275
SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2276
StringRef Constraint,
2278
if (Constraint == "r") {
2279
switch(VT.SimpleTy) {
2280
default: llvm_unreachable("Unhandled type for 'r' inline asm constraint");
2282
return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
2284
return std::make_pair(0U, &AMDGPU::SGPR_32RegClass);
2288
if (Constraint.size() > 1) {
2289
const TargetRegisterClass *RC = nullptr;
2290
if (Constraint[1] == 'v') {
2291
RC = &AMDGPU::VGPR_32RegClass;
2292
} else if (Constraint[1] == 's') {
2293
RC = &AMDGPU::SGPR_32RegClass;
2298
bool Failed = Constraint.substr(2).getAsInteger(10, Idx);
2299
if (!Failed && Idx < RC->getNumRegs())
2300
return std::make_pair(RC->getRegister(Idx), RC);
2303
return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
added
removed
lib/Target/AMDGPU/SIISelLowering.cpp
