1
; Test the MSA intrinsics that are encoded with the I5 instruction format.
2
; There are lots of these so this covers those beginning with 'b'
4
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
7
@llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
8
@llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
10
define void @llvm_mips_bclri_b_test() nounwind {
12
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_bclri_b_ARG1
13
%1 = tail call <16 x i8> @llvm.mips.bclri.b(<16 x i8> %0, i32 7)
14
store <16 x i8> %1, <16 x i8>* @llvm_mips_bclri_b_RES
18
declare <16 x i8> @llvm.mips.bclri.b(<16 x i8>, i32) nounwind
20
; CHECK: llvm_mips_bclri_b_test:
22
; andi.b is equivalent to bclri.b
23
; CHECK: andi.b {{\$w[0-9]}}, {{\$w[0-9]}}, 127
25
; CHECK: .size llvm_mips_bclri_b_test
27
@llvm_mips_bclri_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
28
@llvm_mips_bclri_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
30
define void @llvm_mips_bclri_h_test() nounwind {
32
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_bclri_h_ARG1
33
%1 = tail call <8 x i16> @llvm.mips.bclri.h(<8 x i16> %0, i32 7)
34
store <8 x i16> %1, <8 x i16>* @llvm_mips_bclri_h_RES
38
declare <8 x i16> @llvm.mips.bclri.h(<8 x i16>, i32) nounwind
40
; CHECK: llvm_mips_bclri_h_test:
44
; CHECK: .size llvm_mips_bclri_h_test
46
@llvm_mips_bclri_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
47
@llvm_mips_bclri_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
49
define void @llvm_mips_bclri_w_test() nounwind {
51
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_bclri_w_ARG1
52
%1 = tail call <4 x i32> @llvm.mips.bclri.w(<4 x i32> %0, i32 7)
53
store <4 x i32> %1, <4 x i32>* @llvm_mips_bclri_w_RES
57
declare <4 x i32> @llvm.mips.bclri.w(<4 x i32>, i32) nounwind
59
; CHECK: llvm_mips_bclri_w_test:
63
; CHECK: .size llvm_mips_bclri_w_test
65
@llvm_mips_bclri_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
66
@llvm_mips_bclri_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
68
define void @llvm_mips_bclri_d_test() nounwind {
70
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_bclri_d_ARG1
71
%1 = tail call <2 x i64> @llvm.mips.bclri.d(<2 x i64> %0, i32 7)
72
store <2 x i64> %1, <2 x i64>* @llvm_mips_bclri_d_RES
76
declare <2 x i64> @llvm.mips.bclri.d(<2 x i64>, i32) nounwind
78
; CHECK: llvm_mips_bclri_d_test:
82
; CHECK: .size llvm_mips_bclri_d_test
84
@llvm_mips_binsli_b_ARG1 = global <16 x i8> zeroinitializer, align 16
85
@llvm_mips_binsli_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
86
@llvm_mips_binsli_b_RES = global <16 x i8> zeroinitializer, align 16
88
define void @llvm_mips_binsli_b_test() nounwind {
90
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsli_b_ARG1
91
%1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsli_b_ARG2
92
%2 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, <16 x i8> %1, i32 7)
93
store <16 x i8> %2, <16 x i8>* @llvm_mips_binsli_b_RES
97
declare <16 x i8> @llvm.mips.binsli.b(<16 x i8>, <16 x i8>, i32) nounwind
99
; CHECK: llvm_mips_binsli_b_test:
100
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_b_ARG1)(
101
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_b_ARG2)(
102
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
103
; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
104
; CHECK-DAG: binsli.b [[R3]], [[R4]], 7
105
; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_b_RES)(
106
; CHECK-DAG: st.b [[R3]], 0([[R5]])
107
; CHECK: .size llvm_mips_binsli_b_test
109
@llvm_mips_binsli_h_ARG1 = global <8 x i16> zeroinitializer, align 16
110
@llvm_mips_binsli_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
111
@llvm_mips_binsli_h_RES = global <8 x i16> zeroinitializer, align 16
113
define void @llvm_mips_binsli_h_test() nounwind {
115
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_binsli_h_ARG1
116
%1 = load <8 x i16>, <8 x i16>* @llvm_mips_binsli_h_ARG2
117
%2 = tail call <8 x i16> @llvm.mips.binsli.h(<8 x i16> %0, <8 x i16> %1, i32 7)
118
store <8 x i16> %2, <8 x i16>* @llvm_mips_binsli_h_RES
122
declare <8 x i16> @llvm.mips.binsli.h(<8 x i16>, <8 x i16>, i32) nounwind
124
; CHECK: llvm_mips_binsli_h_test:
125
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_h_ARG1)(
126
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_h_ARG2)(
127
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]])
128
; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]])
129
; CHECK-DAG: binsli.h [[R3]], [[R4]], 7
130
; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_h_RES)(
131
; CHECK-DAG: st.h [[R3]], 0([[R5]])
132
; CHECK: .size llvm_mips_binsli_h_test
134
@llvm_mips_binsli_w_ARG1 = global <4 x i32> zeroinitializer, align 16
135
@llvm_mips_binsli_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
136
@llvm_mips_binsli_w_RES = global <4 x i32> zeroinitializer, align 16
138
define void @llvm_mips_binsli_w_test() nounwind {
140
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_binsli_w_ARG1
141
%1 = load <4 x i32>, <4 x i32>* @llvm_mips_binsli_w_ARG2
142
%2 = tail call <4 x i32> @llvm.mips.binsli.w(<4 x i32> %0, <4 x i32> %1, i32 7)
143
store <4 x i32> %2, <4 x i32>* @llvm_mips_binsli_w_RES
147
declare <4 x i32> @llvm.mips.binsli.w(<4 x i32>, <4 x i32>, i32) nounwind
149
; CHECK: llvm_mips_binsli_w_test:
150
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_w_ARG1)(
151
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_w_ARG2)(
152
; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]])
153
; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]])
154
; CHECK-DAG: binsli.w [[R3]], [[R4]], 7
155
; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_w_RES)(
156
; CHECK-DAG: st.w [[R3]], 0([[R5]])
157
; CHECK: .size llvm_mips_binsli_w_test
159
@llvm_mips_binsli_d_ARG1 = global <2 x i64> zeroinitializer, align 16
160
@llvm_mips_binsli_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16
161
@llvm_mips_binsli_d_RES = global <2 x i64> zeroinitializer, align 16
163
define void @llvm_mips_binsli_d_test() nounwind {
165
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_binsli_d_ARG1
166
%1 = load <2 x i64>, <2 x i64>* @llvm_mips_binsli_d_ARG2
167
; TODO: We use a particularly wide mask here to work around a legalization
168
; issue. If the mask doesn't fit within a 10-bit immediate, it gets
169
; legalized into a constant pool. We should add a test to cover the
170
; other cases once they correctly select binsli.d.
171
%2 = tail call <2 x i64> @llvm.mips.binsli.d(<2 x i64> %0, <2 x i64> %1, i32 61)
172
store <2 x i64> %2, <2 x i64>* @llvm_mips_binsli_d_RES
176
declare <2 x i64> @llvm.mips.binsli.d(<2 x i64>, <2 x i64>, i32) nounwind
178
; CHECK: llvm_mips_binsli_d_test:
179
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_d_ARG1)(
180
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_d_ARG2)(
181
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]])
182
; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]])
183
; CHECK-DAG: binsli.d [[R3]], [[R4]], 61
184
; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_d_RES)(
185
; CHECK-DAG: st.d [[R3]], 0([[R5]])
186
; CHECK: .size llvm_mips_binsli_d_test
188
@llvm_mips_binsri_b_ARG1 = global <16 x i8> zeroinitializer, align 16
189
@llvm_mips_binsri_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
190
@llvm_mips_binsri_b_RES = global <16 x i8> zeroinitializer, align 16
192
define void @llvm_mips_binsri_b_test() nounwind {
194
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_binsri_b_ARG1
195
%1 = load <16 x i8>, <16 x i8>* @llvm_mips_binsri_b_ARG2
196
%2 = tail call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %0, <16 x i8> %1, i32 7)
197
store <16 x i8> %2, <16 x i8>* @llvm_mips_binsri_b_RES
201
declare <16 x i8> @llvm.mips.binsri.b(<16 x i8>, <16 x i8>, i32) nounwind
203
; CHECK: llvm_mips_binsri_b_test:
204
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_b_ARG1)(
205
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_b_ARG2)(
206
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
207
; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
208
; CHECK-DAG: binsri.b [[R3]], [[R4]], 7
209
; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_b_RES)(
210
; CHECK-DAG: st.b [[R3]], 0([[R5]])
211
; CHECK: .size llvm_mips_binsri_b_test
213
@llvm_mips_binsri_h_ARG1 = global <8 x i16> zeroinitializer, align 16
214
@llvm_mips_binsri_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
215
@llvm_mips_binsri_h_RES = global <8 x i16> zeroinitializer, align 16
217
define void @llvm_mips_binsri_h_test() nounwind {
219
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_binsri_h_ARG1
220
%1 = load <8 x i16>, <8 x i16>* @llvm_mips_binsri_h_ARG2
221
%2 = tail call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %0, <8 x i16> %1, i32 7)
222
store <8 x i16> %2, <8 x i16>* @llvm_mips_binsri_h_RES
226
declare <8 x i16> @llvm.mips.binsri.h(<8 x i16>, <8 x i16>, i32) nounwind
228
; CHECK: llvm_mips_binsri_h_test:
229
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_h_ARG1)(
230
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_h_ARG2)(
231
; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]])
232
; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]])
233
; CHECK-DAG: binsri.h [[R3]], [[R4]], 7
234
; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_h_RES)(
235
; CHECK-DAG: st.h [[R3]], 0([[R5]])
236
; CHECK: .size llvm_mips_binsri_h_test
238
@llvm_mips_binsri_w_ARG1 = global <4 x i32> zeroinitializer, align 16
239
@llvm_mips_binsri_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
240
@llvm_mips_binsri_w_RES = global <4 x i32> zeroinitializer, align 16
242
define void @llvm_mips_binsri_w_test() nounwind {
244
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_binsri_w_ARG1
245
%1 = load <4 x i32>, <4 x i32>* @llvm_mips_binsri_w_ARG2
246
%2 = tail call <4 x i32> @llvm.mips.binsri.w(<4 x i32> %0, <4 x i32> %1, i32 7)
247
store <4 x i32> %2, <4 x i32>* @llvm_mips_binsri_w_RES
251
declare <4 x i32> @llvm.mips.binsri.w(<4 x i32>, <4 x i32>, i32) nounwind
253
; CHECK: llvm_mips_binsri_w_test:
254
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_w_ARG1)(
255
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_w_ARG2)(
256
; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]])
257
; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]])
258
; CHECK-DAG: binsri.w [[R3]], [[R4]], 7
259
; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_w_RES)(
260
; CHECK-DAG: st.w [[R3]], 0([[R5]])
261
; CHECK: .size llvm_mips_binsri_w_test
263
@llvm_mips_binsri_d_ARG1 = global <2 x i64> zeroinitializer, align 16
264
@llvm_mips_binsri_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16
265
@llvm_mips_binsri_d_RES = global <2 x i64> zeroinitializer, align 16
267
define void @llvm_mips_binsri_d_test() nounwind {
269
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_binsri_d_ARG1
270
%1 = load <2 x i64>, <2 x i64>* @llvm_mips_binsri_d_ARG2
271
%2 = tail call <2 x i64> @llvm.mips.binsri.d(<2 x i64> %0, <2 x i64> %1, i32 7)
272
store <2 x i64> %2, <2 x i64>* @llvm_mips_binsri_d_RES
276
declare <2 x i64> @llvm.mips.binsri.d(<2 x i64>, <2 x i64>, i32) nounwind
278
; CHECK: llvm_mips_binsri_d_test:
279
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_d_ARG1)(
280
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_d_ARG2)(
281
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]])
282
; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]])
283
; CHECK-DAG: binsri.d [[R3]], [[R4]], 7
284
; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_d_RES)(
285
; CHECK-DAG: st.d [[R3]], 0([[R5]])
286
; CHECK: .size llvm_mips_binsri_d_test
288
@llvm_mips_bnegi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
289
@llvm_mips_bnegi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
291
define void @llvm_mips_bnegi_b_test() nounwind {
293
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_bnegi_b_ARG1
294
%1 = tail call <16 x i8> @llvm.mips.bnegi.b(<16 x i8> %0, i32 7)
295
store <16 x i8> %1, <16 x i8>* @llvm_mips_bnegi_b_RES
299
declare <16 x i8> @llvm.mips.bnegi.b(<16 x i8>, i32) nounwind
301
; CHECK: llvm_mips_bnegi_b_test:
305
; CHECK: .size llvm_mips_bnegi_b_test
307
@llvm_mips_bnegi_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
308
@llvm_mips_bnegi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
310
define void @llvm_mips_bnegi_h_test() nounwind {
312
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_bnegi_h_ARG1
313
%1 = tail call <8 x i16> @llvm.mips.bnegi.h(<8 x i16> %0, i32 7)
314
store <8 x i16> %1, <8 x i16>* @llvm_mips_bnegi_h_RES
318
declare <8 x i16> @llvm.mips.bnegi.h(<8 x i16>, i32) nounwind
320
; CHECK: llvm_mips_bnegi_h_test:
324
; CHECK: .size llvm_mips_bnegi_h_test
326
@llvm_mips_bnegi_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
327
@llvm_mips_bnegi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
329
define void @llvm_mips_bnegi_w_test() nounwind {
331
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_bnegi_w_ARG1
332
%1 = tail call <4 x i32> @llvm.mips.bnegi.w(<4 x i32> %0, i32 7)
333
store <4 x i32> %1, <4 x i32>* @llvm_mips_bnegi_w_RES
337
declare <4 x i32> @llvm.mips.bnegi.w(<4 x i32>, i32) nounwind
339
; CHECK: llvm_mips_bnegi_w_test:
343
; CHECK: .size llvm_mips_bnegi_w_test
345
@llvm_mips_bnegi_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
346
@llvm_mips_bnegi_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
348
define void @llvm_mips_bnegi_d_test() nounwind {
350
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_bnegi_d_ARG1
351
%1 = tail call <2 x i64> @llvm.mips.bnegi.d(<2 x i64> %0, i32 7)
352
store <2 x i64> %1, <2 x i64>* @llvm_mips_bnegi_d_RES
356
declare <2 x i64> @llvm.mips.bnegi.d(<2 x i64>, i32) nounwind
358
; CHECK: llvm_mips_bnegi_d_test:
362
; CHECK: .size llvm_mips_bnegi_d_test
364
@llvm_mips_bseti_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
365
@llvm_mips_bseti_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
367
define void @llvm_mips_bseti_b_test() nounwind {
369
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_bseti_b_ARG1
370
%1 = tail call <16 x i8> @llvm.mips.bseti.b(<16 x i8> %0, i32 7)
371
store <16 x i8> %1, <16 x i8>* @llvm_mips_bseti_b_RES
375
declare <16 x i8> @llvm.mips.bseti.b(<16 x i8>, i32) nounwind
377
; CHECK: llvm_mips_bseti_b_test:
381
; CHECK: .size llvm_mips_bseti_b_test
383
@llvm_mips_bseti_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
384
@llvm_mips_bseti_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
386
define void @llvm_mips_bseti_h_test() nounwind {
388
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_bseti_h_ARG1
389
%1 = tail call <8 x i16> @llvm.mips.bseti.h(<8 x i16> %0, i32 7)
390
store <8 x i16> %1, <8 x i16>* @llvm_mips_bseti_h_RES
394
declare <8 x i16> @llvm.mips.bseti.h(<8 x i16>, i32) nounwind
396
; CHECK: llvm_mips_bseti_h_test:
400
; CHECK: .size llvm_mips_bseti_h_test
402
@llvm_mips_bseti_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
403
@llvm_mips_bseti_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
405
define void @llvm_mips_bseti_w_test() nounwind {
407
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_bseti_w_ARG1
408
%1 = tail call <4 x i32> @llvm.mips.bseti.w(<4 x i32> %0, i32 7)
409
store <4 x i32> %1, <4 x i32>* @llvm_mips_bseti_w_RES
413
declare <4 x i32> @llvm.mips.bseti.w(<4 x i32>, i32) nounwind
415
; CHECK: llvm_mips_bseti_w_test:
419
; CHECK: .size llvm_mips_bseti_w_test
421
@llvm_mips_bseti_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
422
@llvm_mips_bseti_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
424
define void @llvm_mips_bseti_d_test() nounwind {
426
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_bseti_d_ARG1
427
%1 = tail call <2 x i64> @llvm.mips.bseti.d(<2 x i64> %0, i32 7)
428
store <2 x i64> %1, <2 x i64>* @llvm_mips_bseti_d_RES
432
declare <2 x i64> @llvm.mips.bseti.d(<2 x i64>, i32) nounwind
434
; CHECK: llvm_mips_bseti_d_test:
438
; CHECK: .size llvm_mips_bseti_d_test