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//===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file contains the X86 implementation of TargetFrameLowering class.
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//===----------------------------------------------------------------------===//
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#include "X86FrameLowering.h"
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#include "X86InstrBuilder.h"
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#include "X86InstrInfo.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Debug.h"
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// FIXME: completely move here.
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extern cl::opt<bool> ForceStackAlign;
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X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
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unsigned StackAlignOverride)
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: TargetFrameLowering(StackGrowsDown, StackAlignOverride,
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STI.is64Bit() ? -8 : -4),
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STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
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// Cache a bunch of frame-related predicates for this subtarget.
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SlotSize = TRI->getSlotSize();
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Is64Bit = STI.is64Bit();
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IsLP64 = STI.isTarget64BitLP64();
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// standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
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Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
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StackPtr = TRI->getStackRegister();
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bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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return !MF.getFrameInfo()->hasVarSizedObjects() &&
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!MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
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/// canSimplifyCallFramePseudos - If there is a reserved call frame, the
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/// call frame pseudos can be simplified. Having a FP, as in the default
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/// implementation, is not sufficient here since we can't always use it.
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/// Use a more nuanced condition.
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X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
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return hasReservedCallFrame(MF) ||
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(hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
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TRI->hasBasePointer(MF);
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// needsFrameIndexResolution - Do we need to perform FI resolution for
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// this function. Normally, this is required only when the function
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// has any stack objects. However, FI resolution actually has another job,
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// not apparent from the title - it resolves callframesetup/destroy
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// that were not simplified earlier.
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// So, this is required for x86 functions that have push sequences even
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// when there are no stack objects.
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X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
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return MF.getFrameInfo()->hasStackObjects() ||
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MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
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/// hasFP - Return true if the specified function should have a dedicated frame
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/// pointer register. This is true if the function has variable sized allocas
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/// or if frame pointer elimination is disabled.
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bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const MachineModuleInfo &MMI = MF.getMMI();
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return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
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TRI->needsStackRealignment(MF) ||
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MFI->hasVarSizedObjects() ||
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MFI->isFrameAddressTaken() || MFI->hasOpaqueSPAdjustment() ||
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MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
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MMI.callsUnwindInit() || MMI.callsEHReturn() ||
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MFI->hasStackMap() || MFI->hasPatchPoint());
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static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
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return X86::SUB64ri8;
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return X86::SUB64ri32;
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return X86::SUB32ri8;
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static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
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return X86::ADD64ri8;
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return X86::ADD64ri32;
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return X86::ADD32ri8;
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static unsigned getSUBrrOpcode(unsigned isLP64) {
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return isLP64 ? X86::SUB64rr : X86::SUB32rr;
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static unsigned getADDrrOpcode(unsigned isLP64) {
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return isLP64 ? X86::ADD64rr : X86::ADD32rr;
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static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
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return X86::AND64ri8;
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return X86::AND64ri32;
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return X86::AND32ri8;
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static unsigned getLEArOpcode(unsigned IsLP64) {
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return IsLP64 ? X86::LEA64r : X86::LEA32r;
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/// findDeadCallerSavedReg - Return a caller-saved register that isn't live
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/// when it reaches the "return" instruction. We can then pop a stack object
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/// to this register without worry about clobbering it.
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static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const TargetRegisterInfo *TRI,
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const MachineFunction *MF = MBB.getParent();
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const Function *F = MF->getFunction();
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if (!F || MF->getMMI().callsEHReturn())
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static const uint16_t CallerSavedRegs32Bit[] = {
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X86::EAX, X86::EDX, X86::ECX, 0
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static const uint16_t CallerSavedRegs64Bit[] = {
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X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
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X86::R8, X86::R9, X86::R10, X86::R11, 0
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unsigned Opc = MBBI->getOpcode();
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case X86::TCRETURNdi:
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case X86::TCRETURNri:
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case X86::TCRETURNmi:
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case X86::TCRETURNdi64:
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case X86::TCRETURNri64:
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case X86::TCRETURNmi64:
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case X86::EH_RETURN64: {
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SmallSet<uint16_t, 8> Uses;
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for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MBBI->getOperand(i);
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if (!MO.isReg() || MO.isDef())
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unsigned Reg = MO.getReg();
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
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if (!Uses.count(*CS))
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static bool isEAXLiveIn(MachineFunction &MF) {
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for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
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EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
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unsigned Reg = II->first;
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if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
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Reg == X86::AH || Reg == X86::AL)
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/// Check whether or not the terminators of \p MBB needs to read EFLAGS.
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static bool terminatorsNeedFlagsAsInput(const MachineBasicBlock &MBB) {
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for (const MachineInstr &MI : MBB.terminators()) {
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bool BreakNext = false;
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for (const MachineOperand &MO : MI.operands()) {
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unsigned Reg = MO.getReg();
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if (Reg != X86::EFLAGS)
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// This terminator needs an eflag that is not defined
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// by a previous terminator.
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/// emitSPUpdate - Emit a series of instructions to increment / decrement the
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/// stack pointer by a constant value.
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void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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int64_t NumBytes, bool InEpilogue) const {
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bool isSub = NumBytes < 0;
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uint64_t Offset = isSub ? -NumBytes : NumBytes;
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uint64_t Chunk = (1LL << 31) - 1;
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DebugLoc DL = MBB.findDebugLoc(MBBI);
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if (Offset > Chunk) {
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// Rather than emit a long series of instructions for large offsets,
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// load the offset into a register and do one sub/add
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if (isSub && !isEAXLiveIn(*MBB.getParent()))
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Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
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Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
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unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
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BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
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? getSUBrrOpcode(Is64Bit)
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: getADDrrOpcode(Is64Bit);
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MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
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MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
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uint64_t ThisVal = std::min(Offset, Chunk);
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if (ThisVal == (Is64Bit ? 8 : 4)) {
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// Use push / pop instead.
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? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
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: findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
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? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
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: (Is64Bit ? X86::POP64r : X86::POP32r);
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MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
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.addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
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MI->setFlag(MachineInstr::FrameSetup);
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MachineInstrBuilder MI = BuildStackAdjustment(
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MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue);
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MI.setMIFlag(MachineInstr::FrameSetup);
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MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
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int64_t Offset, bool InEpilogue) const {
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assert(Offset != 0 && "zero offset stack adjustment requested");
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// On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
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UseLEA = STI.useLeaForSP();
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// If we can use LEA for SP but we shouldn't, check that none
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// of the terminators uses the eflags. Otherwise we will insert
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// a ADD that will redefine the eflags and break the condition.
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// Alternatively, we could move the ADD, but this may not be possible
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// and is an optimization anyway.
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UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
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if (UseLEA && !STI.useLeaForSP())
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UseLEA = terminatorsNeedFlagsAsInput(MBB);
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// If that assert breaks, that means we do not do the right thing
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// in canUseAsEpilogue.
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assert((UseLEA || !terminatorsNeedFlagsAsInput(MBB)) &&
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"We shouldn't have allowed this insertion point");
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MachineInstrBuilder MI;
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MI = addRegOffset(BuildMI(MBB, MBBI, DL,
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TII.get(getLEArOpcode(Uses64BitFramePtr)),
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StackPtr, false, Offset);
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bool IsSub = Offset < 0;
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uint64_t AbsOffset = IsSub ? -Offset : Offset;
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unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
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: getADDriOpcode(Uses64BitFramePtr, AbsOffset);
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MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
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MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
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/// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
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void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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unsigned StackPtr, uint64_t *NumBytes = nullptr) {
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if (MBBI == MBB.begin()) return;
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MachineBasicBlock::iterator PI = std::prev(MBBI);
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unsigned Opc = PI->getOpcode();
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if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
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Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
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Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
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PI->getOperand(0).getReg() == StackPtr) {
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*NumBytes += PI->getOperand(2).getImm();
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} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
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Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
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PI->getOperand(0).getReg() == StackPtr) {
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*NumBytes -= PI->getOperand(2).getImm();
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int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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bool doMergeWithPrevious) const {
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if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
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(!doMergeWithPrevious && MBBI == MBB.end()))
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MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
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MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
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unsigned Opc = PI->getOpcode();
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if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
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Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
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Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
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PI->getOperand(0).getReg() == StackPtr){
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Offset += PI->getOperand(2).getImm();
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if (!doMergeWithPrevious) MBBI = NI;
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} else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
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Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
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PI->getOperand(0).getReg() == StackPtr) {
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Offset -= PI->getOperand(2).getImm();
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if (!doMergeWithPrevious) MBBI = NI;
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void X86FrameLowering::BuildCFI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc DL,
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MCCFIInstruction CFIInst) const {
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MachineFunction &MF = *MBB.getParent();
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unsigned CFIIndex = MF.getMMI().addFrameInst(CFIInst);
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BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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// Add callee saved registers to move list.
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.empty()) return;
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// Calculate offsets.
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for (std::vector<CalleeSavedInfo>::const_iterator
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I = CSI.begin(), E = CSI.end(); I != E; ++I) {
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int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
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unsigned Reg = I->getReg();
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unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
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BuildCFI(MBB, MBBI, DL,
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MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
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/// usesTheStack - This function checks if any of the users of EFLAGS
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/// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
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/// to use the stack, and if we don't adjust the stack we clobber the first
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/// See X86InstrInfo::copyPhysReg.
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static bool usesTheStack(const MachineFunction &MF) {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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for (MachineRegisterInfo::reg_instr_iterator
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ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
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void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
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CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
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CallOp = X86::CALLpcrel32;
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if (STI.isTargetCygMing()) {
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Symbol = "___chkstk_ms";
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} else if (STI.isTargetCygMing())
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MachineInstrBuilder CI;
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// All current stack probes take AX and SP as input, clobber flags, and
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// preserve all registers. x86_64 probes leave RSP unmodified.
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if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
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// For the large code model, we have to call through a register. Use R11,
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// as it is scratch in all supported calling conventions.
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BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
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.addExternalSymbol(Symbol);
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CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
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CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
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unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
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unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
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CI.addReg(AX, RegState::Implicit)
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.addReg(SP, RegState::Implicit)
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.addReg(AX, RegState::Define | RegState::Implicit)
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.addReg(SP, RegState::Define | RegState::Implicit)
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.addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
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// MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
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// themselves. It also does not clobber %rax so we can reuse it when
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BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
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static unsigned calculateSetFPREG(uint64_t SPAdjust) {
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// Win64 ABI has a less restrictive limitation of 240; 128 works equally well
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// and might require smaller successive adjustments.
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const uint64_t Win64MaxSEHOffset = 128;
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uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
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// Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
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return SEHFrameOffset & -16;
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// If we're forcing a stack realignment we can't rely on just the frame
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// info, we need to know the ABI stack alignment as well in case we
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// have a call out. Otherwise just make sure we have some alignment - we'll
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// go with the minimum SlotSize.
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uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
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unsigned StackAlign = getStackAlignment();
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if (ForceStackAlign) {
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MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
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else if (MaxAlign < SlotSize)
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void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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uint64_t MaxAlign) const {
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uint64_t Val = -MaxAlign;
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BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
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.setMIFlag(MachineInstr::FrameSetup);
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// The EFLAGS implicit def is dead.
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MI->getOperand(3).setIsDead();
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/// emitPrologue - Push callee-saved registers onto the stack, which
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/// automatically adjust the stack pointer. Adjust the stack pointer to allocate
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/// space for local variables. Also emit labels used by the exception handler to
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/// generate the exception handling frames.
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Here's a gist of what gets emitted:
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; Establish frame pointer, if needed
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.cfi_def_cfa_offset 16
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.cfi_offset %rbp, -16
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.cfi_def_cfa_register %rbp
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; Spill general-purpose registers
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[for all callee-saved GPRs]
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.cfi_def_cfa_offset (offset from RETADDR)
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; If the required stack alignment > default stack alignment
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; rsp needs to be re-aligned. This creates a "re-alignment gap"
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; of unknown size in the stack frame.
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[if stack needs re-alignment]
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; Allocate space for locals
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[if target is Windows and allocated space > 4096 bytes]
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; Windows needs special care for allocations larger
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call ___chkstk_ms/___chkstk
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.seh_stackalloc (size of XMM spill slots)
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.seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
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; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
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; they may get spilled on any platform, if the current function
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; calls @llvm.eh.unwind.init
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[for all callee-saved XMM registers]
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movaps %<xmm reg>, -MMM(%rbp)
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[for all callee-saved XMM registers]
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.seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
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; i.e. the offset relative to (%rbp - SEHFrameOffset)
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[for all callee-saved XMM registers]
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movaps %<xmm reg>, KKK(%rsp)
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[for all callee-saved XMM registers]
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.seh_savexmm %<xmm reg>, KKK
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[if needs base pointer]
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[if needs to restore base pointer]
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[for all callee-saved registers]
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.cfi_offset %<reg>, (offset from %rbp)
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.cfi_def_cfa_offset (offset from RETADDR)
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[for all callee-saved registers]
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.cfi_offset %<reg>, (offset from %rsp)
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- .seh directives are emitted only for Windows 64 ABI
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- .cfi directives are emitted for all other ABIs
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- for 32-bit code, substitute %e?? registers for %r??
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void X86FrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
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"MF used frame lowering for wrong subtarget");
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const Function *Fn = MF.getFunction();
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MachineModuleInfo &MMI = MF.getMMI();
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X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
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uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
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uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
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bool HasFP = hasFP(MF);
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bool IsWin64CC = STI.isCallingConvWin64(Fn->getCallingConv());
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bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
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bool NeedsWinCFI = IsWin64Prologue && Fn->needsUnwindTableEntry();
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!IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
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unsigned FramePtr = TRI->getFrameRegister(MF);
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const unsigned MachineFramePtr =
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STI.isTarget64BitILP32()
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? getX86SubSuperRegister(FramePtr, MVT::i64, false)
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unsigned BasePtr = TRI->getBaseRegister();
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// Add RETADDR move area to callee saved frame size.
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int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
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if (TailCallReturnAddrDelta && IsWin64Prologue)
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report_fatal_error("Can't handle guaranteed tail call under win64 yet");
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if (TailCallReturnAddrDelta < 0)
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X86FI->setCalleeSavedFrameSize(
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X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
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bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
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// The default stack probe size is 4096 if the function has no stackprobesize
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unsigned StackProbeSize = 4096;
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if (Fn->hasFnAttribute("stack-probe-size"))
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Fn->getFnAttribute("stack-probe-size")
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.getAsInteger(0, StackProbeSize);
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// If this is x86-64 and the Red Zone is not disabled, if we are a leaf
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// function, and use up to 128 bytes of stack space, don't have a frame
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// pointer, calls, or dynamic alloca then we do not need to adjust the
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// stack pointer (we fit in the Red Zone). We also check that we don't
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// push and pop from the stack.
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if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
688
!TRI->needsStackRealignment(MF) &&
689
!MFI->hasVarSizedObjects() && // No dynamic alloca.
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!MFI->adjustsStack() && // No calls.
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!IsWin64CC && // Win64 has no Red Zone
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!usesTheStack(MF) && // Don't push and pop.
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!MF.shouldSplitStack()) { // Regular stack
694
uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
695
if (HasFP) MinSize += SlotSize;
696
StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
697
MFI->setStackSize(StackSize);
700
// Insert stack pointer adjustment for later moving of return addr. Only
701
// applies to tail call optimized functions where the callee argument stack
702
// size is bigger than the callers.
703
if (TailCallReturnAddrDelta < 0) {
704
BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
705
/*InEpilogue=*/false)
706
.setMIFlag(MachineInstr::FrameSetup);
709
// Mapping for machine moves:
711
// DST: VirtualFP AND
712
// SRC: VirtualFP => DW_CFA_def_cfa_offset
713
// ELSE => DW_CFA_def_cfa
715
// SRC: VirtualFP AND
716
// DST: Register => DW_CFA_def_cfa_register
719
// OFFSET < 0 => DW_CFA_offset_extended_sf
720
// REG < 64 => DW_CFA_offset + Reg
721
// ELSE => DW_CFA_offset_extended
723
uint64_t NumBytes = 0;
724
int stackGrowth = -SlotSize;
727
// Calculate required stack adjustment.
728
uint64_t FrameSize = StackSize - SlotSize;
729
// If required, include space for extra hidden slot for stashing base pointer.
730
if (X86FI->getRestoreBasePointer())
731
FrameSize += SlotSize;
733
NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
735
// Callee-saved registers are pushed on stack before the stack is realigned.
736
if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
737
NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
739
// Get the offset of the stack slot for the EBP register, which is
740
// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
741
// Update the frame offset adjustment.
742
MFI->setOffsetAdjustment(-NumBytes);
744
// Save EBP/RBP into the appropriate stack slot.
745
BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
746
.addReg(MachineFramePtr, RegState::Kill)
747
.setMIFlag(MachineInstr::FrameSetup);
750
// Mark the place where EBP/RBP was saved.
751
// Define the current CFA rule to use the provided offset.
753
BuildCFI(MBB, MBBI, DL,
754
MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
756
// Change the rule for the FramePtr to be an "offset" rule.
757
unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
758
BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
759
nullptr, DwarfFramePtr, 2 * stackGrowth));
763
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
765
.setMIFlag(MachineInstr::FrameSetup);
768
if (!IsWin64Prologue) {
769
// Update EBP with the new base value.
770
BuildMI(MBB, MBBI, DL,
771
TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
774
.setMIFlag(MachineInstr::FrameSetup);
778
// Mark effective beginning of when frame pointer becomes valid.
779
// Define the current CFA to use the EBP/RBP register.
780
unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
781
BuildCFI(MBB, MBBI, DL,
782
MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
785
// Mark the FramePtr as live-in in every block.
786
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
787
I->addLiveIn(MachineFramePtr);
789
NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
792
// Skip the callee-saved push instructions.
793
bool PushedRegs = false;
794
int StackOffset = 2 * stackGrowth;
796
while (MBBI != MBB.end() &&
797
(MBBI->getOpcode() == X86::PUSH32r ||
798
MBBI->getOpcode() == X86::PUSH64r)) {
800
unsigned Reg = MBBI->getOperand(0).getReg();
803
if (!HasFP && NeedsDwarfCFI) {
804
// Mark callee-saved push instruction.
805
// Define the current CFA rule to use the provided offset.
807
BuildCFI(MBB, MBBI, DL,
808
MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
809
StackOffset += stackGrowth;
813
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
814
MachineInstr::FrameSetup);
818
// Realign stack after we pushed callee-saved registers (so that we'll be
819
// able to calculate their offsets from the frame pointer).
820
// Don't do this for Win64, it needs to realign the stack after the prologue.
821
if (!IsWin64Prologue && TRI->needsStackRealignment(MF)) {
822
assert(HasFP && "There should be a frame pointer if stack is realigned.");
823
BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
826
// If there is an SUB32ri of ESP immediately before this instruction, merge
827
// the two. This can be the case when tail call elimination is enabled and
828
// the callee has more arguments then the caller.
829
NumBytes -= mergeSPUpdates(MBB, MBBI, true);
831
// Adjust stack pointer: ESP -= numbytes.
833
// Windows and cygwin/mingw require a prologue helper routine when allocating
834
// more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
835
// uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
836
// stack and adjust the stack pointer in one go. The 64-bit version of
837
// __chkstk is only responsible for probing the stack. The 64-bit prologue is
838
// responsible for adjusting the stack pointer. Touching the stack at 4K
839
// increments is necessary to ensure that the guard pages used by the OS
840
// virtual memory manager are allocated in correct sequence.
841
uint64_t AlignedNumBytes = NumBytes;
842
if (IsWin64Prologue && TRI->needsStackRealignment(MF))
843
AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
844
if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
845
// Check whether EAX is livein for this function.
846
bool isEAXAlive = isEAXLiveIn(MF);
849
// Sanity check that EAX is not livein for this function.
850
// It should not be, so throw an assert.
851
assert(!Is64Bit && "EAX is livein in x64 case!");
854
BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
855
.addReg(X86::EAX, RegState::Kill)
856
.setMIFlag(MachineInstr::FrameSetup);
860
// Handle the 64-bit Windows ABI case where we need to call __chkstk.
861
// Function prologue is responsible for adjusting the stack pointer.
862
if (isUInt<32>(NumBytes)) {
863
BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
865
.setMIFlag(MachineInstr::FrameSetup);
866
} else if (isInt<32>(NumBytes)) {
867
BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
869
.setMIFlag(MachineInstr::FrameSetup);
871
BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
873
.setMIFlag(MachineInstr::FrameSetup);
876
// Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
877
// We'll also use 4 already allocated bytes for EAX.
878
BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
879
.addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
880
.setMIFlag(MachineInstr::FrameSetup);
883
// Save a pointer to the MI where we set AX.
884
MachineBasicBlock::iterator SetRAX = MBBI;
887
// Call __chkstk, __chkstk_ms, or __alloca.
888
emitStackProbeCall(MF, MBB, MBBI, DL);
890
// Apply the frame setup flag to all inserted instrs.
891
for (; SetRAX != MBBI; ++SetRAX)
892
SetRAX->setFlag(MachineInstr::FrameSetup);
896
MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
898
StackPtr, false, NumBytes - 4);
899
MI->setFlag(MachineInstr::FrameSetup);
900
MBB.insert(MBBI, MI);
902
} else if (NumBytes) {
903
emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false);
906
if (NeedsWinCFI && NumBytes)
907
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
909
.setMIFlag(MachineInstr::FrameSetup);
911
int SEHFrameOffset = 0;
912
if (IsWin64Prologue && HasFP) {
913
SEHFrameOffset = calculateSetFPREG(NumBytes);
915
addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
916
StackPtr, false, SEHFrameOffset);
918
BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr).addReg(StackPtr);
921
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
923
.addImm(SEHFrameOffset)
924
.setMIFlag(MachineInstr::FrameSetup);
927
while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
928
const MachineInstr *FrameInstr = &*MBBI;
933
if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
934
if (X86::FR64RegClass.contains(Reg)) {
935
int Offset = getFrameIndexOffset(MF, FI);
936
Offset += SEHFrameOffset;
938
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
941
.setMIFlag(MachineInstr::FrameSetup);
948
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
949
.setMIFlag(MachineInstr::FrameSetup);
951
// Realign stack after we spilled callee-saved registers (so that we'll be
952
// able to calculate their offsets from the frame pointer).
953
// Win64 requires aligning the stack after the prologue.
954
if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
955
assert(HasFP && "There should be a frame pointer if stack is realigned.");
956
BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
959
// If we need a base pointer, set it up here. It's whatever the value
960
// of the stack pointer is at this point. Any variable size objects
961
// will be allocated after this, so we can still use the base pointer
962
// to reference locals.
963
if (TRI->hasBasePointer(MF)) {
964
// Update the base pointer with the current stack pointer.
965
unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
966
BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
968
.setMIFlag(MachineInstr::FrameSetup);
969
if (X86FI->getRestoreBasePointer()) {
970
// Stash value of base pointer. Saving RSP instead of EBP shortens
971
// dependence chain. Used by SjLj EH.
972
unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
973
addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
974
FramePtr, true, X86FI->getRestoreBasePointerOffset())
976
.setMIFlag(MachineInstr::FrameSetup);
979
if (X86FI->getHasSEHFramePtrSave()) {
980
// Stash the value of the frame pointer relative to the base pointer for
981
// Win32 EH. This supports Win32 EH, which does the inverse of the above:
982
// it recovers the frame pointer from the base pointer rather than the
984
unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
985
addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), BasePtr, true,
986
getFrameIndexOffset(MF, X86FI->getSEHFramePtrSaveIndex()))
988
.setMIFlag(MachineInstr::FrameSetup);
992
if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
993
// Mark end of stack pointer adjustment.
994
if (!HasFP && NumBytes) {
995
// Define the current CFA rule to use the provided offset.
997
BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
998
nullptr, -StackSize + stackGrowth));
1001
// Emit DWARF info specifying the offsets of the callee-saved registers.
1003
emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1007
bool X86FrameLowering::canUseLEAForSPInEpilogue(
1008
const MachineFunction &MF) const {
1009
// We can't use LEA instructions for adjusting the stack pointer if this is a
1010
// leaf function in the Win64 ABI. Only ADD instructions may be used to
1011
// deallocate the stack.
1012
// This means that we can use LEA for SP in two situations:
1013
// 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1014
// 2. We *have* a frame pointer which means we are permitted to use LEA.
1015
return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1018
void X86FrameLowering::emitEpilogue(MachineFunction &MF,
1019
MachineBasicBlock &MBB) const {
1020
const MachineFrameInfo *MFI = MF.getFrameInfo();
1021
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1022
MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
1024
if (MBBI != MBB.end())
1025
DL = MBBI->getDebugLoc();
1026
// standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1027
const bool Is64BitILP32 = STI.isTarget64BitILP32();
1028
unsigned FramePtr = TRI->getFrameRegister(MF);
1029
unsigned MachineFramePtr =
1030
Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
1033
bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1035
IsWin64Prologue && MF.getFunction()->needsUnwindTableEntry();
1037
// Get the number of bytes to allocate from the FrameInfo.
1038
uint64_t StackSize = MFI->getStackSize();
1039
uint64_t MaxAlign = calculateMaxStackAlign(MF);
1040
unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1041
uint64_t NumBytes = 0;
1044
// Calculate required stack adjustment.
1045
uint64_t FrameSize = StackSize - SlotSize;
1046
NumBytes = FrameSize - CSSize;
1048
// Callee-saved registers were pushed on stack before the stack was
1050
if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1051
NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1054
BuildMI(MBB, MBBI, DL,
1055
TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
1057
NumBytes = StackSize - CSSize;
1059
uint64_t SEHStackAllocAmt = NumBytes;
1061
// Skip the callee-saved pop instructions.
1062
while (MBBI != MBB.begin()) {
1063
MachineBasicBlock::iterator PI = std::prev(MBBI);
1064
unsigned Opc = PI->getOpcode();
1066
if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1067
!PI->isTerminator())
1072
MachineBasicBlock::iterator FirstCSPop = MBBI;
1074
if (MBBI != MBB.end())
1075
DL = MBBI->getDebugLoc();
1077
// If there is an ADD32ri or SUB32ri of ESP immediately before this
1078
// instruction, merge the two instructions.
1079
if (NumBytes || MFI->hasVarSizedObjects())
1080
mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1082
// If dynamic alloca is used, then reset esp to point to the last callee-saved
1083
// slot before popping them off! Same applies for the case, when stack was
1085
if (TRI->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1086
if (TRI->needsStackRealignment(MF))
1088
unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1089
uint64_t LEAAmount =
1090
IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1092
// There are only two legal forms of epilogue:
1093
// - add SEHAllocationSize, %rsp
1094
// - lea SEHAllocationSize(%FramePtr), %rsp
1096
// 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1097
// However, we may use this sequence if we have a frame pointer because the
1098
// effects of the prologue can safely be undone.
1099
if (LEAAmount != 0) {
1100
unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1101
addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1102
FramePtr, false, LEAAmount);
1105
unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1106
BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1110
} else if (NumBytes) {
1111
// Adjust stack pointer back: ESP += numbytes.
1112
emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
1116
// Windows unwinder will not invoke function's exception handler if IP is
1117
// either in prologue or in epilogue. This behavior causes a problem when a
1118
// call immediately precedes an epilogue, because the return address points
1119
// into the epilogue. To cope with that, we insert an epilogue marker here,
1120
// then replace it with a 'nop' if it ends up immediately after a CALL in the
1121
// final emitted code.
1123
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1125
// Add the return addr area delta back since we are not tail calling.
1126
int Offset = -1 * X86FI->getTCReturnAddrDelta();
1127
assert(Offset >= 0 && "TCDelta should never be positive");
1129
MBBI = MBB.getFirstTerminator();
1131
// Check for possible merge with preceding ADD instruction.
1132
Offset += mergeSPUpdates(MBB, MBBI, true);
1133
emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
1137
int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1139
const MachineFrameInfo *MFI = MF.getFrameInfo();
1140
// Offset will hold the offset from the stack pointer at function entry to the
1142
// We need to factor in additional offsets applied during the prologue to the
1143
// frame, base, and stack pointer depending on which is used.
1144
int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1145
const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1146
unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1147
uint64_t StackSize = MFI->getStackSize();
1148
bool HasFP = hasFP(MF);
1149
bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1150
int64_t FPDelta = 0;
1152
if (IsWin64Prologue) {
1153
assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1155
// Calculate required stack adjustment.
1156
uint64_t FrameSize = StackSize - SlotSize;
1157
// If required, include space for extra hidden slot for stashing base pointer.
1158
if (X86FI->getRestoreBasePointer())
1159
FrameSize += SlotSize;
1160
uint64_t NumBytes = FrameSize - CSSize;
1162
uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1163
if (FI && FI == X86FI->getFAIndex())
1164
return -SEHFrameOffset;
1166
// FPDelta is the offset from the "traditional" FP location of the old base
1167
// pointer followed by return address and the location required by the
1168
// restricted Win64 prologue.
1169
// Add FPDelta to all offsets below that go through the frame pointer.
1170
FPDelta = FrameSize - SEHFrameOffset;
1171
assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1172
"FPDelta isn't aligned per the Win64 ABI!");
1176
if (TRI->hasBasePointer(MF)) {
1177
assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1179
// Skip the saved EBP.
1180
return Offset + SlotSize + FPDelta;
1182
assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1183
return Offset + StackSize;
1185
} else if (TRI->needsStackRealignment(MF)) {
1187
// Skip the saved EBP.
1188
return Offset + SlotSize + FPDelta;
1190
assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1191
return Offset + StackSize;
1193
// FIXME: Support tail calls
1196
return Offset + StackSize;
1198
// Skip the saved EBP.
1201
// Skip the RETADDR move area
1202
int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1203
if (TailCallReturnAddrDelta < 0)
1204
Offset -= TailCallReturnAddrDelta;
1207
return Offset + FPDelta;
1210
int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1211
unsigned &FrameReg) const {
1212
// We can't calculate offset from frame pointer if the stack is realigned,
1213
// so enforce usage of stack/base pointer. The base pointer is used when we
1214
// have dynamic allocas in addition to dynamic realignment.
1215
if (TRI->hasBasePointer(MF))
1216
FrameReg = TRI->getBaseRegister();
1217
else if (TRI->needsStackRealignment(MF))
1218
FrameReg = TRI->getStackRegister();
1220
FrameReg = TRI->getFrameRegister(MF);
1221
return getFrameIndexOffset(MF, FI);
1224
// Simplified from getFrameIndexOffset keeping only StackPointer cases
1225
int X86FrameLowering::getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const {
1226
const MachineFrameInfo *MFI = MF.getFrameInfo();
1227
// Does not include any dynamic realign.
1228
const uint64_t StackSize = MFI->getStackSize();
1231
// Note: LLVM arranges the stack as:
1232
// Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1233
// > "Stack Slots" (<--SP)
1234
// We can always address StackSlots from RSP. We can usually (unless
1235
// needsStackRealignment) address CSRs from RSP, but sometimes need to
1236
// address them from RBP. FixedObjects can be placed anywhere in the stack
1237
// frame depending on their specific requirements (i.e. we can actually
1238
// refer to arguments to the function which are stored in the *callers*
1239
// frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1240
// AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1242
assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1244
// We don't handle tail calls, and shouldn't be seeing them
1246
int TailCallReturnAddrDelta =
1247
MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1248
assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1252
// This is how the math works out:
1254
// %rsp grows (i.e. gets lower) left to right. Each box below is
1255
// one word (eight bytes). Obj0 is the stack slot we're trying to
1258
// ----------------------------------
1259
// | BP | Obj0 | Obj1 | ... | ObjN |
1260
// ----------------------------------
1264
// A is the incoming stack pointer.
1265
// (B - A) is the local area offset (-8 for x86-64) [1]
1266
// (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1268
// |(E - B)| is the StackSize (absolute value, positive). For a
1269
// stack that grown down, this works out to be (B - E). [3]
1271
// E is also the value of %rsp after stack has been set up, and we
1272
// want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1273
// (C - E) == (C - A) - (B - A) + (B - E)
1274
// { Using [1], [2] and [3] above }
1275
// == getObjectOffset - LocalAreaOffset + StackSize
1278
// Get the Offset from the StackPointer
1279
int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1281
return Offset + StackSize;
1283
// Simplified from getFrameIndexReference keeping only StackPointer cases
1284
int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1286
unsigned &FrameReg) const {
1287
assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1289
FrameReg = TRI->getStackRegister();
1290
return getFrameIndexOffsetFromSP(MF, FI);
1293
bool X86FrameLowering::assignCalleeSavedSpillSlots(
1294
MachineFunction &MF, const TargetRegisterInfo *TRI,
1295
std::vector<CalleeSavedInfo> &CSI) const {
1296
MachineFrameInfo *MFI = MF.getFrameInfo();
1297
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1299
unsigned CalleeSavedFrameSize = 0;
1300
int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1303
// emitPrologue always spills frame register the first thing.
1304
SpillSlotOffset -= SlotSize;
1305
MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1307
// Since emitPrologue and emitEpilogue will handle spilling and restoring of
1308
// the frame register, we can delete it from CSI list and not have to worry
1309
// about avoiding it later.
1310
unsigned FPReg = TRI->getFrameRegister(MF);
1311
for (unsigned i = 0; i < CSI.size(); ++i) {
1312
if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1313
CSI.erase(CSI.begin() + i);
1319
// Assign slots for GPRs. It increases frame size.
1320
for (unsigned i = CSI.size(); i != 0; --i) {
1321
unsigned Reg = CSI[i - 1].getReg();
1323
if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1326
SpillSlotOffset -= SlotSize;
1327
CalleeSavedFrameSize += SlotSize;
1329
int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1330
CSI[i - 1].setFrameIdx(SlotIndex);
1333
X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1335
// Assign slots for XMMs.
1336
for (unsigned i = CSI.size(); i != 0; --i) {
1337
unsigned Reg = CSI[i - 1].getReg();
1338
if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1341
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1343
SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1345
SpillSlotOffset -= RC->getSize();
1347
MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1348
CSI[i - 1].setFrameIdx(SlotIndex);
1349
MFI->ensureMaxAlignment(RC->getAlignment());
1355
bool X86FrameLowering::spillCalleeSavedRegisters(
1356
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1357
const std::vector<CalleeSavedInfo> &CSI,
1358
const TargetRegisterInfo *TRI) const {
1359
DebugLoc DL = MBB.findDebugLoc(MI);
1361
// Push GPRs. It increases frame size.
1362
unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1363
for (unsigned i = CSI.size(); i != 0; --i) {
1364
unsigned Reg = CSI[i - 1].getReg();
1366
if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1368
// Add the callee-saved register as live-in. It's killed at the spill.
1371
BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1372
.setMIFlag(MachineInstr::FrameSetup);
1375
// Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1376
// It can be done by spilling XMMs to stack frame.
1377
for (unsigned i = CSI.size(); i != 0; --i) {
1378
unsigned Reg = CSI[i-1].getReg();
1379
if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1381
// Add the callee-saved register as live-in. It's killed at the spill.
1383
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1385
TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1388
MI->setFlag(MachineInstr::FrameSetup);
1395
bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1396
MachineBasicBlock::iterator MI,
1397
const std::vector<CalleeSavedInfo> &CSI,
1398
const TargetRegisterInfo *TRI) const {
1402
DebugLoc DL = MBB.findDebugLoc(MI);
1404
// Reload XMMs from stack frame.
1405
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1406
unsigned Reg = CSI[i].getReg();
1407
if (X86::GR64RegClass.contains(Reg) ||
1408
X86::GR32RegClass.contains(Reg))
1411
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1412
TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1416
unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1417
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1418
unsigned Reg = CSI[i].getReg();
1419
if (!X86::GR64RegClass.contains(Reg) &&
1420
!X86::GR32RegClass.contains(Reg))
1423
BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1428
void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
1429
BitVector &SavedRegs,
1430
RegScavenger *RS) const {
1431
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1433
MachineFrameInfo *MFI = MF.getFrameInfo();
1435
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1436
int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1438
if (TailCallReturnAddrDelta < 0) {
1439
// create RETURNADDR area
1448
MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1449
TailCallReturnAddrDelta - SlotSize, true);
1452
// Spill the BasePtr if it's used.
1453
if (TRI->hasBasePointer(MF))
1454
SavedRegs.set(TRI->getBaseRegister());
1458
HasNestArgument(const MachineFunction *MF) {
1459
const Function *F = MF->getFunction();
1460
for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1462
if (I->hasNestAttr())
1468
/// GetScratchRegister - Get a temp register for performing work in the
1469
/// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1470
/// and the properties of the function either one or two registers will be
1471
/// needed. Set primary to true for the first register, false for the second.
1473
GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1474
CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1477
if (CallingConvention == CallingConv::HiPE) {
1479
return Primary ? X86::R14 : X86::R13;
1481
return Primary ? X86::EBX : X86::EDI;
1486
return Primary ? X86::R11 : X86::R12;
1488
return Primary ? X86::R11D : X86::R12D;
1491
bool IsNested = HasNestArgument(&MF);
1493
if (CallingConvention == CallingConv::X86_FastCall ||
1494
CallingConvention == CallingConv::Fast) {
1496
report_fatal_error("Segmented stacks does not support fastcall with "
1497
"nested function.");
1498
return Primary ? X86::EAX : X86::ECX;
1501
return Primary ? X86::EDX : X86::EAX;
1502
return Primary ? X86::ECX : X86::EAX;
1505
// The stack limit in the TCB is set to this many bytes above the actual stack
1507
static const uint64_t kSplitStackAvailable = 256;
1509
void X86FrameLowering::adjustForSegmentedStacks(
1510
MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1511
MachineFrameInfo *MFI = MF.getFrameInfo();
1513
unsigned TlsReg, TlsOffset;
1516
unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1517
assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1518
"Scratch register is live-in");
1520
if (MF.getFunction()->isVarArg())
1521
report_fatal_error("Segmented stacks do not support vararg functions.");
1522
if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1523
!STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1524
!STI.isTargetDragonFly())
1525
report_fatal_error("Segmented stacks not supported on this platform.");
1527
// Eventually StackSize will be calculated by a link-time pass; which will
1528
// also decide whether checking code needs to be injected into this particular
1530
StackSize = MFI->getStackSize();
1532
// Do not generate a prologue for functions with a stack of size zero
1536
MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1537
MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1538
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1539
bool IsNested = false;
1541
// We need to know if the function has a nest argument only in 64 bit mode.
1543
IsNested = HasNestArgument(&MF);
1545
// The MOV R10, RAX needs to be in a different block, since the RET we emit in
1546
// allocMBB needs to be last (terminating) instruction.
1548
for (MachineBasicBlock::livein_iterator i = PrologueMBB.livein_begin(),
1549
e = PrologueMBB.livein_end();
1551
allocMBB->addLiveIn(*i);
1552
checkMBB->addLiveIn(*i);
1556
allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1558
MF.push_front(allocMBB);
1559
MF.push_front(checkMBB);
1561
// When the frame size is less than 256 we just compare the stack
1562
// boundary directly to the value of the stack pointer, per gcc.
1563
bool CompareStackPointer = StackSize < kSplitStackAvailable;
1565
// Read the limit off the current stacklet off the stack_guard location.
1567
if (STI.isTargetLinux()) {
1569
TlsOffset = IsLP64 ? 0x70 : 0x40;
1570
} else if (STI.isTargetDarwin()) {
1572
TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1573
} else if (STI.isTargetWin64()) {
1575
TlsOffset = 0x28; // pvArbitrary, reserved for application use
1576
} else if (STI.isTargetFreeBSD()) {
1579
} else if (STI.isTargetDragonFly()) {
1581
TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1583
report_fatal_error("Segmented stacks not supported on this platform.");
1586
if (CompareStackPointer)
1587
ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1589
BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1590
.addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1592
BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1593
.addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1595
if (STI.isTargetLinux()) {
1598
} else if (STI.isTargetDarwin()) {
1600
TlsOffset = 0x48 + 90*4;
1601
} else if (STI.isTargetWin32()) {
1603
TlsOffset = 0x14; // pvArbitrary, reserved for application use
1604
} else if (STI.isTargetDragonFly()) {
1606
TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1607
} else if (STI.isTargetFreeBSD()) {
1608
report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1610
report_fatal_error("Segmented stacks not supported on this platform.");
1613
if (CompareStackPointer)
1614
ScratchReg = X86::ESP;
1616
BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1617
.addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1619
if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1620
STI.isTargetDragonFly()) {
1621
BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1622
.addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1623
} else if (STI.isTargetDarwin()) {
1625
// TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1626
unsigned ScratchReg2;
1628
if (CompareStackPointer) {
1629
// The primary scratch register is available for holding the TLS offset.
1630
ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1631
SaveScratch2 = false;
1633
// Need to use a second register to hold the TLS offset
1634
ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1636
// Unfortunately, with fastcc the second scratch register may hold an
1638
SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1641
// If Scratch2 is live-in then it needs to be saved.
1642
assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1643
"Scratch register is live-in and not saved");
1646
BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1647
.addReg(ScratchReg2, RegState::Kill);
1649
BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1651
BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1653
.addReg(ScratchReg2).addImm(1).addReg(0)
1658
BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1662
// This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1663
// It jumps to normal execution of the function body.
1664
BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
1666
// On 32 bit we first push the arguments size and then the frame size. On 64
1667
// bit, we pass the stack frame size in r10 and the argument size in r11.
1669
// Functions with nested arguments use R10, so it needs to be saved across
1670
// the call to _morestack
1672
const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1673
const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1674
const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1675
const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1676
const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1679
BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1681
BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1683
BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1684
.addImm(X86FI->getArgumentStackSize());
1686
BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1687
.addImm(X86FI->getArgumentStackSize());
1688
BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1692
// __morestack is in libgcc
1693
if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1694
// Under the large code model, we cannot assume that __morestack lives
1695
// within 2^31 bytes of the call site, so we cannot use pc-relative
1696
// addressing. We cannot perform the call via a temporary register,
1697
// as the rax register may be used to store the static chain, and all
1698
// other suitable registers may be either callee-save or used for
1699
// parameter passing. We cannot use the stack at this point either
1700
// because __morestack manipulates the stack directly.
1702
// To avoid these issues, perform an indirect call via a read-only memory
1703
// location containing the address.
1705
// This solution is not perfect, as it assumes that the .rodata section
1706
// is laid out within 2^31 bytes of each function body, but this seems
1707
// to be sufficient for JIT.
1708
BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1712
.addExternalSymbol("__morestack_addr")
1714
MF.getMMI().setUsesMorestackAddr(true);
1717
BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1718
.addExternalSymbol("__morestack");
1720
BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1721
.addExternalSymbol("__morestack");
1725
BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1727
BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1729
allocMBB->addSuccessor(&PrologueMBB);
1731
checkMBB->addSuccessor(allocMBB);
1732
checkMBB->addSuccessor(&PrologueMBB);
1739
/// Erlang programs may need a special prologue to handle the stack size they
1740
/// might need at runtime. That is because Erlang/OTP does not implement a C
1741
/// stack but uses a custom implementation of hybrid stack/heap architecture.
1742
/// (for more information see Eric Stenman's Ph.D. thesis:
1743
/// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1746
/// temp0 = sp - MaxStack
1747
/// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1751
/// call inc_stack # doubles the stack space
1752
/// temp0 = sp - MaxStack
1753
/// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1754
void X86FrameLowering::adjustForHiPEPrologue(
1755
MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1756
MachineFrameInfo *MFI = MF.getFrameInfo();
1758
// HiPE-specific values
1759
const unsigned HipeLeafWords = 24;
1760
const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1761
const unsigned Guaranteed = HipeLeafWords * SlotSize;
1762
unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1763
MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1764
unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1766
assert(STI.isTargetLinux() &&
1767
"HiPE prologue is only supported on Linux operating systems.");
1769
// Compute the largest caller's frame that is needed to fit the callees'
1770
// frames. This 'MaxStack' is computed from:
1772
// a) the fixed frame size, which is the space needed for all spilled temps,
1773
// b) outgoing on-stack parameter areas, and
1774
// c) the minimum stack space this function needs to make available for the
1775
// functions it calls (a tunable ABI property).
1776
if (MFI->hasCalls()) {
1777
unsigned MoreStackForCalls = 0;
1779
for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1780
MBBI != MBBE; ++MBBI)
1781
for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1786
// Get callee operand.
1787
const MachineOperand &MO = MI->getOperand(0);
1789
// Only take account of global function calls (no closures etc.).
1793
const Function *F = dyn_cast<Function>(MO.getGlobal());
1797
// Do not update 'MaxStack' for primitive and built-in functions
1798
// (encoded with names either starting with "erlang."/"bif_" or not
1799
// having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1800
// "_", such as the BIF "suspend_0") as they are executed on another
1802
if (F->getName().find("erlang.") != StringRef::npos ||
1803
F->getName().find("bif_") != StringRef::npos ||
1804
F->getName().find_first_of("._") == StringRef::npos)
1807
unsigned CalleeStkArity =
1808
F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1809
if (HipeLeafWords - 1 > CalleeStkArity)
1810
MoreStackForCalls = std::max(MoreStackForCalls,
1811
(HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1813
MaxStack += MoreStackForCalls;
1816
// If the stack frame needed is larger than the guaranteed then runtime checks
1817
// and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1818
if (MaxStack > Guaranteed) {
1819
MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1820
MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1822
for (MachineBasicBlock::livein_iterator I = PrologueMBB.livein_begin(),
1823
E = PrologueMBB.livein_end();
1825
stackCheckMBB->addLiveIn(*I);
1826
incStackMBB->addLiveIn(*I);
1829
MF.push_front(incStackMBB);
1830
MF.push_front(stackCheckMBB);
1832
unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1833
unsigned LEAop, CMPop, CALLop;
1837
LEAop = X86::LEA64r;
1838
CMPop = X86::CMP64rm;
1839
CALLop = X86::CALL64pcrel32;
1840
SPLimitOffset = 0x90;
1844
LEAop = X86::LEA32r;
1845
CMPop = X86::CMP32rm;
1846
CALLop = X86::CALLpcrel32;
1847
SPLimitOffset = 0x4c;
1850
ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1851
assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1852
"HiPE prologue scratch register is live-in");
1854
// Create new MBB for StackCheck:
1855
addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1856
SPReg, false, -MaxStack);
1857
// SPLimitOffset is in a fixed heap location (pointed by BP).
1858
addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1859
.addReg(ScratchReg), PReg, false, SPLimitOffset);
1860
BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
1862
// Create new MBB for IncStack:
1863
BuildMI(incStackMBB, DL, TII.get(CALLop)).
1864
addExternalSymbol("inc_stack_0");
1865
addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1866
SPReg, false, -MaxStack);
1867
addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1868
.addReg(ScratchReg), PReg, false, SPLimitOffset);
1869
BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1871
stackCheckMBB->addSuccessor(&PrologueMBB, 99);
1872
stackCheckMBB->addSuccessor(incStackMBB, 1);
1873
incStackMBB->addSuccessor(&PrologueMBB, 99);
1874
incStackMBB->addSuccessor(incStackMBB, 1);
1881
void X86FrameLowering::
1882
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1883
MachineBasicBlock::iterator I) const {
1884
bool reserveCallFrame = hasReservedCallFrame(MF);
1885
unsigned Opcode = I->getOpcode();
1886
bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1887
DebugLoc DL = I->getDebugLoc();
1888
uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
1889
uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
1892
if (!reserveCallFrame) {
1893
// If the stack pointer can be changed after prologue, turn the
1894
// adjcallstackup instruction into a 'sub ESP, <amt>' and the
1895
// adjcallstackdown instruction into 'add ESP, <amt>'
1899
// We need to keep the stack aligned properly. To do this, we round the
1900
// amount of space needed for the outgoing arguments up to the next
1901
// alignment boundary.
1902
unsigned StackAlign = getStackAlignment();
1903
Amount = RoundUpToAlignment(Amount, StackAlign);
1905
// Factor out the amount that gets handled inside the sequence
1906
// (Pushes of argument for frame setup, callee pops for frame destroy)
1907
Amount -= InternalAmt;
1910
// Add Amount to SP to destroy a frame, and subtract to setup.
1911
int Offset = isDestroy ? Amount : -Amount;
1912
BuildStackAdjustment(MBB, I, DL, Offset, /*InEpilogue=*/false);
1917
if (isDestroy && InternalAmt) {
1918
// If we are performing frame pointer elimination and if the callee pops
1919
// something off the stack pointer, add it back. We do this until we have
1920
// more advanced stack pointer tracking ability.
1921
// We are not tracking the stack pointer adjustment by the callee, so make
1922
// sure we restore the stack pointer immediately after the call, there may
1923
// be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1924
MachineBasicBlock::iterator B = MBB.begin();
1925
while (I != B && !std::prev(I)->isCall())
1927
BuildStackAdjustment(MBB, I, DL, -InternalAmt, /*InEpilogue=*/false);
1931
bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
1932
assert(MBB.getParent() && "Block is not attached to a function!");
1934
if (canUseLEAForSPInEpilogue(*MBB.getParent()))
1937
// If we cannot use LEA to adjust SP, we may need to use ADD, which
1938
// clobbers the EFLAGS. Check that none of the terminators reads the
1939
// EFLAGS, and if one uses it, conservatively assume this is not
1940
// safe to insert the epilogue here.
1941
return !terminatorsNeedFlagsAsInput(MBB);
added
removed
lib/Target/X86/X86FrameLowering.cpp
