1
; RUN: llc < %s -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
2
; RUN: llc < %s -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3
; RUN: llc < %s -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4
; RUN: llc < %s -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5
; RUN: llc < %s -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7
; Verify that the DAG combiner correctly folds bitwise operations across
8
; shuffles, nested shuffles with undef, pairs of nested shuffles, and other
9
; basic and always-safe patterns. Also test that the DAG combiner will combine
10
; target-specific shuffle instructions where reasonable.
12
target triple = "x86_64-unknown-unknown"
14
declare <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32>, i8)
15
declare <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16>, i8)
16
declare <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16>, i8)
18
define <4 x i32> @combine_pshufd1(<4 x i32> %a) {
19
; ALL-LABEL: combine_pshufd1:
20
; ALL: # BB#0: # %entry
23
%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
24
%c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 27)
28
define <4 x i32> @combine_pshufd2(<4 x i32> %a) {
29
; ALL-LABEL: combine_pshufd2:
30
; ALL: # BB#0: # %entry
33
%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
34
%b.cast = bitcast <4 x i32> %b to <8 x i16>
35
%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 -28)
36
%c.cast = bitcast <8 x i16> %c to <4 x i32>
37
%d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
41
define <4 x i32> @combine_pshufd3(<4 x i32> %a) {
42
; ALL-LABEL: combine_pshufd3:
43
; ALL: # BB#0: # %entry
46
%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 27)
47
%b.cast = bitcast <4 x i32> %b to <8 x i16>
48
%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 -28)
49
%c.cast = bitcast <8 x i16> %c to <4 x i32>
50
%d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 27)
54
define <4 x i32> @combine_pshufd4(<4 x i32> %a) {
55
; SSE-LABEL: combine_pshufd4:
56
; SSE: # BB#0: # %entry
57
; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
60
; AVX-LABEL: combine_pshufd4:
61
; AVX: # BB#0: # %entry
62
; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
65
%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -31)
66
%b.cast = bitcast <4 x i32> %b to <8 x i16>
67
%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b.cast, i8 27)
68
%c.cast = bitcast <8 x i16> %c to <4 x i32>
69
%d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -31)
73
define <4 x i32> @combine_pshufd5(<4 x i32> %a) {
74
; SSE-LABEL: combine_pshufd5:
75
; SSE: # BB#0: # %entry
76
; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
79
; AVX-LABEL: combine_pshufd5:
80
; AVX: # BB#0: # %entry
81
; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
84
%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 -76)
85
%b.cast = bitcast <4 x i32> %b to <8 x i16>
86
%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b.cast, i8 27)
87
%c.cast = bitcast <8 x i16> %c to <4 x i32>
88
%d = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %c.cast, i8 -76)
92
define <4 x i32> @combine_pshufd6(<4 x i32> %a) {
93
; SSE-LABEL: combine_pshufd6:
94
; SSE: # BB#0: # %entry
95
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
98
; AVX-LABEL: combine_pshufd6:
99
; AVX: # BB#0: # %entry
100
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
103
%b = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %a, i8 0)
104
%c = call <4 x i32> @llvm.x86.sse2.pshuf.d(<4 x i32> %b, i8 8)
108
define <8 x i16> @combine_pshuflw1(<8 x i16> %a) {
109
; ALL-LABEL: combine_pshuflw1:
110
; ALL: # BB#0: # %entry
113
%b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
114
%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
118
define <8 x i16> @combine_pshuflw2(<8 x i16> %a) {
119
; ALL-LABEL: combine_pshuflw2:
120
; ALL: # BB#0: # %entry
123
%b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
124
%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 -28)
125
%d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
129
define <8 x i16> @combine_pshuflw3(<8 x i16> %a) {
130
; SSE-LABEL: combine_pshuflw3:
131
; SSE: # BB#0: # %entry
132
; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
135
; AVX-LABEL: combine_pshuflw3:
136
; AVX: # BB#0: # %entry
137
; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
140
%b = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %a, i8 27)
141
%c = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %b, i8 27)
142
%d = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %c, i8 27)
146
define <8 x i16> @combine_pshufhw1(<8 x i16> %a) {
147
; SSE-LABEL: combine_pshufhw1:
148
; SSE: # BB#0: # %entry
149
; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
152
; AVX-LABEL: combine_pshufhw1:
153
; AVX: # BB#0: # %entry
154
; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
157
%b = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %a, i8 27)
158
%c = call <8 x i16> @llvm.x86.sse2.pshufl.w(<8 x i16> %b, i8 27)
159
%d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
163
define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
164
; SSE-LABEL: combine_bitwise_ops_test1:
166
; SSE-NEXT: pand %xmm1, %xmm0
167
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
170
; AVX-LABEL: combine_bitwise_ops_test1:
172
; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
173
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
175
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
176
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
177
%and = and <4 x i32> %shuf1, %shuf2
181
define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
182
; SSE-LABEL: combine_bitwise_ops_test2:
184
; SSE-NEXT: por %xmm1, %xmm0
185
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
188
; AVX-LABEL: combine_bitwise_ops_test2:
190
; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
191
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
193
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
194
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
195
%or = or <4 x i32> %shuf1, %shuf2
199
define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
200
; SSE-LABEL: combine_bitwise_ops_test3:
202
; SSE-NEXT: pxor %xmm1, %xmm0
203
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
206
; AVX-LABEL: combine_bitwise_ops_test3:
208
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
209
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
211
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
212
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
213
%xor = xor <4 x i32> %shuf1, %shuf2
217
define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218
; SSE-LABEL: combine_bitwise_ops_test4:
220
; SSE-NEXT: pand %xmm1, %xmm0
221
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
224
; AVX-LABEL: combine_bitwise_ops_test4:
226
; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
227
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
229
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
230
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
231
%and = and <4 x i32> %shuf1, %shuf2
235
define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
236
; SSE-LABEL: combine_bitwise_ops_test5:
238
; SSE-NEXT: por %xmm1, %xmm0
239
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
242
; AVX-LABEL: combine_bitwise_ops_test5:
244
; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
245
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
247
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
248
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
249
%or = or <4 x i32> %shuf1, %shuf2
253
define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
254
; SSE-LABEL: combine_bitwise_ops_test6:
256
; SSE-NEXT: pxor %xmm1, %xmm0
257
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
260
; AVX-LABEL: combine_bitwise_ops_test6:
262
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
263
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
265
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
266
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
267
%xor = xor <4 x i32> %shuf1, %shuf2
272
; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
273
; are not performing a swizzle operations.
275
define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
276
; SSE2-LABEL: combine_bitwise_ops_test1b:
278
; SSE2-NEXT: pand %xmm1, %xmm0
279
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
280
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
281
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
284
; SSSE3-LABEL: combine_bitwise_ops_test1b:
286
; SSSE3-NEXT: pand %xmm1, %xmm0
287
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
288
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
289
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
292
; SSE41-LABEL: combine_bitwise_ops_test1b:
294
; SSE41-NEXT: pand %xmm1, %xmm0
295
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
298
; AVX1-LABEL: combine_bitwise_ops_test1b:
300
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
301
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
304
; AVX2-LABEL: combine_bitwise_ops_test1b:
306
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
307
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
309
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
310
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
311
%and = and <4 x i32> %shuf1, %shuf2
315
define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
316
; SSE2-LABEL: combine_bitwise_ops_test2b:
318
; SSE2-NEXT: por %xmm1, %xmm0
319
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
320
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
321
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
324
; SSSE3-LABEL: combine_bitwise_ops_test2b:
326
; SSSE3-NEXT: por %xmm1, %xmm0
327
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
328
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
329
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
332
; SSE41-LABEL: combine_bitwise_ops_test2b:
334
; SSE41-NEXT: por %xmm1, %xmm0
335
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
338
; AVX1-LABEL: combine_bitwise_ops_test2b:
340
; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
341
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
344
; AVX2-LABEL: combine_bitwise_ops_test2b:
346
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
347
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
349
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
350
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
351
%or = or <4 x i32> %shuf1, %shuf2
355
define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
356
; SSE2-LABEL: combine_bitwise_ops_test3b:
358
; SSE2-NEXT: xorps %xmm1, %xmm0
359
; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
362
; SSSE3-LABEL: combine_bitwise_ops_test3b:
364
; SSSE3-NEXT: xorps %xmm1, %xmm0
365
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
368
; SSE41-LABEL: combine_bitwise_ops_test3b:
370
; SSE41-NEXT: pxor %xmm1, %xmm0
371
; SSE41-NEXT: pxor %xmm1, %xmm1
372
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
375
; AVX1-LABEL: combine_bitwise_ops_test3b:
377
; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
378
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
379
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
382
; AVX2-LABEL: combine_bitwise_ops_test3b:
384
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
385
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
386
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
388
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
389
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
390
%xor = xor <4 x i32> %shuf1, %shuf2
394
define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
395
; SSE2-LABEL: combine_bitwise_ops_test4b:
397
; SSE2-NEXT: pand %xmm1, %xmm0
398
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
399
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
400
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
403
; SSSE3-LABEL: combine_bitwise_ops_test4b:
405
; SSSE3-NEXT: pand %xmm1, %xmm0
406
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
407
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
408
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
411
; SSE41-LABEL: combine_bitwise_ops_test4b:
413
; SSE41-NEXT: pand %xmm1, %xmm0
414
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
417
; AVX1-LABEL: combine_bitwise_ops_test4b:
419
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
420
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
423
; AVX2-LABEL: combine_bitwise_ops_test4b:
425
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
426
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
428
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
429
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
430
%and = and <4 x i32> %shuf1, %shuf2
434
define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
435
; SSE2-LABEL: combine_bitwise_ops_test5b:
437
; SSE2-NEXT: por %xmm1, %xmm0
438
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
439
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
440
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
443
; SSSE3-LABEL: combine_bitwise_ops_test5b:
445
; SSSE3-NEXT: por %xmm1, %xmm0
446
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
447
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
448
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
451
; SSE41-LABEL: combine_bitwise_ops_test5b:
453
; SSE41-NEXT: por %xmm1, %xmm0
454
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
457
; AVX1-LABEL: combine_bitwise_ops_test5b:
459
; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
460
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
463
; AVX2-LABEL: combine_bitwise_ops_test5b:
465
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
466
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
468
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
469
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
470
%or = or <4 x i32> %shuf1, %shuf2
474
define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
475
; SSE2-LABEL: combine_bitwise_ops_test6b:
477
; SSE2-NEXT: xorps %xmm1, %xmm0
478
; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
481
; SSSE3-LABEL: combine_bitwise_ops_test6b:
483
; SSSE3-NEXT: xorps %xmm1, %xmm0
484
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
487
; SSE41-LABEL: combine_bitwise_ops_test6b:
489
; SSE41-NEXT: pxor %xmm1, %xmm0
490
; SSE41-NEXT: pxor %xmm1, %xmm1
491
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
494
; AVX1-LABEL: combine_bitwise_ops_test6b:
496
; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
497
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
498
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
501
; AVX2-LABEL: combine_bitwise_ops_test6b:
503
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
504
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
505
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
507
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
508
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
509
%xor = xor <4 x i32> %shuf1, %shuf2
513
define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
514
; SSE2-LABEL: combine_bitwise_ops_test1c:
516
; SSE2-NEXT: pand %xmm1, %xmm0
517
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
518
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
519
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
522
; SSSE3-LABEL: combine_bitwise_ops_test1c:
524
; SSSE3-NEXT: pand %xmm1, %xmm0
525
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
526
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
527
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
530
; SSE41-LABEL: combine_bitwise_ops_test1c:
532
; SSE41-NEXT: pand %xmm1, %xmm0
533
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
534
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
537
; AVX1-LABEL: combine_bitwise_ops_test1c:
539
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
540
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
541
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
544
; AVX2-LABEL: combine_bitwise_ops_test1c:
546
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
547
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
548
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
550
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
551
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
552
%and = and <4 x i32> %shuf1, %shuf2
556
define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
557
; SSE2-LABEL: combine_bitwise_ops_test2c:
559
; SSE2-NEXT: por %xmm1, %xmm0
560
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
561
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
562
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
565
; SSSE3-LABEL: combine_bitwise_ops_test2c:
567
; SSSE3-NEXT: por %xmm1, %xmm0
568
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
569
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
570
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
573
; SSE41-LABEL: combine_bitwise_ops_test2c:
575
; SSE41-NEXT: por %xmm1, %xmm0
576
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
577
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
580
; AVX1-LABEL: combine_bitwise_ops_test2c:
582
; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
583
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
584
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
587
; AVX2-LABEL: combine_bitwise_ops_test2c:
589
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
590
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
591
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
593
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
594
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
595
%or = or <4 x i32> %shuf1, %shuf2
599
define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
600
; SSE2-LABEL: combine_bitwise_ops_test3c:
602
; SSE2-NEXT: pxor %xmm1, %xmm0
603
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
604
; SSE2-NEXT: pxor %xmm1, %xmm1
605
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
608
; SSSE3-LABEL: combine_bitwise_ops_test3c:
610
; SSSE3-NEXT: pxor %xmm1, %xmm0
611
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,2]
612
; SSSE3-NEXT: pxor %xmm1, %xmm1
613
; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
616
; SSE41-LABEL: combine_bitwise_ops_test3c:
618
; SSE41-NEXT: pxor %xmm1, %xmm0
619
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
620
; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
623
; AVX-LABEL: combine_bitwise_ops_test3c:
625
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
626
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
627
; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
629
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
630
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
631
%xor = xor <4 x i32> %shuf1, %shuf2
635
define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
636
; SSE2-LABEL: combine_bitwise_ops_test4c:
638
; SSE2-NEXT: pand %xmm1, %xmm0
639
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
640
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
641
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
644
; SSSE3-LABEL: combine_bitwise_ops_test4c:
646
; SSSE3-NEXT: pand %xmm1, %xmm0
647
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
648
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
649
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
652
; SSE41-LABEL: combine_bitwise_ops_test4c:
654
; SSE41-NEXT: pand %xmm1, %xmm0
655
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
656
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
659
; AVX1-LABEL: combine_bitwise_ops_test4c:
661
; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
662
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
663
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
666
; AVX2-LABEL: combine_bitwise_ops_test4c:
668
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
669
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
670
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
672
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
673
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
674
%and = and <4 x i32> %shuf1, %shuf2
678
define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
679
; SSE2-LABEL: combine_bitwise_ops_test5c:
681
; SSE2-NEXT: por %xmm1, %xmm0
682
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
683
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
684
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
687
; SSSE3-LABEL: combine_bitwise_ops_test5c:
689
; SSSE3-NEXT: por %xmm1, %xmm0
690
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
691
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
692
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
695
; SSE41-LABEL: combine_bitwise_ops_test5c:
697
; SSE41-NEXT: por %xmm1, %xmm0
698
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
699
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
702
; AVX1-LABEL: combine_bitwise_ops_test5c:
704
; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
705
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
706
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
709
; AVX2-LABEL: combine_bitwise_ops_test5c:
711
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
712
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
713
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
715
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
716
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
717
%or = or <4 x i32> %shuf1, %shuf2
721
define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
722
; SSE2-LABEL: combine_bitwise_ops_test6c:
724
; SSE2-NEXT: pxor %xmm1, %xmm0
725
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
726
; SSE2-NEXT: pxor %xmm0, %xmm0
727
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
730
; SSSE3-LABEL: combine_bitwise_ops_test6c:
732
; SSSE3-NEXT: pxor %xmm1, %xmm0
733
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
734
; SSSE3-NEXT: pxor %xmm0, %xmm0
735
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
738
; SSE41-LABEL: combine_bitwise_ops_test6c:
740
; SSE41-NEXT: pxor %xmm1, %xmm0
741
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,3]
742
; SSE41-NEXT: pxor %xmm0, %xmm0
743
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
746
; AVX1-LABEL: combine_bitwise_ops_test6c:
748
; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
749
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
750
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
751
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
754
; AVX2-LABEL: combine_bitwise_ops_test6c:
756
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
757
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
758
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
759
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
761
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
762
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
763
%xor = xor <4 x i32> %shuf1, %shuf2
767
define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
768
; SSE-LABEL: combine_nested_undef_test1:
770
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
773
; AVX-LABEL: combine_nested_undef_test1:
775
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
777
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
778
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
782
define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
783
; SSE-LABEL: combine_nested_undef_test2:
785
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
788
; AVX-LABEL: combine_nested_undef_test2:
790
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
792
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
793
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
797
define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
798
; SSE-LABEL: combine_nested_undef_test3:
800
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
803
; AVX-LABEL: combine_nested_undef_test3:
805
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
807
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
808
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
812
define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
813
; SSE-LABEL: combine_nested_undef_test4:
815
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
818
; AVX1-LABEL: combine_nested_undef_test4:
820
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
823
; AVX2-LABEL: combine_nested_undef_test4:
825
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
827
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
828
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
832
define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
833
; SSE-LABEL: combine_nested_undef_test5:
835
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
838
; AVX-LABEL: combine_nested_undef_test5:
840
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
842
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
843
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
847
define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
848
; SSE-LABEL: combine_nested_undef_test6:
850
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
853
; AVX-LABEL: combine_nested_undef_test6:
855
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
857
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
858
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
862
define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
863
; SSE-LABEL: combine_nested_undef_test7:
865
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
868
; AVX-LABEL: combine_nested_undef_test7:
870
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
872
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
873
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
877
define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
878
; SSE-LABEL: combine_nested_undef_test8:
880
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
883
; AVX-LABEL: combine_nested_undef_test8:
885
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
887
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
888
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
892
define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
893
; SSE-LABEL: combine_nested_undef_test9:
895
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
898
; AVX-LABEL: combine_nested_undef_test9:
900
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,2,2]
902
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
903
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
907
define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
908
; SSE-LABEL: combine_nested_undef_test10:
910
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
913
; AVX-LABEL: combine_nested_undef_test10:
915
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,3]
917
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
918
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
922
define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
923
; SSE-LABEL: combine_nested_undef_test11:
925
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
928
; AVX-LABEL: combine_nested_undef_test11:
930
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,1]
932
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
933
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
937
define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
938
; SSE-LABEL: combine_nested_undef_test12:
940
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
943
; AVX1-LABEL: combine_nested_undef_test12:
945
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
948
; AVX2-LABEL: combine_nested_undef_test12:
950
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
952
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
953
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
957
; The following pair of shuffles is folded into vector %A.
958
define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
959
; ALL-LABEL: combine_nested_undef_test13:
962
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
963
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
967
; The following pair of shuffles is folded into vector %B.
968
define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
969
; SSE-LABEL: combine_nested_undef_test14:
971
; SSE-NEXT: movaps %xmm1, %xmm0
974
; AVX-LABEL: combine_nested_undef_test14:
976
; AVX-NEXT: vmovaps %xmm1, %xmm0
978
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
979
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
984
; Verify that we don't optimize the following cases. We expect more than one shuffle.
986
; FIXME: Many of these already don't make sense, and the rest should stop
987
; making sense with th enew vector shuffle lowering. Revisit at least testing for
990
define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
991
; SSE2-LABEL: combine_nested_undef_test15:
993
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
994
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,1]
995
; SSE2-NEXT: movaps %xmm1, %xmm0
998
; SSSE3-LABEL: combine_nested_undef_test15:
1000
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
1001
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,1]
1002
; SSSE3-NEXT: movaps %xmm1, %xmm0
1005
; SSE41-LABEL: combine_nested_undef_test15:
1007
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
1008
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1009
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1012
; AVX1-LABEL: combine_nested_undef_test15:
1014
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
1015
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1016
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1019
; AVX2-LABEL: combine_nested_undef_test15:
1021
; AVX2-NEXT: vpbroadcastd %xmm1, %xmm1
1022
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1023
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
1025
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
1026
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1030
define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
1031
; SSE2-LABEL: combine_nested_undef_test16:
1033
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
1034
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,2,3]
1035
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1038
; SSSE3-LABEL: combine_nested_undef_test16:
1040
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
1041
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,2,3]
1042
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1045
; SSE41-LABEL: combine_nested_undef_test16:
1047
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
1048
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
1051
; AVX1-LABEL: combine_nested_undef_test16:
1053
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
1054
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
1057
; AVX2-LABEL: combine_nested_undef_test16:
1059
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
1060
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
1062
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1063
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1067
define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
1068
; SSE2-LABEL: combine_nested_undef_test17:
1070
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
1071
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
1074
; SSSE3-LABEL: combine_nested_undef_test17:
1076
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
1077
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1],xmm1[0,2]
1080
; SSE41-LABEL: combine_nested_undef_test17:
1082
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1083
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1086
; AVX1-LABEL: combine_nested_undef_test17:
1088
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1089
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1092
; AVX2-LABEL: combine_nested_undef_test17:
1094
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1095
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
1097
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1098
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1102
define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
1103
; SSE-LABEL: combine_nested_undef_test18:
1105
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
1108
; AVX-LABEL: combine_nested_undef_test18:
1110
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
1112
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1113
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
1117
define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
1118
; SSE2-LABEL: combine_nested_undef_test19:
1120
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1121
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,0,0,0]
1124
; SSSE3-LABEL: combine_nested_undef_test19:
1126
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1127
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,0,0,0]
1130
; SSE41-LABEL: combine_nested_undef_test19:
1132
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1133
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
1136
; AVX1-LABEL: combine_nested_undef_test19:
1138
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
1139
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
1142
; AVX2-LABEL: combine_nested_undef_test19:
1144
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
1145
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,0,0]
1147
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
1148
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
1152
define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
1153
; SSE2-LABEL: combine_nested_undef_test20:
1155
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
1156
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
1157
; SSE2-NEXT: movaps %xmm1, %xmm0
1160
; SSSE3-LABEL: combine_nested_undef_test20:
1162
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,3]
1163
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
1164
; SSSE3-NEXT: movaps %xmm1, %xmm0
1167
; SSE41-LABEL: combine_nested_undef_test20:
1169
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
1170
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
1173
; AVX1-LABEL: combine_nested_undef_test20:
1175
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
1176
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
1179
; AVX2-LABEL: combine_nested_undef_test20:
1181
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
1182
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,3,0]
1184
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
1185
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
1189
define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
1190
; SSE2-LABEL: combine_nested_undef_test21:
1192
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
1193
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,0,3]
1196
; SSSE3-LABEL: combine_nested_undef_test21:
1198
; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
1199
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,0,3]
1202
; SSE41-LABEL: combine_nested_undef_test21:
1204
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1205
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1208
; AVX1-LABEL: combine_nested_undef_test21:
1210
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1211
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1214
; AVX2-LABEL: combine_nested_undef_test21:
1216
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1217
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1219
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
1220
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1225
; Test that we correctly combine shuffles according to rule
1226
; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
1228
define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
1229
; SSE-LABEL: combine_nested_undef_test22:
1231
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1234
; AVX-LABEL: combine_nested_undef_test22:
1236
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
1238
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1239
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
1243
define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
1244
; SSE-LABEL: combine_nested_undef_test23:
1246
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1249
; AVX-LABEL: combine_nested_undef_test23:
1251
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
1253
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
1254
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
1258
define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
1259
; SSE-LABEL: combine_nested_undef_test24:
1261
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1264
; AVX-LABEL: combine_nested_undef_test24:
1266
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,3]
1268
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1269
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
1273
define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
1274
; SSE-LABEL: combine_nested_undef_test25:
1276
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1279
; AVX1-LABEL: combine_nested_undef_test25:
1281
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1284
; AVX2-LABEL: combine_nested_undef_test25:
1286
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1288
%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
1289
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
1293
define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
1294
; SSE-LABEL: combine_nested_undef_test26:
1296
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1299
; AVX-LABEL: combine_nested_undef_test26:
1301
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
1303
%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
1304
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
1308
define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
1309
; SSE-LABEL: combine_nested_undef_test27:
1311
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1314
; AVX1-LABEL: combine_nested_undef_test27:
1316
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
1319
; AVX2-LABEL: combine_nested_undef_test27:
1321
; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0
1323
%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
1324
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
1328
define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
1329
; SSE-LABEL: combine_nested_undef_test28:
1331
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1334
; AVX-LABEL: combine_nested_undef_test28:
1336
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
1338
%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
1339
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
1343
define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
1344
; SSE-LABEL: combine_test1:
1346
; SSE-NEXT: movaps %xmm1, %xmm0
1349
; AVX-LABEL: combine_test1:
1351
; AVX-NEXT: vmovaps %xmm1, %xmm0
1353
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1354
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1358
define <4 x float> @combine_test2(<4 x float> %a, <4 x float> %b) {
1359
; SSE2-LABEL: combine_test2:
1361
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1362
; SSE2-NEXT: movaps %xmm1, %xmm0
1365
; SSSE3-LABEL: combine_test2:
1367
; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1368
; SSSE3-NEXT: movaps %xmm1, %xmm0
1371
; SSE41-LABEL: combine_test2:
1373
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1376
; AVX-LABEL: combine_test2:
1378
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1380
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1381
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1385
define <4 x float> @combine_test3(<4 x float> %a, <4 x float> %b) {
1386
; SSE-LABEL: combine_test3:
1388
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1391
; AVX-LABEL: combine_test3:
1393
; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1395
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1396
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1400
define <4 x float> @combine_test4(<4 x float> %a, <4 x float> %b) {
1401
; SSE-LABEL: combine_test4:
1403
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1404
; SSE-NEXT: movapd %xmm1, %xmm0
1407
; AVX-LABEL: combine_test4:
1409
; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1411
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1412
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1416
define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
1417
; SSE2-LABEL: combine_test5:
1419
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1420
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1423
; SSSE3-LABEL: combine_test5:
1425
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1426
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1429
; SSE41-LABEL: combine_test5:
1431
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1434
; AVX-LABEL: combine_test5:
1436
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1438
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1439
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1443
define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
1444
; SSE-LABEL: combine_test6:
1446
; SSE-NEXT: movaps %xmm1, %xmm0
1449
; AVX-LABEL: combine_test6:
1451
; AVX-NEXT: vmovaps %xmm1, %xmm0
1453
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1454
%2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1458
define <4 x i32> @combine_test7(<4 x i32> %a, <4 x i32> %b) {
1459
; SSE2-LABEL: combine_test7:
1461
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1462
; SSE2-NEXT: movaps %xmm1, %xmm0
1465
; SSSE3-LABEL: combine_test7:
1467
; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1468
; SSSE3-NEXT: movaps %xmm1, %xmm0
1471
; SSE41-LABEL: combine_test7:
1473
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1476
; AVX1-LABEL: combine_test7:
1478
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1481
; AVX2-LABEL: combine_test7:
1483
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1485
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1486
%2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1490
define <4 x i32> @combine_test8(<4 x i32> %a, <4 x i32> %b) {
1491
; SSE-LABEL: combine_test8:
1493
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1496
; AVX-LABEL: combine_test8:
1498
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1500
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
1501
%2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1505
define <4 x i32> @combine_test9(<4 x i32> %a, <4 x i32> %b) {
1506
; SSE-LABEL: combine_test9:
1508
; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
1509
; SSE-NEXT: movdqa %xmm1, %xmm0
1512
; AVX-LABEL: combine_test9:
1514
; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
1516
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
1517
%2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1521
define <4 x i32> @combine_test10(<4 x i32> %a, <4 x i32> %b) {
1522
; SSE2-LABEL: combine_test10:
1524
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1525
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1528
; SSSE3-LABEL: combine_test10:
1530
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1531
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1534
; SSE41-LABEL: combine_test10:
1536
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1539
; AVX1-LABEL: combine_test10:
1541
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1544
; AVX2-LABEL: combine_test10:
1546
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1548
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1549
%2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
1553
define <4 x float> @combine_test11(<4 x float> %a, <4 x float> %b) {
1554
; ALL-LABEL: combine_test11:
1557
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1558
%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1562
define <4 x float> @combine_test12(<4 x float> %a, <4 x float> %b) {
1563
; SSE2-LABEL: combine_test12:
1565
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1566
; SSE2-NEXT: movaps %xmm1, %xmm0
1569
; SSSE3-LABEL: combine_test12:
1571
; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1572
; SSSE3-NEXT: movaps %xmm1, %xmm0
1575
; SSE41-LABEL: combine_test12:
1577
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1580
; AVX-LABEL: combine_test12:
1582
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1584
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1585
%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1589
define <4 x float> @combine_test13(<4 x float> %a, <4 x float> %b) {
1590
; SSE-LABEL: combine_test13:
1592
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1595
; AVX-LABEL: combine_test13:
1597
; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1599
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1600
%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1604
define <4 x float> @combine_test14(<4 x float> %a, <4 x float> %b) {
1605
; SSE-LABEL: combine_test14:
1607
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1610
; AVX-LABEL: combine_test14:
1612
; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1614
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1615
%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1619
define <4 x float> @combine_test15(<4 x float> %a, <4 x float> %b) {
1620
; SSE2-LABEL: combine_test15:
1622
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1623
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1626
; SSSE3-LABEL: combine_test15:
1628
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1629
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1632
; SSE41-LABEL: combine_test15:
1634
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1637
; AVX-LABEL: combine_test15:
1639
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1641
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1642
%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1646
define <4 x i32> @combine_test16(<4 x i32> %a, <4 x i32> %b) {
1647
; ALL-LABEL: combine_test16:
1650
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1651
%2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1655
define <4 x i32> @combine_test17(<4 x i32> %a, <4 x i32> %b) {
1656
; SSE2-LABEL: combine_test17:
1658
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1659
; SSE2-NEXT: movaps %xmm1, %xmm0
1662
; SSSE3-LABEL: combine_test17:
1664
; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
1665
; SSSE3-NEXT: movaps %xmm1, %xmm0
1668
; SSE41-LABEL: combine_test17:
1670
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1673
; AVX1-LABEL: combine_test17:
1675
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1678
; AVX2-LABEL: combine_test17:
1680
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1682
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
1683
%2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
1687
define <4 x i32> @combine_test18(<4 x i32> %a, <4 x i32> %b) {
1688
; SSE-LABEL: combine_test18:
1690
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1693
; AVX-LABEL: combine_test18:
1695
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1697
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1698
%2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
1702
define <4 x i32> @combine_test19(<4 x i32> %a, <4 x i32> %b) {
1703
; SSE-LABEL: combine_test19:
1705
; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1708
; AVX-LABEL: combine_test19:
1710
; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1712
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 5, i32 5>
1713
%2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1717
define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
1718
; SSE2-LABEL: combine_test20:
1720
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1721
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1724
; SSSE3-LABEL: combine_test20:
1726
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
1727
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
1730
; SSE41-LABEL: combine_test20:
1732
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1735
; AVX1-LABEL: combine_test20:
1737
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
1740
; AVX2-LABEL: combine_test20:
1742
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
1744
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
1745
%2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
1749
define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) {
1750
; SSE-LABEL: combine_test21:
1752
; SSE-NEXT: movdqa %xmm0, %xmm2
1753
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
1754
; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1755
; SSE-NEXT: movdqa %xmm2, (%rdi)
1758
; AVX1-LABEL: combine_test21:
1760
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
1761
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1762
; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1763
; AVX1-NEXT: vmovdqa %xmm2, (%rdi)
1764
; AVX1-NEXT: vzeroupper
1767
; AVX2-LABEL: combine_test21:
1769
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1770
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm0[0],xmm1[0]
1771
; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1772
; AVX2-NEXT: vmovdqa %xmm2, (%rdi)
1773
; AVX2-NEXT: vzeroupper
1775
%1 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1776
%2 = shufflevector <8 x i32> %a, <8 x i32> %a, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
1777
store <4 x i32> %1, <4 x i32>* %ptr, align 16
1781
define <8 x float> @combine_test22(<2 x float>* %a, <2 x float>* %b) {
1782
; SSE-LABEL: combine_test22:
1784
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
1785
; SSE-NEXT: movhpd (%rsi), %xmm0
1788
; AVX-LABEL: combine_test22:
1790
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
1791
; AVX-NEXT: vmovhpd (%rsi), %xmm0, %xmm0
1793
; Current AVX2 lowering of this is still awful, not adding a test case.
1794
%1 = load <2 x float>, <2 x float>* %a, align 8
1795
%2 = load <2 x float>, <2 x float>* %b, align 8
1796
%3 = shufflevector <2 x float> %1, <2 x float> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
1800
; Check some negative cases.
1801
; FIXME: Do any of these really make sense? Are they redundant with the above tests?
1803
define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
1804
; SSE-LABEL: combine_test1b:
1806
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
1807
; SSE-NEXT: movaps %xmm1, %xmm0
1810
; AVX-LABEL: combine_test1b:
1812
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[0,1,2,0]
1814
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1815
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 0>
1819
define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
1820
; SSE2-LABEL: combine_test2b:
1822
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
1823
; SSE2-NEXT: movaps %xmm1, %xmm0
1826
; SSSE3-LABEL: combine_test2b:
1828
; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1831
; SSE41-LABEL: combine_test2b:
1833
; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
1836
; AVX-LABEL: combine_test2b:
1838
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm1[0,0]
1840
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1841
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
1845
define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
1846
; SSE2-LABEL: combine_test3b:
1848
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1849
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
1852
; SSSE3-LABEL: combine_test3b:
1854
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
1855
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
1858
; SSE41-LABEL: combine_test3b:
1860
; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
1861
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3,2,3]
1864
; AVX-LABEL: combine_test3b:
1866
; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
1867
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,3,2,3]
1869
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 6, i32 3>
1870
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 7>
1874
define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
1875
; SSE-LABEL: combine_test4b:
1877
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
1878
; SSE-NEXT: movaps %xmm1, %xmm0
1881
; AVX-LABEL: combine_test4b:
1883
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm1[1,1,2,3]
1885
%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
1886
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 5, i32 5, i32 2, i32 7>
1891
; Verify that we correctly fold shuffles even when we use illegal vector types.
1893
define <4 x i8> @combine_test1c(<4 x i8>* %a, <4 x i8>* %b) {
1894
; SSE2-LABEL: combine_test1c:
1896
; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1897
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1898
; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1899
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1900
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1901
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1902
; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1905
; SSSE3-LABEL: combine_test1c:
1907
; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1908
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1909
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1910
; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1911
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1912
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1913
; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
1916
; SSE41-LABEL: combine_test1c:
1918
; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1919
; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1920
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
1923
; AVX1-LABEL: combine_test1c:
1925
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1926
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1927
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
1930
; AVX2-LABEL: combine_test1c:
1932
; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1933
; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1934
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
1936
%A = load <4 x i8>, <4 x i8>* %a
1937
%B = load <4 x i8>, <4 x i8>* %b
1938
%1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
1939
%2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
1943
define <4 x i8> @combine_test2c(<4 x i8>* %a, <4 x i8>* %b) {
1944
; SSE2-LABEL: combine_test2c:
1946
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1947
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1948
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1949
; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1950
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1951
; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1952
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1955
; SSSE3-LABEL: combine_test2c:
1957
; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1958
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1959
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1960
; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1961
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1962
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1963
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1966
; SSE41-LABEL: combine_test2c:
1968
; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1969
; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1970
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1973
; AVX-LABEL: combine_test2c:
1975
; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1976
; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
1977
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1979
%A = load <4 x i8>, <4 x i8>* %a
1980
%B = load <4 x i8>, <4 x i8>* %b
1981
%1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 0, i32 5, i32 1, i32 5>
1982
%2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
1986
define <4 x i8> @combine_test3c(<4 x i8>* %a, <4 x i8>* %b) {
1987
; SSE2-LABEL: combine_test3c:
1989
; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
1990
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
1991
; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
1992
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
1993
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
1994
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
1995
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
1998
; SSSE3-LABEL: combine_test3c:
2000
; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
2001
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
2002
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
2003
; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
2004
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
2005
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
2006
; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
2009
; SSE41-LABEL: combine_test3c:
2011
; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2012
; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2013
; SSE41-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
2016
; AVX-LABEL: combine_test3c:
2018
; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2019
; AVX-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2020
; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2022
%A = load <4 x i8>, <4 x i8>* %a
2023
%B = load <4 x i8>, <4 x i8>* %b
2024
%1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2025
%2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2029
define <4 x i8> @combine_test4c(<4 x i8>* %a, <4 x i8>* %b) {
2030
; SSE2-LABEL: combine_test4c:
2032
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
2033
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
2034
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
2035
; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
2036
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
2037
; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
2038
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
2039
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
2042
; SSSE3-LABEL: combine_test4c:
2044
; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
2045
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
2046
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
2047
; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
2048
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
2049
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
2050
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,0]
2051
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
2054
; SSE41-LABEL: combine_test4c:
2056
; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2057
; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2058
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
2061
; AVX1-LABEL: combine_test4c:
2063
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2064
; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2065
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]
2068
; AVX2-LABEL: combine_test4c:
2070
; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2071
; AVX2-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
2072
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
2074
%A = load <4 x i8>, <4 x i8>* %a
2075
%B = load <4 x i8>, <4 x i8>* %b
2076
%1 = shufflevector <4 x i8> %A, <4 x i8> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
2077
%2 = shufflevector <4 x i8> %1, <4 x i8> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2082
; The following test cases are generated from this C++ code
2084
;__m128 blend_01(__m128 a, __m128 b)
2087
; s = _mm_blend_ps( s, b, 1<<0 );
2088
; s = _mm_blend_ps( s, b, 1<<1 );
2092
;__m128 blend_02(__m128 a, __m128 b)
2095
; s = _mm_blend_ps( s, b, 1<<0 );
2096
; s = _mm_blend_ps( s, b, 1<<2 );
2100
;__m128 blend_123(__m128 a, __m128 b)
2103
; s = _mm_blend_ps( s, b, 1<<1 );
2104
; s = _mm_blend_ps( s, b, 1<<2 );
2105
; s = _mm_blend_ps( s, b, 1<<3 );
2109
; Ideally, we should collapse the following shuffles into a single one.
2111
define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
2112
; SSE2-LABEL: combine_blend_01:
2114
; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2117
; SSSE3-LABEL: combine_blend_01:
2119
; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2122
; SSE41-LABEL: combine_blend_01:
2124
; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2127
; AVX-LABEL: combine_blend_01:
2129
; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2131
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 undef, i32 2, i32 3>
2132
%shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
2133
ret <4 x float> %shuffle6
2136
define <4 x float> @combine_blend_02(<4 x float> %a, <4 x float> %b) {
2137
; SSE2-LABEL: combine_blend_02:
2139
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
2140
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
2141
; SSE2-NEXT: movaps %xmm1, %xmm0
2144
; SSSE3-LABEL: combine_blend_02:
2146
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
2147
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3]
2148
; SSSE3-NEXT: movaps %xmm1, %xmm0
2151
; SSE41-LABEL: combine_blend_02:
2153
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2156
; AVX-LABEL: combine_blend_02:
2158
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
2160
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 undef, i32 3>
2161
%shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
2162
ret <4 x float> %shuffle6
2165
define <4 x float> @combine_blend_123(<4 x float> %a, <4 x float> %b) {
2166
; SSE2-LABEL: combine_blend_123:
2168
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2169
; SSE2-NEXT: movaps %xmm1, %xmm0
2172
; SSSE3-LABEL: combine_blend_123:
2174
; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
2175
; SSSE3-NEXT: movaps %xmm1, %xmm0
2178
; SSE41-LABEL: combine_blend_123:
2180
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2183
; AVX-LABEL: combine_blend_123:
2185
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
2187
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
2188
%shuffle6 = shufflevector <4 x float> %shuffle, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
2189
%shuffle12 = shufflevector <4 x float> %shuffle6, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
2190
ret <4 x float> %shuffle12
2193
define <4 x i32> @combine_test_movhl_1(<4 x i32> %a, <4 x i32> %b) {
2194
; SSE-LABEL: combine_test_movhl_1:
2196
; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2197
; SSE-NEXT: movdqa %xmm1, %xmm0
2200
; AVX-LABEL: combine_test_movhl_1:
2202
; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2204
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 5, i32 3>
2205
%2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 0, i32 3>
2209
define <4 x i32> @combine_test_movhl_2(<4 x i32> %a, <4 x i32> %b) {
2210
; SSE-LABEL: combine_test_movhl_2:
2212
; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2213
; SSE-NEXT: movdqa %xmm1, %xmm0
2216
; AVX-LABEL: combine_test_movhl_2:
2218
; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2220
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 0, i32 3, i32 6>
2221
%2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 3, i32 7, i32 0, i32 2>
2225
define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
2226
; SSE-LABEL: combine_test_movhl_3:
2228
; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2229
; SSE-NEXT: movdqa %xmm1, %xmm0
2232
; AVX-LABEL: combine_test_movhl_3:
2234
; AVX-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2236
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 6, i32 3, i32 2>
2237
%2 = shufflevector <4 x i32> %1, <4 x i32> %b, <4 x i32> <i32 6, i32 0, i32 3, i32 2>
2242
; Verify that we fold shuffles according to rule:
2243
; (shuffle(shuffle A, Undef, M0), B, M1) -> (shuffle A, B, M2)
2245
define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
2246
; SSE2-LABEL: combine_undef_input_test1:
2248
; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2251
; SSSE3-LABEL: combine_undef_input_test1:
2253
; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2256
; SSE41-LABEL: combine_undef_input_test1:
2258
; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2261
; AVX-LABEL: combine_undef_input_test1:
2263
; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2265
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2266
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2270
define <4 x float> @combine_undef_input_test2(<4 x float> %a, <4 x float> %b) {
2271
; SSE-LABEL: combine_undef_input_test2:
2273
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2276
; AVX-LABEL: combine_undef_input_test2:
2278
; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2280
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2281
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2285
define <4 x float> @combine_undef_input_test3(<4 x float> %a, <4 x float> %b) {
2286
; SSE-LABEL: combine_undef_input_test3:
2288
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2291
; AVX-LABEL: combine_undef_input_test3:
2293
; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2295
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2296
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2300
define <4 x float> @combine_undef_input_test4(<4 x float> %a, <4 x float> %b) {
2301
; SSE-LABEL: combine_undef_input_test4:
2303
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2304
; SSE-NEXT: movapd %xmm1, %xmm0
2307
; AVX-LABEL: combine_undef_input_test4:
2309
; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2311
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2312
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2316
define <4 x float> @combine_undef_input_test5(<4 x float> %a, <4 x float> %b) {
2317
; SSE2-LABEL: combine_undef_input_test5:
2319
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2320
; SSE2-NEXT: movapd %xmm1, %xmm0
2323
; SSSE3-LABEL: combine_undef_input_test5:
2325
; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2326
; SSSE3-NEXT: movapd %xmm1, %xmm0
2329
; SSE41-LABEL: combine_undef_input_test5:
2331
; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2334
; AVX-LABEL: combine_undef_input_test5:
2336
; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2338
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2339
%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2344
; Verify that we fold shuffles according to rule:
2345
; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2347
define <4 x float> @combine_undef_input_test6(<4 x float> %a) {
2348
; ALL-LABEL: combine_undef_input_test6:
2351
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2352
%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 2>
2356
define <4 x float> @combine_undef_input_test7(<4 x float> %a) {
2357
; SSE2-LABEL: combine_undef_input_test7:
2359
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2362
; SSSE3-LABEL: combine_undef_input_test7:
2364
; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2367
; SSE41-LABEL: combine_undef_input_test7:
2369
; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2372
; AVX-LABEL: combine_undef_input_test7:
2374
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2376
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2377
%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
2381
define <4 x float> @combine_undef_input_test8(<4 x float> %a) {
2382
; SSE2-LABEL: combine_undef_input_test8:
2384
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2387
; SSSE3-LABEL: combine_undef_input_test8:
2389
; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2392
; SSE41-LABEL: combine_undef_input_test8:
2394
; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2397
; AVX-LABEL: combine_undef_input_test8:
2399
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2401
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2402
%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 1>
2406
define <4 x float> @combine_undef_input_test9(<4 x float> %a) {
2407
; SSE-LABEL: combine_undef_input_test9:
2409
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2412
; AVX-LABEL: combine_undef_input_test9:
2414
; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2416
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2417
%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
2421
define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
2422
; ALL-LABEL: combine_undef_input_test10:
2425
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2426
%2 = shufflevector <4 x float> %1, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 6, i32 7>
2430
define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
2431
; SSE2-LABEL: combine_undef_input_test11:
2433
; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2436
; SSSE3-LABEL: combine_undef_input_test11:
2438
; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2441
; SSE41-LABEL: combine_undef_input_test11:
2443
; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2446
; AVX-LABEL: combine_undef_input_test11:
2448
; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
2450
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2451
%2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 6>
2455
define <4 x float> @combine_undef_input_test12(<4 x float> %a, <4 x float> %b) {
2456
; SSE-LABEL: combine_undef_input_test12:
2458
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2461
; AVX-LABEL: combine_undef_input_test12:
2463
; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2465
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2466
%2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2470
define <4 x float> @combine_undef_input_test13(<4 x float> %a, <4 x float> %b) {
2471
; SSE-LABEL: combine_undef_input_test13:
2473
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2476
; AVX-LABEL: combine_undef_input_test13:
2478
; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2480
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2481
%2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 5, i32 0, i32 5>
2485
define <4 x float> @combine_undef_input_test14(<4 x float> %a, <4 x float> %b) {
2486
; SSE-LABEL: combine_undef_input_test14:
2488
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
2489
; SSE-NEXT: movapd %xmm1, %xmm0
2492
; AVX-LABEL: combine_undef_input_test14:
2494
; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm1[1],xmm0[1]
2496
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2497
%2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2501
define <4 x float> @combine_undef_input_test15(<4 x float> %a, <4 x float> %b) {
2502
; SSE2-LABEL: combine_undef_input_test15:
2504
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2505
; SSE2-NEXT: movapd %xmm1, %xmm0
2508
; SSSE3-LABEL: combine_undef_input_test15:
2510
; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
2511
; SSSE3-NEXT: movapd %xmm1, %xmm0
2514
; SSE41-LABEL: combine_undef_input_test15:
2516
; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2519
; AVX-LABEL: combine_undef_input_test15:
2521
; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
2523
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2524
%2 = shufflevector <4 x float> %b, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2529
; Verify that shuffles are canonicalized according to rules:
2530
; shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
2532
; This allows to trigger the following combine rule:
2533
; (shuffle(shuffle A, Undef, M0), A, M1) -> (shuffle A, Undef, M2)
2535
; As a result, all the shuffle pairs in each function below should be
2536
; combined into a single legal shuffle operation.
2538
define <4 x float> @combine_undef_input_test16(<4 x float> %a) {
2539
; ALL-LABEL: combine_undef_input_test16:
2542
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 4, i32 2, i32 3, i32 1>
2543
%2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
2547
define <4 x float> @combine_undef_input_test17(<4 x float> %a) {
2548
; SSE2-LABEL: combine_undef_input_test17:
2550
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2553
; SSSE3-LABEL: combine_undef_input_test17:
2555
; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2558
; SSE41-LABEL: combine_undef_input_test17:
2560
; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2563
; AVX-LABEL: combine_undef_input_test17:
2565
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2567
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 6, i32 0, i32 1, i32 7>
2568
%2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 5, i32 6, i32 0, i32 1>
2572
define <4 x float> @combine_undef_input_test18(<4 x float> %a) {
2573
; SSE2-LABEL: combine_undef_input_test18:
2575
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
2578
; SSSE3-LABEL: combine_undef_input_test18:
2580
; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2583
; SSE41-LABEL: combine_undef_input_test18:
2585
; SSE41-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
2588
; AVX-LABEL: combine_undef_input_test18:
2590
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
2592
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 5, i32 1, i32 7>
2593
%2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 0, i32 5>
2597
define <4 x float> @combine_undef_input_test19(<4 x float> %a) {
2598
; SSE-LABEL: combine_undef_input_test19:
2600
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
2603
; AVX-LABEL: combine_undef_input_test19:
2605
; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
2607
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 5, i32 5>
2608
%2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
2612
define <4 x float> @combine_undef_input_test20(<4 x float> %a) {
2613
; ALL-LABEL: combine_undef_input_test20:
2616
%1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 3>
2617
%2 = shufflevector <4 x float> %a, <4 x float> %1, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2621
; These tests are designed to test the ability to combine away unnecessary
2622
; operations feeding into a shuffle. The AVX cases are the important ones as
2623
; they leverage operations which cannot be done naturally on the entire vector
2624
; and thus are decomposed into multiple smaller operations.
2626
define <8 x i32> @combine_unneeded_subvector1(<8 x i32> %a) {
2627
; SSE-LABEL: combine_unneeded_subvector1:
2629
; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2630
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,2,1,0]
2631
; SSE-NEXT: movdqa %xmm0, %xmm1
2634
; AVX1-LABEL: combine_unneeded_subvector1:
2636
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2637
; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2638
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,2,1,0]
2639
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2642
; AVX2-LABEL: combine_unneeded_subvector1:
2644
; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2645
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [7,6,5,4,7,6,5,4]
2646
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
2648
%b = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2649
%c = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 7, i32 6, i32 5, i32 4>
2653
define <8 x i32> @combine_unneeded_subvector2(<8 x i32> %a, <8 x i32> %b) {
2654
; SSE-LABEL: combine_unneeded_subvector2:
2656
; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
2657
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,2,1,0]
2658
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,2,1,0]
2661
; AVX1-LABEL: combine_unneeded_subvector2:
2663
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2664
; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
2665
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
2666
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2667
; AVX1-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2670
; AVX2-LABEL: combine_unneeded_subvector2:
2672
; AVX2-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
2673
; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[2,3],ymm0[2,3]
2674
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,2,1,0,7,6,5,4]
2676
%c = add <8 x i32> %a, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
2677
%d = shufflevector <8 x i32> %b, <8 x i32> %c, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 15, i32 14, i32 13, i32 12>
2681
define <4 x float> @combine_insertps1(<4 x float> %a, <4 x float> %b) {
2682
; SSE2-LABEL: combine_insertps1:
2684
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
2685
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2686
; SSE2-NEXT: movaps %xmm1, %xmm0
2689
; SSSE3-LABEL: combine_insertps1:
2691
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,0]
2692
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3]
2693
; SSSE3-NEXT: movaps %xmm1, %xmm0
2696
; SSE41-LABEL: combine_insertps1:
2698
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2701
; AVX-LABEL: combine_insertps1:
2703
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[2],xmm0[1,2,3]
2706
%c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 6, i32 2, i32 4>
2707
%d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
2711
define <4 x float> @combine_insertps2(<4 x float> %a, <4 x float> %b) {
2712
; SSE2-LABEL: combine_insertps2:
2714
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
2715
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2716
; SSE2-NEXT: movaps %xmm1, %xmm0
2719
; SSSE3-LABEL: combine_insertps2:
2721
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[0,0]
2722
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
2723
; SSSE3-NEXT: movaps %xmm1, %xmm0
2726
; SSE41-LABEL: combine_insertps2:
2728
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2731
; AVX-LABEL: combine_insertps2:
2733
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[2],xmm0[2,3]
2736
%c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 1, i32 6, i32 7>
2737
%d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32> <i32 4, i32 6, i32 2, i32 3>
2741
define <4 x float> @combine_insertps3(<4 x float> %a, <4 x float> %b) {
2742
; SSE2-LABEL: combine_insertps3:
2744
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
2745
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2748
; SSSE3-LABEL: combine_insertps3:
2750
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
2751
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
2754
; SSE41-LABEL: combine_insertps3:
2756
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2759
; AVX-LABEL: combine_insertps3:
2761
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
2764
%c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2765
%d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3>
2769
define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
2770
; SSE2-LABEL: combine_insertps4:
2772
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
2773
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2776
; SSSE3-LABEL: combine_insertps4:
2778
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
2779
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
2782
; SSE41-LABEL: combine_insertps4:
2784
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2787
; AVX-LABEL: combine_insertps4:
2789
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
2792
%c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
2793
%d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 6, i32 5>
2797
define <4 x float> @PR22377(<4 x float> %a, <4 x float> %b) {
2798
; SSE-LABEL: PR22377:
2799
; SSE: # BB#0: # %entry
2800
; SSE-NEXT: movaps %xmm0, %xmm1
2801
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3,1,3]
2802
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,0,2]
2803
; SSE-NEXT: addps %xmm0, %xmm1
2804
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
2807
; AVX-LABEL: PR22377:
2808
; AVX: # BB#0: # %entry
2809
; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[1,3,1,3]
2810
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2]
2811
; AVX-NEXT: vaddps %xmm0, %xmm1, %xmm1
2812
; AVX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
2815
%s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 1, i32 3>
2816
%s2 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
2817
%r2 = fadd <4 x float> %s1, %s2
2818
%s3 = shufflevector <4 x float> %s2, <4 x float> %r2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
2822
define <4 x float> @PR22390(<4 x float> %a, <4 x float> %b) {
2823
; SSE2-LABEL: PR22390:
2824
; SSE2: # BB#0: # %entry
2825
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2826
; SSE2-NEXT: movaps %xmm0, %xmm2
2827
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
2828
; SSE2-NEXT: addps %xmm0, %xmm2
2829
; SSE2-NEXT: movaps %xmm2, %xmm0
2832
; SSSE3-LABEL: PR22390:
2833
; SSSE3: # BB#0: # %entry
2834
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2835
; SSSE3-NEXT: movaps %xmm0, %xmm2
2836
; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
2837
; SSSE3-NEXT: addps %xmm0, %xmm2
2838
; SSSE3-NEXT: movaps %xmm2, %xmm0
2841
; SSE41-LABEL: PR22390:
2842
; SSE41: # BB#0: # %entry
2843
; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2844
; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
2845
; SSE41-NEXT: addps %xmm1, %xmm0
2848
; AVX-LABEL: PR22390:
2849
; AVX: # BB#0: # %entry
2850
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,0,1,2]
2851
; AVX-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
2852
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
2855
%s1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
2856
%s2 = shufflevector <4 x float> %s1, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
2857
%r2 = fadd <4 x float> %s1, %s2
2861
define <8 x float> @PR22412(<8 x float> %a, <8 x float> %b) {
2862
; SSE2-LABEL: PR22412:
2863
; SSE2: # BB#0: # %entry
2864
; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
2865
; SSE2-NEXT: movapd %xmm2, %xmm0
2866
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm3[3,2]
2867
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[3,2]
2868
; SSE2-NEXT: movaps %xmm3, %xmm1
2871
; SSSE3-LABEL: PR22412:
2872
; SSSE3: # BB#0: # %entry
2873
; SSSE3-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
2874
; SSSE3-NEXT: movapd %xmm2, %xmm0
2875
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm3[3,2]
2876
; SSSE3-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[3,2]
2877
; SSSE3-NEXT: movaps %xmm3, %xmm1
2880
; SSE41-LABEL: PR22412:
2881
; SSE41: # BB#0: # %entry
2882
; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm2[1]
2883
; SSE41-NEXT: movapd %xmm0, %xmm1
2884
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm3[3,2]
2885
; SSE41-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm0[3,2]
2886
; SSE41-NEXT: movaps %xmm1, %xmm0
2887
; SSE41-NEXT: movaps %xmm3, %xmm1
2890
; AVX1-LABEL: PR22412:
2891
; AVX1: # BB#0: # %entry
2892
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
2893
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[2,3,0,1]
2894
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,0],ymm1[3,2],ymm0[5,4],ymm1[7,6]
2897
; AVX2-LABEL: PR22412:
2898
; AVX2: # BB#0: # %entry
2899
; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]
2900
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [1,0,7,6,5,4,3,2]
2901
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
2904
%s1 = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
2905
%s2 = shufflevector <8 x float> %s1, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2>