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//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
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// The LLVM Compiler Infrastructure
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//===----------------------------------------------------------------------===//
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// This file defines the target-independent interfaces which should be
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// implemented by each target which is using a TableGen based code generator.
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//===----------------------------------------------------------------------===//
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// Include all information about LLVM intrinsics.
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include "llvm/IR/Intrinsics.td"
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//===----------------------------------------------------------------------===//
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// Register file description - These classes are used to fill in the target
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// description classes.
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class RegisterClass; // Forward def
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// SubRegIndex - Use instances of SubRegIndex to identify subregisters.
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class SubRegIndex<int size, int offset = 0> {
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string Namespace = "";
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// Size - Size (in bits) of the sub-registers represented by this index.
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// Offset - Offset of the first bit that is part of this sub-register index.
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// Set it to -1 if the same index is used to represent sub-registers that can
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// be at different offsets (for example when using an index to access an
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// element in a register tuple).
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// ComposedOf - A list of two SubRegIndex instances, [A, B].
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// This indicates that this SubRegIndex is the result of composing A and B.
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// See ComposedSubRegIndex.
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list<SubRegIndex> ComposedOf = [];
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// CoveringSubRegIndices - A list of two or more sub-register indexes that
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// cover this sub-register.
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// This field should normally be left blank as TableGen can infer it.
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// TableGen automatically detects sub-registers that straddle the registers
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// in the SubRegs field of a Register definition. For example:
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// Q0 = dsub_0 -> D0, dsub_1 -> D1
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// Q1 = dsub_0 -> D2, dsub_1 -> D3
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// D1_D2 = dsub_0 -> D1, dsub_1 -> D2
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// QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
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// TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
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// the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
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// CoveringSubRegIndices = [dsub_1, dsub_2].
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list<SubRegIndex> CoveringSubRegIndices = [];
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// ComposedSubRegIndex - A sub-register that is the result of composing A and B.
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// Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
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class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
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: SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
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!if(!eq(B.Offset, -1), -1,
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!add(A.Offset, B.Offset)))> {
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let ComposedOf = [A, B];
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// RegAltNameIndex - The alternate name set to use for register operands of
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// this register class when printing.
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class RegAltNameIndex {
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string Namespace = "";
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def NoRegAltName : RegAltNameIndex;
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// Register - You should define one instance of this class for each register
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// in the target machine. String n will become the "name" of the register.
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class Register<string n, list<string> altNames = []> {
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string Namespace = "";
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list<string> AltNames = altNames;
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// Aliases - A list of registers that this register overlaps with. A read or
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// modification of this register can potentially read or modify the aliased
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list<Register> Aliases = [];
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// SubRegs - A list of registers that are parts of this register. Note these
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// are "immediate" sub-registers and the registers within the list do not
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// themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
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list<Register> SubRegs = [];
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// SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
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// to address it. Sub-sub-register indices are automatically inherited from
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list<SubRegIndex> SubRegIndices = [];
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// RegAltNameIndices - The alternate name indices which are valid for this
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list<RegAltNameIndex> RegAltNameIndices = [];
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// DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
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// These values can be determined by locating the <target>.h file in the
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// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
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// order of these names correspond to the enumeration used by gcc. A value of
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// -1 indicates that the gcc number is undefined and -2 that register number
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// is invalid for this mode/flavour.
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list<int> DwarfNumbers = [];
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// CostPerUse - Additional cost of instructions using this register compared
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// to other registers in its class. The register allocator will try to
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// minimize the number of instructions using a register with a CostPerUse.
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// This is used by the x86-64 and ARM Thumb targets where some registers
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// require larger instruction encodings.
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// CoveredBySubRegs - When this bit is set, the value of this register is
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// completely determined by the value of its sub-registers. For example, the
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// x86 register AX is covered by its sub-registers AL and AH, but EAX is not
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// covered by its sub-register AX.
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bit CoveredBySubRegs = 0;
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// HWEncoding - The target specific hardware encoding for this register.
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bits<16> HWEncoding = 0;
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// RegisterWithSubRegs - This can be used to define instances of Register which
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// need to specify sub-registers.
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// List "subregs" specifies which registers are sub-registers to this one. This
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// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
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// This allows the code generator to be careful not to put two values with
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// overlapping live ranges into registers which alias.
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class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
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let SubRegs = subregs;
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// DAGOperand - An empty base class that unifies RegisterClass's and other forms
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// of Operand's that are legal as type qualifiers in DAG patterns. This should
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// only ever be used for defining multiclasses that are polymorphic over both
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// RegisterClass's and other Operand's.
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// RegisterClass - Now that all of the registers are defined, and aliases
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// between registers are defined, specify which registers belong to which
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// register classes. This also defines the default allocation order of
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// registers by register allocators.
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class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
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dag regList, RegAltNameIndex idx = NoRegAltName>
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string Namespace = namespace;
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// RegType - Specify the list ValueType of the registers in this register
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// class. Note that all registers in a register class must have the same
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// ValueTypes. This is a list because some targets permit storing different
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// types in same register, for example vector values with 128-bit total size,
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// but different count/size of items, like SSE on x86.
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list<ValueType> RegTypes = regTypes;
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// Size - Specify the spill size in bits of the registers. A default value of
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// zero lets tablgen pick an appropriate size.
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// Alignment - Specify the alignment required of the registers when they are
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// stored or loaded to memory.
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int Alignment = alignment;
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// CopyCost - This value is used to specify the cost of copying a value
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// between two registers in this register class. The default value is one
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// meaning it takes a single instruction to perform the copying. A negative
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// value means copying is extremely expensive or impossible.
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// MemberList - Specify which registers are in this class. If the
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// allocation_order_* method are not specified, this also defines the order of
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// allocation used by the register allocator.
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dag MemberList = regList;
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// AltNameIndex - The alternate register name to use when printing operands
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// of this register class. Every register in the register class must have
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// a valid alternate name for the given index.
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RegAltNameIndex altNameIndex = idx;
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// isAllocatable - Specify that the register class can be used for virtual
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// registers and register allocation. Some register classes are only used to
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// model instruction operand constraints, and should have isAllocatable = 0.
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bit isAllocatable = 1;
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// AltOrders - List of alternative allocation orders. The default order is
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// MemberList itself, and that is good enough for most targets since the
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// register allocators automatically remove reserved registers and move
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// callee-saved registers to the end.
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list<dag> AltOrders = [];
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// AltOrderSelect - The body of a function that selects the allocation order
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// to use in a given machine function. The code will be inserted in a
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// function like this:
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// static inline unsigned f(const MachineFunction &MF) { ... }
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// The function should return 0 to select the default order defined by
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// MemberList, 1 to select the first AltOrders entry and so on.
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code AltOrderSelect = [{}];
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// Specify allocation priority for register allocators using a greedy
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// heuristic. Classes with higher priority values are assigned first. This is
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// useful as it is sometimes beneficial to assign registers to highly
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// constrained classes first. The value has to be in the range [0,63].
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int AllocationPriority = 0;
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// The memberList in a RegisterClass is a dag of set operations. TableGen
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// evaluates these set operations and expand them into register lists. These
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// are the most common operation, see test/TableGen/SetTheory.td for more
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// examples of what is possible:
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// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
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// register class, or a sub-expression. This is also the way to simply list
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// (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
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// (and GPR, CSR) - Set intersection. All registers from the first set that are
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// also in the second set.
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// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
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// numbered registers. Takes an optional 4th operand which is a stride to use
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// when generating the sequence.
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// (shl GPR, 4) - Remove the first N elements.
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// (trunc GPR, 4) - Truncate after the first N elements.
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// (rotl GPR, 1) - Rotate N places to the left.
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// (rotr GPR, 1) - Rotate N places to the right.
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// (decimate GPR, 2) - Pick every N'th element, starting with the first.
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// (interleave A, B, ...) - Interleave the elements from each argument list.
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// All of these operators work on ordered sets, not lists. That means
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// duplicates are removed from sub-expressions.
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// Set operators. The rest is defined in TargetSelectionDAG.td.
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// RegisterTuples - Automatically generate super-registers by forming tuples of
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// sub-registers. This is useful for modeling register sequence constraints
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// with pseudo-registers that are larger than the architectural registers.
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// The sub-register lists are zipped together:
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// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
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// Generates the same registers as:
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// let SubRegIndices = [sube, subo] in {
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// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
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// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
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// The generated pseudo-registers inherit super-classes and fields from their
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// first sub-register. Most fields from the Register class are inferred, and
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// the AsmName and Dwarf numbers are cleared.
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// RegisterTuples instances can be used in other set operations to form
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// register classes and so on. This is the only way of using the generated
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class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
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// SubRegs - N lists of registers to be zipped up. Super-registers are
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// synthesized from the first element of each SubRegs list, the second
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// element and so on.
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list<dag> SubRegs = Regs;
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// SubRegIndices - N SubRegIndex instances. This provides the names of the
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// sub-registers in the synthesized super-registers.
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list<SubRegIndex> SubRegIndices = Indices;
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//===----------------------------------------------------------------------===//
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// DwarfRegNum - This class provides a mapping of the llvm register enumeration
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// to the register numbering used by gcc and gdb. These values are used by a
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// debug information writer to describe where values may be located during
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class DwarfRegNum<list<int> Numbers> {
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// DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
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// These values can be determined by locating the <target>.h file in the
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// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
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// order of these names correspond to the enumeration used by gcc. A value of
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// -1 indicates that the gcc number is undefined and -2 that register number
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// is invalid for this mode/flavour.
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list<int> DwarfNumbers = Numbers;
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// DwarfRegAlias - This class declares that a given register uses the same dwarf
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// numbers as another one. This is useful for making it clear that the two
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// registers do have the same number. It also lets us build a mapping
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// from dwarf register number to llvm register.
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class DwarfRegAlias<Register reg> {
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Register DwarfAlias = reg;
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//===----------------------------------------------------------------------===//
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// Pull in the common support for scheduling
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include "llvm/Target/TargetSchedule.td"
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class Predicate; // Forward def
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//===----------------------------------------------------------------------===//
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// Instruction set description - These classes correspond to the C++ classes in
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// the Target/TargetInstrInfo.h file.
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string Namespace = "";
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dag OutOperandList; // An dag containing the MI def operand list.
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dag InOperandList; // An dag containing the MI use operand list.
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string AsmString = ""; // The .s format to print the instruction with.
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// Pattern - Set to the DAG pattern for this instruction, if we know of one,
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// otherwise, uninitialized.
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// The follow state will eventually be inferred automatically from the
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// instruction pattern.
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list<Register> Uses = []; // Default to using no non-operand registers
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list<Register> Defs = []; // Default to modifying no non-operand registers
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// Predicates - List of predicates which will be turned into isel matching
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list<Predicate> Predicates = [];
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// Size - Size of encoded instruction, or zero if the size cannot be determined
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// DecoderNamespace - The "namespace" in which this instruction exists, on
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// targets like ARM which multiple ISA namespaces exist.
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string DecoderNamespace = "";
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// Code size, for instruction selection.
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// FIXME: What does this actually mean?
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// Added complexity passed onto matching pattern.
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int AddedComplexity = 0;
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// These bits capture information about the high-level semantics of the
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bit isReturn = 0; // Is this instruction a return instruction?
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bit isBranch = 0; // Is this instruction a branch instruction?
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bit isIndirectBranch = 0; // Is this instruction an indirect branch?
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bit isCompare = 0; // Is this instruction a comparison instruction?
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bit isMoveImm = 0; // Is this instruction a move immediate instruction?
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bit isBitcast = 0; // Is this instruction a bitcast instruction?
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bit isSelect = 0; // Is this instruction a select instruction?
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bit isBarrier = 0; // Can control flow fall through this instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
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bit mayLoad = ?; // Is it possible for this inst to read memory?
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bit mayStore = ?; // Is it possible for this inst to write memory?
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bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
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bit isCommutable = 0; // Is this 3 operand instruction commutable?
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bit isTerminator = 0; // Is this part of the terminator for a basic block?
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bit isReMaterializable = 0; // Is this instruction re-materializable?
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bit isPredicable = 0; // Is this instruction predicable?
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bit hasDelaySlot = 0; // Does this instruction have an delay slot?
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bit usesCustomInserter = 0; // Pseudo instr needing special help.
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bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
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bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
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bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
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bit isConvergent = 0; // Is this instruction convergent?
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bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
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bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
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bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
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bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
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// If so, make sure to override
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// TargetInstrInfo::getRegSequenceLikeInputs.
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bit isPseudo = 0; // Is this instruction a pseudo-instruction?
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// If so, won't have encoding information for
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// the [MC]CodeEmitter stuff.
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bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
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// If so, make sure to override
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// TargetInstrInfo::getExtractSubregLikeInputs.
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bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
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// If so, make sure to override
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// TargetInstrInfo::getInsertSubregLikeInputs.
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// Side effect flags - When set, the flags have these meanings:
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// hasSideEffects - The instruction has side effects that are not
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// captured by any operands of the instruction or other flags.
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bit hasSideEffects = ?;
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// Is this instruction a "real" instruction (with a distinct machine
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// encoding), or is it a pseudo instruction used for codegen modeling
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// FIXME: For now this is distinct from isPseudo, above, as code-gen-only
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// instructions can (and often do) still have encoding information
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// associated with them. Once we've migrated all of them over to true
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// pseudo-instructions that are lowered to real instructions prior to
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// the printer/emitter, we can remove this attribute and just use isPseudo.
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// The intended use is:
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// isPseudo: Does not have encoding information and should be expanded,
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// at the latest, during lowering to MCInst.
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// isCodeGenOnly: Does have encoding information and can go through to the
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// CodeEmitter unchanged, but duplicates a canonical instruction
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// definition's encoding and should be ignored when constructing the
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// assembler match tables.
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bit isCodeGenOnly = 0;
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// Is this instruction a pseudo instruction for use by the assembler parser.
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bit isAsmParserOnly = 0;
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InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
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// Scheduling information from TargetSchedule.td.
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list<SchedReadWrite> SchedRW;
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string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
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/// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
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/// be encoded into the output machineinstr.
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string DisableEncoding = "";
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string PostEncoderMethod = "";
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string DecoderMethod = "";
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/// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
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bits<64> TSFlags = 0;
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///@name Assembler Parser Support
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string AsmMatchConverter = "";
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/// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
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/// two-operand matcher inst-alias for a three operand instruction.
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/// For example, the arm instruction "add r3, r3, r5" can be written
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/// as "add r3, r5". The constraint is of the same form as a tied-operand
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/// constraint. For example, "$Rn = $Rd".
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string TwoOperandAliasConstraint = "";
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/// UseNamedOperandTable - If set, the operand indices of this instruction
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/// can be queried via the getNamedOperandIdx() function which is generated
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bit UseNamedOperandTable = 0;
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/// PseudoInstExpansion - Expansion information for a pseudo-instruction.
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/// Which instruction it expands to and how the operands map from the
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class PseudoInstExpansion<dag Result> {
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dag ResultInst = Result; // The instruction to generate.
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/// Predicates - These are extra conditionals which are turned into instruction
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/// selector matching code. Currently each predicate is just a string.
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class Predicate<string cond> {
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string CondString = cond;
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/// AssemblerMatcherPredicate - If this feature can be used by the assembler
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/// matcher, this is true. Targets should set this by inheriting their
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/// feature from the AssemblerPredicate class in addition to Predicate.
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bit AssemblerMatcherPredicate = 0;
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/// AssemblerCondString - Name of the subtarget feature being tested used
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/// as alternative condition string used for assembler matcher.
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/// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
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/// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
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/// It can also list multiple features separated by ",".
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/// e.g. "ModeThumb,FeatureThumb2" is translated to
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/// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
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string AssemblerCondString = "";
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/// PredicateName - User-level name to use for the predicate. Mainly for use
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/// in diagnostics such as missing feature errors in the asm matcher.
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string PredicateName = "";
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/// NoHonorSignDependentRounding - This predicate is true if support for
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/// sign-dependent-rounding is not enabled.
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def NoHonorSignDependentRounding
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: Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
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class Requires<list<Predicate> preds> {
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list<Predicate> Predicates = preds;
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/// ops definition - This is just a simple marker used to identify the operand
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/// list for an instruction. outs and ins are identical both syntactically and
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/// semantically; they are used to define def operands and use operands to
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/// improve readibility. This should be used like this:
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/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
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/// variable_ops definition - Mark this instruction as taking a variable number
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/// PointerLikeRegClass - Values that are designed to have pointer width are
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/// derived from this. TableGen treats the register class as having a symbolic
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/// type that it doesn't know, and resolves the actual regclass to use by using
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/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
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class PointerLikeRegClass<int Kind> {
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int RegClassKind = Kind;
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/// ptr_rc definition - Mark this operand as being a pointer value whose
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/// register class is resolved dynamically via a callback to TargetInstrInfo.
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/// FIXME: We should probably change this to a class which contain a list of
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/// flags. But currently we have but one flag.
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def ptr_rc : PointerLikeRegClass<0>;
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/// unknown definition - Mark this operand as being of unknown type, causing
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/// it to be resolved by inference in the context it is used.
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def unknown : unknown_class;
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/// AsmOperandClass - Representation for the kinds of operands which the target
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/// specific parser can create and the assembly matcher may need to distinguish.
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/// Operand classes are used to define the order in which instructions are
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/// matched, to ensure that the instruction which gets matched for any
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/// particular list of operands is deterministic.
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/// The target specific parser must be able to classify a parsed operand into a
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/// unique class which does not partially overlap with any other classes. It can
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/// match a subset of some other class, in which case the super class field
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/// should be defined.
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class AsmOperandClass {
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/// The name to use for this class, which should be usable as an enum value.
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/// The super classes of this operand.
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list<AsmOperandClass> SuperClasses = [];
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/// The name of the method on the target specific operand to call to test
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/// whether the operand is an instance of this class. If not set, this will
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/// default to "isFoo", where Foo is the AsmOperandClass name. The method
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/// signature should be:
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/// bool isFoo() const;
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string PredicateMethod = ?;
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/// The name of the method on the target specific operand to call to add the
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/// target specific operand to an MCInst. If not set, this will default to
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/// "addFooOperands", where Foo is the AsmOperandClass name. The method
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/// signature should be:
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/// void addFooOperands(MCInst &Inst, unsigned N) const;
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string RenderMethod = ?;
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/// The name of the method on the target specific operand to call to custom
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/// handle the operand parsing. This is useful when the operands do not relate
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/// to immediates or registers and are very instruction specific (as flags to
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/// set in a processor register, coprocessor number, ...).
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string ParserMethod = ?;
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// The diagnostic type to present when referencing this operand in a
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// match failure error message. By default, use a generic "invalid operand"
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// diagnostic. The target AsmParser maps these codes to text.
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string DiagnosticType = "";
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def ImmAsmOperand : AsmOperandClass {
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/// Operand Types - These provide the built-in operand types that may be used
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/// by a target. Targets can optionally provide their own operand types as
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/// needed, though this should not be needed for RISC targets.
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class Operand<ValueType ty> : DAGOperand {
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string PrintMethod = "printOperand";
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string EncoderMethod = "";
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string DecoderMethod = "";
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string OperandType = "OPERAND_UNKNOWN";
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dag MIOperandInfo = (ops);
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// MCOperandPredicate - Optionally, a code fragment operating on
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// const MCOperand &MCOp, and returning a bool, to indicate if
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// the value of MCOp is valid for the specific subclass of Operand
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code MCOperandPredicate;
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// ParserMatchClass - The "match class" that operands of this type fit
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// in. Match classes are used to define the order in which instructions are
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// match, to ensure that which instructions gets matched is deterministic.
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// The target specific parser must be able to classify an parsed operand into
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// a unique class, which does not partially overlap with any other classes. It
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// can match a subset of some other class, in which case the AsmOperandClass
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// should declare the other operand as one of its super classes.
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AsmOperandClass ParserMatchClass = ImmAsmOperand;
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class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
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// RegClass - The register class of the operand.
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RegisterClass RegClass = regclass;
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// PrintMethod - The target method to call to print register operands of
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// this type. The method normally will just use an alt-name index to look
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// up the name to print. Default to the generic printOperand().
624
string PrintMethod = pm;
625
// ParserMatchClass - The "match class" that operands of this type fit
626
// in. Match classes are used to define the order in which instructions are
627
// match, to ensure that which instructions gets matched is deterministic.
629
// The target specific parser must be able to classify an parsed operand into
630
// a unique class, which does not partially overlap with any other classes. It
631
// can match a subset of some other class, in which case the AsmOperandClass
632
// should declare the other operand as one of its super classes.
633
AsmOperandClass ParserMatchClass;
635
string OperandNamespace = "MCOI";
636
string OperandType = "OPERAND_REGISTER";
639
let OperandType = "OPERAND_IMMEDIATE" in {
640
def i1imm : Operand<i1>;
641
def i8imm : Operand<i8>;
642
def i16imm : Operand<i16>;
643
def i32imm : Operand<i32>;
644
def i64imm : Operand<i64>;
646
def f32imm : Operand<f32>;
647
def f64imm : Operand<f64>;
650
/// zero_reg definition - Special node to stand for the zero register.
654
/// All operands which the MC layer classifies as predicates should inherit from
655
/// this class in some manner. This is already handled for the most commonly
656
/// used PredicateOperand, but may be useful in other circumstances.
659
/// OperandWithDefaultOps - This Operand class can be used as the parent class
660
/// for an Operand that needs to be initialized with a default value if
661
/// no value is supplied in a pattern. This class can be used to simplify the
662
/// pattern definitions for instructions that have target specific flags
663
/// encoded as immediate operands.
664
class OperandWithDefaultOps<ValueType ty, dag defaultops>
666
dag DefaultOps = defaultops;
669
/// PredicateOperand - This can be used to define a predicate operand for an
670
/// instruction. OpTypes specifies the MIOperandInfo for the operand, and
671
/// AlwaysVal specifies the value of this predicate when set to "always
673
class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
674
: OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
675
let MIOperandInfo = OpTypes;
678
/// OptionalDefOperand - This is used to define a optional definition operand
679
/// for an instruction. DefaultOps is the register the operand represents if
680
/// none is supplied, e.g. zero_reg.
681
class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
682
: OperandWithDefaultOps<ty, defaultops> {
683
let MIOperandInfo = OpTypes;
687
// InstrInfo - This class should only be instantiated once to provide parameters
688
// which are global to the target machine.
691
// Target can specify its instructions in either big or little-endian formats.
692
// For instance, while both Sparc and PowerPC are big-endian platforms, the
693
// Sparc manual specifies its instructions in the format [31..0] (big), while
694
// PowerPC specifies them using the format [0..31] (little).
695
bit isLittleEndianEncoding = 0;
697
// The instruction properties mayLoad, mayStore, and hasSideEffects are unset
698
// by default, and TableGen will infer their value from the instruction
699
// pattern when possible.
701
// Normally, TableGen will issue an error it it can't infer the value of a
702
// property that hasn't been set explicitly. When guessInstructionProperties
703
// is set, it will guess a safe value instead.
705
// This option is a temporary migration help. It will go away.
706
bit guessInstructionProperties = 1;
708
// TableGen's instruction encoder generator has support for matching operands
709
// to bit-field variables both by name and by position. While matching by
710
// name is preferred, this is currently not possible for complex operands,
711
// and some targets still reply on the positional encoding rules. When
712
// generating a decoder for such targets, the positional encoding rules must
713
// be used by the decoder generator as well.
715
// This option is temporary; it will go away once the TableGen decoder
716
// generator has better support for complex operands and targets have
717
// migrated away from using positionally encoded operands.
718
bit decodePositionallyEncodedOperands = 0;
720
// When set, this indicates that there will be no overlap between those
721
// operands that are matched by ordering (positional operands) and those
724
// This option is temporary; it will go away once the TableGen decoder
725
// generator has better support for complex operands and targets have
726
// migrated away from using positionally encoded operands.
727
bit noNamedPositionallyEncodedOperands = 0;
730
// Standard Pseudo Instructions.
731
// This list must match TargetOpcodes.h and CodeGenTarget.cpp.
732
// Only these instructions are allowed in the TargetOpcode namespace.
733
let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
734
def PHI : Instruction {
735
let OutOperandList = (outs);
736
let InOperandList = (ins variable_ops);
737
let AsmString = "PHINODE";
739
def INLINEASM : Instruction {
740
let OutOperandList = (outs);
741
let InOperandList = (ins variable_ops);
743
let hasSideEffects = 0; // Note side effect is encoded in an operand.
745
def CFI_INSTRUCTION : Instruction {
746
let OutOperandList = (outs);
747
let InOperandList = (ins i32imm:$id);
750
let isNotDuplicable = 1;
752
def EH_LABEL : Instruction {
753
let OutOperandList = (outs);
754
let InOperandList = (ins i32imm:$id);
757
let isNotDuplicable = 1;
759
def GC_LABEL : Instruction {
760
let OutOperandList = (outs);
761
let InOperandList = (ins i32imm:$id);
764
let isNotDuplicable = 1;
766
def KILL : Instruction {
767
let OutOperandList = (outs);
768
let InOperandList = (ins variable_ops);
770
let hasSideEffects = 0;
772
def EXTRACT_SUBREG : Instruction {
773
let OutOperandList = (outs unknown:$dst);
774
let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
776
let hasSideEffects = 0;
778
def INSERT_SUBREG : Instruction {
779
let OutOperandList = (outs unknown:$dst);
780
let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
782
let hasSideEffects = 0;
783
let Constraints = "$supersrc = $dst";
785
def IMPLICIT_DEF : Instruction {
786
let OutOperandList = (outs unknown:$dst);
787
let InOperandList = (ins);
789
let hasSideEffects = 0;
790
let isReMaterializable = 1;
791
let isAsCheapAsAMove = 1;
793
def SUBREG_TO_REG : Instruction {
794
let OutOperandList = (outs unknown:$dst);
795
let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
797
let hasSideEffects = 0;
799
def COPY_TO_REGCLASS : Instruction {
800
let OutOperandList = (outs unknown:$dst);
801
let InOperandList = (ins unknown:$src, i32imm:$regclass);
803
let hasSideEffects = 0;
804
let isAsCheapAsAMove = 1;
806
def DBG_VALUE : Instruction {
807
let OutOperandList = (outs);
808
let InOperandList = (ins variable_ops);
809
let AsmString = "DBG_VALUE";
810
let hasSideEffects = 0;
812
def REG_SEQUENCE : Instruction {
813
let OutOperandList = (outs unknown:$dst);
814
let InOperandList = (ins unknown:$supersrc, variable_ops);
816
let hasSideEffects = 0;
817
let isAsCheapAsAMove = 1;
819
def COPY : Instruction {
820
let OutOperandList = (outs unknown:$dst);
821
let InOperandList = (ins unknown:$src);
823
let hasSideEffects = 0;
824
let isAsCheapAsAMove = 1;
826
def BUNDLE : Instruction {
827
let OutOperandList = (outs);
828
let InOperandList = (ins variable_ops);
829
let AsmString = "BUNDLE";
831
def LIFETIME_START : Instruction {
832
let OutOperandList = (outs);
833
let InOperandList = (ins i32imm:$id);
834
let AsmString = "LIFETIME_START";
835
let hasSideEffects = 0;
837
def LIFETIME_END : Instruction {
838
let OutOperandList = (outs);
839
let InOperandList = (ins i32imm:$id);
840
let AsmString = "LIFETIME_END";
841
let hasSideEffects = 0;
843
def STACKMAP : Instruction {
844
let OutOperandList = (outs);
845
let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
848
let usesCustomInserter = 1;
850
def PATCHPOINT : Instruction {
851
let OutOperandList = (outs unknown:$dst);
852
let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
853
i32imm:$nargs, i32imm:$cc, variable_ops);
856
let usesCustomInserter = 1;
858
def STATEPOINT : Instruction {
859
let OutOperandList = (outs);
860
let InOperandList = (ins variable_ops);
861
let usesCustomInserter = 1;
864
let hasSideEffects = 1;
867
def LOAD_STACK_GUARD : Instruction {
868
let OutOperandList = (outs ptr_rc:$dst);
869
let InOperandList = (ins);
871
bit isReMaterializable = 1;
872
let hasSideEffects = 0;
875
def LOCAL_ESCAPE : Instruction {
876
// This instruction is really just a label. It has to be part of the chain so
877
// that it doesn't get dropped from the DAG, but it produces nothing and has
879
let OutOperandList = (outs);
880
let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
881
let hasSideEffects = 0;
884
def FAULTING_LOAD_OP : Instruction {
885
let OutOperandList = (outs unknown:$dst);
886
let InOperandList = (ins variable_ops);
887
let usesCustomInserter = 1;
892
//===----------------------------------------------------------------------===//
893
// AsmParser - This class can be implemented by targets that wish to implement
896
// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
897
// syntax on X86 for example).
900
// AsmParserClassName - This specifies the suffix to use for the asmparser
901
// class. Generated AsmParser classes are always prefixed with the target
903
string AsmParserClassName = "AsmParser";
905
// AsmParserInstCleanup - If non-empty, this is the name of a custom member
906
// function of the AsmParser class to call on every matched instruction.
907
// This can be used to perform target specific instruction post-processing.
908
string AsmParserInstCleanup = "";
910
// ShouldEmitMatchRegisterName - Set to false if the target needs a hand
911
// written register name matcher
912
bit ShouldEmitMatchRegisterName = 1;
914
/// Does the instruction mnemonic allow '.'
915
bit MnemonicContainsDot = 0;
917
def DefaultAsmParser : AsmParser;
919
//===----------------------------------------------------------------------===//
920
// AsmParserVariant - Subtargets can have multiple different assembly parsers
921
// (e.g. AT&T vs Intel syntax on X86 for example). This class can be
922
// implemented by targets to describe such variants.
924
class AsmParserVariant {
925
// Variant - AsmParsers can be of multiple different variants. Variants are
926
// used to support targets that need to parser multiple formats for the
927
// assembly language.
930
// Name - The AsmParser variant name (e.g., AT&T vs Intel).
933
// CommentDelimiter - If given, the delimiter string used to recognize
934
// comments which are hard coded in the .td assembler strings for individual
936
string CommentDelimiter = "";
938
// RegisterPrefix - If given, the token prefix which indicates a register
939
// token. This is used by the matcher to automatically recognize hard coded
940
// register tokens as constrained registers, instead of tokens, for the
941
// purposes of matching.
942
string RegisterPrefix = "";
944
def DefaultAsmParserVariant : AsmParserVariant;
946
/// AssemblerPredicate - This is a Predicate that can be used when the assembler
947
/// matches instructions and aliases.
948
class AssemblerPredicate<string cond, string name = ""> {
949
bit AssemblerMatcherPredicate = 1;
950
string AssemblerCondString = cond;
951
string PredicateName = name;
954
/// TokenAlias - This class allows targets to define assembler token
955
/// operand aliases. That is, a token literal operand which is equivalent
956
/// to another, canonical, token literal. For example, ARM allows:
957
/// vmov.u32 s4, #0 -> vmov.i32, #0
958
/// 'u32' is a more specific designator for the 32-bit integer type specifier
959
/// and is legal for any instruction which accepts 'i32' as a datatype suffix.
960
/// def : TokenAlias<".u32", ".i32">;
962
/// This works by marking the match class of 'From' as a subclass of the
963
/// match class of 'To'.
964
class TokenAlias<string From, string To> {
965
string FromToken = From;
969
/// MnemonicAlias - This class allows targets to define assembler mnemonic
970
/// aliases. This should be used when all forms of one mnemonic are accepted
971
/// with a different mnemonic. For example, X86 allows:
972
/// sal %al, 1 -> shl %al, 1
973
/// sal %ax, %cl -> shl %ax, %cl
974
/// sal %eax, %cl -> shl %eax, %cl
975
/// etc. Though "sal" is accepted with many forms, all of them are directly
976
/// translated to a shl, so it can be handled with (in the case of X86, it
977
/// actually has one for each suffix as well):
978
/// def : MnemonicAlias<"sal", "shl">;
980
/// Mnemonic aliases are mapped before any other translation in the match phase,
981
/// and do allow Requires predicates, e.g.:
983
/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
984
/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
986
/// Mnemonic aliases can also be constrained to specific variants, e.g.:
988
/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
990
/// If no variant (e.g., "att" or "intel") is specified then the alias is
991
/// applied unconditionally.
992
class MnemonicAlias<string From, string To, string VariantName = ""> {
993
string FromMnemonic = From;
994
string ToMnemonic = To;
995
string AsmVariantName = VariantName;
997
// Predicates - Predicates that must be true for this remapping to happen.
998
list<Predicate> Predicates = [];
1001
/// InstAlias - This defines an alternate assembly syntax that is allowed to
1002
/// match an instruction that has a different (more canonical) assembly
1004
class InstAlias<string Asm, dag Result, int Emit = 1> {
1005
string AsmString = Asm; // The .s format to match the instruction with.
1006
dag ResultInst = Result; // The MCInst to generate.
1008
// This determines which order the InstPrinter detects aliases for
1009
// printing. A larger value makes the alias more likely to be
1010
// emitted. The Instruction's own definition is notionally 0.5, so 0
1011
// disables printing and 1 enables it if there are no conflicting aliases.
1012
int EmitPriority = Emit;
1014
// Predicates - Predicates that must be true for this to match.
1015
list<Predicate> Predicates = [];
1017
// If the instruction specified in Result has defined an AsmMatchConverter
1018
// then setting this to 1 will cause the alias to use the AsmMatchConverter
1019
// function when converting the OperandVector into an MCInst instead of the
1020
// function that is generated by the dag Result.
1021
// Setting this to 0 will cause the alias to ignore the Result instruction's
1022
// defined AsmMatchConverter and instead use the function generated by the
1024
bit UseInstAsmMatchConverter = 1;
1027
//===----------------------------------------------------------------------===//
1028
// AsmWriter - This class can be implemented by targets that need to customize
1029
// the format of the .s file writer.
1031
// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
1032
// on X86 for example).
1035
// AsmWriterClassName - This specifies the suffix to use for the asmwriter
1036
// class. Generated AsmWriter classes are always prefixed with the target
1038
string AsmWriterClassName = "InstPrinter";
1040
// PassSubtarget - Determines whether MCSubtargetInfo should be passed to
1041
// the various print methods.
1042
// FIXME: Remove after all ports are updated.
1043
int PassSubtarget = 0;
1045
// Variant - AsmWriters can be of multiple different variants. Variants are
1046
// used to support targets that need to emit assembly code in ways that are
1047
// mostly the same for different targets, but have minor differences in
1048
// syntax. If the asmstring contains {|} characters in them, this integer
1049
// will specify which alternative to use. For example "{x|y|z}" with Variant
1050
// == 1, will expand to "y".
1053
def DefaultAsmWriter : AsmWriter;
1056
//===----------------------------------------------------------------------===//
1057
// Target - This class contains the "global" target information
1060
// InstructionSet - Instruction set description for this target.
1061
InstrInfo InstructionSet;
1063
// AssemblyParsers - The AsmParser instances available for this target.
1064
list<AsmParser> AssemblyParsers = [DefaultAsmParser];
1066
/// AssemblyParserVariants - The AsmParserVariant instances available for
1068
list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
1070
// AssemblyWriters - The AsmWriter instances available for this target.
1071
list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
1074
//===----------------------------------------------------------------------===//
1075
// SubtargetFeature - A characteristic of the chip set.
1077
class SubtargetFeature<string n, string a, string v, string d,
1078
list<SubtargetFeature> i = []> {
1079
// Name - Feature name. Used by command line (-mattr=) to determine the
1080
// appropriate target chip.
1084
// Attribute - Attribute to be set by feature.
1086
string Attribute = a;
1088
// Value - Value the attribute to be set to by feature.
1092
// Desc - Feature description. Used by command line (-mattr=) to display help
1097
// Implies - Features that this feature implies are present. If one of those
1098
// features isn't set, then this one shouldn't be set either.
1100
list<SubtargetFeature> Implies = i;
1103
/// Specifies a Subtarget feature that this instruction is deprecated on.
1104
class Deprecated<SubtargetFeature dep> {
1105
SubtargetFeature DeprecatedFeatureMask = dep;
1108
/// A custom predicate used to determine if an instruction is
1109
/// deprecated or not.
1110
class ComplexDeprecationPredicate<string dep> {
1111
string ComplexDeprecationPredicate = dep;
1114
//===----------------------------------------------------------------------===//
1115
// Processor chip sets - These values represent each of the chip sets supported
1116
// by the scheduler. Each Processor definition requires corresponding
1117
// instruction itineraries.
1119
class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
1120
// Name - Chip set name. Used by command line (-mcpu=) to determine the
1121
// appropriate target chip.
1125
// SchedModel - The machine model for scheduling and instruction cost.
1127
SchedMachineModel SchedModel = NoSchedModel;
1129
// ProcItin - The scheduling information for the target processor.
1131
ProcessorItineraries ProcItin = pi;
1133
// Features - list of
1134
list<SubtargetFeature> Features = f;
1137
// ProcessorModel allows subtargets to specify the more general
1138
// SchedMachineModel instead if a ProcessorItinerary. Subtargets will
1139
// gradually move to this newer form.
1141
// Although this class always passes NoItineraries to the Processor
1142
// class, the SchedMachineModel may still define valid Itineraries.
1143
class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1144
: Processor<n, NoItineraries, f> {
1148
//===----------------------------------------------------------------------===//
1149
// InstrMapping - This class is used to create mapping tables to relate
1150
// instructions with each other based on the values specified in RowFields,
1151
// ColFields, KeyCol and ValueCols.
1153
class InstrMapping {
1154
// FilterClass - Used to limit search space only to the instructions that
1155
// define the relationship modeled by this InstrMapping record.
1158
// RowFields - List of fields/attributes that should be same for all the
1159
// instructions in a row of the relation table. Think of this as a set of
1160
// properties shared by all the instructions related by this relationship
1161
// model and is used to categorize instructions into subgroups. For instance,
1162
// if we want to define a relation that maps 'Add' instruction to its
1163
// predicated forms, we can define RowFields like this:
1165
// let RowFields = BaseOp
1166
// All add instruction predicated/non-predicated will have to set their BaseOp
1167
// to the same value.
1169
// def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1170
// def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1171
// def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1172
list<string> RowFields = [];
1174
// List of fields/attributes that are same for all the instructions
1175
// in a column of the relation table.
1176
// Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1177
// based on the 'predSense' values. All the instruction in a specific
1178
// column have the same value and it is fixed for the column according
1179
// to the values set in 'ValueCols'.
1180
list<string> ColFields = [];
1182
// Values for the fields/attributes listed in 'ColFields'.
1183
// Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1184
// that models this relation) should be non-predicated.
1185
// In the example above, 'Add' is the key instruction.
1186
list<string> KeyCol = [];
1188
// List of values for the fields/attributes listed in 'ColFields', one for
1189
// each column in the relation table.
1191
// Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1192
// table. First column requires all the instructions to have predSense
1193
// set to 'true' and second column requires it to be 'false'.
1194
list<list<string> > ValueCols = [];
1197
//===----------------------------------------------------------------------===//
1198
// Pull in the common support for calling conventions.
1200
include "llvm/Target/TargetCallingConv.td"
1202
//===----------------------------------------------------------------------===//
1203
// Pull in the common support for DAG isel generation.
1205
include "llvm/Target/TargetSelectionDAG.td"
added
removed
include/llvm/Target/Target.td
