1
; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC
2
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC
3
; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC
4
; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR
8
; ACC - Targets with accumulator based mul/div (i.e. pre-MIPS32r6)
9
; GPR - Targets with register based mul/div (i.e. MIPS32r6)
11
define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {
14
; ACC: dmult ${{[45]}}, ${{[45]}}
16
; GPR: dmul $2, ${{[45]}}, ${{[45]}}
17
%mul = mul i64 %a1, %a0
21
define i64 @m1(i64 %a) nounwind readnone {
24
; ALL: lui $[[T0:[0-9]+]], 21845
25
; ALL: addiu $[[T0]], $[[T0]], 21845
26
; ALL: dsll $[[T0]], $[[T0]], 16
27
; ALL: addiu $[[T0]], $[[T0]], 21845
28
; ALL: dsll $[[T0]], $[[T0]], 16
29
; ALL: addiu $[[T0]], $[[T0]], 21846
31
; ACC: dmult $4, $[[T0]]
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; ACC: mfhi $[[T1:[0-9]+]]
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; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
35
; ALL: dsrl $2, $[[T1]], 63
36
; ALL: daddu $2, $[[T1]], $2
41
define i64 @d0(i64 %a0, i64 %a1) nounwind readnone {
44
; ACC: ddivu $zero, $4, $5
46
; GPR: ddivu $2, $4, $5
47
%div = udiv i64 %a0, %a1
51
define i64 @d1(i64 %a0, i64 %a1) nounwind readnone {
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; ACC: ddiv $zero, $4, $5
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; GPR: ddiv $2, $4, $5
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%div = sdiv i64 %a0, %a1
61
define i64 @d2(i64 %a0, i64 %a1) nounwind readnone {
64
; ACC: ddivu $zero, $4, $5
66
; GPR: dmodu $2, $4, $5
67
%rem = urem i64 %a0, %a1
71
define i64 @d3(i64 %a0, i64 %a1) nounwind readnone {
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; ACC: ddiv $zero, $4, $5
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; GPR: dmod $2, $4, $5
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%rem = srem i64 %a0, %a1