1
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
2
; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
3
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
5
declare i32 @llvm.r600.read.tidig.x() #0
7
; FUNC-LABEL: {{^}}lshr_i32:
8
; SI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
9
; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
10
; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
11
define void @lshr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
12
%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
13
%a = load i32, i32 addrspace(1)* %in
14
%b = load i32, i32 addrspace(1)* %b_ptr
15
%result = lshr i32 %a, %b
16
store i32 %result, i32 addrspace(1)* %out
20
; FUNC-LABEL: {{^}}lshr_v2i32:
21
; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
22
; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
24
; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
25
; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
27
; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28
; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29
define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
30
%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
31
%a = load <2 x i32>, <2 x i32> addrspace(1)* %in
32
%b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
33
%result = lshr <2 x i32> %a, %b
34
store <2 x i32> %result, <2 x i32> addrspace(1)* %out
38
; FUNC-LABEL: {{^}}lshr_v4i32:
39
; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
40
; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
41
; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
42
; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
44
; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
45
; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
46
; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
47
; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
49
; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
50
; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
51
; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
52
; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
53
define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
54
%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
55
%a = load <4 x i32>, <4 x i32> addrspace(1)* %in
56
%b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
57
%result = lshr <4 x i32> %a, %b
58
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
62
; FUNC-LABEL: {{^}}lshr_i64:
63
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
64
; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
66
; EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
67
; EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
68
; EG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
69
; EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
70
; EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
71
; EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
72
; EG-DAG: LSHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
73
; EG-DAG: LSHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
74
; EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
75
; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
76
; EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
77
define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
78
%b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
79
%a = load i64, i64 addrspace(1)* %in
80
%b = load i64, i64 addrspace(1)* %b_ptr
81
%result = lshr i64 %a, %b
82
store i64 %result, i64 addrspace(1)* %out
86
; FUNC-LABEL: {{^}}lshr_v2i64:
87
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
90
; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
91
; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
93
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
94
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
95
; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
96
; EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
97
; EG-DAG: LSHL {{.*}}, 1
98
; EG-DAG: LSHL {{.*}}, 1
99
; EG-DAG: LSHR {{.*}}, [[SHA]]
100
; EG-DAG: LSHR {{.*}}, [[SHB]]
101
; EG-DAG: LSHR {{.*}}, [[SHA]]
102
; EG-DAG: LSHR {{.*}}, [[SHB]]
105
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
106
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
109
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
110
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
111
; EG-DAG: CNDE_INT {{.*}}, 0.0
112
; EG-DAG: CNDE_INT {{.*}}, 0.0
115
define void @lshr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
116
%b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
117
%a = load <2 x i64>, <2 x i64> addrspace(1)* %in
118
%b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
119
%result = lshr <2 x i64> %a, %b
120
store <2 x i64> %result, <2 x i64> addrspace(1)* %out
124
; FUNC-LABEL: {{^}}lshr_v4i64:
125
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128
; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
130
; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
131
; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
132
; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
133
; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
135
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
136
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
137
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
138
; EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
139
; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
140
; EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
141
; EG-DAG: LSHL {{\*? *}}[[COMPSHC]]
142
; EG-DAG: LSHL {{\*? *}}[[COMPSHD]]
143
; EG-DAG: LSHL {{.*}}, 1
144
; EG-DAG: LSHL {{.*}}, 1
145
; EG-DAG: LSHL {{.*}}, 1
146
; EG-DAG: LSHL {{.*}}, 1
147
; EG-DAG: LSHR {{.*}}, [[SHA]]
148
; EG-DAG: LSHR {{.*}}, [[SHB]]
149
; EG-DAG: LSHR {{.*}}, [[SHC]]
150
; EG-DAG: LSHR {{.*}}, [[SHD]]
151
; EG-DAG: LSHR {{.*}}, [[SHA]]
152
; EG-DAG: LSHR {{.*}}, [[SHB]]
153
; EG-DAG: LSHR {{.*}}, [[SHC]]
154
; EG-DAG: LSHR {{.*}}, [[SHD]]
159
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
160
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
161
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
162
; EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
169
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
170
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
171
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
172
; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
173
; EG-DAG: CNDE_INT {{.*}}, 0.0
174
; EG-DAG: CNDE_INT {{.*}}, 0.0
175
; EG-DAG: CNDE_INT {{.*}}, 0.0
176
; EG-DAG: CNDE_INT {{.*}}, 0.0
181
define void @lshr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
182
%b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
183
%a = load <4 x i64>, <4 x i64> addrspace(1)* %in
184
%b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
185
%result = lshr <4 x i64> %a, %b
186
store <4 x i64> %result, <4 x i64> addrspace(1)* %out
190
; Make sure load width gets reduced to i32 load.
191
; GCN-LABEL: {{^}}s_lshr_32_i64:
192
; GCN-DAG: s_load_dword [[HI_A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc{{$}}
193
; GCN-DAG: s_mov_b32 s[[SHI:[0-9]+]], 0{{$}}
194
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
195
; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[HI_A]]
196
; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}}
197
define void @s_lshr_32_i64(i64 addrspace(1)* %out, i64 %a) {
198
%result = lshr i64 %a, 32
199
store i64 %result, i64 addrspace(1)* %out
203
; GCN-LABEL: {{^}}v_lshr_32_i64:
204
; GCN-DAG: buffer_load_dword v[[HI_A:[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
205
; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], 0{{$}}
206
; GCN: buffer_store_dwordx2 v{{\[}}[[HI_A]]:[[VHI]]{{\]}}
207
define void @v_lshr_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
208
%tid = call i32 @llvm.r600.read.tidig.x() #0
209
%gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
210
%gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
211
%a = load i64, i64 addrspace(1)* %gep.in
212
%result = lshr i64 %a, 32
213
store i64 %result, i64 addrspace(1)* %gep.out
217
attributes #0 = { nounwind readnone }