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#ifndef AT91_DBGU_H
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#define AT91_DBGU_H
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#define dbgu_readl(dbgu, field) \
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__raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
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#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
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#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
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#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
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#define AT91_DBGU_CR (0x00) /* Control Register */
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#define AT91_DBGU_MR (0x04) /* Mode Register */
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#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
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#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
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#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
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#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
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#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
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#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
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#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
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#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
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#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
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#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */
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#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */
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#define AT91_DBGU_SR (0x14) /* Status Register */
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#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */
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#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
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#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */
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#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
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#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
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#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
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#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */
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#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */
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#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
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#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
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#endif /* AT91_DBGU */