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/* bnx2x_main.c: Broadcom Everest network driver.
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* Copyright (c) 2007-2011 Broadcom Corporation
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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* Maintained by: Eilon Greenstein <eilong@broadcom.com>
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* Written by: Eliezer Tamir
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* Based on code from Michael Chan's bnx2 driver
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* UDP CSUM errata workaround by Arik Gendelman
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* Slowpath and fastpath rework by Vladislav Zolotarov
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* Statistics and Link management by Yitchak Gertner
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/kernel.h>
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#include <linux/device.h> /* for dev_info() */
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#include <linux/timer.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/dma-mapping.h>
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <asm/byteorder.h>
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#include <linux/time.h>
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#include <linux/ethtool.h>
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#include <linux/mii.h>
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#include <linux/if_vlan.h>
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#include <net/checksum.h>
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#include <net/ip6_checksum.h>
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#include <linux/workqueue.h>
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#include <linux/crc32.h>
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#include <linux/crc32c.h>
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#include <linux/prefetch.h>
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#include <linux/zlib.h>
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#include <linux/stringify.h>
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#include <linux/vmalloc.h>
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#include "bnx2x_init.h"
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#include "bnx2x_init_ops.h"
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#include "bnx2x_cmn.h"
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#include "bnx2x_dcb.h"
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#include <linux/firmware.h>
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#include "bnx2x_fw_file_hdr.h"
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#define FW_FILE_VERSION \
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__stringify(BCM_5710_FW_MAJOR_VERSION) "." \
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__stringify(BCM_5710_FW_MINOR_VERSION) "." \
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__stringify(BCM_5710_FW_REVISION_VERSION) "." \
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__stringify(BCM_5710_FW_ENGINEERING_VERSION)
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#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
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#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
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#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
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/* Time in jiffies before concluding the transmitter is hung */
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#define TX_TIMEOUT (5*HZ)
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static char version[] __devinitdata =
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"Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
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DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
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MODULE_AUTHOR("Eliezer Tamir");
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MODULE_DESCRIPTION("Broadcom NetXtreme II "
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"BCM57710/57711/57711E/"
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"57712/57712_MF/57800/57800_MF/57810/57810_MF/"
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"57840/57840_MF Driver");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(DRV_MODULE_VERSION);
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MODULE_FIRMWARE(FW_FILE_NAME_E1);
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MODULE_FIRMWARE(FW_FILE_NAME_E1H);
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MODULE_FIRMWARE(FW_FILE_NAME_E2);
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static int multi_mode = 1;
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module_param(multi_mode, int, 0);
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MODULE_PARM_DESC(multi_mode, " Multi queue mode "
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"(0 Disable; 1 Enable (default))");
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module_param(num_queues, int, 0);
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MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
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" (default is as a number of CPUs)");
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static int disable_tpa;
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module_param(disable_tpa, int, 0);
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MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
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#define INT_MODE_INTx 1
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#define INT_MODE_MSI 2
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module_param(int_mode, int, 0);
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MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
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static int dropless_fc;
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module_param(dropless_fc, int, 0);
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MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
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module_param(poll, int, 0);
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MODULE_PARM_DESC(poll, " Use polling (for debug)");
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static int mrrs = -1;
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module_param(mrrs, int, 0);
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MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
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module_param(debug, int, 0);
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MODULE_PARM_DESC(debug, " Default debug msglevel");
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struct workqueue_struct *bnx2x_wq;
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enum bnx2x_board_type {
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/* indexed by board_type, above */
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} board_info[] __devinitdata = {
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{ "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
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{ "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
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{ "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
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{ "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
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{ "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
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{ "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
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{ "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
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{ "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
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{ "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
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{ "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
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{ "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
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"Ethernet Multi Function"}
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#ifndef PCI_DEVICE_ID_NX2_57710
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#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
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#ifndef PCI_DEVICE_ID_NX2_57711
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#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
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#ifndef PCI_DEVICE_ID_NX2_57711E
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#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
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#ifndef PCI_DEVICE_ID_NX2_57712
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#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
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#ifndef PCI_DEVICE_ID_NX2_57712_MF
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#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
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#ifndef PCI_DEVICE_ID_NX2_57800
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#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
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#ifndef PCI_DEVICE_ID_NX2_57800_MF
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#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
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#ifndef PCI_DEVICE_ID_NX2_57810
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#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
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#ifndef PCI_DEVICE_ID_NX2_57810_MF
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#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
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#ifndef PCI_DEVICE_ID_NX2_57840
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#define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
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#ifndef PCI_DEVICE_ID_NX2_57840_MF
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#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
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static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
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{ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
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MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
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/****************************************************************************
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* General service functions
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****************************************************************************/
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static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
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u32 addr, dma_addr_t mapping)
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REG_WR(bp, addr, U64_LO(mapping));
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REG_WR(bp, addr + 4, U64_HI(mapping));
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static inline void storm_memset_spq_addr(struct bnx2x *bp,
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dma_addr_t mapping, u16 abs_fid)
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u32 addr = XSEM_REG_FAST_MEMORY +
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XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
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__storm_memset_dma_mapping(bp, addr, mapping);
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static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
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REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
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REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
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REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
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REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
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static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
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REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
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REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
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REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
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REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
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static inline void storm_memset_eq_data(struct bnx2x *bp,
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struct event_ring_data *eq_data,
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size_t size = sizeof(struct event_ring_data);
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u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
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__storm_memset_struct(bp, addr, size, (u32 *)eq_data);
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static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
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u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
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REG_WR16(bp, addr, eq_prod);
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* locking is done by mcp
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static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
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pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
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pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
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pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
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PCICFG_VENDOR_ID_OFFSET);
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static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
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pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
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pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
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pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
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PCICFG_VENDOR_ID_OFFSET);
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#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
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#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
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#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
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#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
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#define DMAE_DP_DST_NONE "dst_addr [none]"
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static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
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u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
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switch (dmae->opcode & DMAE_COMMAND_DST) {
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case DMAE_CMD_DST_PCI:
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if (src_type == DMAE_CMD_SRC_PCI)
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DP(msglvl, "DMAE: opcode 0x%08x\n"
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"src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
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"comp_addr [%x:%08x], comp_val 0x%08x\n",
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dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
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dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
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dmae->comp_addr_hi, dmae->comp_addr_lo,
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DP(msglvl, "DMAE: opcode 0x%08x\n"
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"src [%08x], len [%d*4], dst [%x:%08x]\n"
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"comp_addr [%x:%08x], comp_val 0x%08x\n",
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dmae->opcode, dmae->src_addr_lo >> 2,
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dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
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dmae->comp_addr_hi, dmae->comp_addr_lo,
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case DMAE_CMD_DST_GRC:
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if (src_type == DMAE_CMD_SRC_PCI)
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DP(msglvl, "DMAE: opcode 0x%08x\n"
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"src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
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"comp_addr [%x:%08x], comp_val 0x%08x\n",
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dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
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dmae->len, dmae->dst_addr_lo >> 2,
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dmae->comp_addr_hi, dmae->comp_addr_lo,
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DP(msglvl, "DMAE: opcode 0x%08x\n"
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"src [%08x], len [%d*4], dst [%08x]\n"
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"comp_addr [%x:%08x], comp_val 0x%08x\n",
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dmae->opcode, dmae->src_addr_lo >> 2,
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dmae->len, dmae->dst_addr_lo >> 2,
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dmae->comp_addr_hi, dmae->comp_addr_lo,
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if (src_type == DMAE_CMD_SRC_PCI)
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DP(msglvl, "DMAE: opcode 0x%08x\n"
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"src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
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"comp_addr [%x:%08x] comp_val 0x%08x\n",
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dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
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dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
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DP(msglvl, "DMAE: opcode 0x%08x\n"
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"src_addr [%08x] len [%d * 4] dst_addr [none]\n"
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"comp_addr [%x:%08x] comp_val 0x%08x\n",
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dmae->opcode, dmae->src_addr_lo >> 2,
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dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
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/* copy command into DMAE command memory and set DMAE command go */
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void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
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cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
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for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
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REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
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DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
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idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
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REG_WR(bp, dmae_reg_go_c[idx], 1);
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u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
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return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
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u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
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return opcode & ~DMAE_CMD_SRC_RESET;
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u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
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bool with_comp, u8 comp_type)
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opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
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(dst_type << DMAE_COMMAND_DST_SHIFT));
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opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
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opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
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opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
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(BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
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opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
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opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
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opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
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opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
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static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
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struct dmae_command *dmae,
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u8 src_type, u8 dst_type)
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memset(dmae, 0, sizeof(struct dmae_command));
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dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
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true, DMAE_COMP_PCI);
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/* fill in the completion parameters */
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dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
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dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
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dmae->comp_val = DMAE_COMP_VAL;
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/* issue a dmae command over the init-channel and wailt for completion */
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static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
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struct dmae_command *dmae)
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u32 *wb_comp = bnx2x_sp(bp, wb_comp);
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int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
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DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
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bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
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bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
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* Lock the dmae channel. Disable BHs to prevent a dead-lock
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* as long as this code is called both from syscall context and
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* from ndo_set_rx_mode() flow that may be called from BH.
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spin_lock_bh(&bp->dmae_lock);
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/* reset completion */
463
/* post the command on the channel used for initializations */
464
bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
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/* wait for completion */
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while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
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DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
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BNX2X_ERR("DMAE timeout!\n");
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if (*wb_comp & DMAE_PCI_ERR_FLAG) {
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BNX2X_ERR("DMAE PCI error!\n");
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DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
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bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
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bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
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spin_unlock_bh(&bp->dmae_lock);
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void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
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struct dmae_command dmae;
498
if (!bp->dmae_ready) {
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u32 *data = bnx2x_sp(bp, wb_data[0]);
501
DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
502
" using indirect\n", dst_addr, len32);
503
bnx2x_init_ind_wr(bp, dst_addr, data, len32);
507
/* set opcode and fixed command fields */
508
bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
510
/* fill in addresses and len */
511
dmae.src_addr_lo = U64_LO(dma_addr);
512
dmae.src_addr_hi = U64_HI(dma_addr);
513
dmae.dst_addr_lo = dst_addr >> 2;
514
dmae.dst_addr_hi = 0;
517
bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
519
/* issue the command and wait for completion */
520
bnx2x_issue_dmae_with_comp(bp, &dmae);
523
void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
525
struct dmae_command dmae;
527
if (!bp->dmae_ready) {
528
u32 *data = bnx2x_sp(bp, wb_data[0]);
531
DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
532
" using indirect\n", src_addr, len32);
533
for (i = 0; i < len32; i++)
534
data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
538
/* set opcode and fixed command fields */
539
bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
541
/* fill in addresses and len */
542
dmae.src_addr_lo = src_addr >> 2;
543
dmae.src_addr_hi = 0;
544
dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
545
dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
548
bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
550
/* issue the command and wait for completion */
551
bnx2x_issue_dmae_with_comp(bp, &dmae);
554
static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
557
int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
560
while (len > dmae_wr_max) {
561
bnx2x_write_dmae(bp, phys_addr + offset,
562
addr + offset, dmae_wr_max);
563
offset += dmae_wr_max * 4;
567
bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
570
/* used only for slowpath so not inlined */
571
static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
575
wb_write[0] = val_hi;
576
wb_write[1] = val_lo;
577
REG_WR_DMAE(bp, reg, wb_write, 2);
581
static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
585
REG_RD_DMAE(bp, reg, wb_data, 2);
587
return HILO_U64(wb_data[0], wb_data[1]);
591
static int bnx2x_mc_assert(struct bnx2x *bp)
595
u32 row0, row1, row2, row3;
598
last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
599
XSTORM_ASSERT_LIST_INDEX_OFFSET);
601
BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
603
/* print the asserts */
604
for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
606
row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
607
XSTORM_ASSERT_LIST_OFFSET(i));
608
row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
609
XSTORM_ASSERT_LIST_OFFSET(i) + 4);
610
row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
611
XSTORM_ASSERT_LIST_OFFSET(i) + 8);
612
row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
613
XSTORM_ASSERT_LIST_OFFSET(i) + 12);
615
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
616
BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
617
" 0x%08x 0x%08x 0x%08x\n",
618
i, row3, row2, row1, row0);
626
last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
627
TSTORM_ASSERT_LIST_INDEX_OFFSET);
629
BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
631
/* print the asserts */
632
for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
634
row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
635
TSTORM_ASSERT_LIST_OFFSET(i));
636
row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
637
TSTORM_ASSERT_LIST_OFFSET(i) + 4);
638
row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
639
TSTORM_ASSERT_LIST_OFFSET(i) + 8);
640
row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
641
TSTORM_ASSERT_LIST_OFFSET(i) + 12);
643
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
644
BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
645
" 0x%08x 0x%08x 0x%08x\n",
646
i, row3, row2, row1, row0);
654
last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
655
CSTORM_ASSERT_LIST_INDEX_OFFSET);
657
BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
659
/* print the asserts */
660
for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
662
row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
663
CSTORM_ASSERT_LIST_OFFSET(i));
664
row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
665
CSTORM_ASSERT_LIST_OFFSET(i) + 4);
666
row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
667
CSTORM_ASSERT_LIST_OFFSET(i) + 8);
668
row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
669
CSTORM_ASSERT_LIST_OFFSET(i) + 12);
671
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
672
BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
673
" 0x%08x 0x%08x 0x%08x\n",
674
i, row3, row2, row1, row0);
682
last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
683
USTORM_ASSERT_LIST_INDEX_OFFSET);
685
BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
687
/* print the asserts */
688
for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
690
row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
691
USTORM_ASSERT_LIST_OFFSET(i));
692
row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
693
USTORM_ASSERT_LIST_OFFSET(i) + 4);
694
row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
695
USTORM_ASSERT_LIST_OFFSET(i) + 8);
696
row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
697
USTORM_ASSERT_LIST_OFFSET(i) + 12);
699
if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
700
BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
701
" 0x%08x 0x%08x 0x%08x\n",
702
i, row3, row2, row1, row0);
712
void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
718
u32 trace_shmem_base;
720
BNX2X_ERR("NO MCP - can not dump\n");
723
netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
724
(bp->common.bc_ver & 0xff0000) >> 16,
725
(bp->common.bc_ver & 0xff00) >> 8,
726
(bp->common.bc_ver & 0xff));
728
val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
729
if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
730
printk("%s" "MCP PC at 0x%x\n", lvl, val);
732
if (BP_PATH(bp) == 0)
733
trace_shmem_base = bp->common.shmem_base;
735
trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
736
addr = trace_shmem_base - 0x0800 + 4;
737
mark = REG_RD(bp, addr);
738
mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
739
+ ((mark + 0x3) & ~0x3) - 0x08000000;
740
printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
743
for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
744
for (word = 0; word < 8; word++)
745
data[word] = htonl(REG_RD(bp, offset + 4*word));
747
pr_cont("%s", (char *)data);
749
for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
750
for (word = 0; word < 8; word++)
751
data[word] = htonl(REG_RD(bp, offset + 4*word));
753
pr_cont("%s", (char *)data);
755
printk("%s" "end of fw dump\n", lvl);
758
static inline void bnx2x_fw_dump(struct bnx2x *bp)
760
bnx2x_fw_dump_lvl(bp, KERN_ERR);
763
void bnx2x_panic_dump(struct bnx2x *bp)
767
struct hc_sp_status_block_data sp_sb_data;
768
int func = BP_FUNC(bp);
769
#ifdef BNX2X_STOP_ON_ERROR
770
u16 start = 0, end = 0;
774
bp->stats_state = STATS_STATE_DISABLED;
775
DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
777
BNX2X_ERR("begin crash dump -----------------\n");
781
BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
782
" spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
783
bp->def_idx, bp->def_att_idx, bp->attn_state,
784
bp->spq_prod_idx, bp->stats_counter);
785
BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
786
bp->def_status_blk->atten_status_block.attn_bits,
787
bp->def_status_blk->atten_status_block.attn_bits_ack,
788
bp->def_status_blk->atten_status_block.status_block_id,
789
bp->def_status_blk->atten_status_block.attn_bits_index);
791
for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
793
bp->def_status_blk->sp_sb.index_values[i],
794
(i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
796
for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
797
*((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
798
CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
801
pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
802
sp_sb_data.igu_sb_id,
803
sp_sb_data.igu_seg_id,
804
sp_sb_data.p_func.pf_id,
805
sp_sb_data.p_func.vnic_id,
806
sp_sb_data.p_func.vf_id,
807
sp_sb_data.p_func.vf_valid,
811
for_each_eth_queue(bp, i) {
812
struct bnx2x_fastpath *fp = &bp->fp[i];
814
struct hc_status_block_data_e2 sb_data_e2;
815
struct hc_status_block_data_e1x sb_data_e1x;
816
struct hc_status_block_sm *hc_sm_p =
818
sb_data_e1x.common.state_machine :
819
sb_data_e2.common.state_machine;
820
struct hc_index_data *hc_index_p =
822
sb_data_e1x.index_data :
823
sb_data_e2.index_data;
826
struct bnx2x_fp_txdata txdata;
829
BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
830
" rx_comp_prod(0x%x)"
831
" rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
832
i, fp->rx_bd_prod, fp->rx_bd_cons,
834
fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
835
BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
836
" fp_hc_idx(0x%x)\n",
837
fp->rx_sge_prod, fp->last_max_sge,
838
le16_to_cpu(fp->fp_hc_idx));
841
for_each_cos_in_tx_queue(fp, cos)
843
txdata = fp->txdata[cos];
844
BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
845
" tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
846
" *tx_cons_sb(0x%x)\n",
847
i, txdata.tx_pkt_prod,
848
txdata.tx_pkt_cons, txdata.tx_bd_prod,
850
le16_to_cpu(*txdata.tx_cons_sb));
853
loop = CHIP_IS_E1x(bp) ?
854
HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
862
BNX2X_ERR(" run indexes (");
863
for (j = 0; j < HC_SB_MAX_SM; j++)
865
fp->sb_running_index[j],
866
(j == HC_SB_MAX_SM - 1) ? ")" : " ");
868
BNX2X_ERR(" indexes (");
869
for (j = 0; j < loop; j++)
871
fp->sb_index_values[j],
872
(j == loop - 1) ? ")" : " ");
874
data_size = CHIP_IS_E1x(bp) ?
875
sizeof(struct hc_status_block_data_e1x) :
876
sizeof(struct hc_status_block_data_e2);
877
data_size /= sizeof(u32);
878
sb_data_p = CHIP_IS_E1x(bp) ?
879
(u32 *)&sb_data_e1x :
881
/* copy sb data in here */
882
for (j = 0; j < data_size; j++)
883
*(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
884
CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
887
if (!CHIP_IS_E1x(bp)) {
888
pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
889
"vnic_id(0x%x) same_igu_sb_1b(0x%x) "
891
sb_data_e2.common.p_func.pf_id,
892
sb_data_e2.common.p_func.vf_id,
893
sb_data_e2.common.p_func.vf_valid,
894
sb_data_e2.common.p_func.vnic_id,
895
sb_data_e2.common.same_igu_sb_1b,
896
sb_data_e2.common.state);
898
pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
899
"vnic_id(0x%x) same_igu_sb_1b(0x%x) "
901
sb_data_e1x.common.p_func.pf_id,
902
sb_data_e1x.common.p_func.vf_id,
903
sb_data_e1x.common.p_func.vf_valid,
904
sb_data_e1x.common.p_func.vnic_id,
905
sb_data_e1x.common.same_igu_sb_1b,
906
sb_data_e1x.common.state);
910
for (j = 0; j < HC_SB_MAX_SM; j++) {
911
pr_cont("SM[%d] __flags (0x%x) "
912
"igu_sb_id (0x%x) igu_seg_id(0x%x) "
913
"time_to_expire (0x%x) "
914
"timer_value(0x%x)\n", j,
916
hc_sm_p[j].igu_sb_id,
917
hc_sm_p[j].igu_seg_id,
918
hc_sm_p[j].time_to_expire,
919
hc_sm_p[j].timer_value);
923
for (j = 0; j < loop; j++) {
924
pr_cont("INDEX[%d] flags (0x%x) "
925
"timeout (0x%x)\n", j,
927
hc_index_p[j].timeout);
931
#ifdef BNX2X_STOP_ON_ERROR
934
for_each_rx_queue(bp, i) {
935
struct bnx2x_fastpath *fp = &bp->fp[i];
937
start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
938
end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
939
for (j = start; j != end; j = RX_BD(j + 1)) {
940
u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
941
struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
943
BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
944
i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
947
start = RX_SGE(fp->rx_sge_prod);
948
end = RX_SGE(fp->last_max_sge);
949
for (j = start; j != end; j = RX_SGE(j + 1)) {
950
u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
951
struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
953
BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
954
i, j, rx_sge[1], rx_sge[0], sw_page->page);
957
start = RCQ_BD(fp->rx_comp_cons - 10);
958
end = RCQ_BD(fp->rx_comp_cons + 503);
959
for (j = start; j != end; j = RCQ_BD(j + 1)) {
960
u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
962
BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
963
i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
968
for_each_tx_queue(bp, i) {
969
struct bnx2x_fastpath *fp = &bp->fp[i];
970
for_each_cos_in_tx_queue(fp, cos) {
971
struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
973
start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
974
end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
975
for (j = start; j != end; j = TX_BD(j + 1)) {
976
struct sw_tx_bd *sw_bd =
977
&txdata->tx_buf_ring[j];
979
BNX2X_ERR("fp%d: txdata %d, "
980
"packet[%x]=[%p,%x]\n",
981
i, cos, j, sw_bd->skb,
985
start = TX_BD(txdata->tx_bd_cons - 10);
986
end = TX_BD(txdata->tx_bd_cons + 254);
987
for (j = start; j != end; j = TX_BD(j + 1)) {
988
u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
990
BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
992
i, cos, j, tx_bd[0], tx_bd[1],
1000
BNX2X_ERR("end crash dump -----------------\n");
1004
* FLR Support for E2
1006
* bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1009
#define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1010
#define FLR_WAIT_INTERAVAL 50 /* usec */
1011
#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1013
struct pbf_pN_buf_regs {
1020
struct pbf_pN_cmd_regs {
1026
static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1027
struct pbf_pN_buf_regs *regs,
1030
u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1031
u32 cur_cnt = poll_count;
1033
crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1034
crd = crd_start = REG_RD(bp, regs->crd);
1035
init_crd = REG_RD(bp, regs->init_crd);
1037
DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1038
DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1039
DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1041
while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1042
(init_crd - crd_start))) {
1044
udelay(FLR_WAIT_INTERAVAL);
1045
crd = REG_RD(bp, regs->crd);
1046
crd_freed = REG_RD(bp, regs->crd_freed);
1048
DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1050
DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1052
DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1053
regs->pN, crd_freed);
1057
DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1058
poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1061
static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1062
struct pbf_pN_cmd_regs *regs,
1065
u32 occup, to_free, freed, freed_start;
1066
u32 cur_cnt = poll_count;
1068
occup = to_free = REG_RD(bp, regs->lines_occup);
1069
freed = freed_start = REG_RD(bp, regs->lines_freed);
1071
DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1072
DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1074
while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1076
udelay(FLR_WAIT_INTERAVAL);
1077
occup = REG_RD(bp, regs->lines_occup);
1078
freed = REG_RD(bp, regs->lines_freed);
1080
DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1082
DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1084
DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1089
DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1090
poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1093
static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1094
u32 expected, u32 poll_count)
1096
u32 cur_cnt = poll_count;
1099
while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1100
udelay(FLR_WAIT_INTERAVAL);
1105
static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1106
char *msg, u32 poll_cnt)
1108
u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1110
BNX2X_ERR("%s usage count=%d\n", msg, val);
1116
static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1118
/* adjust polling timeout */
1119
if (CHIP_REV_IS_EMUL(bp))
1120
return FLR_POLL_CNT * 2000;
1122
if (CHIP_REV_IS_FPGA(bp))
1123
return FLR_POLL_CNT * 120;
1125
return FLR_POLL_CNT;
1128
static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1130
struct pbf_pN_cmd_regs cmd_regs[] = {
1131
{0, (CHIP_IS_E3B0(bp)) ?
1132
PBF_REG_TQ_OCCUPANCY_Q0 :
1133
PBF_REG_P0_TQ_OCCUPANCY,
1134
(CHIP_IS_E3B0(bp)) ?
1135
PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1136
PBF_REG_P0_TQ_LINES_FREED_CNT},
1137
{1, (CHIP_IS_E3B0(bp)) ?
1138
PBF_REG_TQ_OCCUPANCY_Q1 :
1139
PBF_REG_P1_TQ_OCCUPANCY,
1140
(CHIP_IS_E3B0(bp)) ?
1141
PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1142
PBF_REG_P1_TQ_LINES_FREED_CNT},
1143
{4, (CHIP_IS_E3B0(bp)) ?
1144
PBF_REG_TQ_OCCUPANCY_LB_Q :
1145
PBF_REG_P4_TQ_OCCUPANCY,
1146
(CHIP_IS_E3B0(bp)) ?
1147
PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1148
PBF_REG_P4_TQ_LINES_FREED_CNT}
1151
struct pbf_pN_buf_regs buf_regs[] = {
1152
{0, (CHIP_IS_E3B0(bp)) ?
1153
PBF_REG_INIT_CRD_Q0 :
1154
PBF_REG_P0_INIT_CRD ,
1155
(CHIP_IS_E3B0(bp)) ?
1158
(CHIP_IS_E3B0(bp)) ?
1159
PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1160
PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1161
{1, (CHIP_IS_E3B0(bp)) ?
1162
PBF_REG_INIT_CRD_Q1 :
1163
PBF_REG_P1_INIT_CRD,
1164
(CHIP_IS_E3B0(bp)) ?
1167
(CHIP_IS_E3B0(bp)) ?
1168
PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1169
PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1170
{4, (CHIP_IS_E3B0(bp)) ?
1171
PBF_REG_INIT_CRD_LB_Q :
1172
PBF_REG_P4_INIT_CRD,
1173
(CHIP_IS_E3B0(bp)) ?
1174
PBF_REG_CREDIT_LB_Q :
1176
(CHIP_IS_E3B0(bp)) ?
1177
PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1178
PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1183
/* Verify the command queues are flushed P0, P1, P4 */
1184
for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1185
bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1188
/* Verify the transmission buffers are flushed P0, P1, P4 */
1189
for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1190
bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1193
#define OP_GEN_PARAM(param) \
1194
(((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1196
#define OP_GEN_TYPE(type) \
1197
(((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1199
#define OP_GEN_AGG_VECT(index) \
1200
(((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1203
static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1206
struct sdm_op_gen op_gen = {0};
1208
u32 comp_addr = BAR_CSTRORM_INTMEM +
1209
CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1212
if (REG_RD(bp, comp_addr)) {
1213
BNX2X_ERR("Cleanup complete is not 0\n");
1217
op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1218
op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1219
op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1220
op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1222
DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1223
REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1225
if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1226
BNX2X_ERR("FW final cleanup did not succeed\n");
1229
/* Zero completion for nxt FLR */
1230
REG_WR(bp, comp_addr, 0);
1235
static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1240
pos = pci_pcie_cap(dev);
1244
pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1245
return status & PCI_EXP_DEVSTA_TRPND;
1248
/* PF FLR specific routines
1250
static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1253
/* wait for CFC PF usage-counter to zero (includes all the VFs) */
1254
if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255
CFC_REG_NUM_LCIDS_INSIDE_PF,
1256
"CFC PF usage counter timed out",
1261
/* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1262
if (bnx2x_flr_clnup_poll_hw_counter(bp,
1263
DORQ_REG_PF_USAGE_CNT,
1264
"DQ PF usage counter timed out",
1268
/* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1269
if (bnx2x_flr_clnup_poll_hw_counter(bp,
1270
QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1271
"QM PF usage counter timed out",
1275
/* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1276
if (bnx2x_flr_clnup_poll_hw_counter(bp,
1277
TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1278
"Timers VNIC usage counter timed out",
1281
if (bnx2x_flr_clnup_poll_hw_counter(bp,
1282
TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1283
"Timers NUM_SCANS usage counter timed out",
1287
/* Wait DMAE PF usage counter to zero */
1288
if (bnx2x_flr_clnup_poll_hw_counter(bp,
1289
dmae_reg_go_c[INIT_DMAE_C(bp)],
1290
"DMAE dommand register timed out",
1297
static void bnx2x_hw_enable_status(struct bnx2x *bp)
1301
val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1302
DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1304
val = REG_RD(bp, PBF_REG_DISABLE_PF);
1305
DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1307
val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1308
DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1310
val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1311
DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1313
val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1314
DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1316
val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1317
DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1319
val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1320
DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1322
val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1323
DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1327
static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1329
u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1331
DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1333
/* Re-enable PF target read access */
1334
REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1336
/* Poll HW usage counters */
1337
if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1340
/* Zero the igu 'trailing edge' and 'leading edge' */
1342
/* Send the FW cleanup command */
1343
if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1348
/* Verify TX hw is flushed */
1349
bnx2x_tx_hw_flushed(bp, poll_cnt);
1351
/* Wait 100ms (not adjusted according to platform) */
1354
/* Verify no pending pci transactions */
1355
if (bnx2x_is_pcie_pending(bp->pdev))
1356
BNX2X_ERR("PCIE Transactions still pending\n");
1359
bnx2x_hw_enable_status(bp);
1362
* Master enable - Due to WB DMAE writes performed before this
1363
* register is re-initialized as part of the regular function init
1365
REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1370
static void bnx2x_hc_int_enable(struct bnx2x *bp)
1372
int port = BP_PORT(bp);
1373
u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1374
u32 val = REG_RD(bp, addr);
1375
int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1376
int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1379
val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1380
HC_CONFIG_0_REG_INT_LINE_EN_0);
1381
val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1382
HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1384
val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1385
val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1386
HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1387
HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1389
val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1390
HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1391
HC_CONFIG_0_REG_INT_LINE_EN_0 |
1392
HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1394
if (!CHIP_IS_E1(bp)) {
1395
DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1398
REG_WR(bp, addr, val);
1400
val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1405
REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1407
DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1408
val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1410
REG_WR(bp, addr, val);
1412
* Ensure that HC_CONFIG is written before leading/trailing edge config
1417
if (!CHIP_IS_E1(bp)) {
1418
/* init leading/trailing edge */
1420
val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1422
/* enable nig and gpio3 attention */
1427
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1428
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1431
/* Make sure that interrupts are indeed enabled from here on */
1435
static void bnx2x_igu_int_enable(struct bnx2x *bp)
1438
int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1439
int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1441
val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1444
val &= ~(IGU_PF_CONF_INT_LINE_EN |
1445
IGU_PF_CONF_SINGLE_ISR_EN);
1446
val |= (IGU_PF_CONF_FUNC_EN |
1447
IGU_PF_CONF_MSI_MSIX_EN |
1448
IGU_PF_CONF_ATTN_BIT_EN);
1450
val &= ~IGU_PF_CONF_INT_LINE_EN;
1451
val |= (IGU_PF_CONF_FUNC_EN |
1452
IGU_PF_CONF_MSI_MSIX_EN |
1453
IGU_PF_CONF_ATTN_BIT_EN |
1454
IGU_PF_CONF_SINGLE_ISR_EN);
1456
val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1457
val |= (IGU_PF_CONF_FUNC_EN |
1458
IGU_PF_CONF_INT_LINE_EN |
1459
IGU_PF_CONF_ATTN_BIT_EN |
1460
IGU_PF_CONF_SINGLE_ISR_EN);
1463
DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1464
val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1466
REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1470
/* init leading/trailing edge */
1472
val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1474
/* enable nig and gpio3 attention */
1479
REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1480
REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1482
/* Make sure that interrupts are indeed enabled from here on */
1486
void bnx2x_int_enable(struct bnx2x *bp)
1488
if (bp->common.int_block == INT_BLOCK_HC)
1489
bnx2x_hc_int_enable(bp);
1491
bnx2x_igu_int_enable(bp);
1494
static void bnx2x_hc_int_disable(struct bnx2x *bp)
1496
int port = BP_PORT(bp);
1497
u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1498
u32 val = REG_RD(bp, addr);
1501
* in E1 we must use only PCI configuration space to disable
1502
* MSI/MSIX capablility
1503
* It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1505
if (CHIP_IS_E1(bp)) {
1506
/* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1507
* Use mask register to prevent from HC sending interrupts
1508
* after we exit the function
1510
REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1512
val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1513
HC_CONFIG_0_REG_INT_LINE_EN_0 |
1514
HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1516
val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1517
HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1518
HC_CONFIG_0_REG_INT_LINE_EN_0 |
1519
HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1521
DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1524
/* flush all outstanding writes */
1527
REG_WR(bp, addr, val);
1528
if (REG_RD(bp, addr) != val)
1529
BNX2X_ERR("BUG! proper val not read from IGU!\n");
1532
static void bnx2x_igu_int_disable(struct bnx2x *bp)
1534
u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1536
val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1537
IGU_PF_CONF_INT_LINE_EN |
1538
IGU_PF_CONF_ATTN_BIT_EN);
1540
DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1542
/* flush all outstanding writes */
1545
REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1546
if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1547
BNX2X_ERR("BUG! proper val not read from IGU!\n");
1550
void bnx2x_int_disable(struct bnx2x *bp)
1552
if (bp->common.int_block == INT_BLOCK_HC)
1553
bnx2x_hc_int_disable(bp);
1555
bnx2x_igu_int_disable(bp);
1558
void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1560
int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1564
/* prevent the HW from sending interrupts */
1565
bnx2x_int_disable(bp);
1567
/* make sure all ISRs are done */
1569
synchronize_irq(bp->msix_table[0].vector);
1574
for_each_eth_queue(bp, i)
1575
synchronize_irq(bp->msix_table[offset++].vector);
1577
synchronize_irq(bp->pdev->irq);
1579
/* make sure sp_task is not running */
1580
cancel_delayed_work(&bp->sp_task);
1581
cancel_delayed_work(&bp->period_task);
1582
flush_workqueue(bnx2x_wq);
1588
* General service functions
1591
/* Return true if succeeded to acquire the lock */
1592
static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1595
u32 resource_bit = (1 << resource);
1596
int func = BP_FUNC(bp);
1597
u32 hw_lock_control_reg;
1599
DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1601
/* Validating that the resource is within range */
1602
if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1604
"resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1605
resource, HW_LOCK_MAX_RESOURCE_VALUE);
1610
hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1612
hw_lock_control_reg =
1613
(MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1615
/* Try to acquire the lock */
1616
REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1617
lock_status = REG_RD(bp, hw_lock_control_reg);
1618
if (lock_status & resource_bit)
1621
DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1626
* bnx2x_get_leader_lock_resource - get the recovery leader resource id
1628
* @bp: driver handle
1630
* Returns the recovery leader resource id according to the engine this function
1631
* belongs to. Currently only only 2 engines is supported.
1633
static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1636
return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1638
return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1642
* bnx2x_trylock_leader_lock- try to aquire a leader lock.
1644
* @bp: driver handle
1646
* Tries to aquire a leader lock for cuurent engine.
1648
static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1650
return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1654
static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1657
void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1659
struct bnx2x *bp = fp->bp;
1660
int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1661
int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1662
enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1663
struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1666
"fp %d cid %d got ramrod #%d state is %x type is %d\n",
1667
fp->index, cid, command, bp->state,
1668
rr_cqe->ramrod_cqe.ramrod_type);
1671
case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1672
DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1673
drv_cmd = BNX2X_Q_CMD_UPDATE;
1676
case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1677
DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1678
drv_cmd = BNX2X_Q_CMD_SETUP;
1681
case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1682
DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1683
drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1686
case (RAMROD_CMD_ID_ETH_HALT):
1687
DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1688
drv_cmd = BNX2X_Q_CMD_HALT;
1691
case (RAMROD_CMD_ID_ETH_TERMINATE):
1692
DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1693
drv_cmd = BNX2X_Q_CMD_TERMINATE;
1696
case (RAMROD_CMD_ID_ETH_EMPTY):
1697
DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1698
drv_cmd = BNX2X_Q_CMD_EMPTY;
1702
BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1703
command, fp->index);
1707
if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1708
q_obj->complete_cmd(bp, q_obj, drv_cmd))
1709
/* q_obj->complete_cmd() failure means that this was
1710
* an unexpected completion.
1712
* In this case we don't want to increase the bp->spq_left
1713
* because apparently we haven't sent this command the first
1716
#ifdef BNX2X_STOP_ON_ERROR
1722
smp_mb__before_atomic_inc();
1723
atomic_inc(&bp->cq_spq_left);
1724
/* push the change in bp->spq_left and towards the memory */
1725
smp_mb__after_atomic_inc();
1727
DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1732
void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1733
u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1735
u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1737
bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1741
irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1743
struct bnx2x *bp = netdev_priv(dev_instance);
1744
u16 status = bnx2x_ack_int(bp);
1749
/* Return here if interrupt is shared and it's not for us */
1750
if (unlikely(status == 0)) {
1751
DP(NETIF_MSG_INTR, "not our interrupt!\n");
1754
DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1756
#ifdef BNX2X_STOP_ON_ERROR
1757
if (unlikely(bp->panic))
1761
for_each_eth_queue(bp, i) {
1762
struct bnx2x_fastpath *fp = &bp->fp[i];
1764
mask = 0x2 << (fp->index + CNIC_PRESENT);
1765
if (status & mask) {
1766
/* Handle Rx or Tx according to SB id */
1767
prefetch(fp->rx_cons_sb);
1768
for_each_cos_in_tx_queue(fp, cos)
1769
prefetch(fp->txdata[cos].tx_cons_sb);
1770
prefetch(&fp->sb_running_index[SM_RX_ID]);
1771
napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1778
if (status & (mask | 0x1)) {
1779
struct cnic_ops *c_ops = NULL;
1781
if (likely(bp->state == BNX2X_STATE_OPEN)) {
1783
c_ops = rcu_dereference(bp->cnic_ops);
1785
c_ops->cnic_handler(bp->cnic_data, NULL);
1793
if (unlikely(status & 0x1)) {
1794
queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1801
if (unlikely(status))
1802
DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1811
* General service functions
1814
int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1817
u32 resource_bit = (1 << resource);
1818
int func = BP_FUNC(bp);
1819
u32 hw_lock_control_reg;
1822
/* Validating that the resource is within range */
1823
if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1825
"resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1826
resource, HW_LOCK_MAX_RESOURCE_VALUE);
1831
hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1833
hw_lock_control_reg =
1834
(MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1837
/* Validating that the resource is not already taken */
1838
lock_status = REG_RD(bp, hw_lock_control_reg);
1839
if (lock_status & resource_bit) {
1840
DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1841
lock_status, resource_bit);
1845
/* Try for 5 second every 5ms */
1846
for (cnt = 0; cnt < 1000; cnt++) {
1847
/* Try to acquire the lock */
1848
REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1849
lock_status = REG_RD(bp, hw_lock_control_reg);
1850
if (lock_status & resource_bit)
1855
DP(NETIF_MSG_HW, "Timeout\n");
1859
int bnx2x_release_leader_lock(struct bnx2x *bp)
1861
return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1864
int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1867
u32 resource_bit = (1 << resource);
1868
int func = BP_FUNC(bp);
1869
u32 hw_lock_control_reg;
1871
DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1873
/* Validating that the resource is within range */
1874
if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1876
"resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1877
resource, HW_LOCK_MAX_RESOURCE_VALUE);
1882
hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1884
hw_lock_control_reg =
1885
(MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1888
/* Validating that the resource is currently taken */
1889
lock_status = REG_RD(bp, hw_lock_control_reg);
1890
if (!(lock_status & resource_bit)) {
1891
DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1892
lock_status, resource_bit);
1896
REG_WR(bp, hw_lock_control_reg, resource_bit);
1901
int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1903
/* The GPIO should be swapped if swap register is set and active */
1904
int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1905
REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1906
int gpio_shift = gpio_num +
1907
(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1908
u32 gpio_mask = (1 << gpio_shift);
1912
if (gpio_num > MISC_REGISTERS_GPIO_3) {
1913
BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1917
/* read GPIO value */
1918
gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1920
/* get the requested pin value */
1921
if ((gpio_reg & gpio_mask) == gpio_mask)
1926
DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1931
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1933
/* The GPIO should be swapped if swap register is set and active */
1934
int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1935
REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1936
int gpio_shift = gpio_num +
1937
(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1938
u32 gpio_mask = (1 << gpio_shift);
1941
if (gpio_num > MISC_REGISTERS_GPIO_3) {
1942
BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1946
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1947
/* read GPIO and mask except the float bits */
1948
gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1951
case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1952
DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1953
gpio_num, gpio_shift);
1954
/* clear FLOAT and set CLR */
1955
gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1956
gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1959
case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1960
DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1961
gpio_num, gpio_shift);
1962
/* clear FLOAT and set SET */
1963
gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1964
gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1967
case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1968
DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1969
gpio_num, gpio_shift);
1971
gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1978
REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1979
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1984
int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1989
/* Any port swapping should be handled by caller. */
1991
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1992
/* read GPIO and mask except the float bits */
1993
gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1994
gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1995
gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1996
gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1999
case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2000
DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2002
gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2005
case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2006
DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2008
gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2011
case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2012
DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2014
gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2018
BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2024
REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2026
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2031
int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2033
/* The GPIO should be swapped if swap register is set and active */
2034
int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2035
REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2036
int gpio_shift = gpio_num +
2037
(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2038
u32 gpio_mask = (1 << gpio_shift);
2041
if (gpio_num > MISC_REGISTERS_GPIO_3) {
2042
BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2046
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2048
gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2051
case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2052
DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2053
"output low\n", gpio_num, gpio_shift);
2054
/* clear SET and set CLR */
2055
gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2056
gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2059
case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2060
DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2061
"output high\n", gpio_num, gpio_shift);
2062
/* clear CLR and set SET */
2063
gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2064
gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2071
REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2072
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2077
static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2079
u32 spio_mask = (1 << spio_num);
2082
if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2083
(spio_num > MISC_REGISTERS_SPIO_7)) {
2084
BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2088
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2089
/* read SPIO and mask except the float bits */
2090
spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2093
case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2094
DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2095
/* clear FLOAT and set CLR */
2096
spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2097
spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2100
case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2101
DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2102
/* clear FLOAT and set SET */
2103
spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2104
spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2107
case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2108
DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2110
spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2117
REG_WR(bp, MISC_REG_SPIO, spio_reg);
2118
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2123
void bnx2x_calc_fc_adv(struct bnx2x *bp)
2125
u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2126
switch (bp->link_vars.ieee_fc &
2127
MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2128
case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2129
bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2133
case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2134
bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2138
case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2139
bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2143
bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2149
u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2151
if (!BP_NOMCP(bp)) {
2153
int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2154
u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2156
* Initialize link parameters structure variables
2157
* It is recommended to turn off RX FC for jumbo frames
2158
* for better performance
2160
if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2161
bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2163
bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2165
bnx2x_acquire_phy_lock(bp);
2167
if (load_mode == LOAD_DIAG) {
2168
struct link_params *lp = &bp->link_params;
2169
lp->loopback_mode = LOOPBACK_XGXS;
2170
/* do PHY loopback at 10G speed, if possible */
2171
if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2172
if (lp->speed_cap_mask[cfx_idx] &
2173
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2174
lp->req_line_speed[cfx_idx] =
2177
lp->req_line_speed[cfx_idx] =
2182
rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2184
bnx2x_release_phy_lock(bp);
2186
bnx2x_calc_fc_adv(bp);
2188
if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2189
bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2190
bnx2x_link_report(bp);
2192
queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2193
bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2196
BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2200
void bnx2x_link_set(struct bnx2x *bp)
2202
if (!BP_NOMCP(bp)) {
2203
bnx2x_acquire_phy_lock(bp);
2204
bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2205
bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2206
bnx2x_release_phy_lock(bp);
2208
bnx2x_calc_fc_adv(bp);
2210
BNX2X_ERR("Bootcode is missing - can not set link\n");
2213
static void bnx2x__link_reset(struct bnx2x *bp)
2215
if (!BP_NOMCP(bp)) {
2216
bnx2x_acquire_phy_lock(bp);
2217
bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2218
bnx2x_release_phy_lock(bp);
2220
BNX2X_ERR("Bootcode is missing - can not reset link\n");
2223
u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2227
if (!BP_NOMCP(bp)) {
2228
bnx2x_acquire_phy_lock(bp);
2229
rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2231
bnx2x_release_phy_lock(bp);
2233
BNX2X_ERR("Bootcode is missing - can not test link\n");
2238
static void bnx2x_init_port_minmax(struct bnx2x *bp)
2240
u32 r_param = bp->link_vars.line_speed / 8;
2241
u32 fair_periodic_timeout_usec;
2244
memset(&(bp->cmng.rs_vars), 0,
2245
sizeof(struct rate_shaping_vars_per_port));
2246
memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2248
/* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2249
bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2251
/* this is the threshold below which no timer arming will occur
2252
1.25 coefficient is for the threshold to be a little bigger
2253
than the real time, to compensate for timer in-accuracy */
2254
bp->cmng.rs_vars.rs_threshold =
2255
(RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2257
/* resolution of fairness timer */
2258
fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2259
/* for 10G it is 1000usec. for 1G it is 10000usec. */
2260
t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2262
/* this is the threshold below which we won't arm the timer anymore */
2263
bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2265
/* we multiply by 1e3/8 to get bytes/msec.
2266
We don't want the credits to pass a credit
2267
of the t_fair*FAIR_MEM (algorithm resolution) */
2268
bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2269
/* since each tick is 4 usec */
2270
bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2273
/* Calculates the sum of vn_min_rates.
2274
It's needed for further normalizing of the min_rates.
2276
sum of vn_min_rates.
2278
0 - if all the min_rates are 0.
2279
In the later case fainess algorithm should be deactivated.
2280
If not all min_rates are zero then those that are zeroes will be set to 1.
2282
static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2287
bp->vn_weight_sum = 0;
2288
for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2289
u32 vn_cfg = bp->mf_config[vn];
2290
u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2291
FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2293
/* Skip hidden vns */
2294
if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2297
/* If min rate is zero - set it to 1 */
2299
vn_min_rate = DEF_MIN_RATE;
2303
bp->vn_weight_sum += vn_min_rate;
2306
/* if ETS or all min rates are zeros - disable fairness */
2307
if (BNX2X_IS_ETS_ENABLED(bp)) {
2308
bp->cmng.flags.cmng_enables &=
2309
~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2310
DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2311
} else if (all_zero) {
2312
bp->cmng.flags.cmng_enables &=
2313
~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2314
DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2315
" fairness will be disabled\n");
2317
bp->cmng.flags.cmng_enables |=
2318
CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2321
/* returns func by VN for current port */
2322
static inline int func_by_vn(struct bnx2x *bp, int vn)
2324
return 2 * vn + BP_PORT(bp);
2327
static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2329
struct rate_shaping_vars_per_vn m_rs_vn;
2330
struct fairness_vars_per_vn m_fair_vn;
2331
u32 vn_cfg = bp->mf_config[vn];
2332
int func = func_by_vn(bp, vn);
2333
u16 vn_min_rate, vn_max_rate;
2336
/* If function is hidden - set min and max to zeroes */
2337
if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2342
u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2344
vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2345
FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2346
/* If fairness is enabled (not all min rates are zeroes) and
2347
if current min rate is zero - set it to 1.
2348
This is a requirement of the algorithm. */
2349
if (bp->vn_weight_sum && (vn_min_rate == 0))
2350
vn_min_rate = DEF_MIN_RATE;
2353
/* maxCfg in percents of linkspeed */
2354
vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2356
/* maxCfg is absolute in 100Mb units */
2357
vn_max_rate = maxCfg * 100;
2361
"func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2362
func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2364
memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2365
memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2367
/* global vn counter - maximal Mbps for this vn */
2368
m_rs_vn.vn_counter.rate = vn_max_rate;
2370
/* quota - number of bytes transmitted in this period */
2371
m_rs_vn.vn_counter.quota =
2372
(vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2374
if (bp->vn_weight_sum) {
2375
/* credit for each period of the fairness algorithm:
2376
number of bytes in T_FAIR (the vn share the port rate).
2377
vn_weight_sum should not be larger than 10000, thus
2378
T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2380
m_fair_vn.vn_credit_delta =
2381
max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2382
(8 * bp->vn_weight_sum))),
2383
(bp->cmng.fair_vars.fair_threshold +
2385
DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2386
m_fair_vn.vn_credit_delta);
2389
/* Store it to internal memory */
2390
for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2391
REG_WR(bp, BAR_XSTRORM_INTMEM +
2392
XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2393
((u32 *)(&m_rs_vn))[i]);
2395
for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2396
REG_WR(bp, BAR_XSTRORM_INTMEM +
2397
XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2398
((u32 *)(&m_fair_vn))[i]);
2401
static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2403
if (CHIP_REV_IS_SLOW(bp))
2404
return CMNG_FNS_NONE;
2406
return CMNG_FNS_MINMAX;
2408
return CMNG_FNS_NONE;
2411
void bnx2x_read_mf_cfg(struct bnx2x *bp)
2413
int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2416
return; /* what should be the default bvalue in this case */
2418
/* For 2 port configuration the absolute function number formula
2420
* abs_func = 2 * vn + BP_PORT + BP_PATH
2422
* and there are 4 functions per port
2424
* For 4 port configuration it is
2425
* abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2427
* and there are 2 functions per port
2429
for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2430
int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2432
if (func >= E1H_FUNC_MAX)
2436
MF_CFG_RD(bp, func_mf_config[func].config);
2440
static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2443
if (cmng_type == CMNG_FNS_MINMAX) {
2446
/* clear cmng_enables */
2447
bp->cmng.flags.cmng_enables = 0;
2449
/* read mf conf from shmem */
2451
bnx2x_read_mf_cfg(bp);
2453
/* Init rate shaping and fairness contexts */
2454
bnx2x_init_port_minmax(bp);
2456
/* vn_weight_sum and enable fairness if not 0 */
2457
bnx2x_calc_vn_weight_sum(bp);
2459
/* calculate and set min-max rate for each vn */
2461
for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2462
bnx2x_init_vn_minmax(bp, vn);
2464
/* always enable rate shaping and fairness */
2465
bp->cmng.flags.cmng_enables |=
2466
CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2467
if (!bp->vn_weight_sum)
2468
DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2469
" fairness will be disabled\n");
2473
/* rate shaping and fairness are disabled */
2475
"rate shaping and fairness are disabled\n");
2478
static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2483
/* Set the attention towards other drivers on the same port */
2484
for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2485
if (vn == BP_VN(bp))
2488
func = func_by_vn(bp, vn);
2489
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2490
(LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2494
/* This function is called upon link interrupt */
2495
static void bnx2x_link_attn(struct bnx2x *bp)
2497
/* Make sure that we are synced with the current statistics */
2498
bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2500
bnx2x_link_update(&bp->link_params, &bp->link_vars);
2502
if (bp->link_vars.link_up) {
2504
/* dropless flow control */
2505
if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2506
int port = BP_PORT(bp);
2507
u32 pause_enabled = 0;
2509
if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2512
REG_WR(bp, BAR_USTRORM_INTMEM +
2513
USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2517
if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2518
struct host_port_stats *pstats;
2520
pstats = bnx2x_sp(bp, port_stats);
2521
/* reset old mac stats */
2522
memset(&(pstats->mac_stx[0]), 0,
2523
sizeof(struct mac_stx));
2525
if (bp->state == BNX2X_STATE_OPEN)
2526
bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2529
if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2530
int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2532
if (cmng_fns != CMNG_FNS_NONE) {
2533
bnx2x_cmng_fns_init(bp, false, cmng_fns);
2534
storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2536
/* rate shaping and fairness are disabled */
2538
"single function mode without fairness\n");
2541
__bnx2x_link_report(bp);
2544
bnx2x_link_sync_notify(bp);
2547
void bnx2x__link_status_update(struct bnx2x *bp)
2549
if (bp->state != BNX2X_STATE_OPEN)
2552
bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2554
if (bp->link_vars.link_up)
2555
bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2557
bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2559
/* indicate link status */
2560
bnx2x_link_report(bp);
2563
static void bnx2x_pmf_update(struct bnx2x *bp)
2565
int port = BP_PORT(bp);
2569
DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2572
* We need the mb() to ensure the ordering between the writing to
2573
* bp->port.pmf here and reading it from the bnx2x_periodic_task().
2577
/* queue a periodic task */
2578
queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2580
bnx2x_dcbx_pmf_update(bp);
2582
/* enable nig attention */
2583
val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2584
if (bp->common.int_block == INT_BLOCK_HC) {
2585
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2586
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2587
} else if (!CHIP_IS_E1x(bp)) {
2588
REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2589
REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2592
bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2600
* General service functions
2603
/* send the MCP a request, block until there is a reply */
2604
u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2606
int mb_idx = BP_FW_MB_IDX(bp);
2610
u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2612
mutex_lock(&bp->fw_mb_mutex);
2614
SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2615
SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2617
DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2618
(command | seq), param);
2621
/* let the FW do it's magic ... */
2624
rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2626
/* Give the FW up to 5 second (500*10ms) */
2627
} while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2629
DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2630
cnt*delay, rc, seq);
2632
/* is this a reply to our command? */
2633
if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2634
rc &= FW_MSG_CODE_MASK;
2637
BNX2X_ERR("FW failed to respond!\n");
2641
mutex_unlock(&bp->fw_mb_mutex);
2646
static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2649
/* Statistics are not supported for CNIC Clients at the moment */
2656
void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2658
if (CHIP_IS_E1x(bp)) {
2659
struct tstorm_eth_function_common_config tcfg = {0};
2661
storm_memset_func_cfg(bp, &tcfg, p->func_id);
2664
/* Enable the function in the FW */
2665
storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2666
storm_memset_func_en(bp, p->func_id, 1);
2669
if (p->func_flgs & FUNC_FLG_SPQ) {
2670
storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2671
REG_WR(bp, XSEM_REG_FAST_MEMORY +
2672
XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2677
* bnx2x_get_tx_only_flags - Return common flags
2681
* @zero_stats TRUE if statistics zeroing is needed
2683
* Return the flags that are common for the Tx-only and not normal connections.
2685
static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2686
struct bnx2x_fastpath *fp,
2689
unsigned long flags = 0;
2691
/* PF driver will always initialize the Queue to an ACTIVE state */
2692
__set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2694
/* tx only connections collect statistics (on the same index as the
2695
* parent connection). The statistics are zeroed when the parent
2696
* connection is initialized.
2698
if (stat_counter_valid(bp, fp)) {
2699
__set_bit(BNX2X_Q_FLG_STATS, &flags);
2701
__set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2707
static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2708
struct bnx2x_fastpath *fp,
2711
unsigned long flags = 0;
2713
/* calculate other queue flags */
2715
__set_bit(BNX2X_Q_FLG_OV, &flags);
2718
__set_bit(BNX2X_Q_FLG_FCOE, &flags);
2720
if (!fp->disable_tpa) {
2721
__set_bit(BNX2X_Q_FLG_TPA, &flags);
2722
__set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2726
__set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2727
__set_bit(BNX2X_Q_FLG_MCAST, &flags);
2730
/* Always set HW VLAN stripping */
2731
__set_bit(BNX2X_Q_FLG_VLAN, &flags);
2734
return flags | bnx2x_get_common_flags(bp, fp, true);
2737
static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2738
struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2741
gen_init->stat_id = bnx2x_stats_id(fp);
2742
gen_init->spcl_id = fp->cl_id;
2744
/* Always use mini-jumbo MTU for FCoE L2 ring */
2746
gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2748
gen_init->mtu = bp->dev->mtu;
2750
gen_init->cos = cos;
2753
static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2754
struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2755
struct bnx2x_rxq_setup_params *rxq_init)
2759
u16 tpa_agg_size = 0;
2761
if (!fp->disable_tpa) {
2762
pause->sge_th_lo = SGE_TH_LO(bp);
2763
pause->sge_th_hi = SGE_TH_HI(bp);
2765
/* validate SGE ring has enough to cross high threshold */
2766
WARN_ON(bp->dropless_fc &&
2767
pause->sge_th_hi + FW_PREFETCH_CNT >
2768
MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2770
tpa_agg_size = min_t(u32,
2771
(min_t(u32, 8, MAX_SKB_FRAGS) *
2772
SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2773
max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2775
max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2776
(~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2777
sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2781
/* pause - not for e1 */
2782
if (!CHIP_IS_E1(bp)) {
2783
pause->bd_th_lo = BD_TH_LO(bp);
2784
pause->bd_th_hi = BD_TH_HI(bp);
2786
pause->rcq_th_lo = RCQ_TH_LO(bp);
2787
pause->rcq_th_hi = RCQ_TH_HI(bp);
2789
* validate that rings have enough entries to cross
2792
WARN_ON(bp->dropless_fc &&
2793
pause->bd_th_hi + FW_PREFETCH_CNT >
2795
WARN_ON(bp->dropless_fc &&
2796
pause->rcq_th_hi + FW_PREFETCH_CNT >
2797
NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2803
rxq_init->dscr_map = fp->rx_desc_mapping;
2804
rxq_init->sge_map = fp->rx_sge_mapping;
2805
rxq_init->rcq_map = fp->rx_comp_mapping;
2806
rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2808
/* This should be a maximum number of data bytes that may be
2809
* placed on the BD (not including paddings).
2811
rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2812
IP_HEADER_ALIGNMENT_PADDING;
2814
rxq_init->cl_qzone_id = fp->cl_qzone_id;
2815
rxq_init->tpa_agg_sz = tpa_agg_size;
2816
rxq_init->sge_buf_sz = sge_sz;
2817
rxq_init->max_sges_pkt = max_sge;
2818
rxq_init->rss_engine_id = BP_FUNC(bp);
2820
/* Maximum number or simultaneous TPA aggregation for this Queue.
2822
* For PF Clients it should be the maximum avaliable number.
2823
* VF driver(s) may want to define it to a smaller value.
2825
rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2827
rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2828
rxq_init->fw_sb_id = fp->fw_sb_id;
2831
rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2833
rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2836
static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2837
struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2840
txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2841
txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2842
txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2843
txq_init->fw_sb_id = fp->fw_sb_id;
2846
* set the tss leading client id for TX classfication ==
2847
* leading RSS client id
2849
txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2851
if (IS_FCOE_FP(fp)) {
2852
txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2853
txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2857
static void bnx2x_pf_init(struct bnx2x *bp)
2859
struct bnx2x_func_init_params func_init = {0};
2860
struct event_ring_data eq_data = { {0} };
2863
if (!CHIP_IS_E1x(bp)) {
2864
/* reset IGU PF statistics: MSIX + ATTN */
2866
REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2867
BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2868
(CHIP_MODE_IS_4_PORT(bp) ?
2869
BP_FUNC(bp) : BP_VN(bp))*4, 0);
2871
REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2872
BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2873
BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2874
(CHIP_MODE_IS_4_PORT(bp) ?
2875
BP_FUNC(bp) : BP_VN(bp))*4, 0);
2878
/* function setup flags */
2879
flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2881
/* This flag is relevant for E1x only.
2882
* E2 doesn't have a TPA configuration in a function level.
2884
flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2886
func_init.func_flgs = flags;
2887
func_init.pf_id = BP_FUNC(bp);
2888
func_init.func_id = BP_FUNC(bp);
2889
func_init.spq_map = bp->spq_mapping;
2890
func_init.spq_prod = bp->spq_prod_idx;
2892
bnx2x_func_init(bp, &func_init);
2894
memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2897
* Congestion management values depend on the link rate
2898
* There is no active link so initial link rate is set to 10 Gbps.
2899
* When the link comes up The congestion management values are
2900
* re-calculated according to the actual link rate.
2902
bp->link_vars.line_speed = SPEED_10000;
2903
bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2905
/* Only the PMF sets the HW */
2907
storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2909
/* init Event Queue */
2910
eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2911
eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2912
eq_data.producer = bp->eq_prod;
2913
eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2914
eq_data.sb_id = DEF_SB_ID;
2915
storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2919
static void bnx2x_e1h_disable(struct bnx2x *bp)
2921
int port = BP_PORT(bp);
2923
bnx2x_tx_disable(bp);
2925
REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2928
static void bnx2x_e1h_enable(struct bnx2x *bp)
2930
int port = BP_PORT(bp);
2932
REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2934
/* Tx queue should be only reenabled */
2935
netif_tx_wake_all_queues(bp->dev);
2938
* Should not call netif_carrier_on since it will be called if the link
2939
* is up when checking for link state
2943
/* called due to MCP event (on pmf):
2944
* reread new bandwidth configuration
2946
* notify others function about the change
2948
static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2950
if (bp->link_vars.link_up) {
2951
bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2952
bnx2x_link_sync_notify(bp);
2954
storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2957
static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2959
bnx2x_config_mf_bw(bp);
2960
bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2963
static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2965
DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2967
if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2970
* This is the only place besides the function initialization
2971
* where the bp->flags can change so it is done without any
2974
if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2975
DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2976
bp->flags |= MF_FUNC_DIS;
2978
bnx2x_e1h_disable(bp);
2980
DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2981
bp->flags &= ~MF_FUNC_DIS;
2983
bnx2x_e1h_enable(bp);
2985
dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2987
if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2988
bnx2x_config_mf_bw(bp);
2989
dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2992
/* Report results to MCP */
2994
bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2996
bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2999
/* must be called under the spq lock */
3000
static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3002
struct eth_spe *next_spe = bp->spq_prod_bd;
3004
if (bp->spq_prod_bd == bp->spq_last_bd) {
3005
bp->spq_prod_bd = bp->spq;
3006
bp->spq_prod_idx = 0;
3007
DP(NETIF_MSG_TIMER, "end of spq\n");
3015
/* must be called under the spq lock */
3016
static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3018
int func = BP_FUNC(bp);
3021
* Make sure that BD data is updated before writing the producer:
3022
* BD data is written to the memory, the producer is read from the
3023
* memory, thus we need a full memory barrier to ensure the ordering.
3027
REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3033
* bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3035
* @cmd: command to check
3036
* @cmd_type: command type
3038
static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3040
if ((cmd_type == NONE_CONNECTION_TYPE) ||
3041
(cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3042
(cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3043
(cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3044
(cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3045
(cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3046
(cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3055
* bnx2x_sp_post - place a single command on an SP ring
3057
* @bp: driver handle
3058
* @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3059
* @cid: SW CID the command is related to
3060
* @data_hi: command private data address (high 32 bits)
3061
* @data_lo: command private data address (low 32 bits)
3062
* @cmd_type: command type (e.g. NONE, ETH)
3064
* SP data is handled as if it's always an address pair, thus data fields are
3065
* not swapped to little endian in upper functions. Instead this function swaps
3066
* data as if it's two u32 fields.
3068
int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3069
u32 data_hi, u32 data_lo, int cmd_type)
3071
struct eth_spe *spe;
3073
bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3075
#ifdef BNX2X_STOP_ON_ERROR
3076
if (unlikely(bp->panic))
3080
spin_lock_bh(&bp->spq_lock);
3083
if (!atomic_read(&bp->eq_spq_left)) {
3084
BNX2X_ERR("BUG! EQ ring full!\n");
3085
spin_unlock_bh(&bp->spq_lock);
3089
} else if (!atomic_read(&bp->cq_spq_left)) {
3090
BNX2X_ERR("BUG! SPQ ring full!\n");
3091
spin_unlock_bh(&bp->spq_lock);
3096
spe = bnx2x_sp_get_next(bp);
3098
/* CID needs port number to be encoded int it */
3099
spe->hdr.conn_and_cmd_data =
3100
cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3103
type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3105
type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3106
SPE_HDR_FUNCTION_ID);
3108
spe->hdr.type = cpu_to_le16(type);
3110
spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3111
spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3114
* It's ok if the actual decrement is issued towards the memory
3115
* somewhere between the spin_lock and spin_unlock. Thus no
3116
* more explict memory barrier is needed.
3119
atomic_dec(&bp->eq_spq_left);
3121
atomic_dec(&bp->cq_spq_left);
3124
DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3125
"SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3126
"type(0x%x) left (CQ, EQ) (%x,%x)\n",
3127
bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3128
(u32)(U64_LO(bp->spq_mapping) +
3129
(void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3130
HW_CID(bp, cid), data_hi, data_lo, type,
3131
atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3133
bnx2x_sp_prod_update(bp);
3134
spin_unlock_bh(&bp->spq_lock);
3138
/* acquire split MCP access lock register */
3139
static int bnx2x_acquire_alr(struct bnx2x *bp)
3145
for (j = 0; j < 1000; j++) {
3147
REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3148
val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3149
if (val & (1L << 31))
3154
if (!(val & (1L << 31))) {
3155
BNX2X_ERR("Cannot acquire MCP access lock register\n");
3162
/* release split MCP access lock register */
3163
static void bnx2x_release_alr(struct bnx2x *bp)
3165
REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3168
#define BNX2X_DEF_SB_ATT_IDX 0x0001
3169
#define BNX2X_DEF_SB_IDX 0x0002
3171
static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3173
struct host_sp_status_block *def_sb = bp->def_status_blk;
3176
barrier(); /* status block is written to by the chip */
3177
if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3178
bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3179
rc |= BNX2X_DEF_SB_ATT_IDX;
3182
if (bp->def_idx != def_sb->sp_sb.running_index) {
3183
bp->def_idx = def_sb->sp_sb.running_index;
3184
rc |= BNX2X_DEF_SB_IDX;
3187
/* Do not reorder: indecies reading should complete before handling */
3193
* slow path service functions
3196
static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3198
int port = BP_PORT(bp);
3199
u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3200
MISC_REG_AEU_MASK_ATTN_FUNC_0;
3201
u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3202
NIG_REG_MASK_INTERRUPT_PORT0;
3207
if (bp->attn_state & asserted)
3208
BNX2X_ERR("IGU ERROR\n");
3210
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3211
aeu_mask = REG_RD(bp, aeu_addr);
3213
DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3214
aeu_mask, asserted);
3215
aeu_mask &= ~(asserted & 0x3ff);
3216
DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3218
REG_WR(bp, aeu_addr, aeu_mask);
3219
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3221
DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3222
bp->attn_state |= asserted;
3223
DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3225
if (asserted & ATTN_HARD_WIRED_MASK) {
3226
if (asserted & ATTN_NIG_FOR_FUNC) {
3228
bnx2x_acquire_phy_lock(bp);
3230
/* save nig interrupt mask */
3231
nig_mask = REG_RD(bp, nig_int_mask_addr);
3233
/* If nig_mask is not set, no need to call the update
3237
REG_WR(bp, nig_int_mask_addr, 0);
3239
bnx2x_link_attn(bp);
3242
/* handle unicore attn? */
3244
if (asserted & ATTN_SW_TIMER_4_FUNC)
3245
DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3247
if (asserted & GPIO_2_FUNC)
3248
DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3250
if (asserted & GPIO_3_FUNC)
3251
DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3253
if (asserted & GPIO_4_FUNC)
3254
DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3257
if (asserted & ATTN_GENERAL_ATTN_1) {
3258
DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3259
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3261
if (asserted & ATTN_GENERAL_ATTN_2) {
3262
DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3263
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3265
if (asserted & ATTN_GENERAL_ATTN_3) {
3266
DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3267
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3270
if (asserted & ATTN_GENERAL_ATTN_4) {
3271
DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3272
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3274
if (asserted & ATTN_GENERAL_ATTN_5) {
3275
DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3276
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3278
if (asserted & ATTN_GENERAL_ATTN_6) {
3279
DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3280
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3284
} /* if hardwired */
3286
if (bp->common.int_block == INT_BLOCK_HC)
3287
reg_addr = (HC_REG_COMMAND_REG + port*32 +
3288
COMMAND_REG_ATTN_BITS_SET);
3290
reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3292
DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3293
(bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3294
REG_WR(bp, reg_addr, asserted);
3296
/* now set back the mask */
3297
if (asserted & ATTN_NIG_FOR_FUNC) {
3298
REG_WR(bp, nig_int_mask_addr, nig_mask);
3299
bnx2x_release_phy_lock(bp);
3303
static inline void bnx2x_fan_failure(struct bnx2x *bp)
3305
int port = BP_PORT(bp);
3307
/* mark the failure */
3310
dev_info.port_hw_config[port].external_phy_config);
3312
ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3313
ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3314
SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3317
/* log the failure */
3318
netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3319
" the driver to shutdown the card to prevent permanent"
3320
" damage. Please contact OEM Support for assistance\n");
3323
static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3325
int port = BP_PORT(bp);
3329
reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3330
MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3332
if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3334
val = REG_RD(bp, reg_offset);
3335
val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3336
REG_WR(bp, reg_offset, val);
3338
BNX2X_ERR("SPIO5 hw attention\n");
3340
/* Fan failure attention */
3341
bnx2x_hw_reset_phy(&bp->link_params);
3342
bnx2x_fan_failure(bp);
3345
if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3346
bnx2x_acquire_phy_lock(bp);
3347
bnx2x_handle_module_detect_int(&bp->link_params);
3348
bnx2x_release_phy_lock(bp);
3351
if (attn & HW_INTERRUT_ASSERT_SET_0) {
3353
val = REG_RD(bp, reg_offset);
3354
val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3355
REG_WR(bp, reg_offset, val);
3357
BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3358
(u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3363
static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3367
if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3369
val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3370
BNX2X_ERR("DB hw attention 0x%x\n", val);
3371
/* DORQ discard attention */
3373
BNX2X_ERR("FATAL error from DORQ\n");
3376
if (attn & HW_INTERRUT_ASSERT_SET_1) {
3378
int port = BP_PORT(bp);
3381
reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3382
MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3384
val = REG_RD(bp, reg_offset);
3385
val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3386
REG_WR(bp, reg_offset, val);
3388
BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3389
(u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3394
static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3398
if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3400
val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3401
BNX2X_ERR("CFC hw attention 0x%x\n", val);
3402
/* CFC error attention */
3404
BNX2X_ERR("FATAL error from CFC\n");
3407
if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3408
val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3409
BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3410
/* RQ_USDMDP_FIFO_OVERFLOW */
3412
BNX2X_ERR("FATAL error from PXP\n");
3414
if (!CHIP_IS_E1x(bp)) {
3415
val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3416
BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3420
if (attn & HW_INTERRUT_ASSERT_SET_2) {
3422
int port = BP_PORT(bp);
3425
reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3426
MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3428
val = REG_RD(bp, reg_offset);
3429
val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3430
REG_WR(bp, reg_offset, val);
3432
BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3433
(u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3438
static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3442
if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3444
if (attn & BNX2X_PMF_LINK_ASSERT) {
3445
int func = BP_FUNC(bp);
3447
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3448
bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3449
func_mf_config[BP_ABS_FUNC(bp)].config);
3451
func_mb[BP_FW_MB_IDX(bp)].drv_status);
3452
if (val & DRV_STATUS_DCC_EVENT_MASK)
3454
(val & DRV_STATUS_DCC_EVENT_MASK));
3456
if (val & DRV_STATUS_SET_MF_BW)
3457
bnx2x_set_mf_bw(bp);
3459
if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3460
bnx2x_pmf_update(bp);
3463
(val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3464
bp->dcbx_enabled > 0)
3465
/* start dcbx state machine */
3466
bnx2x_dcbx_set_params(bp,
3467
BNX2X_DCBX_STATE_NEG_RECEIVED);
3468
if (bp->link_vars.periodic_flags &
3469
PERIODIC_FLAGS_LINK_EVENT) {
3470
/* sync with link */
3471
bnx2x_acquire_phy_lock(bp);
3472
bp->link_vars.periodic_flags &=
3473
~PERIODIC_FLAGS_LINK_EVENT;
3474
bnx2x_release_phy_lock(bp);
3476
bnx2x_link_sync_notify(bp);
3477
bnx2x_link_report(bp);
3479
/* Always call it here: bnx2x_link_report() will
3480
* prevent the link indication duplication.
3482
bnx2x__link_status_update(bp);
3483
} else if (attn & BNX2X_MC_ASSERT_BITS) {
3485
BNX2X_ERR("MC assert!\n");
3486
bnx2x_mc_assert(bp);
3487
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3488
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3489
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3490
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3493
} else if (attn & BNX2X_MCP_ASSERT) {
3495
BNX2X_ERR("MCP assert!\n");
3496
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3500
BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3503
if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3504
BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3505
if (attn & BNX2X_GRC_TIMEOUT) {
3506
val = CHIP_IS_E1(bp) ? 0 :
3507
REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3508
BNX2X_ERR("GRC time-out 0x%08x\n", val);
3510
if (attn & BNX2X_GRC_RSV) {
3511
val = CHIP_IS_E1(bp) ? 0 :
3512
REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3513
BNX2X_ERR("GRC reserved 0x%08x\n", val);
3515
REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3521
* 0-7 - Engine0 load counter.
3522
* 8-15 - Engine1 load counter.
3523
* 16 - Engine0 RESET_IN_PROGRESS bit.
3524
* 17 - Engine1 RESET_IN_PROGRESS bit.
3525
* 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3527
* 19 - Engine1 ONE_IS_LOADED.
3528
* 20 - Chip reset flow bit. When set none-leader must wait for both engines
3529
* leader to complete (check for both RESET_IN_PROGRESS bits and not for
3530
* just the one belonging to its engine).
3533
#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3535
#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3536
#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3537
#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3538
#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3539
#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3540
#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3541
#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3544
* Set the GLOBAL_RESET bit.
3546
* Should be run under rtnl lock
3548
void bnx2x_set_reset_global(struct bnx2x *bp)
3550
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3552
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3558
* Clear the GLOBAL_RESET bit.
3560
* Should be run under rtnl lock
3562
static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3564
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3566
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3572
* Checks the GLOBAL_RESET bit.
3574
* should be run under rtnl lock
3576
static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3578
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3580
DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3581
return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3585
* Clear RESET_IN_PROGRESS bit for the current engine.
3587
* Should be run under rtnl lock
3589
static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3591
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3592
u32 bit = BP_PATH(bp) ?
3593
BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3597
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3603
* Set RESET_IN_PROGRESS for the current engine.
3605
* should be run under rtnl lock
3607
void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3609
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3610
u32 bit = BP_PATH(bp) ?
3611
BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3615
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3621
* Checks the RESET_IN_PROGRESS bit for the given engine.
3622
* should be run under rtnl lock
3624
bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3626
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3628
BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3630
/* return false if bit is set */
3631
return (val & bit) ? false : true;
3635
* Increment the load counter for the current engine.
3637
* should be run under rtnl lock
3639
void bnx2x_inc_load_cnt(struct bnx2x *bp)
3641
u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3642
u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3643
BNX2X_PATH0_LOAD_CNT_MASK;
3644
u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3645
BNX2X_PATH0_LOAD_CNT_SHIFT;
3647
DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3649
/* get the current counter value */
3650
val1 = (val & mask) >> shift;
3655
/* clear the old value */
3658
/* set the new one */
3659
val |= ((val1 << shift) & mask);
3661
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3667
* bnx2x_dec_load_cnt - decrement the load counter
3669
* @bp: driver handle
3671
* Should be run under rtnl lock.
3672
* Decrements the load counter for the current engine. Returns
3673
* the new counter value.
3675
u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3677
u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3678
u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3679
BNX2X_PATH0_LOAD_CNT_MASK;
3680
u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3681
BNX2X_PATH0_LOAD_CNT_SHIFT;
3683
DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3685
/* get the current counter value */
3686
val1 = (val & mask) >> shift;
3691
/* clear the old value */
3694
/* set the new one */
3695
val |= ((val1 << shift) & mask);
3697
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3705
* Read the load counter for the current engine.
3707
* should be run under rtnl lock
3709
static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3711
u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3712
BNX2X_PATH0_LOAD_CNT_MASK);
3713
u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3714
BNX2X_PATH0_LOAD_CNT_SHIFT);
3715
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3717
DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3719
val = (val & mask) >> shift;
3721
DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3727
* Reset the load counter for the current engine.
3729
* should be run under rtnl lock
3731
static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3733
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3734
u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3735
BNX2X_PATH0_LOAD_CNT_MASK);
3737
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3740
static inline void _print_next_block(int idx, const char *blk)
3742
pr_cont("%s%s", idx ? ", " : "", blk);
3745
static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3750
for (i = 0; sig; i++) {
3751
cur_bit = ((u32)0x1 << i);
3752
if (sig & cur_bit) {
3754
case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3756
_print_next_block(par_num++, "BRB");
3758
case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3760
_print_next_block(par_num++, "PARSER");
3762
case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3764
_print_next_block(par_num++, "TSDM");
3766
case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3768
_print_next_block(par_num++,
3771
case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3773
_print_next_block(par_num++, "TCM");
3775
case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3777
_print_next_block(par_num++, "TSEMI");
3779
case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3781
_print_next_block(par_num++, "XPB");
3793
static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3794
bool *global, bool print)
3798
for (i = 0; sig; i++) {
3799
cur_bit = ((u32)0x1 << i);
3800
if (sig & cur_bit) {
3802
case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3804
_print_next_block(par_num++, "PBF");
3806
case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3808
_print_next_block(par_num++, "QM");
3810
case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3812
_print_next_block(par_num++, "TM");
3814
case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3816
_print_next_block(par_num++, "XSDM");
3818
case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3820
_print_next_block(par_num++, "XCM");
3822
case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3824
_print_next_block(par_num++, "XSEMI");
3826
case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3828
_print_next_block(par_num++,
3831
case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3833
_print_next_block(par_num++, "NIG");
3835
case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3837
_print_next_block(par_num++,
3841
case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3843
_print_next_block(par_num++, "DEBUG");
3845
case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3847
_print_next_block(par_num++, "USDM");
3849
case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3851
_print_next_block(par_num++, "UCM");
3853
case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3855
_print_next_block(par_num++, "USEMI");
3857
case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3859
_print_next_block(par_num++, "UPB");
3861
case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3863
_print_next_block(par_num++, "CSDM");
3865
case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3867
_print_next_block(par_num++, "CCM");
3879
static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3884
for (i = 0; sig; i++) {
3885
cur_bit = ((u32)0x1 << i);
3886
if (sig & cur_bit) {
3888
case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3890
_print_next_block(par_num++, "CSEMI");
3892
case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3894
_print_next_block(par_num++, "PXP");
3896
case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3898
_print_next_block(par_num++,
3899
"PXPPCICLOCKCLIENT");
3901
case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3903
_print_next_block(par_num++, "CFC");
3905
case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3907
_print_next_block(par_num++, "CDU");
3909
case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3911
_print_next_block(par_num++, "DMAE");
3913
case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3915
_print_next_block(par_num++, "IGU");
3917
case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3919
_print_next_block(par_num++, "MISC");
3931
static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3932
bool *global, bool print)
3936
for (i = 0; sig; i++) {
3937
cur_bit = ((u32)0x1 << i);
3938
if (sig & cur_bit) {
3940
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3942
_print_next_block(par_num++, "MCP ROM");
3945
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3947
_print_next_block(par_num++,
3951
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3953
_print_next_block(par_num++,
3957
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3959
_print_next_block(par_num++,
3973
static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3978
for (i = 0; sig; i++) {
3979
cur_bit = ((u32)0x1 << i);
3980
if (sig & cur_bit) {
3982
case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3984
_print_next_block(par_num++, "PGLUE_B");
3986
case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3988
_print_next_block(par_num++, "ATC");
4000
static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4003
if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4004
(sig[1] & HW_PRTY_ASSERT_SET_1) ||
4005
(sig[2] & HW_PRTY_ASSERT_SET_2) ||
4006
(sig[3] & HW_PRTY_ASSERT_SET_3) ||
4007
(sig[4] & HW_PRTY_ASSERT_SET_4)) {
4009
DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
4010
"[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4012
sig[0] & HW_PRTY_ASSERT_SET_0,
4013
sig[1] & HW_PRTY_ASSERT_SET_1,
4014
sig[2] & HW_PRTY_ASSERT_SET_2,
4015
sig[3] & HW_PRTY_ASSERT_SET_3,
4016
sig[4] & HW_PRTY_ASSERT_SET_4);
4019
"Parity errors detected in blocks: ");
4020
par_num = bnx2x_check_blocks_with_parity0(
4021
sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4022
par_num = bnx2x_check_blocks_with_parity1(
4023
sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4024
par_num = bnx2x_check_blocks_with_parity2(
4025
sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4026
par_num = bnx2x_check_blocks_with_parity3(
4027
sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4028
par_num = bnx2x_check_blocks_with_parity4(
4029
sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4040
* bnx2x_chk_parity_attn - checks for parity attentions.
4042
* @bp: driver handle
4043
* @global: true if there was a global attention
4044
* @print: show parity attention in syslog
4046
bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4048
struct attn_route attn = { {0} };
4049
int port = BP_PORT(bp);
4051
attn.sig[0] = REG_RD(bp,
4052
MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4054
attn.sig[1] = REG_RD(bp,
4055
MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4057
attn.sig[2] = REG_RD(bp,
4058
MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4060
attn.sig[3] = REG_RD(bp,
4061
MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4064
if (!CHIP_IS_E1x(bp))
4065
attn.sig[4] = REG_RD(bp,
4066
MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4069
return bnx2x_parity_attn(bp, global, print, attn.sig);
4073
static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4076
if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4078
val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4079
BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4080
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4081
BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4083
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4084
BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4085
"INCORRECT_RCV_BEHAVIOR\n");
4086
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4087
BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4088
"WAS_ERROR_ATTN\n");
4089
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4090
BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4091
"VF_LENGTH_VIOLATION_ATTN\n");
4093
PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4094
BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4095
"VF_GRC_SPACE_VIOLATION_ATTN\n");
4097
PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4098
BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4099
"VF_MSIX_BAR_VIOLATION_ATTN\n");
4100
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4101
BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4102
"TCPL_ERROR_ATTN\n");
4103
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4104
BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4105
"TCPL_IN_TWO_RCBS_ATTN\n");
4106
if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4107
BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4108
"CSSNOOP_FIFO_OVERFLOW\n");
4110
if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4111
val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4112
BNX2X_ERR("ATC hw attention 0x%x\n", val);
4113
if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4114
BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4115
if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4116
BNX2X_ERR("ATC_ATC_INT_STS_REG"
4117
"_ATC_TCPL_TO_NOT_PEND\n");
4118
if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4119
BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4120
"ATC_GPA_MULTIPLE_HITS\n");
4121
if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4122
BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4123
"ATC_RCPL_TO_EMPTY_CNT\n");
4124
if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4125
BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4126
if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4127
BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4128
"ATC_IREQ_LESS_THAN_STU\n");
4131
if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4132
AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4133
BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4134
(u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4135
AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4140
static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4142
struct attn_route attn, *group_mask;
4143
int port = BP_PORT(bp);
4148
bool global = false;
4150
/* need to take HW lock because MCP or other port might also
4151
try to handle this event */
4152
bnx2x_acquire_alr(bp);
4154
if (bnx2x_chk_parity_attn(bp, &global, true)) {
4155
#ifndef BNX2X_STOP_ON_ERROR
4156
bp->recovery_state = BNX2X_RECOVERY_INIT;
4157
schedule_delayed_work(&bp->sp_rtnl_task, 0);
4158
/* Disable HW interrupts */
4159
bnx2x_int_disable(bp);
4160
/* In case of parity errors don't handle attentions so that
4161
* other function would "see" parity errors.
4166
bnx2x_release_alr(bp);
4170
attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4171
attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4172
attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4173
attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4174
if (!CHIP_IS_E1x(bp))
4176
REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4180
DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4181
attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4183
for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4184
if (deasserted & (1 << index)) {
4185
group_mask = &bp->attn_group[index];
4187
DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4190
group_mask->sig[0], group_mask->sig[1],
4191
group_mask->sig[2], group_mask->sig[3],
4192
group_mask->sig[4]);
4194
bnx2x_attn_int_deasserted4(bp,
4195
attn.sig[4] & group_mask->sig[4]);
4196
bnx2x_attn_int_deasserted3(bp,
4197
attn.sig[3] & group_mask->sig[3]);
4198
bnx2x_attn_int_deasserted1(bp,
4199
attn.sig[1] & group_mask->sig[1]);
4200
bnx2x_attn_int_deasserted2(bp,
4201
attn.sig[2] & group_mask->sig[2]);
4202
bnx2x_attn_int_deasserted0(bp,
4203
attn.sig[0] & group_mask->sig[0]);
4207
bnx2x_release_alr(bp);
4209
if (bp->common.int_block == INT_BLOCK_HC)
4210
reg_addr = (HC_REG_COMMAND_REG + port*32 +
4211
COMMAND_REG_ATTN_BITS_CLR);
4213
reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4216
DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4217
(bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4218
REG_WR(bp, reg_addr, val);
4220
if (~bp->attn_state & deasserted)
4221
BNX2X_ERR("IGU ERROR\n");
4223
reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4224
MISC_REG_AEU_MASK_ATTN_FUNC_0;
4226
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4227
aeu_mask = REG_RD(bp, reg_addr);
4229
DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4230
aeu_mask, deasserted);
4231
aeu_mask |= (deasserted & 0x3ff);
4232
DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4234
REG_WR(bp, reg_addr, aeu_mask);
4235
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4237
DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4238
bp->attn_state &= ~deasserted;
4239
DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4242
static void bnx2x_attn_int(struct bnx2x *bp)
4244
/* read local copy of bits */
4245
u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4247
u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4249
u32 attn_state = bp->attn_state;
4251
/* look for changed bits */
4252
u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4253
u32 deasserted = ~attn_bits & attn_ack & attn_state;
4256
"attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4257
attn_bits, attn_ack, asserted, deasserted);
4259
if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4260
BNX2X_ERR("BAD attention state\n");
4262
/* handle bits that were raised */
4264
bnx2x_attn_int_asserted(bp, asserted);
4267
bnx2x_attn_int_deasserted(bp, deasserted);
4270
void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4271
u16 index, u8 op, u8 update)
4273
u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4275
bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4279
static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4281
/* No memory barriers */
4282
storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4283
mmiowb(); /* keep prod updates ordered */
4287
static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4288
union event_ring_elem *elem)
4290
u8 err = elem->message.error;
4292
if (!bp->cnic_eth_dev.starting_cid ||
4293
(cid < bp->cnic_eth_dev.starting_cid &&
4294
cid != bp->cnic_eth_dev.iscsi_l2_cid))
4297
DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4299
if (unlikely(err)) {
4301
BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4303
bnx2x_panic_dump(bp);
4305
bnx2x_cnic_cfc_comp(bp, cid, err);
4310
static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4312
struct bnx2x_mcast_ramrod_params rparam;
4315
memset(&rparam, 0, sizeof(rparam));
4317
rparam.mcast_obj = &bp->mcast_obj;
4319
netif_addr_lock_bh(bp->dev);
4321
/* Clear pending state for the last command */
4322
bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4324
/* If there are pending mcast commands - send them */
4325
if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4326
rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4328
BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4332
netif_addr_unlock_bh(bp->dev);
4335
static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4336
union event_ring_elem *elem)
4338
unsigned long ramrod_flags = 0;
4340
u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4341
struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4343
/* Always push next commands out, don't wait here */
4344
__set_bit(RAMROD_CONT, &ramrod_flags);
4346
switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4347
case BNX2X_FILTER_MAC_PENDING:
4349
if (cid == BNX2X_ISCSI_ETH_CID)
4350
vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4353
vlan_mac_obj = &bp->fp[cid].mac_obj;
4356
case BNX2X_FILTER_MCAST_PENDING:
4357
/* This is only relevant for 57710 where multicast MACs are
4358
* configured as unicast MACs using the same ramrod.
4360
bnx2x_handle_mcast_eqe(bp);
4363
BNX2X_ERR("Unsupported classification command: %d\n",
4364
elem->message.data.eth_event.echo);
4368
rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4371
BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4373
DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4378
static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4381
static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4383
netif_addr_lock_bh(bp->dev);
4385
clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4387
/* Send rx_mode command again if was requested */
4388
if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4389
bnx2x_set_storm_rx_mode(bp);
4391
else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4393
bnx2x_set_iscsi_eth_rx_mode(bp, true);
4394
else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4396
bnx2x_set_iscsi_eth_rx_mode(bp, false);
4399
netif_addr_unlock_bh(bp->dev);
4402
static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4403
struct bnx2x *bp, u32 cid)
4405
DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4407
if (cid == BNX2X_FCOE_ETH_CID)
4408
return &bnx2x_fcoe(bp, q_obj);
4411
return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4414
static void bnx2x_eq_int(struct bnx2x *bp)
4416
u16 hw_cons, sw_cons, sw_prod;
4417
union event_ring_elem *elem;
4421
struct bnx2x_queue_sp_obj *q_obj;
4422
struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4423
struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4425
hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4427
/* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4428
* when we get the the next-page we nned to adjust so the loop
4429
* condition below will be met. The next element is the size of a
4430
* regular element and hence incrementing by 1
4432
if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4435
/* This function may never run in parallel with itself for a
4436
* specific bp, thus there is no need in "paired" read memory
4439
sw_cons = bp->eq_cons;
4440
sw_prod = bp->eq_prod;
4442
DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4443
hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4445
for (; sw_cons != hw_cons;
4446
sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4449
elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4451
cid = SW_CID(elem->message.data.cfc_del_event.cid);
4452
opcode = elem->message.opcode;
4455
/* handle eq element */
4457
case EVENT_RING_OPCODE_STAT_QUERY:
4458
DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4460
/* nothing to do with stats comp */
4463
case EVENT_RING_OPCODE_CFC_DEL:
4464
/* handle according to cid range */
4466
* we may want to verify here that the bp state is
4470
"got delete ramrod for MULTI[%d]\n", cid);
4472
if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4475
q_obj = bnx2x_cid_to_q_obj(bp, cid);
4477
if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4484
case EVENT_RING_OPCODE_STOP_TRAFFIC:
4485
DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
4486
if (f_obj->complete_cmd(bp, f_obj,
4487
BNX2X_F_CMD_TX_STOP))
4489
bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4492
case EVENT_RING_OPCODE_START_TRAFFIC:
4493
DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
4494
if (f_obj->complete_cmd(bp, f_obj,
4495
BNX2X_F_CMD_TX_START))
4497
bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4499
case EVENT_RING_OPCODE_FUNCTION_START:
4500
DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
4501
if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4506
case EVENT_RING_OPCODE_FUNCTION_STOP:
4507
DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
4508
if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4514
switch (opcode | bp->state) {
4515
case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4517
case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4518
BNX2X_STATE_OPENING_WAIT4_PORT):
4519
cid = elem->message.data.eth_event.echo &
4521
DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4523
rss_raw->clear_pending(rss_raw);
4526
case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4527
case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4528
case (EVENT_RING_OPCODE_SET_MAC |
4529
BNX2X_STATE_CLOSING_WAIT4_HALT):
4530
case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4532
case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4534
case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4535
BNX2X_STATE_CLOSING_WAIT4_HALT):
4536
DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4537
bnx2x_handle_classification_eqe(bp, elem);
4540
case (EVENT_RING_OPCODE_MULTICAST_RULES |
4542
case (EVENT_RING_OPCODE_MULTICAST_RULES |
4544
case (EVENT_RING_OPCODE_MULTICAST_RULES |
4545
BNX2X_STATE_CLOSING_WAIT4_HALT):
4546
DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4547
bnx2x_handle_mcast_eqe(bp);
4550
case (EVENT_RING_OPCODE_FILTERS_RULES |
4552
case (EVENT_RING_OPCODE_FILTERS_RULES |
4554
case (EVENT_RING_OPCODE_FILTERS_RULES |
4555
BNX2X_STATE_CLOSING_WAIT4_HALT):
4556
DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4557
bnx2x_handle_rx_mode_eqe(bp);
4560
/* unknown event log error and continue */
4561
BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4562
elem->message.opcode, bp->state);
4568
smp_mb__before_atomic_inc();
4569
atomic_add(spqe_cnt, &bp->eq_spq_left);
4571
bp->eq_cons = sw_cons;
4572
bp->eq_prod = sw_prod;
4573
/* Make sure that above mem writes were issued towards the memory */
4576
/* update producer */
4577
bnx2x_update_eq_prod(bp, bp->eq_prod);
4580
static void bnx2x_sp_task(struct work_struct *work)
4582
struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4585
status = bnx2x_update_dsb_idx(bp);
4586
/* if (status == 0) */
4587
/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4589
DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4592
if (status & BNX2X_DEF_SB_ATT_IDX) {
4594
status &= ~BNX2X_DEF_SB_ATT_IDX;
4597
/* SP events: STAT_QUERY and others */
4598
if (status & BNX2X_DEF_SB_IDX) {
4600
struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4602
if ((!NO_FCOE(bp)) &&
4603
(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4605
* Prevent local bottom-halves from running as
4606
* we are going to change the local NAPI list.
4609
napi_schedule(&bnx2x_fcoe(bp, napi));
4613
/* Handle EQ completions */
4616
bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4617
le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4619
status &= ~BNX2X_DEF_SB_IDX;
4622
if (unlikely(status))
4623
DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4626
bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4627
le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4630
irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4632
struct net_device *dev = dev_instance;
4633
struct bnx2x *bp = netdev_priv(dev);
4635
bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4636
IGU_INT_DISABLE, 0);
4638
#ifdef BNX2X_STOP_ON_ERROR
4639
if (unlikely(bp->panic))
4645
struct cnic_ops *c_ops;
4648
c_ops = rcu_dereference(bp->cnic_ops);
4650
c_ops->cnic_handler(bp->cnic_data, NULL);
4654
queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4659
/* end of slow path */
4662
void bnx2x_drv_pulse(struct bnx2x *bp)
4664
SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4665
bp->fw_drv_pulse_wr_seq);
4669
static void bnx2x_timer(unsigned long data)
4672
struct bnx2x *bp = (struct bnx2x *) data;
4674
if (!netif_running(bp->dev))
4678
struct bnx2x_fastpath *fp = &bp->fp[0];
4680
for_each_cos_in_tx_queue(fp, cos)
4681
bnx2x_tx_int(bp, &fp->txdata[cos]);
4682
bnx2x_rx_int(fp, 1000);
4685
if (!BP_NOMCP(bp)) {
4686
int mb_idx = BP_FW_MB_IDX(bp);
4690
++bp->fw_drv_pulse_wr_seq;
4691
bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4692
/* TBD - add SYSTEM_TIME */
4693
drv_pulse = bp->fw_drv_pulse_wr_seq;
4694
bnx2x_drv_pulse(bp);
4696
mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4697
MCP_PULSE_SEQ_MASK);
4698
/* The delta between driver pulse and mcp response
4699
* should be 1 (before mcp response) or 0 (after mcp response)
4701
if ((drv_pulse != mcp_pulse) &&
4702
(drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4703
/* someone lost a heartbeat... */
4704
BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4705
drv_pulse, mcp_pulse);
4709
if (bp->state == BNX2X_STATE_OPEN)
4710
bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4712
mod_timer(&bp->timer, jiffies + bp->current_interval);
4715
/* end of Statistics */
4720
* nic init service functions
4723
static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4726
if (!(len%4) && !(addr%4))
4727
for (i = 0; i < len; i += 4)
4728
REG_WR(bp, addr + i, fill);
4730
for (i = 0; i < len; i++)
4731
REG_WR8(bp, addr + i, fill);
4735
/* helper: writes FP SP data to FW - data_size in dwords */
4736
static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4742
for (index = 0; index < data_size; index++)
4743
REG_WR(bp, BAR_CSTRORM_INTMEM +
4744
CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4746
*(sb_data_p + index));
4749
static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4753
struct hc_status_block_data_e2 sb_data_e2;
4754
struct hc_status_block_data_e1x sb_data_e1x;
4756
/* disable the function first */
4757
if (!CHIP_IS_E1x(bp)) {
4758
memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4759
sb_data_e2.common.state = SB_DISABLED;
4760
sb_data_e2.common.p_func.vf_valid = false;
4761
sb_data_p = (u32 *)&sb_data_e2;
4762
data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4764
memset(&sb_data_e1x, 0,
4765
sizeof(struct hc_status_block_data_e1x));
4766
sb_data_e1x.common.state = SB_DISABLED;
4767
sb_data_e1x.common.p_func.vf_valid = false;
4768
sb_data_p = (u32 *)&sb_data_e1x;
4769
data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4771
bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4773
bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4774
CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4775
CSTORM_STATUS_BLOCK_SIZE);
4776
bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4777
CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4778
CSTORM_SYNC_BLOCK_SIZE);
4781
/* helper: writes SP SB data to FW */
4782
static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4783
struct hc_sp_status_block_data *sp_sb_data)
4785
int func = BP_FUNC(bp);
4787
for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4788
REG_WR(bp, BAR_CSTRORM_INTMEM +
4789
CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4791
*((u32 *)sp_sb_data + i));
4794
static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4796
int func = BP_FUNC(bp);
4797
struct hc_sp_status_block_data sp_sb_data;
4798
memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4800
sp_sb_data.state = SB_DISABLED;
4801
sp_sb_data.p_func.vf_valid = false;
4803
bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4805
bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4806
CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4807
CSTORM_SP_STATUS_BLOCK_SIZE);
4808
bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4809
CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4810
CSTORM_SP_SYNC_BLOCK_SIZE);
4816
void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4817
int igu_sb_id, int igu_seg_id)
4819
hc_sm->igu_sb_id = igu_sb_id;
4820
hc_sm->igu_seg_id = igu_seg_id;
4821
hc_sm->timer_value = 0xFF;
4822
hc_sm->time_to_expire = 0xFFFFFFFF;
4826
/* allocates state machine ids. */
4828
void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4830
/* zero out state machine indices */
4832
index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4835
index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4836
index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4837
index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4838
index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4842
index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4843
SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4846
index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4847
SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4848
index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4849
SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4850
index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4851
SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4852
index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4853
SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4856
static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4857
u8 vf_valid, int fw_sb_id, int igu_sb_id)
4861
struct hc_status_block_data_e2 sb_data_e2;
4862
struct hc_status_block_data_e1x sb_data_e1x;
4863
struct hc_status_block_sm *hc_sm_p;
4867
if (CHIP_INT_MODE_IS_BC(bp))
4868
igu_seg_id = HC_SEG_ACCESS_NORM;
4870
igu_seg_id = IGU_SEG_ACCESS_NORM;
4872
bnx2x_zero_fp_sb(bp, fw_sb_id);
4874
if (!CHIP_IS_E1x(bp)) {
4875
memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4876
sb_data_e2.common.state = SB_ENABLED;
4877
sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4878
sb_data_e2.common.p_func.vf_id = vfid;
4879
sb_data_e2.common.p_func.vf_valid = vf_valid;
4880
sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4881
sb_data_e2.common.same_igu_sb_1b = true;
4882
sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4883
sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4884
hc_sm_p = sb_data_e2.common.state_machine;
4885
sb_data_p = (u32 *)&sb_data_e2;
4886
data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4887
bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4889
memset(&sb_data_e1x, 0,
4890
sizeof(struct hc_status_block_data_e1x));
4891
sb_data_e1x.common.state = SB_ENABLED;
4892
sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4893
sb_data_e1x.common.p_func.vf_id = 0xff;
4894
sb_data_e1x.common.p_func.vf_valid = false;
4895
sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4896
sb_data_e1x.common.same_igu_sb_1b = true;
4897
sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4898
sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4899
hc_sm_p = sb_data_e1x.common.state_machine;
4900
sb_data_p = (u32 *)&sb_data_e1x;
4901
data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4902
bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4905
bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4906
igu_sb_id, igu_seg_id);
4907
bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4908
igu_sb_id, igu_seg_id);
4910
DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4912
/* write indecies to HW */
4913
bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4916
static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4917
u16 tx_usec, u16 rx_usec)
4919
bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
4921
bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4922
HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4924
bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4925
HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4927
bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4928
HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4932
static void bnx2x_init_def_sb(struct bnx2x *bp)
4934
struct host_sp_status_block *def_sb = bp->def_status_blk;
4935
dma_addr_t mapping = bp->def_status_blk_mapping;
4936
int igu_sp_sb_index;
4938
int port = BP_PORT(bp);
4939
int func = BP_FUNC(bp);
4940
int reg_offset, reg_offset_en5;
4943
struct hc_sp_status_block_data sp_sb_data;
4944
memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4946
if (CHIP_INT_MODE_IS_BC(bp)) {
4947
igu_sp_sb_index = DEF_SB_IGU_ID;
4948
igu_seg_id = HC_SEG_ACCESS_DEF;
4950
igu_sp_sb_index = bp->igu_dsb_id;
4951
igu_seg_id = IGU_SEG_ACCESS_DEF;
4955
section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4956
atten_status_block);
4957
def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4961
reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4962
MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4963
reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
4964
MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
4965
for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4967
/* take care of sig[0]..sig[4] */
4968
for (sindex = 0; sindex < 4; sindex++)
4969
bp->attn_group[index].sig[sindex] =
4970
REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4972
if (!CHIP_IS_E1x(bp))
4974
* enable5 is separate from the rest of the registers,
4975
* and therefore the address skip is 4
4976
* and not 16 between the different groups
4978
bp->attn_group[index].sig[4] = REG_RD(bp,
4979
reg_offset_en5 + 0x4*index);
4981
bp->attn_group[index].sig[4] = 0;
4984
if (bp->common.int_block == INT_BLOCK_HC) {
4985
reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4986
HC_REG_ATTN_MSG0_ADDR_L);
4988
REG_WR(bp, reg_offset, U64_LO(section));
4989
REG_WR(bp, reg_offset + 4, U64_HI(section));
4990
} else if (!CHIP_IS_E1x(bp)) {
4991
REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4992
REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4995
section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4998
bnx2x_zero_sp_sb(bp);
5000
sp_sb_data.state = SB_ENABLED;
5001
sp_sb_data.host_sb_addr.lo = U64_LO(section);
5002
sp_sb_data.host_sb_addr.hi = U64_HI(section);
5003
sp_sb_data.igu_sb_id = igu_sp_sb_index;
5004
sp_sb_data.igu_seg_id = igu_seg_id;
5005
sp_sb_data.p_func.pf_id = func;
5006
sp_sb_data.p_func.vnic_id = BP_VN(bp);
5007
sp_sb_data.p_func.vf_id = 0xff;
5009
bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5011
bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5014
void bnx2x_update_coalesce(struct bnx2x *bp)
5018
for_each_eth_queue(bp, i)
5019
bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5020
bp->tx_ticks, bp->rx_ticks);
5023
static void bnx2x_init_sp_ring(struct bnx2x *bp)
5025
spin_lock_init(&bp->spq_lock);
5026
atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5028
bp->spq_prod_idx = 0;
5029
bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5030
bp->spq_prod_bd = bp->spq;
5031
bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5034
static void bnx2x_init_eq_ring(struct bnx2x *bp)
5037
for (i = 1; i <= NUM_EQ_PAGES; i++) {
5038
union event_ring_elem *elem =
5039
&bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5041
elem->next_page.addr.hi =
5042
cpu_to_le32(U64_HI(bp->eq_mapping +
5043
BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5044
elem->next_page.addr.lo =
5045
cpu_to_le32(U64_LO(bp->eq_mapping +
5046
BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5049
bp->eq_prod = NUM_EQ_DESC;
5050
bp->eq_cons_sb = BNX2X_EQ_INDEX;
5051
/* we want a warning message before it gets rought... */
5052
atomic_set(&bp->eq_spq_left,
5053
min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5057
/* called with netif_addr_lock_bh() */
5058
void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5059
unsigned long rx_mode_flags,
5060
unsigned long rx_accept_flags,
5061
unsigned long tx_accept_flags,
5062
unsigned long ramrod_flags)
5064
struct bnx2x_rx_mode_ramrod_params ramrod_param;
5067
memset(&ramrod_param, 0, sizeof(ramrod_param));
5069
/* Prepare ramrod parameters */
5070
ramrod_param.cid = 0;
5071
ramrod_param.cl_id = cl_id;
5072
ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5073
ramrod_param.func_id = BP_FUNC(bp);
5075
ramrod_param.pstate = &bp->sp_state;
5076
ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5078
ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5079
ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5081
set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5083
ramrod_param.ramrod_flags = ramrod_flags;
5084
ramrod_param.rx_mode_flags = rx_mode_flags;
5086
ramrod_param.rx_accept_flags = rx_accept_flags;
5087
ramrod_param.tx_accept_flags = tx_accept_flags;
5089
rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5091
BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5096
/* called with netif_addr_lock_bh() */
5097
void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5099
unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5100
unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5105
/* Configure rx_mode of FCoE Queue */
5106
__set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5109
switch (bp->rx_mode) {
5110
case BNX2X_RX_MODE_NONE:
5112
* 'drop all' supersedes any accept flags that may have been
5113
* passed to the function.
5116
case BNX2X_RX_MODE_NORMAL:
5117
__set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5118
__set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5119
__set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5121
/* internal switching mode */
5122
__set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5123
__set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5124
__set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5127
case BNX2X_RX_MODE_ALLMULTI:
5128
__set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5129
__set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5130
__set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5132
/* internal switching mode */
5133
__set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5134
__set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5135
__set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5138
case BNX2X_RX_MODE_PROMISC:
5139
/* According to deffinition of SI mode, iface in promisc mode
5140
* should receive matched and unmatched (in resolution of port)
5143
__set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5144
__set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5145
__set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5146
__set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5148
/* internal switching mode */
5149
__set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5150
__set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5153
__set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5155
__set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5159
BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5163
if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5164
__set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5165
__set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5168
__set_bit(RAMROD_RX, &ramrod_flags);
5169
__set_bit(RAMROD_TX, &ramrod_flags);
5171
bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5172
tx_accept_flags, ramrod_flags);
5175
static void bnx2x_init_internal_common(struct bnx2x *bp)
5181
* In switch independent mode, the TSTORM needs to accept
5182
* packets that failed classification, since approximate match
5183
* mac addresses aren't written to NIG LLH
5185
REG_WR8(bp, BAR_TSTRORM_INTMEM +
5186
TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5187
else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5188
REG_WR8(bp, BAR_TSTRORM_INTMEM +
5189
TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5191
/* Zero this manually as its initialization is
5192
currently missing in the initTool */
5193
for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5194
REG_WR(bp, BAR_USTRORM_INTMEM +
5195
USTORM_AGG_DATA_OFFSET + i * 4, 0);
5196
if (!CHIP_IS_E1x(bp)) {
5197
REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5198
CHIP_INT_MODE_IS_BC(bp) ?
5199
HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5203
static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5205
switch (load_code) {
5206
case FW_MSG_CODE_DRV_LOAD_COMMON:
5207
case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5208
bnx2x_init_internal_common(bp);
5211
case FW_MSG_CODE_DRV_LOAD_PORT:
5215
case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5216
/* internal memory per function is
5217
initialized inside bnx2x_pf_init */
5221
BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5226
static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5228
return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5231
static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5233
return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5236
static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5238
if (CHIP_IS_E1x(fp->bp))
5239
return BP_L_ID(fp->bp) + fp->index;
5240
else /* We want Client ID to be the same as IGU SB ID for 57712 */
5241
return bnx2x_fp_igu_sb_id(fp);
5244
static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5246
struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5248
unsigned long q_type = 0;
5249
u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5252
fp->cl_id = bnx2x_fp_cl_id(fp);
5253
fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5254
fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5255
/* qZone id equals to FW (per path) client id */
5256
fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5259
fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5260
/* Setup SB indicies */
5261
fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5263
/* Configure Queue State object */
5264
__set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5265
__set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5267
BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5270
for_each_cos_in_tx_queue(fp, cos) {
5271
bnx2x_init_txdata(bp, &fp->txdata[cos],
5272
CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5273
FP_COS_TO_TXQ(fp, cos),
5274
BNX2X_TX_SB_INDEX_BASE + cos);
5275
cids[cos] = fp->txdata[cos].cid;
5278
bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5279
BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5280
bnx2x_sp_mapping(bp, q_rdata), q_type);
5283
* Configure classification DBs: Always enable Tx switching
5285
bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5287
DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5288
"cl_id %d fw_sb %d igu_sb %d\n",
5289
fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5291
bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5292
fp->fw_sb_id, fp->igu_sb_id);
5294
bnx2x_update_fpsb_idx(fp);
5297
void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5301
for_each_eth_queue(bp, i)
5302
bnx2x_init_eth_fp(bp, i);
5305
bnx2x_init_fcoe_fp(bp);
5307
bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5308
BNX2X_VF_ID_INVALID, false,
5309
bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5313
/* Initialize MOD_ABS interrupts */
5314
bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5315
bp->common.shmem_base, bp->common.shmem2_base,
5317
/* ensure status block indices were read */
5320
bnx2x_init_def_sb(bp);
5321
bnx2x_update_dsb_idx(bp);
5322
bnx2x_init_rx_rings(bp);
5323
bnx2x_init_tx_rings(bp);
5324
bnx2x_init_sp_ring(bp);
5325
bnx2x_init_eq_ring(bp);
5326
bnx2x_init_internal(bp, load_code);
5328
bnx2x_stats_init(bp);
5330
/* flush all before enabling interrupts */
5334
bnx2x_int_enable(bp);
5336
/* Check for SPIO5 */
5337
bnx2x_attn_int_deasserted0(bp,
5338
REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5339
AEU_INPUTS_ATTN_BITS_SPIO5);
5342
/* end of nic init */
5345
* gzip service functions
5348
static int bnx2x_gunzip_init(struct bnx2x *bp)
5350
bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5351
&bp->gunzip_mapping, GFP_KERNEL);
5352
if (bp->gunzip_buf == NULL)
5355
bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5356
if (bp->strm == NULL)
5359
bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5360
if (bp->strm->workspace == NULL)
5370
dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5371
bp->gunzip_mapping);
5372
bp->gunzip_buf = NULL;
5375
netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5376
" un-compression\n");
5380
static void bnx2x_gunzip_end(struct bnx2x *bp)
5383
vfree(bp->strm->workspace);
5388
if (bp->gunzip_buf) {
5389
dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5390
bp->gunzip_mapping);
5391
bp->gunzip_buf = NULL;
5395
static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5399
/* check gzip header */
5400
if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5401
BNX2X_ERR("Bad gzip header\n");
5409
if (zbuf[3] & FNAME)
5410
while ((zbuf[n++] != 0) && (n < len));
5412
bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5413
bp->strm->avail_in = len - n;
5414
bp->strm->next_out = bp->gunzip_buf;
5415
bp->strm->avail_out = FW_BUF_SIZE;
5417
rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5421
rc = zlib_inflate(bp->strm, Z_FINISH);
5422
if ((rc != Z_OK) && (rc != Z_STREAM_END))
5423
netdev_err(bp->dev, "Firmware decompression error: %s\n",
5426
bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5427
if (bp->gunzip_outlen & 0x3)
5428
netdev_err(bp->dev, "Firmware decompression error:"
5429
" gunzip_outlen (%d) not aligned\n",
5431
bp->gunzip_outlen >>= 2;
5433
zlib_inflateEnd(bp->strm);
5435
if (rc == Z_STREAM_END)
5441
/* nic load/unload */
5444
* General service functions
5447
/* send a NIG loopback debug packet */
5448
static void bnx2x_lb_pckt(struct bnx2x *bp)
5452
/* Ethernet source and destination addresses */
5453
wb_write[0] = 0x55555555;
5454
wb_write[1] = 0x55555555;
5455
wb_write[2] = 0x20; /* SOP */
5456
REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5458
/* NON-IP protocol */
5459
wb_write[0] = 0x09000000;
5460
wb_write[1] = 0x55555555;
5461
wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5462
REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5465
/* some of the internal memories
5466
* are not directly readable from the driver
5467
* to test them we send debug packets
5469
static int bnx2x_int_mem_test(struct bnx2x *bp)
5475
if (CHIP_REV_IS_FPGA(bp))
5477
else if (CHIP_REV_IS_EMUL(bp))
5482
/* Disable inputs of parser neighbor blocks */
5483
REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5484
REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5485
REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5486
REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5488
/* Write 0 to parser credits for CFC search request */
5489
REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5491
/* send Ethernet packet */
5494
/* TODO do i reset NIG statistic? */
5495
/* Wait until NIG register shows 1 packet of size 0x10 */
5496
count = 1000 * factor;
5499
bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5500
val = *bnx2x_sp(bp, wb_data[0]);
5508
BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5512
/* Wait until PRS register shows 1 packet */
5513
count = 1000 * factor;
5515
val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5523
BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5527
/* Reset and init BRB, PRS */
5528
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5530
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5532
bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5533
bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5535
DP(NETIF_MSG_HW, "part2\n");
5537
/* Disable inputs of parser neighbor blocks */
5538
REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5539
REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5540
REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5541
REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5543
/* Write 0 to parser credits for CFC search request */
5544
REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5546
/* send 10 Ethernet packets */
5547
for (i = 0; i < 10; i++)
5550
/* Wait until NIG register shows 10 + 1
5551
packets of size 11*0x10 = 0xb0 */
5552
count = 1000 * factor;
5555
bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5556
val = *bnx2x_sp(bp, wb_data[0]);
5564
BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5568
/* Wait until PRS register shows 2 packets */
5569
val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5571
BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5573
/* Write 1 to parser credits for CFC search request */
5574
REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5576
/* Wait until PRS register shows 3 packets */
5577
msleep(10 * factor);
5578
/* Wait until NIG register shows 1 packet of size 0x10 */
5579
val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5581
BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5583
/* clear NIG EOP FIFO */
5584
for (i = 0; i < 11; i++)
5585
REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5586
val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5588
BNX2X_ERR("clear of NIG failed\n");
5592
/* Reset and init BRB, PRS, NIG */
5593
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5595
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5597
bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5598
bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5601
REG_WR(bp, PRS_REG_NIC_MODE, 1);
5604
/* Enable inputs of parser neighbor blocks */
5605
REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5606
REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5607
REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5608
REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5610
DP(NETIF_MSG_HW, "done\n");
5615
static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5617
REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5618
if (!CHIP_IS_E1x(bp))
5619
REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5621
REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5622
REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5623
REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5625
* mask read length error interrupts in brb for parser
5626
* (parsing unit and 'checksum and crc' unit)
5627
* these errors are legal (PU reads fixed length and CAC can cause
5628
* read length error on truncated packets)
5630
REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5631
REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5632
REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5633
REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5634
REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5635
REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5636
/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5637
/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5638
REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5639
REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5640
REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5641
/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5642
/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5643
REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5644
REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5645
REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5646
REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5647
/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5648
/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5650
if (CHIP_REV_IS_FPGA(bp))
5651
REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5652
else if (!CHIP_IS_E1x(bp))
5653
REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5654
(PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5655
| PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5656
| PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5657
| PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5658
| PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5660
REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5661
REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5662
REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5663
REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5664
/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5666
if (!CHIP_IS_E1x(bp))
5667
/* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5668
REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5670
REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5671
REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5672
/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5673
REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5676
static void bnx2x_reset_common(struct bnx2x *bp)
5681
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5684
if (CHIP_IS_E3(bp)) {
5685
val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5686
val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5689
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5692
static void bnx2x_setup_dmae(struct bnx2x *bp)
5695
spin_lock_init(&bp->dmae_lock);
5698
static void bnx2x_init_pxp(struct bnx2x *bp)
5701
int r_order, w_order;
5703
pci_read_config_word(bp->pdev,
5704
pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
5705
DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5706
w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5708
r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5710
DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5714
bnx2x_init_pxp_arb(bp, r_order, w_order);
5717
static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5727
val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5728
SHARED_HW_CFG_FAN_FAILURE_MASK;
5730
if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5734
* The fan failure mechanism is usually related to the PHY type since
5735
* the power consumption of the board is affected by the PHY. Currently,
5736
* fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5738
else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5739
for (port = PORT_0; port < PORT_MAX; port++) {
5741
bnx2x_fan_failure_det_req(
5743
bp->common.shmem_base,
5744
bp->common.shmem2_base,
5748
DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5750
if (is_required == 0)
5753
/* Fan failure is indicated by SPIO 5 */
5754
bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5755
MISC_REGISTERS_SPIO_INPUT_HI_Z);
5757
/* set to active low mode */
5758
val = REG_RD(bp, MISC_REG_SPIO_INT);
5759
val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5760
MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5761
REG_WR(bp, MISC_REG_SPIO_INT, val);
5763
/* enable interrupt to signal the IGU */
5764
val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5765
val |= (1 << MISC_REGISTERS_SPIO_5);
5766
REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5769
static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5775
if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5778
switch (BP_ABS_FUNC(bp)) {
5780
offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5783
offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5786
offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5789
offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5792
offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5795
offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5798
offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5801
offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5807
REG_WR(bp, offset, pretend_func_num);
5809
DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5812
void bnx2x_pf_disable(struct bnx2x *bp)
5814
u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5815
val &= ~IGU_PF_CONF_FUNC_EN;
5817
REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5818
REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5819
REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5822
static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5824
u32 shmem_base[2], shmem2_base[2];
5825
shmem_base[0] = bp->common.shmem_base;
5826
shmem2_base[0] = bp->common.shmem2_base;
5827
if (!CHIP_IS_E1x(bp)) {
5829
SHMEM2_RD(bp, other_shmem_base_addr);
5831
SHMEM2_RD(bp, other_shmem2_base_addr);
5833
bnx2x_acquire_phy_lock(bp);
5834
bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5835
bp->common.chip_id);
5836
bnx2x_release_phy_lock(bp);
5840
* bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5842
* @bp: driver handle
5844
static int bnx2x_init_hw_common(struct bnx2x *bp)
5848
DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5851
* take the UNDI lock to protect undi_unload flow from accessing
5852
* registers while we're resetting the chip
5854
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
5856
bnx2x_reset_common(bp);
5857
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5860
if (CHIP_IS_E3(bp)) {
5861
val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5862
val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5864
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5866
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
5868
bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5870
if (!CHIP_IS_E1x(bp)) {
5874
* 4-port mode or 2-port mode we need to turn of master-enable
5875
* for everyone, after that, turn it back on for self.
5876
* so, we disregard multi-function or not, and always disable
5877
* for all functions on the given path, this means 0,2,4,6 for
5878
* path 0 and 1,3,5,7 for path 1
5880
for (abs_func_id = BP_PATH(bp);
5881
abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5882
if (abs_func_id == BP_ABS_FUNC(bp)) {
5884
PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5889
bnx2x_pretend_func(bp, abs_func_id);
5890
/* clear pf enable */
5891
bnx2x_pf_disable(bp);
5892
bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5896
bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5897
if (CHIP_IS_E1(bp)) {
5898
/* enable HW interrupt from PXP on USDM overflow
5899
bit 16 on INT_MASK_0 */
5900
REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5903
bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5907
REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5908
REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5909
REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5910
REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5911
REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5912
/* make sure this value is 0 */
5913
REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5915
/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5916
REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5917
REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5918
REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5919
REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5922
bnx2x_ilt_init_page_size(bp, INITOP_SET);
5924
if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5925
REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5927
/* let the HW do it's magic ... */
5929
/* finish PXP init */
5930
val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5932
BNX2X_ERR("PXP2 CFG failed\n");
5935
val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5937
BNX2X_ERR("PXP2 RD_INIT failed\n");
5941
/* Timers bug workaround E2 only. We need to set the entire ILT to
5942
* have entries with value "0" and valid bit on.
5943
* This needs to be done by the first PF that is loaded in a path
5944
* (i.e. common phase)
5946
if (!CHIP_IS_E1x(bp)) {
5947
/* In E2 there is a bug in the timers block that can cause function 6 / 7
5948
* (i.e. vnic3) to start even if it is marked as "scan-off".
5949
* This occurs when a different function (func2,3) is being marked
5950
* as "scan-off". Real-life scenario for example: if a driver is being
5951
* load-unloaded while func6,7 are down. This will cause the timer to access
5952
* the ilt, translate to a logical address and send a request to read/write.
5953
* Since the ilt for the function that is down is not valid, this will cause
5954
* a translation error which is unrecoverable.
5955
* The Workaround is intended to make sure that when this happens nothing fatal
5956
* will occur. The workaround:
5957
* 1. First PF driver which loads on a path will:
5958
* a. After taking the chip out of reset, by using pretend,
5959
* it will write "0" to the following registers of
5961
* REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5962
* REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5963
* REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5964
* And for itself it will write '1' to
5965
* PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5966
* dmae-operations (writing to pram for example.)
5967
* note: can be done for only function 6,7 but cleaner this
5969
* b. Write zero+valid to the entire ILT.
5970
* c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5971
* VNIC3 (of that port). The range allocated will be the
5972
* entire ILT. This is needed to prevent ILT range error.
5973
* 2. Any PF driver load flow:
5974
* a. ILT update with the physical addresses of the allocated
5976
* b. Wait 20msec. - note that this timeout is needed to make
5977
* sure there are no requests in one of the PXP internal
5978
* queues with "old" ILT addresses.
5979
* c. PF enable in the PGLC.
5980
* d. Clear the was_error of the PF in the PGLC. (could have
5981
* occured while driver was down)
5982
* e. PF enable in the CFC (WEAK + STRONG)
5983
* f. Timers scan enable
5984
* 3. PF driver unload flow:
5985
* a. Clear the Timers scan_en.
5986
* b. Polling for scan_on=0 for that PF.
5987
* c. Clear the PF enable bit in the PXP.
5988
* d. Clear the PF enable in the CFC (WEAK + STRONG)
5989
* e. Write zero+valid to all ILT entries (The valid bit must
5991
* f. If this is VNIC 3 of a port then also init
5992
* first_timers_ilt_entry to zero and last_timers_ilt_entry
5993
* to the last enrty in the ILT.
5996
* Currently the PF error in the PGLC is non recoverable.
5997
* In the future the there will be a recovery routine for this error.
5998
* Currently attention is masked.
5999
* Having an MCP lock on the load/unload process does not guarantee that
6000
* there is no Timer disable during Func6/7 enable. This is because the
6001
* Timers scan is currently being cleared by the MCP on FLR.
6002
* Step 2.d can be done only for PF6/7 and the driver can also check if
6003
* there is error before clearing it. But the flow above is simpler and
6005
* All ILT entries are written by zero+valid and not just PF6/7
6006
* ILT entries since in the future the ILT entries allocation for
6007
* PF-s might be dynamic.
6009
struct ilt_client_info ilt_cli;
6010
struct bnx2x_ilt ilt;
6011
memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6012
memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6014
/* initialize dummy TM client */
6016
ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6017
ilt_cli.client_num = ILT_CLIENT_TM;
6019
/* Step 1: set zeroes to all ilt page entries with valid bit on
6020
* Step 2: set the timers first/last ilt entry to point
6021
* to the entire range to prevent ILT range error for 3rd/4th
6022
* vnic (this code assumes existance of the vnic)
6024
* both steps performed by call to bnx2x_ilt_client_init_op()
6025
* with dummy TM client
6027
* we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6028
* and his brother are split registers
6030
bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6031
bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6032
bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6034
REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6035
REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6036
REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6040
REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6041
REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6043
if (!CHIP_IS_E1x(bp)) {
6044
int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6045
(CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6046
bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6048
bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6050
/* let the HW do it's magic ... */
6053
val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6054
} while (factor-- && (val != 1));
6057
BNX2X_ERR("ATC_INIT failed\n");
6062
bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6064
/* clean the DMAE memory */
6066
bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6068
bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6070
bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6072
bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6074
bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6076
bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6077
bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6078
bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6079
bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6081
bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6084
/* QM queues pointers table */
6085
bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6087
/* soft reset pulse */
6088
REG_WR(bp, QM_REG_SOFT_RESET, 1);
6089
REG_WR(bp, QM_REG_SOFT_RESET, 0);
6092
bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6095
bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6096
REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6097
if (!CHIP_REV_IS_SLOW(bp))
6098
/* enable hw interrupt from doorbell Q */
6099
REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6101
bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6103
bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6104
REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6106
if (!CHIP_IS_E1(bp))
6107
REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6109
if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6110
/* Bit-map indicating which L2 hdrs may appear
6111
* after the basic Ethernet header
6113
REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6114
bp->path_has_ovlan ? 7 : 6);
6116
bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6117
bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6118
bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6119
bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6121
if (!CHIP_IS_E1x(bp)) {
6122
/* reset VFC memories */
6123
REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6124
VFC_MEMORIES_RST_REG_CAM_RST |
6125
VFC_MEMORIES_RST_REG_RAM_RST);
6126
REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6127
VFC_MEMORIES_RST_REG_CAM_RST |
6128
VFC_MEMORIES_RST_REG_RAM_RST);
6133
bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6134
bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6135
bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6136
bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6139
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6141
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6144
bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6145
bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6146
bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6148
if (!CHIP_IS_E1x(bp))
6149
REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6150
bp->path_has_ovlan ? 7 : 6);
6152
REG_WR(bp, SRC_REG_SOFT_RST, 1);
6154
bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6157
REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6158
REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6159
REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6160
REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6161
REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6162
REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6163
REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6164
REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6165
REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6166
REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6168
REG_WR(bp, SRC_REG_SOFT_RST, 0);
6170
if (sizeof(union cdu_context) != 1024)
6171
/* we currently assume that a context is 1024 bytes */
6172
dev_alert(&bp->pdev->dev, "please adjust the size "
6173
"of cdu_context(%ld)\n",
6174
(long)sizeof(union cdu_context));
6176
bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6177
val = (4 << 24) + (0 << 12) + 1024;
6178
REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6180
bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6181
REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6182
/* enable context validation interrupt from CFC */
6183
REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6185
/* set the thresholds to prevent CFC/CDU race */
6186
REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6188
bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6190
if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6191
REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6193
bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6194
bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6196
/* Reset PCIE errors for debug */
6197
REG_WR(bp, 0x2814, 0xffffffff);
6198
REG_WR(bp, 0x3820, 0xffffffff);
6200
if (!CHIP_IS_E1x(bp)) {
6201
REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6202
(PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6203
PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6204
REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6205
(PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6206
PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6207
PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6208
REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6209
(PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6210
PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6211
PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6214
bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6215
if (!CHIP_IS_E1(bp)) {
6216
/* in E3 this done in per-port section */
6217
if (!CHIP_IS_E3(bp))
6218
REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6220
if (CHIP_IS_E1H(bp))
6221
/* not applicable for E2 (and above ...) */
6222
REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6224
if (CHIP_REV_IS_SLOW(bp))
6227
/* finish CFC init */
6228
val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6230
BNX2X_ERR("CFC LL_INIT failed\n");
6233
val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6235
BNX2X_ERR("CFC AC_INIT failed\n");
6238
val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6240
BNX2X_ERR("CFC CAM_INIT failed\n");
6243
REG_WR(bp, CFC_REG_DEBUG0, 0);
6245
if (CHIP_IS_E1(bp)) {
6246
/* read NIG statistic
6247
to see if this is our first up since powerup */
6248
bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6249
val = *bnx2x_sp(bp, wb_data[0]);
6251
/* do internal memory self test */
6252
if ((val == 0) && bnx2x_int_mem_test(bp)) {
6253
BNX2X_ERR("internal mem self test failed\n");
6258
bnx2x_setup_fan_failure_detection(bp);
6260
/* clear PXP2 attentions */
6261
REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6263
bnx2x_enable_blocks_attention(bp);
6264
bnx2x_enable_blocks_parity(bp);
6266
if (!BP_NOMCP(bp)) {
6267
if (CHIP_IS_E1x(bp))
6268
bnx2x__common_init_phy(bp);
6270
BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6276
* bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6278
* @bp: driver handle
6280
static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6282
int rc = bnx2x_init_hw_common(bp);
6287
/* In E2 2-PORT mode, same ext phy is used for the two paths */
6289
bnx2x__common_init_phy(bp);
6294
static int bnx2x_init_hw_port(struct bnx2x *bp)
6296
int port = BP_PORT(bp);
6297
int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6301
bnx2x__link_reset(bp);
6303
DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6305
REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6307
bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6308
bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6309
bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6311
/* Timers bug workaround: disables the pf_master bit in pglue at
6312
* common phase, we need to enable it here before any dmae access are
6313
* attempted. Therefore we manually added the enable-master to the
6314
* port phase (it also happens in the function phase)
6316
if (!CHIP_IS_E1x(bp))
6317
REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6319
bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6320
bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6321
bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6322
bnx2x_init_block(bp, BLOCK_QM, init_phase);
6324
bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6325
bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6326
bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6327
bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6329
/* QM cid (connection) count */
6330
bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6333
bnx2x_init_block(bp, BLOCK_TM, init_phase);
6334
REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6335
REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6338
bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6340
if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6341
bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6344
low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6345
else if (bp->dev->mtu > 4096) {
6346
if (bp->flags & ONE_PORT_FLAG)
6350
/* (24*1024 + val*4)/256 */
6351
low = 96 + (val/64) +
6352
((val % 64) ? 1 : 0);
6355
low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6356
high = low + 56; /* 14*1024/256 */
6357
REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6358
REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6361
if (CHIP_MODE_IS_4_PORT(bp))
6362
REG_WR(bp, (BP_PORT(bp) ?
6363
BRB1_REG_MAC_GUARANTIED_1 :
6364
BRB1_REG_MAC_GUARANTIED_0), 40);
6367
bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6368
if (CHIP_IS_E3B0(bp))
6369
/* Ovlan exists only if we are in multi-function +
6370
* switch-dependent mode, in switch-independent there
6371
* is no ovlan headers
6373
REG_WR(bp, BP_PORT(bp) ?
6374
PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6375
PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6376
(bp->path_has_ovlan ? 7 : 6));
6378
bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6379
bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6380
bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6381
bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6383
bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6384
bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6385
bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6386
bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6388
bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6389
bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6391
bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6393
if (CHIP_IS_E1x(bp)) {
6394
/* configure PBF to work without PAUSE mtu 9000 */
6395
REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6397
/* update threshold */
6398
REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6399
/* update init credit */
6400
REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6403
REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6405
REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6409
bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6411
bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6412
bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6414
if (CHIP_IS_E1(bp)) {
6415
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6416
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6418
bnx2x_init_block(bp, BLOCK_HC, init_phase);
6420
bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6422
bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6423
/* init aeu_mask_attn_func_0/1:
6424
* - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6425
* - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6426
* bits 4-7 are used for "per vn group attention" */
6427
val = IS_MF(bp) ? 0xF7 : 0x7;
6428
/* Enable DCBX attention for all but E1 */
6429
val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6430
REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6432
bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6434
if (!CHIP_IS_E1x(bp)) {
6435
/* Bit-map indicating which L2 hdrs may appear after the
6436
* basic Ethernet header
6438
REG_WR(bp, BP_PORT(bp) ?
6439
NIG_REG_P1_HDRS_AFTER_BASIC :
6440
NIG_REG_P0_HDRS_AFTER_BASIC,
6441
IS_MF_SD(bp) ? 7 : 6);
6444
REG_WR(bp, BP_PORT(bp) ?
6445
NIG_REG_LLH1_MF_MODE :
6446
NIG_REG_LLH_MF_MODE, IS_MF(bp));
6448
if (!CHIP_IS_E3(bp))
6449
REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6451
if (!CHIP_IS_E1(bp)) {
6452
/* 0x2 disable mf_ov, 0x1 enable */
6453
REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6454
(IS_MF_SD(bp) ? 0x1 : 0x2));
6456
if (!CHIP_IS_E1x(bp)) {
6458
switch (bp->mf_mode) {
6459
case MULTI_FUNCTION_SD:
6462
case MULTI_FUNCTION_SI:
6467
REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6468
NIG_REG_LLH0_CLS_TYPE), val);
6471
REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6472
REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6473
REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6478
/* If SPIO5 is set to generate interrupts, enable it for this port */
6479
val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6480
if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6481
u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6482
MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6483
val = REG_RD(bp, reg_addr);
6484
val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6485
REG_WR(bp, reg_addr, val);
6491
static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6496
reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6498
reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6500
bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6503
static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6505
bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6508
static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6510
u32 i, base = FUNC_ILT_BASE(func);
6511
for (i = base; i < base + ILT_PER_FUNC; i++)
6512
bnx2x_ilt_wr(bp, i, 0);
6515
static int bnx2x_init_hw_func(struct bnx2x *bp)
6517
int port = BP_PORT(bp);
6518
int func = BP_FUNC(bp);
6519
int init_phase = PHASE_PF0 + func;
6520
struct bnx2x_ilt *ilt = BP_ILT(bp);
6523
u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6524
int i, main_mem_width;
6526
DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6528
/* FLR cleanup - hmmm */
6529
if (!CHIP_IS_E1x(bp))
6530
bnx2x_pf_flr_clnup(bp);
6532
/* set MSI reconfigure capability */
6533
if (bp->common.int_block == INT_BLOCK_HC) {
6534
addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6535
val = REG_RD(bp, addr);
6536
val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6537
REG_WR(bp, addr, val);
6540
bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6541
bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6544
cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6546
for (i = 0; i < L2_ILT_LINES(bp); i++) {
6547
ilt->lines[cdu_ilt_start + i].page =
6548
bp->context.vcxt + (ILT_PAGE_CIDS * i);
6549
ilt->lines[cdu_ilt_start + i].page_mapping =
6550
bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6551
/* cdu ilt pages are allocated manually so there's no need to
6554
bnx2x_ilt_init_op(bp, INITOP_SET);
6557
bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6559
/* T1 hash bits value determines the T1 number of entries */
6560
REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6565
REG_WR(bp, PRS_REG_NIC_MODE, 1);
6566
#endif /* BCM_CNIC */
6568
if (!CHIP_IS_E1x(bp)) {
6569
u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6571
/* Turn on a single ISR mode in IGU if driver is going to use
6574
if (!(bp->flags & USING_MSIX_FLAG))
6575
pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6577
* Timers workaround bug: function init part.
6578
* Need to wait 20msec after initializing ILT,
6579
* needed to make sure there are no requests in
6580
* one of the PXP internal queues with "old" ILT addresses
6584
* Master enable - Due to WB DMAE writes performed before this
6585
* register is re-initialized as part of the regular function
6588
REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6589
/* Enable the function in IGU */
6590
REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6595
bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6597
if (!CHIP_IS_E1x(bp))
6598
REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6600
bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6601
bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6602
bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6603
bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6604
bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6605
bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6606
bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6607
bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6608
bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6609
bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6610
bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6611
bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6612
bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6614
if (!CHIP_IS_E1x(bp))
6615
REG_WR(bp, QM_REG_PF_EN, 1);
6617
if (!CHIP_IS_E1x(bp)) {
6618
REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6619
REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6620
REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6621
REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6623
bnx2x_init_block(bp, BLOCK_QM, init_phase);
6625
bnx2x_init_block(bp, BLOCK_TM, init_phase);
6626
bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6627
bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6628
bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6629
bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6630
bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6631
bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6632
bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6633
bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6634
bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6635
bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6636
if (!CHIP_IS_E1x(bp))
6637
REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6639
bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6641
bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6643
if (!CHIP_IS_E1x(bp))
6644
REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6647
REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6648
REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6651
bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6653
/* HC init per function */
6654
if (bp->common.int_block == INT_BLOCK_HC) {
6655
if (CHIP_IS_E1H(bp)) {
6656
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6658
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6659
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6661
bnx2x_init_block(bp, BLOCK_HC, init_phase);
6664
int num_segs, sb_idx, prod_offset;
6666
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6668
if (!CHIP_IS_E1x(bp)) {
6669
REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6670
REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6673
bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6675
if (!CHIP_IS_E1x(bp)) {
6679
* E2 mode: address 0-135 match to the mapping memory;
6680
* 136 - PF0 default prod; 137 - PF1 default prod;
6681
* 138 - PF2 default prod; 139 - PF3 default prod;
6682
* 140 - PF0 attn prod; 141 - PF1 attn prod;
6683
* 142 - PF2 attn prod; 143 - PF3 attn prod;
6686
* E1.5 mode - In backward compatible mode;
6687
* for non default SB; each even line in the memory
6688
* holds the U producer and each odd line hold
6689
* the C producer. The first 128 producers are for
6690
* NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6691
* producers are for the DSB for each PF.
6692
* Each PF has five segments: (the order inside each
6693
* segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6694
* 132-135 C prods; 136-139 X prods; 140-143 T prods;
6695
* 144-147 attn prods;
6697
/* non-default-status-blocks */
6698
num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6699
IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6700
for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6701
prod_offset = (bp->igu_base_sb + sb_idx) *
6704
for (i = 0; i < num_segs; i++) {
6705
addr = IGU_REG_PROD_CONS_MEMORY +
6706
(prod_offset + i) * 4;
6707
REG_WR(bp, addr, 0);
6709
/* send consumer update with value 0 */
6710
bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6711
USTORM_ID, 0, IGU_INT_NOP, 1);
6712
bnx2x_igu_clear_sb(bp,
6713
bp->igu_base_sb + sb_idx);
6716
/* default-status-blocks */
6717
num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6718
IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6720
if (CHIP_MODE_IS_4_PORT(bp))
6721
dsb_idx = BP_FUNC(bp);
6723
dsb_idx = BP_VN(bp);
6725
prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6726
IGU_BC_BASE_DSB_PROD + dsb_idx :
6727
IGU_NORM_BASE_DSB_PROD + dsb_idx);
6730
* igu prods come in chunks of E1HVN_MAX (4) -
6731
* does not matters what is the current chip mode
6733
for (i = 0; i < (num_segs * E1HVN_MAX);
6735
addr = IGU_REG_PROD_CONS_MEMORY +
6736
(prod_offset + i)*4;
6737
REG_WR(bp, addr, 0);
6739
/* send consumer update with 0 */
6740
if (CHIP_INT_MODE_IS_BC(bp)) {
6741
bnx2x_ack_sb(bp, bp->igu_dsb_id,
6742
USTORM_ID, 0, IGU_INT_NOP, 1);
6743
bnx2x_ack_sb(bp, bp->igu_dsb_id,
6744
CSTORM_ID, 0, IGU_INT_NOP, 1);
6745
bnx2x_ack_sb(bp, bp->igu_dsb_id,
6746
XSTORM_ID, 0, IGU_INT_NOP, 1);
6747
bnx2x_ack_sb(bp, bp->igu_dsb_id,
6748
TSTORM_ID, 0, IGU_INT_NOP, 1);
6749
bnx2x_ack_sb(bp, bp->igu_dsb_id,
6750
ATTENTION_ID, 0, IGU_INT_NOP, 1);
6752
bnx2x_ack_sb(bp, bp->igu_dsb_id,
6753
USTORM_ID, 0, IGU_INT_NOP, 1);
6754
bnx2x_ack_sb(bp, bp->igu_dsb_id,
6755
ATTENTION_ID, 0, IGU_INT_NOP, 1);
6757
bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6759
/* !!! these should become driver const once
6760
rf-tool supports split-68 const */
6761
REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6762
REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6763
REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6764
REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6765
REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6766
REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6770
/* Reset PCIE errors for debug */
6771
REG_WR(bp, 0x2114, 0xffffffff);
6772
REG_WR(bp, 0x2120, 0xffffffff);
6774
if (CHIP_IS_E1x(bp)) {
6775
main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6776
main_mem_base = HC_REG_MAIN_MEMORY +
6777
BP_PORT(bp) * (main_mem_size * 4);
6778
main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6781
val = REG_RD(bp, main_mem_prty_clr);
6783
DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6785
"function init (0x%x)!\n", val);
6787
/* Clear "false" parity errors in MSI-X table */
6788
for (i = main_mem_base;
6789
i < main_mem_base + main_mem_size * 4;
6790
i += main_mem_width) {
6791
bnx2x_read_dmae(bp, i, main_mem_width / 4);
6792
bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6793
i, main_mem_width / 4);
6795
/* Clear HC parity attention */
6796
REG_RD(bp, main_mem_prty_clr);
6799
#ifdef BNX2X_STOP_ON_ERROR
6800
/* Enable STORMs SP logging */
6801
REG_WR8(bp, BAR_USTRORM_INTMEM +
6802
USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6803
REG_WR8(bp, BAR_TSTRORM_INTMEM +
6804
TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6805
REG_WR8(bp, BAR_CSTRORM_INTMEM +
6806
CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6807
REG_WR8(bp, BAR_XSTRORM_INTMEM +
6808
XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6811
bnx2x_phy_probe(&bp->link_params);
6817
void bnx2x_free_mem(struct bnx2x *bp)
6820
bnx2x_free_fp_mem(bp);
6821
/* end of fastpath */
6823
BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6824
sizeof(struct host_sp_status_block));
6826
BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6827
bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6829
BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6830
sizeof(struct bnx2x_slowpath));
6832
BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6835
bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6837
BNX2X_FREE(bp->ilt->lines);
6840
if (!CHIP_IS_E1x(bp))
6841
BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6842
sizeof(struct host_hc_status_block_e2));
6844
BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6845
sizeof(struct host_hc_status_block_e1x));
6847
BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6850
BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6852
BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6853
BCM_PAGE_SIZE * NUM_EQ_PAGES);
6856
static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6860
/* number of eth_queues */
6861
u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6863
/* Total number of FW statistics requests =
6864
* 1 for port stats + 1 for PF stats + num_eth_queues */
6865
bp->fw_stats_num = 2 + num_queue_stats;
6868
/* Request is built from stats_query_header and an array of
6869
* stats_query_cmd_group each of which contains
6870
* STATS_QUERY_CMD_COUNT rules. The real number or requests is
6871
* configured in the stats_query_header.
6873
num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6874
(((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6876
bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6877
num_groups * sizeof(struct stats_query_cmd_group);
6879
/* Data for statistics requests + stats_conter
6881
* stats_counter holds per-STORM counters that are incremented
6882
* when STORM has finished with the current request.
6884
bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6885
sizeof(struct per_pf_stats) +
6886
sizeof(struct per_queue_stats) * num_queue_stats +
6887
sizeof(struct stats_counter);
6889
BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6890
bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6893
bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6894
bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6896
bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6897
((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6899
bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6900
bp->fw_stats_req_sz;
6904
BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6905
bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6910
int bnx2x_alloc_mem(struct bnx2x *bp)
6913
if (!CHIP_IS_E1x(bp))
6914
/* size = the status block + ramrod buffers */
6915
BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6916
sizeof(struct host_hc_status_block_e2));
6918
BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6919
sizeof(struct host_hc_status_block_e1x));
6921
/* allocate searcher T2 table */
6922
BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6926
BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6927
sizeof(struct host_sp_status_block));
6929
BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6930
sizeof(struct bnx2x_slowpath));
6932
/* Allocated memory for FW statistics */
6933
if (bnx2x_alloc_fw_stats_mem(bp))
6936
bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
6938
BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6941
BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6943
if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6946
/* Slow path ring */
6947
BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6950
BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6951
BCM_PAGE_SIZE * NUM_EQ_PAGES);
6955
/* need to be done at the end, since it's self adjusting to amount
6956
* of memory available for RSS queues
6958
if (bnx2x_alloc_fp_mem(bp))
6968
* Init service functions
6971
int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6972
struct bnx2x_vlan_mac_obj *obj, bool set,
6973
int mac_type, unsigned long *ramrod_flags)
6976
struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6978
memset(&ramrod_param, 0, sizeof(ramrod_param));
6980
/* Fill general parameters */
6981
ramrod_param.vlan_mac_obj = obj;
6982
ramrod_param.ramrod_flags = *ramrod_flags;
6984
/* Fill a user request section if needed */
6985
if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6986
memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6988
__set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6990
/* Set the command: ADD or DEL */
6992
ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6994
ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
6997
rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6999
BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7003
int bnx2x_del_all_macs(struct bnx2x *bp,
7004
struct bnx2x_vlan_mac_obj *mac_obj,
7005
int mac_type, bool wait_for_comp)
7008
unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7010
/* Wait for completion of requested */
7012
__set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7014
/* Set the mac type of addresses we want to clear */
7015
__set_bit(mac_type, &vlan_mac_flags);
7017
rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7019
BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7024
int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7026
unsigned long ramrod_flags = 0;
7028
DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7030
__set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7031
/* Eth MAC is set on RSS leading client (fp[0]) */
7032
return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7033
BNX2X_ETH_MAC, &ramrod_flags);
7036
int bnx2x_setup_leading(struct bnx2x *bp)
7038
return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7042
* bnx2x_set_int_mode - configure interrupt mode
7044
* @bp: driver handle
7046
* In case of MSI-X it will also try to enable MSI-X.
7048
static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
7052
bnx2x_enable_msi(bp);
7053
/* falling through... */
7055
bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7056
DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
7059
/* Set number of queues according to bp->multi_mode value */
7060
bnx2x_set_num_queues(bp);
7062
DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7065
/* if we can't use MSI-X we only need one fp,
7066
* so try to enable MSI-X with the requested number of fp's
7067
* and fallback to MSI or legacy INTx with one fp
7069
if (bnx2x_enable_msix(bp)) {
7070
/* failed to enable MSI-X */
7073
"Multi requested but failed to "
7074
"enable MSI-X (%d), "
7075
"set number of queues to %d\n",
7077
1 + NON_ETH_CONTEXT_USE);
7078
bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7080
/* Try to enable MSI */
7081
if (!(bp->flags & DISABLE_MSI_FLAG))
7082
bnx2x_enable_msi(bp);
7088
/* must be called prioir to any HW initializations */
7089
static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7091
return L2_ILT_LINES(bp);
7094
void bnx2x_ilt_set_info(struct bnx2x *bp)
7096
struct ilt_client_info *ilt_client;
7097
struct bnx2x_ilt *ilt = BP_ILT(bp);
7100
ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7101
DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7104
ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7105
ilt_client->client_num = ILT_CLIENT_CDU;
7106
ilt_client->page_size = CDU_ILT_PAGE_SZ;
7107
ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7108
ilt_client->start = line;
7109
line += bnx2x_cid_ilt_lines(bp);
7111
line += CNIC_ILT_LINES;
7113
ilt_client->end = line - 1;
7115
DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7116
"flags 0x%x, hw psz %d\n",
7119
ilt_client->page_size,
7121
ilog2(ilt_client->page_size >> 12));
7124
if (QM_INIT(bp->qm_cid_count)) {
7125
ilt_client = &ilt->clients[ILT_CLIENT_QM];
7126
ilt_client->client_num = ILT_CLIENT_QM;
7127
ilt_client->page_size = QM_ILT_PAGE_SZ;
7128
ilt_client->flags = 0;
7129
ilt_client->start = line;
7131
/* 4 bytes for each cid */
7132
line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7135
ilt_client->end = line - 1;
7137
DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7138
"flags 0x%x, hw psz %d\n",
7141
ilt_client->page_size,
7143
ilog2(ilt_client->page_size >> 12));
7147
ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7149
ilt_client->client_num = ILT_CLIENT_SRC;
7150
ilt_client->page_size = SRC_ILT_PAGE_SZ;
7151
ilt_client->flags = 0;
7152
ilt_client->start = line;
7153
line += SRC_ILT_LINES;
7154
ilt_client->end = line - 1;
7156
DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7157
"flags 0x%x, hw psz %d\n",
7160
ilt_client->page_size,
7162
ilog2(ilt_client->page_size >> 12));
7165
ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7169
ilt_client = &ilt->clients[ILT_CLIENT_TM];
7171
ilt_client->client_num = ILT_CLIENT_TM;
7172
ilt_client->page_size = TM_ILT_PAGE_SZ;
7173
ilt_client->flags = 0;
7174
ilt_client->start = line;
7175
line += TM_ILT_LINES;
7176
ilt_client->end = line - 1;
7178
DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7179
"flags 0x%x, hw psz %d\n",
7182
ilt_client->page_size,
7184
ilog2(ilt_client->page_size >> 12));
7187
ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7189
BUG_ON(line > ILT_MAX_LINES);
7193
* bnx2x_pf_q_prep_init - prepare INIT transition parameters
7195
* @bp: driver handle
7196
* @fp: pointer to fastpath
7197
* @init_params: pointer to parameters structure
7199
* parameters configured:
7200
* - HC configuration
7201
* - Queue's CDU context
7203
static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7204
struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7208
/* FCoE Queue uses Default SB, thus has no HC capabilities */
7209
if (!IS_FCOE_FP(fp)) {
7210
__set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7211
__set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7213
/* If HC is supporterd, enable host coalescing in the transition
7216
__set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7217
__set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7220
init_params->rx.hc_rate = bp->rx_ticks ?
7221
(1000000 / bp->rx_ticks) : 0;
7222
init_params->tx.hc_rate = bp->tx_ticks ?
7223
(1000000 / bp->tx_ticks) : 0;
7226
init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7230
* CQ index among the SB indices: FCoE clients uses the default
7231
* SB, therefore it's different.
7233
init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7234
init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7237
/* set maximum number of COSs supported by this queue */
7238
init_params->max_cos = fp->max_cos;
7240
DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n",
7241
fp->index, init_params->max_cos);
7243
/* set the context pointers queue object */
7244
for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7245
init_params->cxts[cos] =
7246
&bp->context.vcxt[fp->txdata[cos].cid].eth;
7249
int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7250
struct bnx2x_queue_state_params *q_params,
7251
struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7252
int tx_index, bool leading)
7254
memset(tx_only_params, 0, sizeof(*tx_only_params));
7256
/* Set the command */
7257
q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7259
/* Set tx-only QUEUE flags: don't zero statistics */
7260
tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7262
/* choose the index of the cid to send the slow path on */
7263
tx_only_params->cid_index = tx_index;
7265
/* Set general TX_ONLY_SETUP parameters */
7266
bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7268
/* Set Tx TX_ONLY_SETUP parameters */
7269
bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7271
DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7272
"cos %d, primary cid %d, cid %d, "
7273
"client id %d, sp-client id %d, flags %lx\n",
7274
tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7275
q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7276
tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7278
/* send the ramrod */
7279
return bnx2x_queue_state_change(bp, q_params);
7284
* bnx2x_setup_queue - setup queue
7286
* @bp: driver handle
7287
* @fp: pointer to fastpath
7288
* @leading: is leading
7290
* This function performs 2 steps in a Queue state machine
7291
* actually: 1) RESET->INIT 2) INIT->SETUP
7294
int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7297
struct bnx2x_queue_state_params q_params = {0};
7298
struct bnx2x_queue_setup_params *setup_params =
7299
&q_params.params.setup;
7300
struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7301
&q_params.params.tx_only;
7305
DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index);
7307
/* reset IGU state skip FCoE L2 queue */
7308
if (!IS_FCOE_FP(fp))
7309
bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7312
q_params.q_obj = &fp->q_obj;
7313
/* We want to wait for completion in this context */
7314
__set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7316
/* Prepare the INIT parameters */
7317
bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7319
/* Set the command */
7320
q_params.cmd = BNX2X_Q_CMD_INIT;
7322
/* Change the state to INIT */
7323
rc = bnx2x_queue_state_change(bp, &q_params);
7325
BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7329
DP(BNX2X_MSG_SP, "init complete\n");
7332
/* Now move the Queue to the SETUP state... */
7333
memset(setup_params, 0, sizeof(*setup_params));
7335
/* Set QUEUE flags */
7336
setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7338
/* Set general SETUP parameters */
7339
bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7340
FIRST_TX_COS_INDEX);
7342
bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7343
&setup_params->rxq_params);
7345
bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7346
FIRST_TX_COS_INDEX);
7348
/* Set the command */
7349
q_params.cmd = BNX2X_Q_CMD_SETUP;
7351
/* Change the state to SETUP */
7352
rc = bnx2x_queue_state_change(bp, &q_params);
7354
BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7358
/* loop through the relevant tx-only indices */
7359
for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7360
tx_index < fp->max_cos;
7363
/* prepare and send tx-only ramrod*/
7364
rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7365
tx_only_params, tx_index, leading);
7367
BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7368
fp->index, tx_index);
7376
static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7378
struct bnx2x_fastpath *fp = &bp->fp[index];
7379
struct bnx2x_fp_txdata *txdata;
7380
struct bnx2x_queue_state_params q_params = {0};
7383
DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid);
7385
q_params.q_obj = &fp->q_obj;
7386
/* We want to wait for completion in this context */
7387
__set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7390
/* close tx-only connections */
7391
for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7392
tx_index < fp->max_cos;
7395
/* ascertain this is a normal queue*/
7396
txdata = &fp->txdata[tx_index];
7398
DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n",
7401
/* send halt terminate on tx-only connection */
7402
q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7403
memset(&q_params.params.terminate, 0,
7404
sizeof(q_params.params.terminate));
7405
q_params.params.terminate.cid_index = tx_index;
7407
rc = bnx2x_queue_state_change(bp, &q_params);
7411
/* send halt terminate on tx-only connection */
7412
q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7413
memset(&q_params.params.cfc_del, 0,
7414
sizeof(q_params.params.cfc_del));
7415
q_params.params.cfc_del.cid_index = tx_index;
7416
rc = bnx2x_queue_state_change(bp, &q_params);
7420
/* Stop the primary connection: */
7421
/* ...halt the connection */
7422
q_params.cmd = BNX2X_Q_CMD_HALT;
7423
rc = bnx2x_queue_state_change(bp, &q_params);
7427
/* ...terminate the connection */
7428
q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7429
memset(&q_params.params.terminate, 0,
7430
sizeof(q_params.params.terminate));
7431
q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7432
rc = bnx2x_queue_state_change(bp, &q_params);
7435
/* ...delete cfc entry */
7436
q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7437
memset(&q_params.params.cfc_del, 0,
7438
sizeof(q_params.params.cfc_del));
7439
q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7440
return bnx2x_queue_state_change(bp, &q_params);
7444
static void bnx2x_reset_func(struct bnx2x *bp)
7446
int port = BP_PORT(bp);
7447
int func = BP_FUNC(bp);
7450
/* Disable the function in the FW */
7451
REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7452
REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7453
REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7454
REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7457
for_each_eth_queue(bp, i) {
7458
struct bnx2x_fastpath *fp = &bp->fp[i];
7459
REG_WR8(bp, BAR_CSTRORM_INTMEM +
7460
CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7466
REG_WR8(bp, BAR_CSTRORM_INTMEM +
7467
CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7471
REG_WR8(bp, BAR_CSTRORM_INTMEM +
7472
CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7475
for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7476
REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7480
if (bp->common.int_block == INT_BLOCK_HC) {
7481
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7482
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7484
REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7485
REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7489
/* Disable Timer scan */
7490
REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7492
* Wait for at least 10ms and up to 2 second for the timers scan to
7495
for (i = 0; i < 200; i++) {
7497
if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7502
bnx2x_clear_func_ilt(bp, func);
7504
/* Timers workaround bug for E2: if this is vnic-3,
7505
* we need to set the entire ilt range for this timers.
7507
if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7508
struct ilt_client_info ilt_cli;
7509
/* use dummy TM client */
7510
memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7512
ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7513
ilt_cli.client_num = ILT_CLIENT_TM;
7515
bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7518
/* this assumes that reset_port() called before reset_func()*/
7519
if (!CHIP_IS_E1x(bp))
7520
bnx2x_pf_disable(bp);
7525
static void bnx2x_reset_port(struct bnx2x *bp)
7527
int port = BP_PORT(bp);
7530
/* Reset physical Link */
7531
bnx2x__link_reset(bp);
7533
REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7535
/* Do not rcv packets to BRB */
7536
REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7537
/* Do not direct rcv packets that are not for MCP to the BRB */
7538
REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7539
NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7542
REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7545
/* Check for BRB port occupancy */
7546
val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7548
DP(NETIF_MSG_IFDOWN,
7549
"BRB1 is not empty %d blocks are occupied\n", val);
7551
/* TODO: Close Doorbell port? */
7554
static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7556
struct bnx2x_func_state_params func_params = {0};
7558
/* Prepare parameters for function state transitions */
7559
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7561
func_params.f_obj = &bp->func_obj;
7562
func_params.cmd = BNX2X_F_CMD_HW_RESET;
7564
func_params.params.hw_init.load_phase = load_code;
7566
return bnx2x_func_state_change(bp, &func_params);
7569
static inline int bnx2x_func_stop(struct bnx2x *bp)
7571
struct bnx2x_func_state_params func_params = {0};
7574
/* Prepare parameters for function state transitions */
7575
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7576
func_params.f_obj = &bp->func_obj;
7577
func_params.cmd = BNX2X_F_CMD_STOP;
7580
* Try to stop the function the 'good way'. If fails (in case
7581
* of a parity error during bnx2x_chip_cleanup()) and we are
7582
* not in a debug mode, perform a state transaction in order to
7583
* enable further HW_RESET transaction.
7585
rc = bnx2x_func_state_change(bp, &func_params);
7587
#ifdef BNX2X_STOP_ON_ERROR
7590
BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7592
__set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7593
return bnx2x_func_state_change(bp, &func_params);
7601
* bnx2x_send_unload_req - request unload mode from the MCP.
7603
* @bp: driver handle
7604
* @unload_mode: requested function's unload mode
7606
* Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7608
u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7611
int port = BP_PORT(bp);
7613
/* Select the UNLOAD request mode */
7614
if (unload_mode == UNLOAD_NORMAL)
7615
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7617
else if (bp->flags & NO_WOL_FLAG)
7618
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7621
u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7622
u8 *mac_addr = bp->dev->dev_addr;
7626
/* The mac address is written to entries 1-4 to
7627
* preserve entry 0 which is used by the PMF
7629
u8 entry = (BP_VN(bp) + 1)*8;
7631
val = (mac_addr[0] << 8) | mac_addr[1];
7632
EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7634
val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7635
(mac_addr[4] << 8) | mac_addr[5];
7636
EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7638
/* Enable the PME and clear the status */
7639
pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
7640
pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
7641
pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
7643
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7646
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7648
/* Send the request to the MCP */
7650
reset_code = bnx2x_fw_command(bp, reset_code, 0);
7652
int path = BP_PATH(bp);
7654
DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7656
path, load_count[path][0], load_count[path][1],
7657
load_count[path][2]);
7658
load_count[path][0]--;
7659
load_count[path][1 + port]--;
7660
DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7662
path, load_count[path][0], load_count[path][1],
7663
load_count[path][2]);
7664
if (load_count[path][0] == 0)
7665
reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7666
else if (load_count[path][1 + port] == 0)
7667
reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7669
reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7676
* bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7678
* @bp: driver handle
7680
void bnx2x_send_unload_done(struct bnx2x *bp)
7682
/* Report UNLOAD_DONE to MCP */
7684
bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7687
static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7690
int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7696
* (assumption: No Attention from MCP at this stage)
7697
* PMF probably in the middle of TXdisable/enable transaction
7698
* 1. Sync IRS for default SB
7699
* 2. Sync SP queue - this guarantes us that attention handling started
7700
* 3. Wait, that TXdisable/enable transaction completes
7702
* 1+2 guranty that if DCBx attention was scheduled it already changed
7703
* pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7704
* received complettion for the transaction the state is TX_STOPPED.
7705
* State will return to STARTED after completion of TX_STOPPED-->STARTED
7709
/* make sure default SB ISR is done */
7711
synchronize_irq(bp->msix_table[0].vector);
7713
synchronize_irq(bp->pdev->irq);
7715
flush_workqueue(bnx2x_wq);
7717
while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7718
BNX2X_F_STATE_STARTED && tout--)
7721
if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7722
BNX2X_F_STATE_STARTED) {
7723
#ifdef BNX2X_STOP_ON_ERROR
7727
* Failed to complete the transaction in a "good way"
7728
* Force both transactions with CLR bit
7730
struct bnx2x_func_state_params func_params = {0};
7732
DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7733
"Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7735
func_params.f_obj = &bp->func_obj;
7736
__set_bit(RAMROD_DRV_CLR_ONLY,
7737
&func_params.ramrod_flags);
7739
/* STARTED-->TX_ST0PPED */
7740
func_params.cmd = BNX2X_F_CMD_TX_STOP;
7741
bnx2x_func_state_change(bp, &func_params);
7743
/* TX_ST0PPED-->STARTED */
7744
func_params.cmd = BNX2X_F_CMD_TX_START;
7745
return bnx2x_func_state_change(bp, &func_params);
7752
void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7754
int port = BP_PORT(bp);
7757
struct bnx2x_mcast_ramrod_params rparam = {0};
7760
/* Wait until tx fastpath tasks complete */
7761
for_each_tx_queue(bp, i) {
7762
struct bnx2x_fastpath *fp = &bp->fp[i];
7764
for_each_cos_in_tx_queue(fp, cos)
7765
rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7766
#ifdef BNX2X_STOP_ON_ERROR
7772
/* Give HW time to discard old tx messages */
7773
usleep_range(1000, 1000);
7775
/* Clean all ETH MACs */
7776
rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7778
BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7780
/* Clean up UC list */
7781
rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7784
BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7788
if (!CHIP_IS_E1(bp))
7789
REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7791
/* Set "drop all" (stop Rx).
7792
* We need to take a netif_addr_lock() here in order to prevent
7793
* a race between the completion code and this code.
7795
netif_addr_lock_bh(bp->dev);
7796
/* Schedule the rx_mode command */
7797
if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7798
set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7800
bnx2x_set_storm_rx_mode(bp);
7802
/* Cleanup multicast configuration */
7803
rparam.mcast_obj = &bp->mcast_obj;
7804
rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7806
BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7808
netif_addr_unlock_bh(bp->dev);
7813
* Send the UNLOAD_REQUEST to the MCP. This will return if
7814
* this function should perform FUNC, PORT or COMMON HW
7817
reset_code = bnx2x_send_unload_req(bp, unload_mode);
7820
* (assumption: No Attention from MCP at this stage)
7821
* PMF probably in the middle of TXdisable/enable transaction
7823
rc = bnx2x_func_wait_started(bp);
7825
BNX2X_ERR("bnx2x_func_wait_started failed\n");
7826
#ifdef BNX2X_STOP_ON_ERROR
7831
/* Close multi and leading connections
7832
* Completions for ramrods are collected in a synchronous way
7834
for_each_queue(bp, i)
7835
if (bnx2x_stop_queue(bp, i))
7836
#ifdef BNX2X_STOP_ON_ERROR
7841
/* If SP settings didn't get completed so far - something
7842
* very wrong has happen.
7844
if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7845
BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7847
#ifndef BNX2X_STOP_ON_ERROR
7850
rc = bnx2x_func_stop(bp);
7852
BNX2X_ERR("Function stop failed!\n");
7853
#ifdef BNX2X_STOP_ON_ERROR
7858
/* Disable HW interrupts, NAPI */
7859
bnx2x_netif_stop(bp, 1);
7864
/* Reset the chip */
7865
rc = bnx2x_reset_hw(bp, reset_code);
7867
BNX2X_ERR("HW_RESET failed\n");
7870
/* Report UNLOAD_DONE to MCP */
7871
bnx2x_send_unload_done(bp);
7874
void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7878
DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7880
if (CHIP_IS_E1(bp)) {
7881
int port = BP_PORT(bp);
7882
u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7883
MISC_REG_AEU_MASK_ATTN_FUNC_0;
7885
val = REG_RD(bp, addr);
7887
REG_WR(bp, addr, val);
7889
val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7890
val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7891
MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7892
REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7896
/* Close gates #2, #3 and #4: */
7897
static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7901
/* Gates #2 and #4a are closed/opened for "not E1" only */
7902
if (!CHIP_IS_E1(bp)) {
7904
REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7906
REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7910
if (CHIP_IS_E1x(bp)) {
7911
/* Prevent interrupts from HC on both ports */
7912
val = REG_RD(bp, HC_REG_CONFIG_1);
7913
REG_WR(bp, HC_REG_CONFIG_1,
7914
(!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7915
(val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7917
val = REG_RD(bp, HC_REG_CONFIG_0);
7918
REG_WR(bp, HC_REG_CONFIG_0,
7919
(!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7920
(val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7922
/* Prevent incomming interrupts in IGU */
7923
val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7925
REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7927
(val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7928
(val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7931
DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7932
close ? "closing" : "opening");
7936
#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7938
static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7940
/* Do some magic... */
7941
u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7942
*magic_val = val & SHARED_MF_CLP_MAGIC;
7943
MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7947
* bnx2x_clp_reset_done - restore the value of the `magic' bit.
7949
* @bp: driver handle
7950
* @magic_val: old value of the `magic' bit.
7952
static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7954
/* Restore the `magic' bit value... */
7955
u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7956
MF_CFG_WR(bp, shared_mf_config.clp_mb,
7957
(val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7961
* bnx2x_reset_mcp_prep - prepare for MCP reset.
7963
* @bp: driver handle
7964
* @magic_val: old value of 'magic' bit.
7966
* Takes care of CLP configurations.
7968
static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7971
u32 validity_offset;
7973
DP(NETIF_MSG_HW, "Starting\n");
7975
/* Set `magic' bit in order to save MF config */
7976
if (!CHIP_IS_E1(bp))
7977
bnx2x_clp_reset_prep(bp, magic_val);
7979
/* Get shmem offset */
7980
shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7981
validity_offset = offsetof(struct shmem_region, validity_map[0]);
7983
/* Clear validity map flags */
7985
REG_WR(bp, shmem + validity_offset, 0);
7988
#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7989
#define MCP_ONE_TIMEOUT 100 /* 100 ms */
7992
* bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7994
* @bp: driver handle
7996
static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7998
/* special handling for emulation and FPGA,
7999
wait 10 times longer */
8000
if (CHIP_REV_IS_SLOW(bp))
8001
msleep(MCP_ONE_TIMEOUT*10);
8003
msleep(MCP_ONE_TIMEOUT);
8007
* initializes bp->common.shmem_base and waits for validity signature to appear
8009
static int bnx2x_init_shmem(struct bnx2x *bp)
8015
bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8016
if (bp->common.shmem_base) {
8017
val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8018
if (val & SHR_MEM_VALIDITY_MB)
8022
bnx2x_mcp_wait_one(bp);
8024
} while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8026
BNX2X_ERR("BAD MCP validity signature\n");
8031
static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8033
int rc = bnx2x_init_shmem(bp);
8035
/* Restore the `magic' bit value */
8036
if (!CHIP_IS_E1(bp))
8037
bnx2x_clp_reset_done(bp, magic_val);
8042
static void bnx2x_pxp_prep(struct bnx2x *bp)
8044
if (!CHIP_IS_E1(bp)) {
8045
REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8046
REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8052
* Reset the whole chip except for:
8054
* - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8057
* - MISC (including AEU)
8061
static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8063
u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8064
u32 global_bits2, stay_reset2;
8067
* Bits that have to be set in reset_mask2 if we want to reset 'global'
8068
* (per chip) blocks.
8071
MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8072
MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8074
/* Don't reset the following blocks */
8076
MISC_REGISTERS_RESET_REG_1_RST_HC |
8077
MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8078
MISC_REGISTERS_RESET_REG_1_RST_PXP;
8081
MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8082
MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8083
MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8084
MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8085
MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8086
MISC_REGISTERS_RESET_REG_2_RST_GRC |
8087
MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8088
MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8089
MISC_REGISTERS_RESET_REG_2_RST_ATC |
8090
MISC_REGISTERS_RESET_REG_2_PGLC;
8093
* Keep the following blocks in reset:
8094
* - all xxMACs are handled by the bnx2x_link code.
8097
MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8098
MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8099
MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8100
MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8101
MISC_REGISTERS_RESET_REG_2_UMAC0 |
8102
MISC_REGISTERS_RESET_REG_2_UMAC1 |
8103
MISC_REGISTERS_RESET_REG_2_XMAC |
8104
MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8106
/* Full reset masks according to the chip */
8107
reset_mask1 = 0xffffffff;
8110
reset_mask2 = 0xffff;
8111
else if (CHIP_IS_E1H(bp))
8112
reset_mask2 = 0x1ffff;
8113
else if (CHIP_IS_E2(bp))
8114
reset_mask2 = 0xfffff;
8115
else /* CHIP_IS_E3 */
8116
reset_mask2 = 0x3ffffff;
8118
/* Don't reset global blocks unless we need to */
8120
reset_mask2 &= ~global_bits2;
8123
* In case of attention in the QM, we need to reset PXP
8124
* (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8125
* because otherwise QM reset would release 'close the gates' shortly
8126
* before resetting the PXP, then the PSWRQ would send a write
8127
* request to PGLUE. Then when PXP is reset, PGLUE would try to
8128
* read the payload data from PSWWR, but PSWWR would not
8129
* respond. The write queue in PGLUE would stuck, dmae commands
8130
* would not return. Therefore it's important to reset the second
8131
* reset register (containing the
8132
* MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8133
* first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8136
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8137
reset_mask2 & (~not_reset_mask2));
8139
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8140
reset_mask1 & (~not_reset_mask1));
8145
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8146
reset_mask2 & (~stay_reset2));
8151
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8156
* bnx2x_er_poll_igu_vq - poll for pending writes bit.
8157
* It should get cleared in no more than 1s.
8159
* @bp: driver handle
8161
* It should get cleared in no more than 1s. Returns 0 if
8162
* pending writes bit gets cleared.
8164
static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8170
pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8175
usleep_range(1000, 1000);
8176
} while (cnt-- > 0);
8179
BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8187
static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8191
u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8194
/* Empty the Tetris buffer, wait for 1s */
8196
sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8197
blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8198
port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8199
port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8200
pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8201
if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8202
((port_is_idle_0 & 0x1) == 0x1) &&
8203
((port_is_idle_1 & 0x1) == 0x1) &&
8204
(pgl_exp_rom2 == 0xffffffff))
8206
usleep_range(1000, 1000);
8207
} while (cnt-- > 0);
8210
DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8212
" outstanding read requests after 1s!\n");
8213
DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8214
" port_is_idle_0=0x%08x,"
8215
" port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8216
sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8223
/* Close gates #2, #3 and #4 */
8224
bnx2x_set_234_gates(bp, true);
8226
/* Poll for IGU VQs for 57712 and newer chips */
8227
if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8231
/* TBD: Indicate that "process kill" is in progress to MCP */
8233
/* Clear "unprepared" bit */
8234
REG_WR(bp, MISC_REG_UNPREPARED, 0);
8237
/* Make sure all is written to the chip before the reset */
8240
/* Wait for 1ms to empty GLUE and PCI-E core queues,
8241
* PSWHST, GRC and PSWRD Tetris buffer.
8243
usleep_range(1000, 1000);
8245
/* Prepare to chip reset: */
8248
bnx2x_reset_mcp_prep(bp, &val);
8254
/* reset the chip */
8255
bnx2x_process_kill_chip_reset(bp, global);
8258
/* Recover after reset: */
8260
if (global && bnx2x_reset_mcp_comp(bp, val))
8263
/* TBD: Add resetting the NO_MCP mode DB here */
8268
/* Open the gates #2, #3 and #4 */
8269
bnx2x_set_234_gates(bp, false);
8271
/* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8272
* reset state, re-enable attentions. */
8277
int bnx2x_leader_reset(struct bnx2x *bp)
8280
bool global = bnx2x_reset_is_global(bp);
8282
/* Try to recover after the failure */
8283
if (bnx2x_process_kill(bp, global)) {
8284
netdev_err(bp->dev, "Something bad had happen on engine %d! "
8285
"Aii!\n", BP_PATH(bp));
8287
goto exit_leader_reset;
8291
* Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8294
bnx2x_set_reset_done(bp);
8296
bnx2x_clear_reset_global(bp);
8300
bnx2x_release_leader_lock(bp);
8305
static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8307
netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8309
/* Disconnect this device */
8310
netif_device_detach(bp->dev);
8313
* Block ifup for all function on this engine until "process kill"
8316
bnx2x_set_reset_in_progress(bp);
8318
/* Shut down the power */
8319
bnx2x_set_power_state(bp, PCI_D3hot);
8321
bp->recovery_state = BNX2X_RECOVERY_FAILED;
8327
* Assumption: runs under rtnl lock. This together with the fact
8328
* that it's called only from bnx2x_sp_rtnl() ensure that it
8329
* will never be called when netif_running(bp->dev) is false.
8331
static void bnx2x_parity_recover(struct bnx2x *bp)
8333
bool global = false;
8335
DP(NETIF_MSG_HW, "Handling parity\n");
8337
switch (bp->recovery_state) {
8338
case BNX2X_RECOVERY_INIT:
8339
DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8340
bnx2x_chk_parity_attn(bp, &global, false);
8342
/* Try to get a LEADER_LOCK HW lock */
8343
if (bnx2x_trylock_leader_lock(bp)) {
8344
bnx2x_set_reset_in_progress(bp);
8346
* Check if there is a global attention and if
8347
* there was a global attention, set the global
8352
bnx2x_set_reset_global(bp);
8357
/* Stop the driver */
8358
/* If interface has been removed - break */
8359
if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8362
bp->recovery_state = BNX2X_RECOVERY_WAIT;
8365
* Reset MCP command sequence number and MCP mail box
8366
* sequence as we are going to reset the MCP.
8370
bp->fw_drv_pulse_wr_seq = 0;
8373
/* Ensure "is_leader", MCP command sequence and
8374
* "recovery_state" update values are seen on other
8380
case BNX2X_RECOVERY_WAIT:
8381
DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8382
if (bp->is_leader) {
8383
int other_engine = BP_PATH(bp) ? 0 : 1;
8384
u32 other_load_counter =
8385
bnx2x_get_load_cnt(bp, other_engine);
8387
bnx2x_get_load_cnt(bp, BP_PATH(bp));
8388
global = bnx2x_reset_is_global(bp);
8391
* In case of a parity in a global block, let
8392
* the first leader that performs a
8393
* leader_reset() reset the global blocks in
8394
* order to clear global attentions. Otherwise
8395
* the the gates will remain closed for that
8399
(global && other_load_counter)) {
8400
/* Wait until all other functions get
8403
schedule_delayed_work(&bp->sp_rtnl_task,
8407
/* If all other functions got down -
8408
* try to bring the chip back to
8409
* normal. In any case it's an exit
8410
* point for a leader.
8412
if (bnx2x_leader_reset(bp)) {
8413
bnx2x_recovery_failed(bp);
8417
/* If we are here, means that the
8418
* leader has succeeded and doesn't
8419
* want to be a leader any more. Try
8420
* to continue as a none-leader.
8424
} else { /* non-leader */
8425
if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8426
/* Try to get a LEADER_LOCK HW lock as
8427
* long as a former leader may have
8428
* been unloaded by the user or
8429
* released a leadership by another
8432
if (bnx2x_trylock_leader_lock(bp)) {
8433
/* I'm a leader now! Restart a
8440
schedule_delayed_work(&bp->sp_rtnl_task,
8446
* If there was a global attention, wait
8447
* for it to be cleared.
8449
if (bnx2x_reset_is_global(bp)) {
8450
schedule_delayed_work(
8456
if (bnx2x_nic_load(bp, LOAD_NORMAL))
8457
bnx2x_recovery_failed(bp);
8459
bp->recovery_state =
8460
BNX2X_RECOVERY_DONE;
8473
/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8474
* scheduled on a general queue in order to prevent a dead lock.
8476
static void bnx2x_sp_rtnl_task(struct work_struct *work)
8478
struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8482
if (!netif_running(bp->dev))
8485
/* if stop on error is defined no recovery flows should be executed */
8486
#ifdef BNX2X_STOP_ON_ERROR
8487
BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8488
"so reset not done to allow debug dump,\n"
8489
"you will need to reboot when done\n");
8490
goto sp_rtnl_not_reset;
8493
if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8495
* Clear all pending SP commands as we are going to reset the
8498
bp->sp_rtnl_state = 0;
8501
bnx2x_parity_recover(bp);
8506
if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8508
* Clear all pending SP commands as we are going to reset the
8511
bp->sp_rtnl_state = 0;
8514
bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8515
bnx2x_nic_load(bp, LOAD_NORMAL);
8519
#ifdef BNX2X_STOP_ON_ERROR
8522
if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8523
bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8529
/* end of nic load/unload */
8531
static void bnx2x_period_task(struct work_struct *work)
8533
struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8535
if (!netif_running(bp->dev))
8536
goto period_task_exit;
8538
if (CHIP_REV_IS_SLOW(bp)) {
8539
BNX2X_ERR("period task called on emulation, ignoring\n");
8540
goto period_task_exit;
8543
bnx2x_acquire_phy_lock(bp);
8545
* The barrier is needed to ensure the ordering between the writing to
8546
* the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8551
bnx2x_period_func(&bp->link_params, &bp->link_vars);
8553
/* Re-queue task in 1 sec */
8554
queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8557
bnx2x_release_phy_lock(bp);
8563
* Init service functions
8566
static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8568
u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8569
u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8570
return base + (BP_ABS_FUNC(bp)) * stride;
8573
static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8575
u32 reg = bnx2x_get_pretend_reg(bp);
8577
/* Flush all outstanding writes */
8580
/* Pretend to be function 0 */
8582
REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8584
/* From now we are in the "like-E1" mode */
8585
bnx2x_int_disable(bp);
8587
/* Flush all outstanding writes */
8590
/* Restore the original function */
8591
REG_WR(bp, reg, BP_ABS_FUNC(bp));
8595
static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8598
bnx2x_int_disable(bp);
8600
bnx2x_undi_int_disable_e1h(bp);
8603
static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8607
/* Check if there is any driver already loaded */
8608
val = REG_RD(bp, MISC_REG_UNPREPARED);
8611
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8613
* Check if it is the UNDI driver
8614
* UNDI driver initializes CID offset for normal bell to 0x7
8616
val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8618
u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8619
/* save our pf_num */
8620
int orig_pf_num = bp->pf_num;
8622
u32 swap_en, swap_val, value;
8624
/* clear the UNDI indication */
8625
REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8627
BNX2X_DEV_INFO("UNDI is active! reset device\n");
8629
/* try unload UNDI on port 0 */
8632
(SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8633
DRV_MSG_SEQ_NUMBER_MASK);
8634
reset_code = bnx2x_fw_command(bp, reset_code, 0);
8636
/* if UNDI is loaded on the other port */
8637
if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8639
/* send "DONE" for previous unload */
8640
bnx2x_fw_command(bp,
8641
DRV_MSG_CODE_UNLOAD_DONE, 0);
8643
/* unload UNDI on port 1 */
8646
(SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8647
DRV_MSG_SEQ_NUMBER_MASK);
8648
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8650
bnx2x_fw_command(bp, reset_code, 0);
8653
bnx2x_undi_int_disable(bp);
8656
/* close input traffic and wait for it */
8657
/* Do not rcv packets to BRB */
8658
REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8659
NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8660
/* Do not direct rcv packets that are not for MCP to
8662
REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8663
NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8665
REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8666
MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8669
/* save NIG port swap info */
8670
swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8671
swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8674
GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8678
if (CHIP_IS_E3(bp)) {
8679
value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8680
value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8684
GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8687
/* take the NIG out of reset and restore swap values */
8689
GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8690
MISC_REGISTERS_RESET_REG_1_RST_NIG);
8691
REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8692
REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8694
/* send unload done to the MCP */
8695
bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8697
/* restore our func and fw_seq */
8698
bp->pf_num = orig_pf_num;
8700
(SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8701
DRV_MSG_SEQ_NUMBER_MASK);
8704
/* now it's safe to release the lock */
8705
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8709
static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8711
u32 val, val2, val3, val4, id;
8714
/* Get the chip revision id and number. */
8715
/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8716
val = REG_RD(bp, MISC_REG_CHIP_NUM);
8717
id = ((val & 0xffff) << 16);
8718
val = REG_RD(bp, MISC_REG_CHIP_REV);
8719
id |= ((val & 0xf) << 12);
8720
val = REG_RD(bp, MISC_REG_CHIP_METAL);
8721
id |= ((val & 0xff) << 4);
8722
val = REG_RD(bp, MISC_REG_BOND_ID);
8724
bp->common.chip_id = id;
8726
/* Set doorbell size */
8727
bp->db_size = (1 << BNX2X_DB_SHIFT);
8729
if (!CHIP_IS_E1x(bp)) {
8730
val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8732
val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8734
val = (val >> 1) & 1;
8735
BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8737
bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8740
if (CHIP_MODE_IS_4_PORT(bp))
8741
bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8743
bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8745
bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8746
bp->pfid = bp->pf_num; /* 0..7 */
8749
bp->link_params.chip_id = bp->common.chip_id;
8750
BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8752
val = (REG_RD(bp, 0x2874) & 0x55);
8753
if ((bp->common.chip_id & 0x1) ||
8754
(CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8755
bp->flags |= ONE_PORT_FLAG;
8756
BNX2X_DEV_INFO("single port device\n");
8759
val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8760
bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8761
(val & MCPR_NVM_CFG4_FLASH_SIZE));
8762
BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8763
bp->common.flash_size, bp->common.flash_size);
8765
bnx2x_init_shmem(bp);
8769
bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8770
MISC_REG_GENERIC_CR_1 :
8771
MISC_REG_GENERIC_CR_0));
8773
bp->link_params.shmem_base = bp->common.shmem_base;
8774
bp->link_params.shmem2_base = bp->common.shmem2_base;
8775
BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8776
bp->common.shmem_base, bp->common.shmem2_base);
8778
if (!bp->common.shmem_base) {
8779
BNX2X_DEV_INFO("MCP not active\n");
8780
bp->flags |= NO_MCP_FLAG;
8784
bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8785
BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8787
bp->link_params.hw_led_mode = ((bp->common.hw_config &
8788
SHARED_HW_CFG_LED_MODE_MASK) >>
8789
SHARED_HW_CFG_LED_MODE_SHIFT);
8791
bp->link_params.feature_config_flags = 0;
8792
val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8793
if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8794
bp->link_params.feature_config_flags |=
8795
FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8797
bp->link_params.feature_config_flags &=
8798
~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8800
val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8801
bp->common.bc_ver = val;
8802
BNX2X_DEV_INFO("bc_ver %X\n", val);
8803
if (val < BNX2X_BC_VER) {
8804
/* for now only warn
8805
* later we might need to enforce this */
8806
BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8807
"please upgrade BC\n", BNX2X_BC_VER, val);
8809
bp->link_params.feature_config_flags |=
8810
(val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8811
FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8813
bp->link_params.feature_config_flags |=
8814
(val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8815
FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8817
bp->link_params.feature_config_flags |=
8818
(val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8819
FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8821
pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8822
bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8824
BNX2X_DEV_INFO("%sWoL capable\n",
8825
(bp->flags & NO_WOL_FLAG) ? "not " : "");
8827
val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8828
val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8829
val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8830
val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8832
dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8833
val, val2, val3, val4);
8836
#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8837
#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8839
static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8841
int pfid = BP_FUNC(bp);
8844
u8 fid, igu_sb_cnt = 0;
8846
bp->igu_base_sb = 0xff;
8847
if (CHIP_INT_MODE_IS_BC(bp)) {
8849
igu_sb_cnt = bp->igu_sb_cnt;
8850
bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8853
bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8854
(CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8859
/* IGU in normal mode - read CAM */
8860
for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8862
val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8863
if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8866
if ((fid & IGU_FID_ENCODE_IS_PF)) {
8867
if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8869
if (IGU_VEC(val) == 0)
8870
/* default status block */
8871
bp->igu_dsb_id = igu_sb_id;
8873
if (bp->igu_base_sb == 0xff)
8874
bp->igu_base_sb = igu_sb_id;
8880
#ifdef CONFIG_PCI_MSI
8882
* It's expected that number of CAM entries for this functions is equal
8883
* to the number evaluated based on the MSI-X table size. We want a
8884
* harsh warning if these values are different!
8886
WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8889
if (igu_sb_cnt == 0)
8890
BNX2X_ERR("CAM configuration error\n");
8893
static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8896
int cfg_size = 0, idx, port = BP_PORT(bp);
8898
/* Aggregation of supported attributes of all external phys */
8899
bp->port.supported[0] = 0;
8900
bp->port.supported[1] = 0;
8901
switch (bp->link_params.num_phys) {
8903
bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8907
bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8911
if (bp->link_params.multi_phy_config &
8912
PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8913
bp->port.supported[1] =
8914
bp->link_params.phy[EXT_PHY1].supported;
8915
bp->port.supported[0] =
8916
bp->link_params.phy[EXT_PHY2].supported;
8918
bp->port.supported[0] =
8919
bp->link_params.phy[EXT_PHY1].supported;
8920
bp->port.supported[1] =
8921
bp->link_params.phy[EXT_PHY2].supported;
8927
if (!(bp->port.supported[0] || bp->port.supported[1])) {
8928
BNX2X_ERR("NVRAM config error. BAD phy config."
8929
"PHY1 config 0x%x, PHY2 config 0x%x\n",
8931
dev_info.port_hw_config[port].external_phy_config),
8933
dev_info.port_hw_config[port].external_phy_config2));
8938
bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8940
switch (switch_cfg) {
8942
bp->port.phy_addr = REG_RD(
8943
bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8945
case SWITCH_CFG_10G:
8946
bp->port.phy_addr = REG_RD(
8947
bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8950
BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8951
bp->port.link_config[0]);
8955
BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8956
/* mask what we support according to speed_cap_mask per configuration */
8957
for (idx = 0; idx < cfg_size; idx++) {
8958
if (!(bp->link_params.speed_cap_mask[idx] &
8959
PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8960
bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8962
if (!(bp->link_params.speed_cap_mask[idx] &
8963
PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8964
bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8966
if (!(bp->link_params.speed_cap_mask[idx] &
8967
PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8968
bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8970
if (!(bp->link_params.speed_cap_mask[idx] &
8971
PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8972
bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8974
if (!(bp->link_params.speed_cap_mask[idx] &
8975
PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8976
bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8977
SUPPORTED_1000baseT_Full);
8979
if (!(bp->link_params.speed_cap_mask[idx] &
8980
PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8981
bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8983
if (!(bp->link_params.speed_cap_mask[idx] &
8984
PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8985
bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8989
BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8990
bp->port.supported[1]);
8993
static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8995
u32 link_config, idx, cfg_size = 0;
8996
bp->port.advertising[0] = 0;
8997
bp->port.advertising[1] = 0;
8998
switch (bp->link_params.num_phys) {
9007
for (idx = 0; idx < cfg_size; idx++) {
9008
bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9009
link_config = bp->port.link_config[idx];
9010
switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9011
case PORT_FEATURE_LINK_SPEED_AUTO:
9012
if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9013
bp->link_params.req_line_speed[idx] =
9015
bp->port.advertising[idx] |=
9016
bp->port.supported[idx];
9018
/* force 10G, no AN */
9019
bp->link_params.req_line_speed[idx] =
9021
bp->port.advertising[idx] |=
9022
(ADVERTISED_10000baseT_Full |
9028
case PORT_FEATURE_LINK_SPEED_10M_FULL:
9029
if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9030
bp->link_params.req_line_speed[idx] =
9032
bp->port.advertising[idx] |=
9033
(ADVERTISED_10baseT_Full |
9036
BNX2X_ERR("NVRAM config error. "
9037
"Invalid link_config 0x%x"
9038
" speed_cap_mask 0x%x\n",
9040
bp->link_params.speed_cap_mask[idx]);
9045
case PORT_FEATURE_LINK_SPEED_10M_HALF:
9046
if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9047
bp->link_params.req_line_speed[idx] =
9049
bp->link_params.req_duplex[idx] =
9051
bp->port.advertising[idx] |=
9052
(ADVERTISED_10baseT_Half |
9055
BNX2X_ERR("NVRAM config error. "
9056
"Invalid link_config 0x%x"
9057
" speed_cap_mask 0x%x\n",
9059
bp->link_params.speed_cap_mask[idx]);
9064
case PORT_FEATURE_LINK_SPEED_100M_FULL:
9065
if (bp->port.supported[idx] &
9066
SUPPORTED_100baseT_Full) {
9067
bp->link_params.req_line_speed[idx] =
9069
bp->port.advertising[idx] |=
9070
(ADVERTISED_100baseT_Full |
9073
BNX2X_ERR("NVRAM config error. "
9074
"Invalid link_config 0x%x"
9075
" speed_cap_mask 0x%x\n",
9077
bp->link_params.speed_cap_mask[idx]);
9082
case PORT_FEATURE_LINK_SPEED_100M_HALF:
9083
if (bp->port.supported[idx] &
9084
SUPPORTED_100baseT_Half) {
9085
bp->link_params.req_line_speed[idx] =
9087
bp->link_params.req_duplex[idx] =
9089
bp->port.advertising[idx] |=
9090
(ADVERTISED_100baseT_Half |
9093
BNX2X_ERR("NVRAM config error. "
9094
"Invalid link_config 0x%x"
9095
" speed_cap_mask 0x%x\n",
9097
bp->link_params.speed_cap_mask[idx]);
9102
case PORT_FEATURE_LINK_SPEED_1G:
9103
if (bp->port.supported[idx] &
9104
SUPPORTED_1000baseT_Full) {
9105
bp->link_params.req_line_speed[idx] =
9107
bp->port.advertising[idx] |=
9108
(ADVERTISED_1000baseT_Full |
9111
BNX2X_ERR("NVRAM config error. "
9112
"Invalid link_config 0x%x"
9113
" speed_cap_mask 0x%x\n",
9115
bp->link_params.speed_cap_mask[idx]);
9120
case PORT_FEATURE_LINK_SPEED_2_5G:
9121
if (bp->port.supported[idx] &
9122
SUPPORTED_2500baseX_Full) {
9123
bp->link_params.req_line_speed[idx] =
9125
bp->port.advertising[idx] |=
9126
(ADVERTISED_2500baseX_Full |
9129
BNX2X_ERR("NVRAM config error. "
9130
"Invalid link_config 0x%x"
9131
" speed_cap_mask 0x%x\n",
9133
bp->link_params.speed_cap_mask[idx]);
9138
case PORT_FEATURE_LINK_SPEED_10G_CX4:
9139
if (bp->port.supported[idx] &
9140
SUPPORTED_10000baseT_Full) {
9141
bp->link_params.req_line_speed[idx] =
9143
bp->port.advertising[idx] |=
9144
(ADVERTISED_10000baseT_Full |
9147
BNX2X_ERR("NVRAM config error. "
9148
"Invalid link_config 0x%x"
9149
" speed_cap_mask 0x%x\n",
9151
bp->link_params.speed_cap_mask[idx]);
9155
case PORT_FEATURE_LINK_SPEED_20G:
9156
bp->link_params.req_line_speed[idx] = SPEED_20000;
9160
BNX2X_ERR("NVRAM config error. "
9161
"BAD link speed link_config 0x%x\n",
9163
bp->link_params.req_line_speed[idx] =
9165
bp->port.advertising[idx] =
9166
bp->port.supported[idx];
9170
bp->link_params.req_flow_ctrl[idx] = (link_config &
9171
PORT_FEATURE_FLOW_CONTROL_MASK);
9172
if ((bp->link_params.req_flow_ctrl[idx] ==
9173
BNX2X_FLOW_CTRL_AUTO) &&
9174
!(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9175
bp->link_params.req_flow_ctrl[idx] =
9176
BNX2X_FLOW_CTRL_NONE;
9179
BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9180
" 0x%x advertising 0x%x\n",
9181
bp->link_params.req_line_speed[idx],
9182
bp->link_params.req_duplex[idx],
9183
bp->link_params.req_flow_ctrl[idx],
9184
bp->port.advertising[idx]);
9188
static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9190
mac_hi = cpu_to_be16(mac_hi);
9191
mac_lo = cpu_to_be32(mac_lo);
9192
memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9193
memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9196
static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9198
int port = BP_PORT(bp);
9200
u32 ext_phy_type, ext_phy_config;
9202
bp->link_params.bp = bp;
9203
bp->link_params.port = port;
9205
bp->link_params.lane_config =
9206
SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9208
bp->link_params.speed_cap_mask[0] =
9210
dev_info.port_hw_config[port].speed_capability_mask);
9211
bp->link_params.speed_cap_mask[1] =
9213
dev_info.port_hw_config[port].speed_capability_mask2);
9214
bp->port.link_config[0] =
9215
SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9217
bp->port.link_config[1] =
9218
SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9220
bp->link_params.multi_phy_config =
9221
SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9222
/* If the device is capable of WoL, set the default state according
9225
config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9226
bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9227
(config & PORT_FEATURE_WOL_ENABLED));
9229
BNX2X_DEV_INFO("lane_config 0x%08x "
9230
"speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9231
bp->link_params.lane_config,
9232
bp->link_params.speed_cap_mask[0],
9233
bp->port.link_config[0]);
9235
bp->link_params.switch_cfg = (bp->port.link_config[0] &
9236
PORT_FEATURE_CONNECTED_SWITCH_MASK);
9237
bnx2x_phy_probe(&bp->link_params);
9238
bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9240
bnx2x_link_settings_requested(bp);
9243
* If connected directly, work with the internal PHY, otherwise, work
9244
* with the external PHY
9248
dev_info.port_hw_config[port].external_phy_config);
9249
ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9250
if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9251
bp->mdio.prtad = bp->port.phy_addr;
9253
else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9254
(ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9256
XGXS_EXT_PHY_ADDR(ext_phy_config);
9259
* Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9260
* In MF mode, it is set to cover self test cases
9263
bp->port.need_hw_lock = 1;
9265
bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9266
bp->common.shmem_base,
9267
bp->common.shmem2_base);
9271
static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9273
int port = BP_PORT(bp);
9274
int func = BP_ABS_FUNC(bp);
9276
u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9277
drv_lic_key[port].max_iscsi_conn);
9278
u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9279
drv_lic_key[port].max_fcoe_conn);
9281
/* Get the number of maximum allowed iSCSI and FCoE connections */
9282
bp->cnic_eth_dev.max_iscsi_conn =
9283
(max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9284
BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9286
bp->cnic_eth_dev.max_fcoe_conn =
9287
(max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9288
BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9293
bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9295
dev_info.port_hw_config[port].
9296
fcoe_wwn_port_name_upper);
9297
bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9299
dev_info.port_hw_config[port].
9300
fcoe_wwn_port_name_lower);
9303
bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9305
dev_info.port_hw_config[port].
9306
fcoe_wwn_node_name_upper);
9307
bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9309
dev_info.port_hw_config[port].
9310
fcoe_wwn_node_name_lower);
9311
} else if (!IS_MF_SD(bp)) {
9312
u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9315
* Read the WWN info only if the FCoE feature is enabled for
9318
if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9320
bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9321
MF_CFG_RD(bp, func_ext_config[func].
9322
fcoe_wwn_port_name_upper);
9323
bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9324
MF_CFG_RD(bp, func_ext_config[func].
9325
fcoe_wwn_port_name_lower);
9328
bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9329
MF_CFG_RD(bp, func_ext_config[func].
9330
fcoe_wwn_node_name_upper);
9331
bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9332
MF_CFG_RD(bp, func_ext_config[func].
9333
fcoe_wwn_node_name_lower);
9337
BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9338
bp->cnic_eth_dev.max_iscsi_conn,
9339
bp->cnic_eth_dev.max_fcoe_conn);
9342
* If maximum allowed number of connections is zero -
9343
* disable the feature.
9345
if (!bp->cnic_eth_dev.max_iscsi_conn)
9346
bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9348
if (!bp->cnic_eth_dev.max_fcoe_conn)
9349
bp->flags |= NO_FCOE_FLAG;
9353
static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9356
int func = BP_ABS_FUNC(bp);
9357
int port = BP_PORT(bp);
9359
u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9360
u8 *fip_mac = bp->fip_mac;
9363
/* Zero primary MAC configuration */
9364
memset(bp->dev->dev_addr, 0, ETH_ALEN);
9367
BNX2X_ERROR("warning: random MAC workaround active\n");
9368
random_ether_addr(bp->dev->dev_addr);
9369
} else if (IS_MF(bp)) {
9370
val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9371
val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9372
if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9373
(val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9374
bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9377
/* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9378
* FCoE MAC then the appropriate feature should be disabled.
9381
u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9382
if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9383
val2 = MF_CFG_RD(bp, func_ext_config[func].
9384
iscsi_mac_addr_upper);
9385
val = MF_CFG_RD(bp, func_ext_config[func].
9386
iscsi_mac_addr_lower);
9387
bnx2x_set_mac_buf(iscsi_mac, val, val2);
9388
BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9391
bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9393
if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9394
val2 = MF_CFG_RD(bp, func_ext_config[func].
9395
fcoe_mac_addr_upper);
9396
val = MF_CFG_RD(bp, func_ext_config[func].
9397
fcoe_mac_addr_lower);
9398
bnx2x_set_mac_buf(fip_mac, val, val2);
9399
BNX2X_DEV_INFO("Read FCoE L2 MAC to %pM\n",
9403
bp->flags |= NO_FCOE_FLAG;
9407
/* in SF read MACs from port configuration */
9408
val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9409
val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9410
bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9413
val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9415
val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9417
bnx2x_set_mac_buf(iscsi_mac, val, val2);
9419
val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9420
fcoe_fip_mac_upper);
9421
val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9422
fcoe_fip_mac_lower);
9423
bnx2x_set_mac_buf(fip_mac, val, val2);
9427
memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9428
memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9431
/* Set the FCoE MAC in MF_SD mode */
9432
if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9433
memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9435
/* Disable iSCSI if MAC configuration is
9438
if (!is_valid_ether_addr(iscsi_mac)) {
9439
bp->flags |= NO_ISCSI_FLAG;
9440
memset(iscsi_mac, 0, ETH_ALEN);
9443
/* Disable FCoE if MAC configuration is
9446
if (!is_valid_ether_addr(fip_mac)) {
9447
bp->flags |= NO_FCOE_FLAG;
9448
memset(bp->fip_mac, 0, ETH_ALEN);
9452
if (!is_valid_ether_addr(bp->dev->dev_addr))
9453
dev_err(&bp->pdev->dev,
9454
"bad Ethernet MAC address configuration: "
9455
"%pM, change it manually before bringing up "
9456
"the appropriate network interface\n",
9460
static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9462
int /*abs*/func = BP_ABS_FUNC(bp);
9467
bnx2x_get_common_hwinfo(bp);
9470
* initialize IGU parameters
9472
if (CHIP_IS_E1x(bp)) {
9473
bp->common.int_block = INT_BLOCK_HC;
9475
bp->igu_dsb_id = DEF_SB_IGU_ID;
9476
bp->igu_base_sb = 0;
9478
bp->common.int_block = INT_BLOCK_IGU;
9480
/* do not allow device reset during IGU info preocessing */
9481
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9483
val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9485
if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9488
BNX2X_DEV_INFO("FORCING Normal Mode\n");
9490
val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9491
REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9492
REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9494
while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9496
usleep_range(1000, 1000);
9499
if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9500
dev_err(&bp->pdev->dev,
9501
"FORCING Normal Mode failed!!!\n");
9506
if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9507
BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9508
bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9510
BNX2X_DEV_INFO("IGU Normal Mode\n");
9512
bnx2x_get_igu_cam_info(bp);
9514
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9518
* set base FW non-default (fast path) status block id, this value is
9519
* used to initialize the fw_sb_id saved on the fp/queue structure to
9520
* determine the id used by the FW.
9522
if (CHIP_IS_E1x(bp))
9523
bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9525
* 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9526
* the same queue are indicated on the same IGU SB). So we prefer
9527
* FW and IGU SBs to be the same value.
9529
bp->base_fw_ndsb = bp->igu_base_sb;
9531
BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9532
"base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9533
bp->igu_sb_cnt, bp->base_fw_ndsb);
9536
* Initialize MF configuration
9543
if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9544
BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9545
bp->common.shmem2_base, SHMEM2_RD(bp, size),
9546
(u32)offsetof(struct shmem2_region, mf_cfg_addr));
9548
if (SHMEM2_HAS(bp, mf_cfg_addr))
9549
bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9551
bp->common.mf_cfg_base = bp->common.shmem_base +
9552
offsetof(struct shmem_region, func_mb) +
9553
E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9555
* get mf configuration:
9556
* 1. existence of MF configuration
9557
* 2. MAC address must be legal (check only upper bytes)
9558
* for Switch-Independent mode;
9559
* OVLAN must be legal for Switch-Dependent mode
9560
* 3. SF_MODE configures specific MF mode
9562
if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9563
/* get mf configuration */
9565
dev_info.shared_feature_config.config);
9566
val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9569
case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9570
val = MF_CFG_RD(bp, func_mf_config[func].
9572
/* check for legal mac (upper bytes)*/
9573
if (val != 0xffff) {
9574
bp->mf_mode = MULTI_FUNCTION_SI;
9575
bp->mf_config[vn] = MF_CFG_RD(bp,
9576
func_mf_config[func].config);
9578
BNX2X_DEV_INFO("illegal MAC address "
9581
case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9582
/* get OV configuration */
9584
func_mf_config[FUNC_0].e1hov_tag);
9585
val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9587
if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9588
bp->mf_mode = MULTI_FUNCTION_SD;
9589
bp->mf_config[vn] = MF_CFG_RD(bp,
9590
func_mf_config[func].config);
9592
BNX2X_DEV_INFO("illegal OV for SD\n");
9595
/* Unknown configuration: reset mf_config */
9596
bp->mf_config[vn] = 0;
9597
BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9601
BNX2X_DEV_INFO("%s function mode\n",
9602
IS_MF(bp) ? "multi" : "single");
9604
switch (bp->mf_mode) {
9605
case MULTI_FUNCTION_SD:
9606
val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9607
FUNC_MF_CFG_E1HOV_TAG_MASK;
9608
if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9610
bp->path_has_ovlan = true;
9612
BNX2X_DEV_INFO("MF OV for func %d is %d "
9613
"(0x%04x)\n", func, bp->mf_ov,
9616
dev_err(&bp->pdev->dev,
9617
"No valid MF OV for func %d, "
9618
"aborting\n", func);
9622
case MULTI_FUNCTION_SI:
9623
BNX2X_DEV_INFO("func %d is in MF "
9624
"switch-independent mode\n", func);
9628
dev_err(&bp->pdev->dev,
9629
"VN %d is in a single function mode, "
9636
/* check if other port on the path needs ovlan:
9637
* Since MF configuration is shared between ports
9638
* Possible mixed modes are only
9639
* {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9641
if (CHIP_MODE_IS_4_PORT(bp) &&
9642
!bp->path_has_ovlan &&
9644
bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9645
u8 other_port = !BP_PORT(bp);
9646
u8 other_func = BP_PATH(bp) + 2*other_port;
9648
func_mf_config[other_func].e1hov_tag);
9649
if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9650
bp->path_has_ovlan = true;
9654
/* adjust igu_sb_cnt to MF for E1x */
9655
if (CHIP_IS_E1x(bp) && IS_MF(bp))
9656
bp->igu_sb_cnt /= E1HVN_MAX;
9659
bnx2x_get_port_hwinfo(bp);
9661
/* Get MAC addresses */
9662
bnx2x_get_mac_hwinfo(bp);
9665
bnx2x_get_cnic_info(bp);
9668
/* Get current FW pulse sequence */
9669
if (!BP_NOMCP(bp)) {
9670
int mb_idx = BP_FW_MB_IDX(bp);
9672
bp->fw_drv_pulse_wr_seq =
9673
(SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9674
DRV_PULSE_SEQ_MASK);
9675
BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9681
static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9683
int cnt, i, block_end, rodi;
9684
char vpd_data[BNX2X_VPD_LEN+1];
9685
char str_id_reg[VENDOR_ID_LEN+1];
9686
char str_id_cap[VENDOR_ID_LEN+1];
9689
cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9690
memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9692
if (cnt < BNX2X_VPD_LEN)
9695
i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9696
PCI_VPD_LRDT_RO_DATA);
9701
block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9702
pci_vpd_lrdt_size(&vpd_data[i]);
9704
i += PCI_VPD_LRDT_TAG_SIZE;
9706
if (block_end > BNX2X_VPD_LEN)
9709
rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9710
PCI_VPD_RO_KEYWORD_MFR_ID);
9714
len = pci_vpd_info_field_size(&vpd_data[rodi]);
9716
if (len != VENDOR_ID_LEN)
9719
rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9721
/* vendor specific info */
9722
snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9723
snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9724
if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9725
!strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9727
rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9728
PCI_VPD_RO_KEYWORD_VENDOR0);
9730
len = pci_vpd_info_field_size(&vpd_data[rodi]);
9732
rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9734
if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9735
memcpy(bp->fw_ver, &vpd_data[rodi], len);
9736
bp->fw_ver[len] = ' ';
9745
static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9749
if (CHIP_REV_IS_FPGA(bp))
9750
SET_FLAGS(flags, MODE_FPGA);
9751
else if (CHIP_REV_IS_EMUL(bp))
9752
SET_FLAGS(flags, MODE_EMUL);
9754
SET_FLAGS(flags, MODE_ASIC);
9756
if (CHIP_MODE_IS_4_PORT(bp))
9757
SET_FLAGS(flags, MODE_PORT4);
9759
SET_FLAGS(flags, MODE_PORT2);
9762
SET_FLAGS(flags, MODE_E2);
9763
else if (CHIP_IS_E3(bp)) {
9764
SET_FLAGS(flags, MODE_E3);
9765
if (CHIP_REV(bp) == CHIP_REV_Ax)
9766
SET_FLAGS(flags, MODE_E3_A0);
9767
else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9768
SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
9772
SET_FLAGS(flags, MODE_MF);
9773
switch (bp->mf_mode) {
9774
case MULTI_FUNCTION_SD:
9775
SET_FLAGS(flags, MODE_MF_SD);
9777
case MULTI_FUNCTION_SI:
9778
SET_FLAGS(flags, MODE_MF_SI);
9782
SET_FLAGS(flags, MODE_SF);
9784
#if defined(__LITTLE_ENDIAN)
9785
SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9786
#else /*(__BIG_ENDIAN)*/
9787
SET_FLAGS(flags, MODE_BIG_ENDIAN);
9789
INIT_MODE_FLAGS(bp) = flags;
9792
static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9798
mutex_init(&bp->port.phy_mutex);
9799
mutex_init(&bp->fw_mb_mutex);
9800
spin_lock_init(&bp->stats_lock);
9802
mutex_init(&bp->cnic_mutex);
9805
INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9806
INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
9807
INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
9808
rc = bnx2x_get_hwinfo(bp);
9812
bnx2x_set_modes_bitmap(bp);
9814
rc = bnx2x_alloc_mem_bp(bp);
9818
bnx2x_read_fwinfo(bp);
9822
/* need to reset chip if undi was active */
9824
bnx2x_undi_unload(bp);
9826
/* init fw_seq after undi_unload! */
9827
if (!BP_NOMCP(bp)) {
9829
(SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9830
DRV_MSG_SEQ_NUMBER_MASK);
9831
BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9834
if (CHIP_REV_IS_FPGA(bp))
9835
dev_err(&bp->pdev->dev, "FPGA detected\n");
9837
if (BP_NOMCP(bp) && (func == 0))
9838
dev_err(&bp->pdev->dev, "MCP disabled, "
9839
"must load devices in order!\n");
9841
bp->multi_mode = multi_mode;
9845
bp->flags &= ~TPA_ENABLE_FLAG;
9846
bp->dev->features &= ~NETIF_F_LRO;
9848
bp->flags |= TPA_ENABLE_FLAG;
9849
bp->dev->features |= NETIF_F_LRO;
9851
bp->disable_tpa = disable_tpa;
9854
bp->dropless_fc = 0;
9856
bp->dropless_fc = dropless_fc;
9860
bp->tx_ring_size = MAX_TX_AVAIL;
9862
/* make sure that the numbers are in the right granularity */
9863
bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9864
bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9866
timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9867
bp->current_interval = (poll ? poll : timer_interval);
9869
init_timer(&bp->timer);
9870
bp->timer.expires = jiffies + bp->current_interval;
9871
bp->timer.data = (unsigned long) bp;
9872
bp->timer.function = bnx2x_timer;
9874
bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9875
bnx2x_dcbx_init_params(bp);
9878
if (CHIP_IS_E1x(bp))
9879
bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9881
bp->cnic_base_cl_id = FP_SB_MAX_E2;
9884
/* multiple tx priority */
9885
if (CHIP_IS_E1x(bp))
9886
bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9887
if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9888
bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9889
if (CHIP_IS_E3B0(bp))
9890
bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9896
/****************************************************************************
9897
* General service functions
9898
****************************************************************************/
9901
* net_device service functions
9904
/* called with rtnl_lock */
9905
static int bnx2x_open(struct net_device *dev)
9907
struct bnx2x *bp = netdev_priv(dev);
9908
bool global = false;
9909
int other_engine = BP_PATH(bp) ? 0 : 1;
9910
u32 other_load_counter, load_counter;
9912
netif_carrier_off(dev);
9914
bnx2x_set_power_state(bp, PCI_D0);
9916
other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9917
load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9920
* If parity had happen during the unload, then attentions
9921
* and/or RECOVERY_IN_PROGRES may still be set. In this case we
9922
* want the first function loaded on the current engine to
9923
* complete the recovery.
9925
if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9926
bnx2x_chk_parity_attn(bp, &global, true))
9929
* If there are attentions and they are in a global
9930
* blocks, set the GLOBAL_RESET bit regardless whether
9931
* it will be this function that will complete the
9935
bnx2x_set_reset_global(bp);
9938
* Only the first function on the current engine should
9939
* try to recover in open. In case of attentions in
9940
* global blocks only the first in the chip should try
9943
if ((!load_counter &&
9944
(!global || !other_load_counter)) &&
9945
bnx2x_trylock_leader_lock(bp) &&
9946
!bnx2x_leader_reset(bp)) {
9947
netdev_info(bp->dev, "Recovered in open\n");
9951
/* recovery has failed... */
9952
bnx2x_set_power_state(bp, PCI_D3hot);
9953
bp->recovery_state = BNX2X_RECOVERY_FAILED;
9955
netdev_err(bp->dev, "Recovery flow hasn't been properly"
9956
" completed yet. Try again later. If u still see this"
9957
" message after a few retries then power cycle is"
9963
bp->recovery_state = BNX2X_RECOVERY_DONE;
9964
return bnx2x_nic_load(bp, LOAD_OPEN);
9967
/* called with rtnl_lock */
9968
static int bnx2x_close(struct net_device *dev)
9970
struct bnx2x *bp = netdev_priv(dev);
9972
/* Unload the driver, release IRQs */
9973
bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9976
bnx2x_set_power_state(bp, PCI_D3hot);
9981
static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9982
struct bnx2x_mcast_ramrod_params *p)
9984
int mc_count = netdev_mc_count(bp->dev);
9985
struct bnx2x_mcast_list_elem *mc_mac =
9986
kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9987
struct netdev_hw_addr *ha;
9992
INIT_LIST_HEAD(&p->mcast_list);
9994
netdev_for_each_mc_addr(ha, bp->dev) {
9995
mc_mac->mac = bnx2x_mc_addr(ha);
9996
list_add_tail(&mc_mac->link, &p->mcast_list);
10000
p->mcast_list_len = mc_count;
10005
static inline void bnx2x_free_mcast_macs_list(
10006
struct bnx2x_mcast_ramrod_params *p)
10008
struct bnx2x_mcast_list_elem *mc_mac =
10009
list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
10017
* bnx2x_set_uc_list - configure a new unicast MACs list.
10019
* @bp: driver handle
10021
* We will use zero (0) as a MAC type for these MACs.
10023
static inline int bnx2x_set_uc_list(struct bnx2x *bp)
10026
struct net_device *dev = bp->dev;
10027
struct netdev_hw_addr *ha;
10028
struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
10029
unsigned long ramrod_flags = 0;
10031
/* First schedule a cleanup up of old configuration */
10032
rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
10034
BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10038
netdev_for_each_uc_addr(ha, dev) {
10039
rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10040
BNX2X_UC_LIST_MAC, &ramrod_flags);
10042
BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10048
/* Execute the pending commands */
10049
__set_bit(RAMROD_CONT, &ramrod_flags);
10050
return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10051
BNX2X_UC_LIST_MAC, &ramrod_flags);
10054
static inline int bnx2x_set_mc_list(struct bnx2x *bp)
10056
struct net_device *dev = bp->dev;
10057
struct bnx2x_mcast_ramrod_params rparam = {0};
10060
rparam.mcast_obj = &bp->mcast_obj;
10062
/* first, clear all configured multicast MACs */
10063
rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10065
BNX2X_ERR("Failed to clear multicast "
10066
"configuration: %d\n", rc);
10070
/* then, configure a new MACs list */
10071
if (netdev_mc_count(dev)) {
10072
rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10074
BNX2X_ERR("Failed to create multicast MACs "
10079
/* Now add the new MACs */
10080
rc = bnx2x_config_mcast(bp, &rparam,
10081
BNX2X_MCAST_CMD_ADD);
10083
BNX2X_ERR("Failed to set a new multicast "
10084
"configuration: %d\n", rc);
10086
bnx2x_free_mcast_macs_list(&rparam);
10093
/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10094
void bnx2x_set_rx_mode(struct net_device *dev)
10096
struct bnx2x *bp = netdev_priv(dev);
10097
u32 rx_mode = BNX2X_RX_MODE_NORMAL;
10099
if (bp->state != BNX2X_STATE_OPEN) {
10100
DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10104
DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
10106
if (dev->flags & IFF_PROMISC)
10107
rx_mode = BNX2X_RX_MODE_PROMISC;
10108
else if ((dev->flags & IFF_ALLMULTI) ||
10109
((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10111
rx_mode = BNX2X_RX_MODE_ALLMULTI;
10113
/* some multicasts */
10114
if (bnx2x_set_mc_list(bp) < 0)
10115
rx_mode = BNX2X_RX_MODE_ALLMULTI;
10117
if (bnx2x_set_uc_list(bp) < 0)
10118
rx_mode = BNX2X_RX_MODE_PROMISC;
10121
bp->rx_mode = rx_mode;
10123
/* Schedule the rx_mode command */
10124
if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10125
set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10129
bnx2x_set_storm_rx_mode(bp);
10132
/* called with rtnl_lock */
10133
static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10134
int devad, u16 addr)
10136
struct bnx2x *bp = netdev_priv(netdev);
10140
DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10141
prtad, devad, addr);
10143
/* The HW expects different devad if CL22 is used */
10144
devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10146
bnx2x_acquire_phy_lock(bp);
10147
rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
10148
bnx2x_release_phy_lock(bp);
10149
DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
10156
/* called with rtnl_lock */
10157
static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10158
u16 addr, u16 value)
10160
struct bnx2x *bp = netdev_priv(netdev);
10163
DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10164
" value 0x%x\n", prtad, devad, addr, value);
10166
/* The HW expects different devad if CL22 is used */
10167
devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10169
bnx2x_acquire_phy_lock(bp);
10170
rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
10171
bnx2x_release_phy_lock(bp);
10175
/* called with rtnl_lock */
10176
static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10178
struct bnx2x *bp = netdev_priv(dev);
10179
struct mii_ioctl_data *mdio = if_mii(ifr);
10181
DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10182
mdio->phy_id, mdio->reg_num, mdio->val_in);
10184
if (!netif_running(dev))
10187
return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
10190
#ifdef CONFIG_NET_POLL_CONTROLLER
10191
static void poll_bnx2x(struct net_device *dev)
10193
struct bnx2x *bp = netdev_priv(dev);
10195
disable_irq(bp->pdev->irq);
10196
bnx2x_interrupt(bp->pdev->irq, dev);
10197
enable_irq(bp->pdev->irq);
10201
static const struct net_device_ops bnx2x_netdev_ops = {
10202
.ndo_open = bnx2x_open,
10203
.ndo_stop = bnx2x_close,
10204
.ndo_start_xmit = bnx2x_start_xmit,
10205
.ndo_select_queue = bnx2x_select_queue,
10206
.ndo_set_rx_mode = bnx2x_set_rx_mode,
10207
.ndo_set_mac_address = bnx2x_change_mac_addr,
10208
.ndo_validate_addr = eth_validate_addr,
10209
.ndo_do_ioctl = bnx2x_ioctl,
10210
.ndo_change_mtu = bnx2x_change_mtu,
10211
.ndo_fix_features = bnx2x_fix_features,
10212
.ndo_set_features = bnx2x_set_features,
10213
.ndo_tx_timeout = bnx2x_tx_timeout,
10214
#ifdef CONFIG_NET_POLL_CONTROLLER
10215
.ndo_poll_controller = poll_bnx2x,
10217
.ndo_setup_tc = bnx2x_setup_tc,
10219
#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10220
.ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10224
static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10226
struct device *dev = &bp->pdev->dev;
10228
if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10229
bp->flags |= USING_DAC_FLAG;
10230
if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10231
dev_err(dev, "dma_set_coherent_mask failed, "
10235
} else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10236
dev_err(dev, "System does not support DMA, aborting\n");
10243
static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10244
struct net_device *dev,
10245
unsigned long board_type)
10250
SET_NETDEV_DEV(dev, &pdev->dev);
10251
bp = netdev_priv(dev);
10256
bp->pf_num = PCI_FUNC(pdev->devfn);
10258
rc = pci_enable_device(pdev);
10260
dev_err(&bp->pdev->dev,
10261
"Cannot enable PCI device, aborting\n");
10265
if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10266
dev_err(&bp->pdev->dev,
10267
"Cannot find PCI device base address, aborting\n");
10269
goto err_out_disable;
10272
if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10273
dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10274
" base address, aborting\n");
10276
goto err_out_disable;
10279
if (atomic_read(&pdev->enable_cnt) == 1) {
10280
rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10282
dev_err(&bp->pdev->dev,
10283
"Cannot obtain PCI resources, aborting\n");
10284
goto err_out_disable;
10287
pci_set_master(pdev);
10288
pci_save_state(pdev);
10291
bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10292
if (bp->pm_cap == 0) {
10293
dev_err(&bp->pdev->dev,
10294
"Cannot find power management capability, aborting\n");
10296
goto err_out_release;
10299
if (!pci_is_pcie(pdev)) {
10300
dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10302
goto err_out_release;
10305
rc = bnx2x_set_coherency_mask(bp);
10307
goto err_out_release;
10309
dev->mem_start = pci_resource_start(pdev, 0);
10310
dev->base_addr = dev->mem_start;
10311
dev->mem_end = pci_resource_end(pdev, 0);
10313
dev->irq = pdev->irq;
10315
bp->regview = pci_ioremap_bar(pdev, 0);
10316
if (!bp->regview) {
10317
dev_err(&bp->pdev->dev,
10318
"Cannot map register space, aborting\n");
10320
goto err_out_release;
10323
bnx2x_set_power_state(bp, PCI_D0);
10325
/* clean indirect addresses */
10326
pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10327
PCICFG_VENDOR_ID_OFFSET);
10329
* Clean the following indirect addresses for all functions since it
10330
* is not used by the driver.
10332
REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10333
REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10334
REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10335
REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
10337
if (CHIP_IS_E1x(bp)) {
10338
REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10339
REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10340
REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10341
REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10345
* Enable internal target-read (in case we are probed after PF FLR).
10346
* Must be done prior to any BAR read access. Only for 57712 and up
10348
if (board_type != BCM57710 &&
10349
board_type != BCM57711 &&
10350
board_type != BCM57711E)
10351
REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10353
/* Reset the load counter */
10354
bnx2x_clear_load_cnt(bp);
10356
dev->watchdog_timeo = TX_TIMEOUT;
10358
dev->netdev_ops = &bnx2x_netdev_ops;
10359
bnx2x_set_ethtool_ops(dev);
10361
dev->priv_flags |= IFF_UNICAST_FLT;
10363
dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10364
NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_LRO |
10365
NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
10367
dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10368
NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10370
dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10371
if (bp->flags & USING_DAC_FLAG)
10372
dev->features |= NETIF_F_HIGHDMA;
10374
/* Add Loopback capability to the device */
10375
dev->hw_features |= NETIF_F_LOOPBACK;
10378
dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10381
/* get_port_hwinfo() will set prtad and mmds properly */
10382
bp->mdio.prtad = MDIO_PRTAD_NONE;
10384
bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10385
bp->mdio.dev = dev;
10386
bp->mdio.mdio_read = bnx2x_mdio_read;
10387
bp->mdio.mdio_write = bnx2x_mdio_write;
10392
if (atomic_read(&pdev->enable_cnt) == 1)
10393
pci_release_regions(pdev);
10396
pci_disable_device(pdev);
10397
pci_set_drvdata(pdev, NULL);
10403
static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10404
int *width, int *speed)
10406
u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10408
*width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10410
/* return value of 1=2.5GHz 2=5GHz */
10411
*speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10414
static int bnx2x_check_firmware(struct bnx2x *bp)
10416
const struct firmware *firmware = bp->firmware;
10417
struct bnx2x_fw_file_hdr *fw_hdr;
10418
struct bnx2x_fw_file_section *sections;
10419
u32 offset, len, num_ops;
10424
if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10427
fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10428
sections = (struct bnx2x_fw_file_section *)fw_hdr;
10430
/* Make sure none of the offsets and sizes make us read beyond
10431
* the end of the firmware data */
10432
for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10433
offset = be32_to_cpu(sections[i].offset);
10434
len = be32_to_cpu(sections[i].len);
10435
if (offset + len > firmware->size) {
10436
dev_err(&bp->pdev->dev,
10437
"Section %d length is out of bounds\n", i);
10442
/* Likewise for the init_ops offsets */
10443
offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10444
ops_offsets = (u16 *)(firmware->data + offset);
10445
num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10447
for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10448
if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10449
dev_err(&bp->pdev->dev,
10450
"Section offset %d is out of bounds\n", i);
10455
/* Check FW version */
10456
offset = be32_to_cpu(fw_hdr->fw_version.offset);
10457
fw_ver = firmware->data + offset;
10458
if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10459
(fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10460
(fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10461
(fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10462
dev_err(&bp->pdev->dev,
10463
"Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10464
fw_ver[0], fw_ver[1], fw_ver[2],
10465
fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10466
BCM_5710_FW_MINOR_VERSION,
10467
BCM_5710_FW_REVISION_VERSION,
10468
BCM_5710_FW_ENGINEERING_VERSION);
10475
static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10477
const __be32 *source = (const __be32 *)_source;
10478
u32 *target = (u32 *)_target;
10481
for (i = 0; i < n/4; i++)
10482
target[i] = be32_to_cpu(source[i]);
10486
Ops array is stored in the following format:
10487
{op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10489
static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10491
const __be32 *source = (const __be32 *)_source;
10492
struct raw_op *target = (struct raw_op *)_target;
10495
for (i = 0, j = 0; i < n/8; i++, j += 2) {
10496
tmp = be32_to_cpu(source[j]);
10497
target[i].op = (tmp >> 24) & 0xff;
10498
target[i].offset = tmp & 0xffffff;
10499
target[i].raw_data = be32_to_cpu(source[j + 1]);
10504
* IRO array is stored in the following format:
10505
* {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10507
static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10509
const __be32 *source = (const __be32 *)_source;
10510
struct iro *target = (struct iro *)_target;
10513
for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10514
target[i].base = be32_to_cpu(source[j]);
10516
tmp = be32_to_cpu(source[j]);
10517
target[i].m1 = (tmp >> 16) & 0xffff;
10518
target[i].m2 = tmp & 0xffff;
10520
tmp = be32_to_cpu(source[j]);
10521
target[i].m3 = (tmp >> 16) & 0xffff;
10522
target[i].size = tmp & 0xffff;
10527
static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10529
const __be16 *source = (const __be16 *)_source;
10530
u16 *target = (u16 *)_target;
10533
for (i = 0; i < n/2; i++)
10534
target[i] = be16_to_cpu(source[i]);
10537
#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10539
u32 len = be32_to_cpu(fw_hdr->arr.len); \
10540
bp->arr = kmalloc(len, GFP_KERNEL); \
10542
pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10545
func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10546
(u8 *)bp->arr, len); \
10549
int bnx2x_init_firmware(struct bnx2x *bp)
10551
struct bnx2x_fw_file_hdr *fw_hdr;
10555
if (!bp->firmware) {
10556
const char *fw_file_name;
10558
if (CHIP_IS_E1(bp))
10559
fw_file_name = FW_FILE_NAME_E1;
10560
else if (CHIP_IS_E1H(bp))
10561
fw_file_name = FW_FILE_NAME_E1H;
10562
else if (!CHIP_IS_E1x(bp))
10563
fw_file_name = FW_FILE_NAME_E2;
10565
BNX2X_ERR("Unsupported chip revision\n");
10568
BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10570
rc = request_firmware(&bp->firmware, fw_file_name,
10573
BNX2X_ERR("Can't load firmware file %s\n",
10575
goto request_firmware_exit;
10578
rc = bnx2x_check_firmware(bp);
10580
BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10581
goto request_firmware_exit;
10585
fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10587
/* Initialize the pointers to the init arrays */
10589
BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10592
BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10595
BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10598
/* STORMs firmware */
10599
INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10600
be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10601
INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10602
be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10603
INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10604
be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10605
INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10606
be32_to_cpu(fw_hdr->usem_pram_data.offset);
10607
INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10608
be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10609
INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10610
be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10611
INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10612
be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10613
INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10614
be32_to_cpu(fw_hdr->csem_pram_data.offset);
10616
BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10621
kfree(bp->init_ops_offsets);
10622
init_offsets_alloc_err:
10623
kfree(bp->init_ops);
10624
init_ops_alloc_err:
10625
kfree(bp->init_data);
10626
request_firmware_exit:
10627
release_firmware(bp->firmware);
10632
static void bnx2x_release_firmware(struct bnx2x *bp)
10634
kfree(bp->init_ops_offsets);
10635
kfree(bp->init_ops);
10636
kfree(bp->init_data);
10637
release_firmware(bp->firmware);
10638
bp->firmware = NULL;
10642
static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10643
.init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10644
.init_hw_cmn = bnx2x_init_hw_common,
10645
.init_hw_port = bnx2x_init_hw_port,
10646
.init_hw_func = bnx2x_init_hw_func,
10648
.reset_hw_cmn = bnx2x_reset_common,
10649
.reset_hw_port = bnx2x_reset_port,
10650
.reset_hw_func = bnx2x_reset_func,
10652
.gunzip_init = bnx2x_gunzip_init,
10653
.gunzip_end = bnx2x_gunzip_end,
10655
.init_fw = bnx2x_init_firmware,
10656
.release_fw = bnx2x_release_firmware,
10659
void bnx2x__init_func_obj(struct bnx2x *bp)
10661
/* Prepare DMAE related driver resources */
10662
bnx2x_setup_dmae(bp);
10664
bnx2x_init_func_obj(bp, &bp->func_obj,
10665
bnx2x_sp(bp, func_rdata),
10666
bnx2x_sp_mapping(bp, func_rdata),
10667
&bnx2x_func_sp_drv);
10670
/* must be called after sriov-enable */
10671
static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10673
int cid_count = BNX2X_L2_CID_COUNT(bp);
10676
cid_count += CNIC_CID_MAX;
10678
return roundup(cid_count, QM_CID_ROUND);
10682
* bnx2x_get_num_none_def_sbs - return the number of none default SBs
10687
static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10692
pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10695
* If MSI-X is not supported - return number of SBs needed to support
10696
* one fast path queue: one FP queue + SB for CNIC
10699
return 1 + CNIC_PRESENT;
10702
* The value in the PCI configuration space is the index of the last
10703
* entry, namely one less than the actual size of the table, which is
10704
* exactly what we want to return from this function: number of all SBs
10705
* without the default SB.
10707
pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10708
return control & PCI_MSIX_FLAGS_QSIZE;
10711
static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10712
const struct pci_device_id *ent)
10714
struct net_device *dev = NULL;
10716
int pcie_width, pcie_speed;
10717
int rc, max_non_def_sbs;
10718
int rx_count, tx_count, rss_count;
10720
* An estimated maximum supported CoS number according to the chip
10722
* We will try to roughly estimate the maximum number of CoSes this chip
10723
* may support in order to minimize the memory allocated for Tx
10724
* netdev_queue's. This number will be accurately calculated during the
10725
* initialization of bp->max_cos based on the chip versions AND chip
10726
* revision in the bnx2x_init_bp().
10728
u8 max_cos_est = 0;
10730
switch (ent->driver_data) {
10734
max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10739
max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10748
max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
10752
pr_err("Unknown board_type (%ld), aborting\n",
10757
max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10760
* Do not allow the maximum SB count to grow above 16
10761
* since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10762
* We will use the FP_SB_MAX_E1x macro for this matter.
10764
max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10766
WARN_ON(!max_non_def_sbs);
10768
/* Maximum number of RSS queues: one IGU SB goes to CNIC */
10769
rss_count = max_non_def_sbs - CNIC_PRESENT;
10771
/* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10772
rx_count = rss_count + FCOE_PRESENT;
10775
* Maximum number of netdev Tx queues:
10776
* Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10778
tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
10780
/* dev zeroed in init_etherdev */
10781
dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
10783
dev_err(&pdev->dev, "Cannot allocate net device\n");
10787
bp = netdev_priv(dev);
10789
DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10790
tx_count, rx_count);
10792
bp->igu_sb_cnt = max_non_def_sbs;
10793
bp->msg_enable = debug;
10794
pci_set_drvdata(pdev, dev);
10796
rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10802
DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs);
10804
rc = bnx2x_init_bp(bp);
10806
goto init_one_exit;
10809
* Map doorbels here as we need the real value of bp->max_cos which
10810
* is initialized in bnx2x_init_bp().
10812
bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10813
min_t(u64, BNX2X_DB_SIZE(bp),
10814
pci_resource_len(pdev, 2)));
10815
if (!bp->doorbells) {
10816
dev_err(&bp->pdev->dev,
10817
"Cannot map doorbell space, aborting\n");
10819
goto init_one_exit;
10822
/* calc qm_cid_count */
10823
bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
10826
/* disable FCOE L2 queue for E1x and E3*/
10827
if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp))
10828
bp->flags |= NO_FCOE_FLAG;
10832
/* Configure interrupt mode: try to enable MSI-X/MSI if
10833
* needed, set bp->num_queues appropriately.
10835
bnx2x_set_int_mode(bp);
10837
/* Add all NAPI objects */
10838
bnx2x_add_all_napi(bp);
10840
rc = register_netdev(dev);
10842
dev_err(&pdev->dev, "Cannot register net device\n");
10843
goto init_one_exit;
10847
if (!NO_FCOE(bp)) {
10848
/* Add storage MAC address */
10850
dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10855
bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10857
netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
10858
board_info[ent->driver_data].name,
10859
(CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10861
((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10862
(CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10863
"5GHz (Gen2)" : "2.5GHz",
10864
dev->base_addr, bp->pdev->irq, dev->dev_addr);
10870
iounmap(bp->regview);
10873
iounmap(bp->doorbells);
10877
if (atomic_read(&pdev->enable_cnt) == 1)
10878
pci_release_regions(pdev);
10880
pci_disable_device(pdev);
10881
pci_set_drvdata(pdev, NULL);
10886
static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10888
struct net_device *dev = pci_get_drvdata(pdev);
10892
dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10895
bp = netdev_priv(dev);
10898
/* Delete storage MAC address */
10899
if (!NO_FCOE(bp)) {
10901
dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10907
/* Delete app tlvs from dcbnl */
10908
bnx2x_dcbnl_update_applist(bp, true);
10911
unregister_netdev(dev);
10913
/* Delete all NAPI objects */
10914
bnx2x_del_all_napi(bp);
10916
/* Power on: we can't let PCI layer write to us while we are in D3 */
10917
bnx2x_set_power_state(bp, PCI_D0);
10919
/* Disable MSI/MSI-X */
10920
bnx2x_disable_msi(bp);
10923
bnx2x_set_power_state(bp, PCI_D3hot);
10925
/* Make sure RESET task is not scheduled before continuing */
10926
cancel_delayed_work_sync(&bp->sp_rtnl_task);
10929
iounmap(bp->regview);
10932
iounmap(bp->doorbells);
10934
bnx2x_release_firmware(bp);
10936
bnx2x_free_mem_bp(bp);
10940
if (atomic_read(&pdev->enable_cnt) == 1)
10941
pci_release_regions(pdev);
10943
pci_disable_device(pdev);
10944
pci_set_drvdata(pdev, NULL);
10947
static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10951
bp->state = BNX2X_STATE_ERROR;
10953
bp->rx_mode = BNX2X_RX_MODE_NONE;
10956
bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10959
bnx2x_tx_disable(bp);
10961
bnx2x_netif_stop(bp, 0);
10963
del_timer_sync(&bp->timer);
10965
bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10968
bnx2x_free_irq(bp);
10970
/* Free SKBs, SGEs, TPA pool and driver internals */
10971
bnx2x_free_skbs(bp);
10973
for_each_rx_queue(bp, i)
10974
bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10976
bnx2x_free_mem(bp);
10978
bp->state = BNX2X_STATE_CLOSED;
10980
netif_carrier_off(bp->dev);
10985
static void bnx2x_eeh_recover(struct bnx2x *bp)
10989
mutex_init(&bp->port.phy_mutex);
10991
bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10992
bp->link_params.shmem_base = bp->common.shmem_base;
10993
BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10995
if (!bp->common.shmem_base ||
10996
(bp->common.shmem_base < 0xA0000) ||
10997
(bp->common.shmem_base >= 0xC0000)) {
10998
BNX2X_DEV_INFO("MCP not active\n");
10999
bp->flags |= NO_MCP_FLAG;
11003
val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
11004
if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11005
!= (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
11006
BNX2X_ERR("BAD MCP validity signature\n");
11008
if (!BP_NOMCP(bp)) {
11010
(SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11011
DRV_MSG_SEQ_NUMBER_MASK);
11012
BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11017
* bnx2x_io_error_detected - called when PCI error is detected
11018
* @pdev: Pointer to PCI device
11019
* @state: The current pci connection state
11021
* This function is called after a PCI bus error affecting
11022
* this device has been detected.
11024
static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11025
pci_channel_state_t state)
11027
struct net_device *dev = pci_get_drvdata(pdev);
11028
struct bnx2x *bp = netdev_priv(dev);
11032
netif_device_detach(dev);
11034
if (state == pci_channel_io_perm_failure) {
11036
return PCI_ERS_RESULT_DISCONNECT;
11039
if (netif_running(dev))
11040
bnx2x_eeh_nic_unload(bp);
11042
pci_disable_device(pdev);
11046
/* Request a slot reset */
11047
return PCI_ERS_RESULT_NEED_RESET;
11051
* bnx2x_io_slot_reset - called after the PCI bus has been reset
11052
* @pdev: Pointer to PCI device
11054
* Restart the card from scratch, as if from a cold-boot.
11056
static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11058
struct net_device *dev = pci_get_drvdata(pdev);
11059
struct bnx2x *bp = netdev_priv(dev);
11063
if (pci_enable_device(pdev)) {
11064
dev_err(&pdev->dev,
11065
"Cannot re-enable PCI device after reset\n");
11067
return PCI_ERS_RESULT_DISCONNECT;
11070
pci_set_master(pdev);
11071
pci_restore_state(pdev);
11073
if (netif_running(dev))
11074
bnx2x_set_power_state(bp, PCI_D0);
11078
return PCI_ERS_RESULT_RECOVERED;
11082
* bnx2x_io_resume - called when traffic can start flowing again
11083
* @pdev: Pointer to PCI device
11085
* This callback is called when the error recovery driver tells us that
11086
* its OK to resume normal operation.
11088
static void bnx2x_io_resume(struct pci_dev *pdev)
11090
struct net_device *dev = pci_get_drvdata(pdev);
11091
struct bnx2x *bp = netdev_priv(dev);
11093
if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
11094
netdev_err(bp->dev, "Handling parity error recovery. "
11095
"Try again later\n");
11101
bnx2x_eeh_recover(bp);
11103
if (netif_running(dev))
11104
bnx2x_nic_load(bp, LOAD_NORMAL);
11106
netif_device_attach(dev);
11111
static struct pci_error_handlers bnx2x_err_handler = {
11112
.error_detected = bnx2x_io_error_detected,
11113
.slot_reset = bnx2x_io_slot_reset,
11114
.resume = bnx2x_io_resume,
11117
static struct pci_driver bnx2x_pci_driver = {
11118
.name = DRV_MODULE_NAME,
11119
.id_table = bnx2x_pci_tbl,
11120
.probe = bnx2x_init_one,
11121
.remove = __devexit_p(bnx2x_remove_one),
11122
.suspend = bnx2x_suspend,
11123
.resume = bnx2x_resume,
11124
.err_handler = &bnx2x_err_handler,
11127
static int __init bnx2x_init(void)
11131
pr_info("%s", version);
11133
bnx2x_wq = create_singlethread_workqueue("bnx2x");
11134
if (bnx2x_wq == NULL) {
11135
pr_err("Cannot create workqueue\n");
11139
ret = pci_register_driver(&bnx2x_pci_driver);
11141
pr_err("Cannot register driver\n");
11142
destroy_workqueue(bnx2x_wq);
11147
static void __exit bnx2x_cleanup(void)
11149
pci_unregister_driver(&bnx2x_pci_driver);
11151
destroy_workqueue(bnx2x_wq);
11154
void bnx2x_notify_link_changed(struct bnx2x *bp)
11156
REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11159
module_init(bnx2x_init);
11160
module_exit(bnx2x_cleanup);
11164
* bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11166
* @bp: driver handle
11167
* @set: set or clear the CAM entry
11169
* This function will wait until the ramdord completion returns.
11170
* Return 0 if success, -ENODEV if ramrod doesn't return.
11172
static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11174
unsigned long ramrod_flags = 0;
11176
__set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11177
return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11178
&bp->iscsi_l2_mac_obj, true,
11179
BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11182
/* count denotes the number of new completions we have seen */
11183
static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11185
struct eth_spe *spe;
11187
#ifdef BNX2X_STOP_ON_ERROR
11188
if (unlikely(bp->panic))
11192
spin_lock_bh(&bp->spq_lock);
11193
BUG_ON(bp->cnic_spq_pending < count);
11194
bp->cnic_spq_pending -= count;
11197
for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11198
u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11199
& SPE_HDR_CONN_TYPE) >>
11200
SPE_HDR_CONN_TYPE_SHIFT;
11201
u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11202
>> SPE_HDR_CMD_ID_SHIFT) & 0xff;
11204
/* Set validation for iSCSI L2 client before sending SETUP
11207
if (type == ETH_CONNECTION_TYPE) {
11208
if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
11209
bnx2x_set_ctx_validation(bp, &bp->context.
11210
vcxt[BNX2X_ISCSI_ETH_CID].eth,
11211
BNX2X_ISCSI_ETH_CID);
11215
* There may be not more than 8 L2, not more than 8 L5 SPEs
11216
* and in the air. We also check that number of outstanding
11217
* COMMON ramrods is not more than the EQ and SPQ can
11220
if (type == ETH_CONNECTION_TYPE) {
11221
if (!atomic_read(&bp->cq_spq_left))
11224
atomic_dec(&bp->cq_spq_left);
11225
} else if (type == NONE_CONNECTION_TYPE) {
11226
if (!atomic_read(&bp->eq_spq_left))
11229
atomic_dec(&bp->eq_spq_left);
11230
} else if ((type == ISCSI_CONNECTION_TYPE) ||
11231
(type == FCOE_CONNECTION_TYPE)) {
11232
if (bp->cnic_spq_pending >=
11233
bp->cnic_eth_dev.max_kwqe_pending)
11236
bp->cnic_spq_pending++;
11238
BNX2X_ERR("Unknown SPE type: %d\n", type);
11243
spe = bnx2x_sp_get_next(bp);
11244
*spe = *bp->cnic_kwq_cons;
11246
DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11247
bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11249
if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11250
bp->cnic_kwq_cons = bp->cnic_kwq;
11252
bp->cnic_kwq_cons++;
11254
bnx2x_sp_prod_update(bp);
11255
spin_unlock_bh(&bp->spq_lock);
11258
static int bnx2x_cnic_sp_queue(struct net_device *dev,
11259
struct kwqe_16 *kwqes[], u32 count)
11261
struct bnx2x *bp = netdev_priv(dev);
11264
#ifdef BNX2X_STOP_ON_ERROR
11265
if (unlikely(bp->panic))
11269
spin_lock_bh(&bp->spq_lock);
11271
for (i = 0; i < count; i++) {
11272
struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11274
if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11277
*bp->cnic_kwq_prod = *spe;
11279
bp->cnic_kwq_pending++;
11281
DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11282
spe->hdr.conn_and_cmd_data, spe->hdr.type,
11283
spe->data.update_data_addr.hi,
11284
spe->data.update_data_addr.lo,
11285
bp->cnic_kwq_pending);
11287
if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11288
bp->cnic_kwq_prod = bp->cnic_kwq;
11290
bp->cnic_kwq_prod++;
11293
spin_unlock_bh(&bp->spq_lock);
11295
if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11296
bnx2x_cnic_sp_post(bp, 0);
11301
static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11303
struct cnic_ops *c_ops;
11306
mutex_lock(&bp->cnic_mutex);
11307
c_ops = rcu_dereference_protected(bp->cnic_ops,
11308
lockdep_is_held(&bp->cnic_mutex));
11310
rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11311
mutex_unlock(&bp->cnic_mutex);
11316
static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11318
struct cnic_ops *c_ops;
11322
c_ops = rcu_dereference(bp->cnic_ops);
11324
rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11331
* for commands that have no data
11333
int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11335
struct cnic_ctl_info ctl = {0};
11339
return bnx2x_cnic_ctl_send(bp, &ctl);
11342
static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11344
struct cnic_ctl_info ctl = {0};
11346
/* first we tell CNIC and only then we count this as a completion */
11347
ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11348
ctl.data.comp.cid = cid;
11349
ctl.data.comp.error = err;
11351
bnx2x_cnic_ctl_send_bh(bp, &ctl);
11352
bnx2x_cnic_sp_post(bp, 0);
11356
/* Called with netif_addr_lock_bh() taken.
11357
* Sets an rx_mode config for an iSCSI ETH client.
11359
* Completion should be checked outside.
11361
static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11363
unsigned long accept_flags = 0, ramrod_flags = 0;
11364
u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11365
int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11368
/* Start accepting on iSCSI L2 ring. Accept all multicasts
11369
* because it's the only way for UIO Queue to accept
11370
* multicasts (in non-promiscuous mode only one Queue per
11371
* function will receive multicast packets (leading in our
11374
__set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11375
__set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11376
__set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11377
__set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11379
/* Clear STOP_PENDING bit if START is requested */
11380
clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11382
sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11384
/* Clear START_PENDING bit if STOP is requested */
11385
clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11387
if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11388
set_bit(sched_state, &bp->sp_state);
11390
__set_bit(RAMROD_RX, &ramrod_flags);
11391
bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11397
static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11399
struct bnx2x *bp = netdev_priv(dev);
11402
switch (ctl->cmd) {
11403
case DRV_CTL_CTXTBL_WR_CMD: {
11404
u32 index = ctl->data.io.offset;
11405
dma_addr_t addr = ctl->data.io.dma_addr;
11407
bnx2x_ilt_wr(bp, index, addr);
11411
case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11412
int count = ctl->data.credit.credit_count;
11414
bnx2x_cnic_sp_post(bp, count);
11418
/* rtnl_lock is held. */
11419
case DRV_CTL_START_L2_CMD: {
11420
struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11421
unsigned long sp_bits = 0;
11423
/* Configure the iSCSI classification object */
11424
bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11425
cp->iscsi_l2_client_id,
11426
cp->iscsi_l2_cid, BP_FUNC(bp),
11427
bnx2x_sp(bp, mac_rdata),
11428
bnx2x_sp_mapping(bp, mac_rdata),
11429
BNX2X_FILTER_MAC_PENDING,
11430
&bp->sp_state, BNX2X_OBJ_TYPE_RX,
11433
/* Set iSCSI MAC address */
11434
rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11441
/* Start accepting on iSCSI L2 ring */
11443
netif_addr_lock_bh(dev);
11444
bnx2x_set_iscsi_eth_rx_mode(bp, true);
11445
netif_addr_unlock_bh(dev);
11447
/* bits to wait on */
11448
__set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11449
__set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11451
if (!bnx2x_wait_sp_comp(bp, sp_bits))
11452
BNX2X_ERR("rx_mode completion timed out!\n");
11457
/* rtnl_lock is held. */
11458
case DRV_CTL_STOP_L2_CMD: {
11459
unsigned long sp_bits = 0;
11461
/* Stop accepting on iSCSI L2 ring */
11462
netif_addr_lock_bh(dev);
11463
bnx2x_set_iscsi_eth_rx_mode(bp, false);
11464
netif_addr_unlock_bh(dev);
11466
/* bits to wait on */
11467
__set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11468
__set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11470
if (!bnx2x_wait_sp_comp(bp, sp_bits))
11471
BNX2X_ERR("rx_mode completion timed out!\n");
11476
/* Unset iSCSI L2 MAC */
11477
rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11478
BNX2X_ISCSI_ETH_MAC, true);
11481
case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11482
int count = ctl->data.credit.credit_count;
11484
smp_mb__before_atomic_inc();
11485
atomic_add(count, &bp->cq_spq_left);
11486
smp_mb__after_atomic_inc();
11491
BNX2X_ERR("unknown command %x\n", ctl->cmd);
11498
void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11500
struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11502
if (bp->flags & USING_MSIX_FLAG) {
11503
cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11504
cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11505
cp->irq_arr[0].vector = bp->msix_table[1].vector;
11507
cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11508
cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11510
if (!CHIP_IS_E1x(bp))
11511
cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11513
cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11515
cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11516
cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11517
cp->irq_arr[1].status_blk = bp->def_status_blk;
11518
cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11519
cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11524
static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11527
struct bnx2x *bp = netdev_priv(dev);
11528
struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11533
bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11537
bp->cnic_kwq_cons = bp->cnic_kwq;
11538
bp->cnic_kwq_prod = bp->cnic_kwq;
11539
bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11541
bp->cnic_spq_pending = 0;
11542
bp->cnic_kwq_pending = 0;
11544
bp->cnic_data = data;
11547
cp->drv_state |= CNIC_DRV_STATE_REGD;
11548
cp->iro_arr = bp->iro_arr;
11550
bnx2x_setup_cnic_irq_info(bp);
11552
rcu_assign_pointer(bp->cnic_ops, ops);
11557
static int bnx2x_unregister_cnic(struct net_device *dev)
11559
struct bnx2x *bp = netdev_priv(dev);
11560
struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11562
mutex_lock(&bp->cnic_mutex);
11564
rcu_assign_pointer(bp->cnic_ops, NULL);
11565
mutex_unlock(&bp->cnic_mutex);
11567
kfree(bp->cnic_kwq);
11568
bp->cnic_kwq = NULL;
11573
struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11575
struct bnx2x *bp = netdev_priv(dev);
11576
struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11578
/* If both iSCSI and FCoE are disabled - return NULL in
11579
* order to indicate CNIC that it should not try to work
11580
* with this device.
11582
if (NO_ISCSI(bp) && NO_FCOE(bp))
11585
cp->drv_owner = THIS_MODULE;
11586
cp->chip_id = CHIP_ID(bp);
11587
cp->pdev = bp->pdev;
11588
cp->io_base = bp->regview;
11589
cp->io_base2 = bp->doorbells;
11590
cp->max_kwqe_pending = 8;
11591
cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11592
cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11593
bnx2x_cid_ilt_lines(bp);
11594
cp->ctx_tbl_len = CNIC_ILT_LINES;
11595
cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11596
cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11597
cp->drv_ctl = bnx2x_drv_ctl;
11598
cp->drv_register_cnic = bnx2x_register_cnic;
11599
cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11600
cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11601
cp->iscsi_l2_client_id =
11602
bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11603
cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11605
if (NO_ISCSI_OOO(bp))
11606
cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11609
cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11612
cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11614
DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11615
"starting cid %d\n",
11617
cp->ctx_tbl_offset,
11622
EXPORT_SYMBOL(bnx2x_cnic_probe);
11624
#endif /* BCM_CNIC */
added
removed
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
