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//------------------------------------------------------------------------------
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// <copyright file="common_drv.c" company="Atheros">
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// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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//------------------------------------------------------------------------------
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//==============================================================================
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// Author(s): ="Atheros"
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//==============================================================================
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#include "hw/mbox_host_reg.h"
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#include "hw/rtc_reg.h"
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#include "hw/mbox_reg.h"
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#include "hw/apb_map.h"
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#include "targaddrs.h"
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#include "common_drv.h"
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#define ATH_MODULE_NAME misc
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#include "ar6000_diag.h"
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static ATH_DEBUG_MODULE_DBG_INFO *g_pModuleInfoHead = NULL;
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static A_MUTEX_T g_ModuleListLock;
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static bool g_ModuleDebugInit = false;
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#ifdef ATH_DEBUG_MODULE
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ATH_DEBUG_INSTANTIATE_MODULE_VAR(misc,
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"Common and misc APIs",
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ATH_DEBUG_MASK_DEFAULTS,
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#define HOST_INTEREST_ITEM_ADDRESS(target, item) \
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((((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
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(((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0)))
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#define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080
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#define AR6002_LOCAL_COUNT_ADDRESS 0x00018080
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#define AR6003_LOCAL_COUNT_ADDRESS 0x00018080
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#define CPU_DBG_SEL_ADDRESS 0x00000483
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#define CPU_DBG_ADDRESS 0x00000484
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static u8 custDataAR6002[AR6002_CUST_DATA_SIZE];
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static u8 custDataAR6003[AR6003_CUST_DATA_SIZE];
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/* Compile the 4BYTE version of the window register setup routine,
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* This mitigates host interconnect issues with non-4byte aligned bus requests, some
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* interconnects use bus adapters that impose strict limitations.
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* Since diag window access is not intended for performance critical operations, the 4byte mode should
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* be satisfactory even though it generates 4X the bus activity. */
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#ifdef USE_4BYTE_REGISTER_ACCESS
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/* set the window address register (using 4-byte register access ). */
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int ar6000_SetAddressWindowRegister(struct hif_device *hifDevice, u32 RegisterAddr, u32 Address)
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/* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
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* last to initiate the access cycle */
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for (i = 1; i <= 3; i++) {
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/* fill the buffer with the address byte value we want to hit 4 times*/
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addrValue[0] = ((u8 *)&Address)[i];
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addrValue[1] = addrValue[0];
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addrValue[2] = addrValue[0];
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addrValue[3] = addrValue[0];
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/* hit each byte of the register address with a 4-byte write operation to the same address,
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* this is a harmless operation */
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status = HIFReadWrite(hifDevice,
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HIF_WR_SYNC_BYTE_FIX,
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
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Address, RegisterAddr));
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/* write the address register again, this time write the whole 4-byte value.
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* The effect here is that the LSB write causes the cycle to start, the extra
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* 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
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status = HIFReadWrite(hifDevice,
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HIF_WR_SYNC_BYTE_INC,
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
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Address, RegisterAddr));
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/* set the window address register */
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int ar6000_SetAddressWindowRegister(struct hif_device *hifDevice, u32 RegisterAddr, u32 Address)
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/* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
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* last to initiate the access cycle */
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status = HIFReadWrite(hifDevice,
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RegisterAddr+1, /* write upper 3 bytes */
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((u8 *)(&Address))+1,
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HIF_WR_SYNC_BYTE_INC,
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
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RegisterAddr, Address));
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/* write the LSB of the register, this initiates the operation */
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status = HIFReadWrite(hifDevice,
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HIF_WR_SYNC_BYTE_INC,
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
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RegisterAddr, Address));
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* Read from the AR6000 through its diagnostic window.
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* No cooperation from the Target is required for this.
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ar6000_ReadRegDiag(struct hif_device *hifDevice, u32 *address, u32 *data)
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/* set window register to start read cycle */
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status = ar6000_SetAddressWindowRegister(hifDevice,
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WINDOW_READ_ADDR_ADDRESS,
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status = HIFReadWrite(hifDevice,
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HIF_RD_SYNC_BYTE_INC,
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
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* Write to the AR6000 through its diagnostic window.
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* No cooperation from the Target is required for this.
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ar6000_WriteRegDiag(struct hif_device *hifDevice, u32 *address, u32 *data)
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status = HIFReadWrite(hifDevice,
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HIF_WR_SYNC_BYTE_INC,
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data));
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/* set window register, which starts the write cycle */
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return ar6000_SetAddressWindowRegister(hifDevice,
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WINDOW_WRITE_ADDR_ADDRESS,
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ar6000_ReadDataDiag(struct hif_device *hifDevice, u32 address,
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u8 *data, u32 length)
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for (count = 0; count < length; count += 4, address += 4) {
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if ((status = ar6000_ReadRegDiag(hifDevice, &address,
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(u32 *)&data[count])) != 0)
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ar6000_WriteDataDiag(struct hif_device *hifDevice, u32 address,
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u8 *data, u32 length)
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for (count = 0; count < length; count += 4, address += 4) {
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if ((status = ar6000_WriteRegDiag(hifDevice, &address,
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(u32 *)&data[count])) != 0)
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ar6k_ReadTargetRegister(struct hif_device *hifDevice, int regsel, u32 *regval)
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u8 register_selection[4];
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register_selection[0] = register_selection[1] = register_selection[2] = register_selection[3] = (regsel & 0xff);
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status = HIFReadWrite(hifDevice,
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HIF_WR_SYNC_BYTE_FIX,
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write CPU_DBG_SEL (%d)\n", regsel));
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status = HIFReadWrite(hifDevice,
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HIF_RD_SYNC_BYTE_INC,
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from CPU_DBG_ADDRESS\n"));
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*regval = vals[0]<<0 | vals[1]<<8 | vals[2]<<16 | vals[3]<<24;
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ar6k_FetchTargetRegs(struct hif_device *hifDevice, u32 *targregs)
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for (i=0; i<AR6003_FETCH_TARG_REGS_COUNT; i++) {
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(void)ar6k_ReadTargetRegister(hifDevice, i, &val);
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_do_write_diag(struct hif_device *hifDevice, u32 addr, u32 value)
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status = ar6000_WriteRegDiag(hifDevice, &addr, &value);
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n"));
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* Delay up to wait_msecs millisecs to allow Target to enter BMI phase,
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* which is a good sign that it's alive and well. This is used after
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* explicitly forcing the Target to reset.
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* The wait_msecs time should be sufficiently long to cover any reasonable
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* boot-time delay. For instance, AR6001 firmware allow one second for a
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* low frequency crystal to settle before it calibrates the refclk frequency.
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* TBD: Might want to add special handling for AR6K_OPTION_BMI_DISABLE.
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_delay_until_target_alive(struct hif_device *hifDevice, s32 wait_msecs, u32 TargetType)
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/* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */
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if (TargetType == TARGET_TYPE_AR6002) {
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address = AR6002_LOCAL_COUNT_ADDRESS;
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} else if (TargetType == TARGET_TYPE_AR6003) {
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address = AR6003_LOCAL_COUNT_ADDRESS;
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for (i=0; actual_wait < wait_msecs; i++) {
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if (ar6000_ReadRegDiag(hifDevice, &address, &data) != 0) {
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/* No need to wait longer -- we have a BMI credit */
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return A_ERROR; /* timed out */
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#define AR6001_RESET_CONTROL_ADDRESS 0x0C000000
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#define AR6002_RESET_CONTROL_ADDRESS 0x00004000
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#define AR6003_RESET_CONTROL_ADDRESS 0x00004000
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int ar6000_reset_device(struct hif_device *hifDevice, u32 TargetType, bool waitForCompletion, bool coldReset)
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// address = RESET_CONTROL_ADDRESS;
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data = RESET_CONTROL_COLD_RST_MASK;
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data = RESET_CONTROL_MBOX_RST_MASK;
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/* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */
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if (TargetType == TARGET_TYPE_AR6002) {
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address = AR6002_RESET_CONTROL_ADDRESS;
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} else if (TargetType == TARGET_TYPE_AR6003) {
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address = AR6003_RESET_CONTROL_ADDRESS;
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status = ar6000_WriteRegDiag(hifDevice, &address, &data);
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if (!waitForCompletion) {
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/* Up to 2 second delay to allow things to settle down */
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(void)_delay_until_target_alive(hifDevice, 2000, TargetType);
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* Read back the RESET CAUSE register to ensure that the cold reset
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// address = RESET_CAUSE_ADDRESS;
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/* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */
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if (TargetType == TARGET_TYPE_AR6002) {
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address = 0x000040C0;
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} else if (TargetType == TARGET_TYPE_AR6003) {
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address = 0x000040C0;
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status = ar6000_ReadRegDiag(hifDevice, &address, &data);
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data));
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data &= RESET_CAUSE_LAST_MASK;
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n"));
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AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n"));
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/* This should be called in BMI phase after firmware is downloaded */
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ar6000_copy_cust_data_from_target(struct hif_device *hifDevice, u32 TargetType)
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u8 AR6003CustDataShadow[AR6003_CUST_DATA_SIZE+4];
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if (BMIReadMemory(hifDevice,
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HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_board_data),
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(u8 *)&eepHeaderAddr,
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadMemory for reading board data address failed \n"));
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if (TargetType == TARGET_TYPE_AR6003) {
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eepHeaderAddr += 36; /* AR6003 customer data section offset is 37 */
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for (i=0; i<AR6003_CUST_DATA_SIZE+4; i+=4){
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if (BMIReadSOCRegister(hifDevice, eepHeaderAddr, (u32 *)&AR6003CustDataShadow[i])!= 0) {
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
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memcpy(custDataAR6003, AR6003CustDataShadow+1, AR6003_CUST_DATA_SIZE);
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if (TargetType == TARGET_TYPE_AR6002) {
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eepHeaderAddr += 64; /* AR6002 customer data sectioin offset is 64 */
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for (i=0; i<AR6002_CUST_DATA_SIZE; i+=4){
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if (BMIReadSOCRegister(hifDevice, eepHeaderAddr, (u32 *)&custDataAR6002[i])!= 0) {
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
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/* This is the function to call when need to use the cust data */
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u8 *ar6000_get_cust_data_buffer(u32 TargetType)
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if (TargetType == TARGET_TYPE_AR6003)
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return custDataAR6003;
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if (TargetType == TARGET_TYPE_AR6002)
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return custDataAR6002;
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#define REG_DUMP_COUNT_AR6001 38 /* WORDs, derived from AR600x_regdump.h */
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#define REG_DUMP_COUNT_AR6002 60
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#define REG_DUMP_COUNT_AR6003 60
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#define REGISTER_DUMP_LEN_MAX 60
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#if REG_DUMP_COUNT_AR6001 > REGISTER_DUMP_LEN_MAX
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#error "REG_DUMP_COUNT_AR6001 too large"
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#if REG_DUMP_COUNT_AR6002 > REGISTER_DUMP_LEN_MAX
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#error "REG_DUMP_COUNT_AR6002 too large"
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#if REG_DUMP_COUNT_AR6003 > REGISTER_DUMP_LEN_MAX
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#error "REG_DUMP_COUNT_AR6003 too large"
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void ar6000_dump_target_assert_info(struct hif_device *hifDevice, u32 TargetType)
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u32 regDumpValues[REGISTER_DUMP_LEN_MAX];
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u32 regDumpCount = 0;
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/* the reg dump pointer is copied to the host interest area */
564
address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state);
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address = TARG_VTOP(TargetType, address);
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if (TargetType == TARGET_TYPE_AR6002) {
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regDumpCount = REG_DUMP_COUNT_AR6002;
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} else if (TargetType == TARGET_TYPE_AR6003) {
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regDumpCount = REG_DUMP_COUNT_AR6003;
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/* read RAM location through diagnostic window */
576
status = ar6000_ReadRegDiag(hifDevice, &address, ®DumpArea);
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AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n"));
583
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea));
585
if (regDumpArea == 0) {
590
regDumpArea = TARG_VTOP(TargetType, regDumpArea);
592
/* fetch register dump data */
593
status = ar6000_ReadDataDiag(hifDevice,
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(u8 *)®DumpValues[0],
596
regDumpCount * (sizeof(u32)));
599
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n"));
602
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n"));
604
for (i = 0; i < regDumpCount; i++) {
605
//ATHR_DISPLAY_MSG (_T(" %d : 0x%8.8X \n"), i, regDumpValues[i]);
606
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d : 0x%8.8X \n",i, regDumpValues[i]));
610
* For Every logPrintf() Open the File so that in case of Crashes
611
* We will have until the Last Message Flushed on to the File
612
* So use logPrintf Sparingly..!!
614
tgtassertPrintf (ATH_DEBUG_TRC," %d: 0x%8.8X \n",i, regDumpValues[i]);
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/* set HTC/Mbox operational parameters, this can only be called when the target is in the
624
int ar6000_set_htc_params(struct hif_device *hifDevice,
626
u32 MboxIsrYieldValue,
627
u8 HtcControlBuffers)
630
u32 blocksizes[HTC_MAILBOX_NUM_MAX];
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/* get the block sizes */
634
status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
635
blocksizes, sizeof(blocksizes));
638
AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n"));
641
/* note: we actually get the block size for mailbox 1, for SDIO the block
642
* size on mailbox 0 is artificially set to 1 */
643
/* must be a power of 2 */
644
A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0);
646
if (HtcControlBuffers != 0) {
647
/* set override for number of control buffers to use */
648
blocksizes[1] |= ((u32)HtcControlBuffers) << 16;
651
/* set the host interest area for the block size */
652
status = BMIWriteMemory(hifDevice,
653
HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz),
654
(u8 *)&blocksizes[1],
658
AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n"));
662
AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n",
663
blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz)));
665
if (MboxIsrYieldValue != 0) {
666
/* set the host interest area for the mbox ISR yield limit */
667
status = BMIWriteMemory(hifDevice,
668
HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit),
669
(u8 *)&MboxIsrYieldValue,
673
AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n"));
683
void DebugDumpBytes(u8 *buffer, u16 length, char *pDescription)
686
char byteOffsetStr[10];
688
u16 offset, count, byteOffset;
690
A_PRINTF("<---------Dumping %d Bytes : %s ------>\n", length, pDescription);
695
for(i = 0; i < length; i++) {
696
A_SPRINTF(stream + offset, "%2.2X ", buffer[i]);
703
A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
704
A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
705
A_MEMZERO(stream, 60);
711
A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
712
A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
715
A_PRINTF("<------------------------------------------------->\n");
718
void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
721
struct ath_debug_mask_description *pDesc;
727
pDesc = pInfo->pMaskDescriptions;
729
A_PRINTF("========================================================\n\n");
730
A_PRINTF("Module Debug Info => Name : %s \n", pInfo->ModuleName);
731
A_PRINTF(" => Descr. : %s \n", pInfo->ModuleDescription);
732
A_PRINTF("\n Current mask => 0x%8.8X \n", pInfo->CurrentMask);
733
A_PRINTF("\n Avail. Debug Masks :\n\n");
735
for (i = 0; i < pInfo->MaxDescriptions; i++,pDesc++) {
736
A_PRINTF(" => 0x%8.8X -- %s \n", pDesc->Mask, pDesc->Description);
740
A_PRINTF(" => * none defined * \n");
743
A_PRINTF("\n Standard Debug Masks :\n\n");
744
/* print standard masks */
745
A_PRINTF(" => 0x%8.8X -- Errors \n", ATH_DEBUG_ERR);
746
A_PRINTF(" => 0x%8.8X -- Warnings \n", ATH_DEBUG_WARN);
747
A_PRINTF(" => 0x%8.8X -- Informational \n", ATH_DEBUG_INFO);
748
A_PRINTF(" => 0x%8.8X -- Tracing \n", ATH_DEBUG_TRC);
749
A_PRINTF("\n========================================================\n");
754
static ATH_DEBUG_MODULE_DBG_INFO *FindModule(char *module_name)
756
ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
758
if (!g_ModuleDebugInit) {
762
while (pInfo != NULL) {
763
/* TODO: need to use something other than strlen */
764
if (memcmp(pInfo->ModuleName,module_name,strlen(module_name)) == 0) {
767
pInfo = pInfo->pNext;
774
void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
776
if (!g_ModuleDebugInit) {
780
A_MUTEX_LOCK(&g_ModuleListLock);
782
if (!(pInfo->Flags & ATH_DEBUG_INFO_FLAGS_REGISTERED)) {
783
if (g_pModuleInfoHead == NULL) {
784
g_pModuleInfoHead = pInfo;
786
pInfo->pNext = g_pModuleInfoHead;
787
g_pModuleInfoHead = pInfo;
789
pInfo->Flags |= ATH_DEBUG_INFO_FLAGS_REGISTERED;
792
A_MUTEX_UNLOCK(&g_ModuleListLock);
795
void a_dump_module_debug_info_by_name(char *module_name)
797
ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
799
if (!g_ModuleDebugInit) {
803
if (memcmp(module_name,"all",3) == 0) {
805
while (pInfo != NULL) {
806
a_dump_module_debug_info(pInfo);
807
pInfo = pInfo->pNext;
812
pInfo = FindModule(module_name);
815
a_dump_module_debug_info(pInfo);
820
int a_get_module_mask(char *module_name, u32 *pMask)
822
ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
828
*pMask = pInfo->CurrentMask;
832
int a_set_module_mask(char *module_name, u32 Mask)
834
ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
840
pInfo->CurrentMask = Mask;
841
A_PRINTF("Module %s, new mask: 0x%8.8X \n",module_name,pInfo->CurrentMask);
846
void a_module_debug_support_init(void)
848
if (g_ModuleDebugInit) {
851
A_MUTEX_INIT(&g_ModuleListLock);
852
g_pModuleInfoHead = NULL;
853
g_ModuleDebugInit = true;
854
A_REGISTER_MODULE_DEBUG_INFO(misc);
857
void a_module_debug_support_cleanup(void)
859
ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
860
ATH_DEBUG_MODULE_DBG_INFO *pCur;
862
if (!g_ModuleDebugInit) {
866
g_ModuleDebugInit = false;
868
A_MUTEX_LOCK(&g_ModuleListLock);
870
while (pInfo != NULL) {
872
pInfo = pInfo->pNext;
874
/* clear registered flag */
875
pCur->Flags &= ~ATH_DEBUG_INFO_FLAGS_REGISTERED;
878
A_MUTEX_UNLOCK(&g_ModuleListLock);
880
A_MUTEX_DELETE(&g_ModuleListLock);
881
g_pModuleInfoHead = NULL;
884
/* can only be called during bmi init stage */
885
int ar6000_set_hci_bridge_flags(struct hif_device *hifDevice,
893
if (TargetType != TARGET_TYPE_AR6003) {
894
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Target Type:%d, does not support HCI bridging! \n",
899
/* set hci bridge flags */
900
status = BMIWriteMemory(hifDevice,
901
HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_hci_bridge_flags),