1
/* ----------------------------------------------------------------------------
2
Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3
nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
5
The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6
Access Controller for Ethernet (MACE). It is essentially the Am2150
7
PCMCIA Ethernet card contained in the Am2150 Demo Kit.
9
Written by Roger C. Pao <rpao@paonet.org>
10
Copyright 1995 Roger C. Pao
11
Linux 2.5 cleanups Copyright Red Hat 2003
13
This software may be used and distributed according to the terms of
14
the GNU General Public License.
16
Ported to Linux 1.3.* network driver environment by
17
Matti Aarnio <mea@utu.fi>
21
Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22
Am79C940 (MACE) Data Sheet, 1994
23
Am79C90 (C-LANCE) Data Sheet, 1994
24
Linux PCMCIA Programmer's Guide v1.17
25
/usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
27
Eric Mears, New Media Corporation
28
Tom Pollard, New Media Corporation
29
Dean Siasoyco, New Media Corporation
30
Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31
Donald Becker <becker@scyld.com>
32
David Hinds <dahinds@users.sourceforge.net>
34
The Linux client driver is based on the 3c589_cs.c client driver by
37
The Linux network driver outline is based on the 3c589_cs.c driver,
38
the 8390.c driver, and the example skeleton.c kernel code, which are
41
The Am2150 network driver hardware interface code is based on the
42
OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
44
Special thanks for testing and help in debugging this driver goes
47
-------------------------------------------------------------------------------
48
Driver Notes and Issues
49
-------------------------------------------------------------------------------
51
1. Developed on a Dell 320SLi
52
PCMCIA Card Services 2.6.2
53
Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
55
2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56
'insmod pcmcia_core.o io_speed=300'.
57
This will avoid problems with fast systems which causes rx_framecnt
58
to return random values.
60
3. If hot extraction does not work for you, use 'ifconfig eth0 down'
63
4. There is a bad slow-down problem in this driver.
65
5. Future: Multicast processing. In the meantime, do _not_ compile your
66
kernel with multicast ip enabled.
68
-------------------------------------------------------------------------------
70
-------------------------------------------------------------------------------
72
* 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
73
* Fixed hang on card eject as we probe it
74
* Cleaned up to use new style locking.
76
* Revision 0.16 1995/07/01 06:42:17 rpao
77
* Bug fix: nmclan_reset() called CardServices incorrectly.
79
* Revision 0.15 1995/05/24 08:09:47 rpao
80
* Re-implement MULTI_TX dev->tbusy handling.
82
* Revision 0.14 1995/05/23 03:19:30 rpao
83
* Added, in nmclan_config(), "tuple.Attributes = 0;".
84
* Modified MACE ID check to ignore chip revision level.
85
* Avoid tx_free_frames race condition between _start_xmit and _interrupt.
87
* Revision 0.13 1995/05/18 05:56:34 rpao
89
* Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90
* Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
92
* Revision 0.12 1995/05/14 00:12:23 rpao
93
* Statistics overhaul.
97
Bug fix: MACE statistics counters used wrong I/O ports.
98
Bug fix: mace_interrupt() needed to allow statistics to be
99
processed without RX or TX interrupts pending.
101
Multiple transmit request processing.
102
Modified statistics to use MACE counters where possible.
103
95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
106
Bug fix: Make all non-exported functions private by using
108
Bug fix: Test IntrCnt _before_ reading MACE_IR.
109
95/05/10 rpao V0.07 Statistics.
110
95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
112
---------------------------------------------------------------------------- */
114
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
116
#define DRV_NAME "nmclan_cs"
117
#define DRV_VERSION "0.16"
120
/* ----------------------------------------------------------------------------
121
Conditional Compilation Options
122
---------------------------------------------------------------------------- */
125
#define RESET_ON_TIMEOUT 1
126
#define TX_INTERRUPTABLE 1
127
#define RESET_XILINX 0
129
/* ----------------------------------------------------------------------------
131
---------------------------------------------------------------------------- */
133
#include <linux/module.h>
134
#include <linux/kernel.h>
135
#include <linux/init.h>
136
#include <linux/ptrace.h>
137
#include <linux/slab.h>
138
#include <linux/string.h>
139
#include <linux/timer.h>
140
#include <linux/interrupt.h>
141
#include <linux/in.h>
142
#include <linux/delay.h>
143
#include <linux/ethtool.h>
144
#include <linux/netdevice.h>
145
#include <linux/etherdevice.h>
146
#include <linux/skbuff.h>
147
#include <linux/if_arp.h>
148
#include <linux/ioport.h>
149
#include <linux/bitops.h>
151
#include <pcmcia/cisreg.h>
152
#include <pcmcia/cistpl.h>
153
#include <pcmcia/ds.h>
155
#include <asm/uaccess.h>
157
#include <asm/system.h>
159
/* ----------------------------------------------------------------------------
161
---------------------------------------------------------------------------- */
163
#define ETHER_ADDR_LEN ETH_ALEN
164
/* 6 bytes in an Ethernet Address */
165
#define MACE_LADRF_LEN 8
166
/* 8 bytes in Logical Address Filter */
168
/* Loop Control Defines */
169
#define MACE_MAX_IR_ITERATIONS 10
170
#define MACE_MAX_RX_ITERATIONS 12
172
TBD: Dean brought this up, and I assumed the hardware would
175
If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
176
non-zero when the isr exits. We may not get another interrupt
177
to process the remaining packets for some time.
181
The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
182
which manages the interface between the MACE and the PCMCIA bus. It
183
also includes buffer management for the 32K x 8 SRAM to control up to
184
four transmit and 12 receive frames at a time.
186
#define AM2150_MAX_TX_FRAMES 4
187
#define AM2150_MAX_RX_FRAMES 12
189
/* Am2150 Ethernet Card I/O Mapping */
190
#define AM2150_RCV 0x00
191
#define AM2150_XMT 0x04
192
#define AM2150_XMT_SKIP 0x09
193
#define AM2150_RCV_NEXT 0x0A
194
#define AM2150_RCV_FRAME_COUNT 0x0B
195
#define AM2150_MACE_BANK 0x0C
196
#define AM2150_MACE_BASE 0x10
199
#define MACE_RCVFIFO 0
200
#define MACE_XMTFIFO 1
206
#define MACE_FIFOFC 7
210
#define MACE_BIUCC 11
211
#define MACE_FIFOCC 12
212
#define MACE_MACCC 13
213
#define MACE_PLSCC 14
214
#define MACE_PHYCC 15
215
#define MACE_CHIPIDL 16
216
#define MACE_CHIPIDH 17
219
#define MACE_LADRF 20
225
#define MACE_RNTPC 26
226
#define MACE_RCVCC 27
233
#define MACE_XMTRC_EXDEF 0x80
234
#define MACE_XMTRC_XMTRC 0x0F
236
#define MACE_XMTFS_XMTSV 0x80
237
#define MACE_XMTFS_UFLO 0x40
238
#define MACE_XMTFS_LCOL 0x20
239
#define MACE_XMTFS_MORE 0x10
240
#define MACE_XMTFS_ONE 0x08
241
#define MACE_XMTFS_DEFER 0x04
242
#define MACE_XMTFS_LCAR 0x02
243
#define MACE_XMTFS_RTRY 0x01
245
#define MACE_RCVFS_RCVSTS 0xF000
246
#define MACE_RCVFS_OFLO 0x8000
247
#define MACE_RCVFS_CLSN 0x4000
248
#define MACE_RCVFS_FRAM 0x2000
249
#define MACE_RCVFS_FCS 0x1000
251
#define MACE_FIFOFC_RCVFC 0xF0
252
#define MACE_FIFOFC_XMTFC 0x0F
254
#define MACE_IR_JAB 0x80
255
#define MACE_IR_BABL 0x40
256
#define MACE_IR_CERR 0x20
257
#define MACE_IR_RCVCCO 0x10
258
#define MACE_IR_RNTPCO 0x08
259
#define MACE_IR_MPCO 0x04
260
#define MACE_IR_RCVINT 0x02
261
#define MACE_IR_XMTINT 0x01
263
#define MACE_MACCC_PROM 0x80
264
#define MACE_MACCC_DXMT2PD 0x40
265
#define MACE_MACCC_EMBA 0x20
266
#define MACE_MACCC_RESERVED 0x10
267
#define MACE_MACCC_DRCVPA 0x08
268
#define MACE_MACCC_DRCVBC 0x04
269
#define MACE_MACCC_ENXMT 0x02
270
#define MACE_MACCC_ENRCV 0x01
272
#define MACE_PHYCC_LNKFL 0x80
273
#define MACE_PHYCC_DLNKTST 0x40
274
#define MACE_PHYCC_REVPOL 0x20
275
#define MACE_PHYCC_DAPC 0x10
276
#define MACE_PHYCC_LRT 0x08
277
#define MACE_PHYCC_ASEL 0x04
278
#define MACE_PHYCC_RWAKE 0x02
279
#define MACE_PHYCC_AWAKE 0x01
281
#define MACE_IAC_ADDRCHG 0x80
282
#define MACE_IAC_PHYADDR 0x04
283
#define MACE_IAC_LOGADDR 0x02
285
#define MACE_UTR_RTRE 0x80
286
#define MACE_UTR_RTRD 0x40
287
#define MACE_UTR_RPA 0x20
288
#define MACE_UTR_FCOLL 0x10
289
#define MACE_UTR_RCVFCSE 0x08
290
#define MACE_UTR_LOOP_INCL_MENDEC 0x06
291
#define MACE_UTR_LOOP_NO_MENDEC 0x04
292
#define MACE_UTR_LOOP_EXTERNAL 0x02
293
#define MACE_UTR_LOOP_NONE 0x00
294
#define MACE_UTR_RESERVED 0x01
296
/* Switch MACE register bank (only 0 and 1 are valid) */
297
#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
299
#define MACE_IMR_DEFAULT \
310
#undef MACE_IMR_DEFAULT
311
#define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
313
#define TX_TIMEOUT ((400*HZ)/1000)
315
/* ----------------------------------------------------------------------------
317
---------------------------------------------------------------------------- */
319
typedef struct _mace_statistics {
334
/* RFS1--Receive Status (RCVSTS) */
340
/* RFS2--Runt Packet Count (RNTPC) */
343
/* RFS3--Receive Collision Count (RCVCC) */
364
typedef struct _mace_private {
365
struct pcmcia_device *p_dev;
366
struct net_device_stats linux_stats; /* Linux statistics counters */
367
mace_statistics mace_stats; /* MACE chip statistics counters */
369
/* restore_multicast_list() state variables */
370
int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
371
int multicast_num_addrs;
373
char tx_free_frames; /* Number of free transmit frame buffers */
374
char tx_irq_disabled; /* MACE TX interrupt disabled */
376
spinlock_t bank_lock; /* Must be held if you step off bank 0 */
379
/* ----------------------------------------------------------------------------
380
Private Global Variables
381
---------------------------------------------------------------------------- */
383
static const char *if_names[]={
384
"Auto", "10baseT", "BNC",
387
/* ----------------------------------------------------------------------------
389
These are the parameters that can be set during loading with
391
---------------------------------------------------------------------------- */
393
MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
394
MODULE_LICENSE("GPL");
396
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
398
/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
399
INT_MODULE_PARM(if_port, 0);
402
/* ----------------------------------------------------------------------------
404
---------------------------------------------------------------------------- */
406
static int nmclan_config(struct pcmcia_device *link);
407
static void nmclan_release(struct pcmcia_device *link);
409
static void nmclan_reset(struct net_device *dev);
410
static int mace_config(struct net_device *dev, struct ifmap *map);
411
static int mace_open(struct net_device *dev);
412
static int mace_close(struct net_device *dev);
413
static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
414
struct net_device *dev);
415
static void mace_tx_timeout(struct net_device *dev);
416
static irqreturn_t mace_interrupt(int irq, void *dev_id);
417
static struct net_device_stats *mace_get_stats(struct net_device *dev);
418
static int mace_rx(struct net_device *dev, unsigned char RxCnt);
419
static void restore_multicast_list(struct net_device *dev);
420
static void set_multicast_list(struct net_device *dev);
421
static const struct ethtool_ops netdev_ethtool_ops;
424
static void nmclan_detach(struct pcmcia_device *p_dev);
426
static const struct net_device_ops mace_netdev_ops = {
427
.ndo_open = mace_open,
428
.ndo_stop = mace_close,
429
.ndo_start_xmit = mace_start_xmit,
430
.ndo_tx_timeout = mace_tx_timeout,
431
.ndo_set_config = mace_config,
432
.ndo_get_stats = mace_get_stats,
433
.ndo_set_rx_mode = set_multicast_list,
434
.ndo_change_mtu = eth_change_mtu,
435
.ndo_set_mac_address = eth_mac_addr,
436
.ndo_validate_addr = eth_validate_addr,
439
static int nmclan_probe(struct pcmcia_device *link)
442
struct net_device *dev;
444
dev_dbg(&link->dev, "nmclan_attach()\n");
446
/* Create new ethernet device */
447
dev = alloc_etherdev(sizeof(mace_private));
450
lp = netdev_priv(dev);
454
spin_lock_init(&lp->bank_lock);
455
link->resource[0]->end = 32;
456
link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
457
link->config_flags |= CONF_ENABLE_IRQ;
458
link->config_index = 1;
459
link->config_regs = PRESENT_OPTION;
461
lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
463
dev->netdev_ops = &mace_netdev_ops;
464
SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
465
dev->watchdog_timeo = TX_TIMEOUT;
467
return nmclan_config(link);
468
} /* nmclan_attach */
470
static void nmclan_detach(struct pcmcia_device *link)
472
struct net_device *dev = link->priv;
474
dev_dbg(&link->dev, "nmclan_detach\n");
476
unregister_netdev(dev);
478
nmclan_release(link);
481
} /* nmclan_detach */
483
/* ----------------------------------------------------------------------------
485
Reads a MACE register. This is bank independent; however, the
486
caller must ensure that this call is not interruptable. We are
487
assuming that during normal operation, the MACE is always in
489
---------------------------------------------------------------------------- */
490
static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
496
case 0: /* register 0-15 */
497
data = inb(ioaddr + AM2150_MACE_BASE + reg);
499
case 1: /* register 16-31 */
500
spin_lock_irqsave(&lp->bank_lock, flags);
502
data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
504
spin_unlock_irqrestore(&lp->bank_lock, flags);
510
/* ----------------------------------------------------------------------------
512
Writes to a MACE register. This is bank independent; however,
513
the caller must ensure that this call is not interruptable. We
514
are assuming that during normal operation, the MACE is always in
516
---------------------------------------------------------------------------- */
517
static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
523
case 0: /* register 0-15 */
524
outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
526
case 1: /* register 16-31 */
527
spin_lock_irqsave(&lp->bank_lock, flags);
529
outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
531
spin_unlock_irqrestore(&lp->bank_lock, flags);
536
/* ----------------------------------------------------------------------------
538
Resets the MACE chip.
539
---------------------------------------------------------------------------- */
540
static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
545
/* MACE Software reset */
546
mace_write(lp, ioaddr, MACE_BIUCC, 1);
547
while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
548
/* Wait for reset bit to be cleared automatically after <= 200ns */;
551
pr_err("reset failed, card removed?\n");
556
mace_write(lp, ioaddr, MACE_BIUCC, 0);
558
/* The Am2150 requires that the MACE FIFOs operate in burst mode. */
559
mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
561
mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
562
mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
565
* Bit 2-1 PORTSEL[1-0] Port Select.
568
* 10 DAI Port (reserved in Am2150)
570
* For this card, only the first two are valid.
571
* So, PLSCC should be set to
574
* Or just set ASEL in PHYCC below!
578
mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
581
mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
584
mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
585
/* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
586
and the MACE device will automatically select the operating media
591
mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
592
/* Poll ADDRCHG bit */
594
while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
598
pr_err("ADDRCHG timeout, card removed?\n");
602
/* Set PADR register */
603
for (i = 0; i < ETHER_ADDR_LEN; i++)
604
mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
606
/* MAC Configuration Control Register should be written last */
607
/* Let set_multicast_list set this. */
608
/* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
609
mace_write(lp, ioaddr, MACE_MACCC, 0x00);
613
static int nmclan_config(struct pcmcia_device *link)
615
struct net_device *dev = link->priv;
616
mace_private *lp = netdev_priv(dev);
622
dev_dbg(&link->dev, "nmclan_config\n");
625
ret = pcmcia_request_io(link);
628
ret = pcmcia_request_exclusive_irq(link, mace_interrupt);
631
ret = pcmcia_enable_device(link);
635
dev->irq = link->irq;
636
dev->base_addr = link->resource[0]->start;
638
ioaddr = dev->base_addr;
640
/* Read the ethernet address from the CIS. */
641
len = pcmcia_get_tuple(link, 0x80, &buf);
642
if (!buf || len < ETHER_ADDR_LEN) {
646
memcpy(dev->dev_addr, buf, ETHER_ADDR_LEN);
649
/* Verify configuration by reading the MACE ID. */
653
sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
654
sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
655
if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
656
dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
659
pr_notice("mace id not found: %x %x should be 0x40 0x?9\n",
665
if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
668
/* The if_port symbol can be set when the module is loaded */
670
dev->if_port = if_port;
672
pr_notice("invalid if_port requested\n");
674
SET_NETDEV_DEV(dev, &link->dev);
676
i = register_netdev(dev);
678
pr_notice("register_netdev() failed\n");
682
netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n",
683
dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr);
687
nmclan_release(link);
689
} /* nmclan_config */
691
static void nmclan_release(struct pcmcia_device *link)
693
dev_dbg(&link->dev, "nmclan_release\n");
694
pcmcia_disable_device(link);
697
static int nmclan_suspend(struct pcmcia_device *link)
699
struct net_device *dev = link->priv;
702
netif_device_detach(dev);
707
static int nmclan_resume(struct pcmcia_device *link)
709
struct net_device *dev = link->priv;
713
netif_device_attach(dev);
720
/* ----------------------------------------------------------------------------
722
Reset and restore all of the Xilinx and MACE registers.
723
---------------------------------------------------------------------------- */
724
static void nmclan_reset(struct net_device *dev)
726
mace_private *lp = netdev_priv(dev);
729
struct pcmcia_device *link = &lp->link;
732
/* Save original COR value */
733
pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
736
dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
738
pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
739
/* Need to wait for 20 ms for PCMCIA to finish reset. */
741
/* Restore original COR configuration index */
742
pcmcia_write_config_byte(link, CISREG_COR,
743
(COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
744
/* Xilinx is now completely reset along with the MACE chip. */
745
lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
747
#endif /* #if RESET_XILINX */
749
/* Xilinx is now completely reset along with the MACE chip. */
750
lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
752
/* Reinitialize the MACE chip for operation. */
753
mace_init(lp, dev->base_addr, dev->dev_addr);
754
mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
756
/* Restore the multicast list and enable TX and RX. */
757
restore_multicast_list(dev);
760
/* ----------------------------------------------------------------------------
762
[Someone tell me what this is supposed to do? Is if_port a defined
763
standard? If so, there should be defines to indicate 1=10Base-T,
764
2=10Base-2, etc. including limited automatic detection.]
765
---------------------------------------------------------------------------- */
766
static int mace_config(struct net_device *dev, struct ifmap *map)
768
if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
769
if (map->port <= 2) {
770
dev->if_port = map->port;
771
netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
778
/* ----------------------------------------------------------------------------
781
---------------------------------------------------------------------------- */
782
static int mace_open(struct net_device *dev)
784
unsigned int ioaddr = dev->base_addr;
785
mace_private *lp = netdev_priv(dev);
786
struct pcmcia_device *link = lp->p_dev;
788
if (!pcmcia_dev_present(link))
795
netif_start_queue(dev);
798
return 0; /* Always succeed */
801
/* ----------------------------------------------------------------------------
803
Closes device driver.
804
---------------------------------------------------------------------------- */
805
static int mace_close(struct net_device *dev)
807
unsigned int ioaddr = dev->base_addr;
808
mace_private *lp = netdev_priv(dev);
809
struct pcmcia_device *link = lp->p_dev;
811
dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
813
/* Mask off all interrupts from the MACE chip. */
814
outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
817
netif_stop_queue(dev);
822
static void netdev_get_drvinfo(struct net_device *dev,
823
struct ethtool_drvinfo *info)
825
strcpy(info->driver, DRV_NAME);
826
strcpy(info->version, DRV_VERSION);
827
sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
830
static const struct ethtool_ops netdev_ethtool_ops = {
831
.get_drvinfo = netdev_get_drvinfo,
834
/* ----------------------------------------------------------------------------
836
This routine begins the packet transmit function. When completed,
837
it will generate a transmit interrupt.
839
According to /usr/src/linux/net/inet/dev.c, if _start_xmit
840
returns 0, the "packet is now solely the responsibility of the
841
driver." If _start_xmit returns non-zero, the "transmission
842
failed, put skb back into a list."
843
---------------------------------------------------------------------------- */
845
static void mace_tx_timeout(struct net_device *dev)
847
mace_private *lp = netdev_priv(dev);
848
struct pcmcia_device *link = lp->p_dev;
850
netdev_notice(dev, "transmit timed out -- ");
852
pr_cont("resetting card\n");
853
pcmcia_reset_card(link->socket);
854
#else /* #if RESET_ON_TIMEOUT */
855
pr_cont("NOT resetting card\n");
856
#endif /* #if RESET_ON_TIMEOUT */
857
dev->trans_start = jiffies; /* prevent tx timeout */
858
netif_wake_queue(dev);
861
static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
862
struct net_device *dev)
864
mace_private *lp = netdev_priv(dev);
865
unsigned int ioaddr = dev->base_addr;
867
netif_stop_queue(dev);
869
pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
870
dev->name, (long)skb->len);
872
#if (!TX_INTERRUPTABLE)
873
/* Disable MACE TX interrupts. */
874
outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
875
ioaddr + AM2150_MACE_BASE + MACE_IMR);
876
lp->tx_irq_disabled=1;
877
#endif /* #if (!TX_INTERRUPTABLE) */
880
/* This block must not be interrupted by another transmit request!
881
mace_tx_timeout will take care of timer-based retransmissions from
882
the upper layers. The interrupt handler is guaranteed never to
883
service a transmit interrupt while we are in here.
886
lp->linux_stats.tx_bytes += skb->len;
887
lp->tx_free_frames--;
889
/* WARNING: Write the _exact_ number of bytes written in the header! */
890
/* Put out the word header [must be an outw()] . . . */
891
outw(skb->len, ioaddr + AM2150_XMT);
892
/* . . . and the packet [may be any combination of outw() and outb()] */
893
outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
895
/* Odd byte transfer */
896
outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
900
if (lp->tx_free_frames > 0)
901
netif_start_queue(dev);
902
#endif /* #if MULTI_TX */
905
#if (!TX_INTERRUPTABLE)
906
/* Re-enable MACE TX interrupts. */
907
lp->tx_irq_disabled=0;
908
outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
909
#endif /* #if (!TX_INTERRUPTABLE) */
914
} /* mace_start_xmit */
916
/* ----------------------------------------------------------------------------
918
The interrupt handler.
919
---------------------------------------------------------------------------- */
920
static irqreturn_t mace_interrupt(int irq, void *dev_id)
922
struct net_device *dev = (struct net_device *) dev_id;
923
mace_private *lp = netdev_priv(dev);
926
int IntrCnt = MACE_MAX_IR_ITERATIONS;
929
pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
934
ioaddr = dev->base_addr;
936
if (lp->tx_irq_disabled) {
938
if (lp->tx_irq_disabled)
939
msg = "Interrupt with tx_irq_disabled";
941
msg = "Re-entering the interrupt handler";
942
netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n",
944
inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
945
inb(ioaddr + AM2150_MACE_BASE + MACE_IMR));
946
/* WARNING: MACE_IR has been read! */
950
if (!netif_device_present(dev)) {
951
netdev_dbg(dev, "interrupt from dead card\n");
956
/* WARNING: MACE_IR is a READ/CLEAR port! */
957
status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
959
pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
961
if (status & MACE_IR_RCVINT) {
962
mace_rx(dev, MACE_MAX_RX_ITERATIONS);
965
if (status & MACE_IR_XMTINT) {
966
unsigned char fifofc;
970
fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
971
if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
972
lp->linux_stats.tx_errors++;
973
outb(0xFF, ioaddr + AM2150_XMT_SKIP);
976
/* Transmit Retry Count (XMTRC, reg 4) */
977
xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
978
if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
979
lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
982
(xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
983
MACE_XMTFS_XMTSV /* Transmit Status Valid */
985
lp->mace_stats.xmtsv++;
987
if (xmtfs & ~MACE_XMTFS_XMTSV) {
988
if (xmtfs & MACE_XMTFS_UFLO) {
989
/* Underflow. Indicates that the Transmit FIFO emptied before
990
the end of frame was reached. */
991
lp->mace_stats.uflo++;
993
if (xmtfs & MACE_XMTFS_LCOL) {
995
lp->mace_stats.lcol++;
997
if (xmtfs & MACE_XMTFS_MORE) {
998
/* MORE than one retry was needed */
999
lp->mace_stats.more++;
1001
if (xmtfs & MACE_XMTFS_ONE) {
1002
/* Exactly ONE retry occurred */
1003
lp->mace_stats.one++;
1005
if (xmtfs & MACE_XMTFS_DEFER) {
1006
/* Transmission was defered */
1007
lp->mace_stats.defer++;
1009
if (xmtfs & MACE_XMTFS_LCAR) {
1010
/* Loss of carrier */
1011
lp->mace_stats.lcar++;
1013
if (xmtfs & MACE_XMTFS_RTRY) {
1014
/* Retry error: transmit aborted after 16 attempts */
1015
lp->mace_stats.rtry++;
1017
} /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1019
} /* if (xmtfs & MACE_XMTFS_XMTSV) */
1021
lp->linux_stats.tx_packets++;
1022
lp->tx_free_frames++;
1023
netif_wake_queue(dev);
1024
} /* if (status & MACE_IR_XMTINT) */
1026
if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1027
if (status & MACE_IR_JAB) {
1028
/* Jabber Error. Excessive transmit duration (20-150ms). */
1029
lp->mace_stats.jab++;
1031
if (status & MACE_IR_BABL) {
1032
/* Babble Error. >1518 bytes transmitted. */
1033
lp->mace_stats.babl++;
1035
if (status & MACE_IR_CERR) {
1036
/* Collision Error. CERR indicates the absence of the
1037
Signal Quality Error Test message after a packet
1039
lp->mace_stats.cerr++;
1041
if (status & MACE_IR_RCVCCO) {
1042
/* Receive Collision Count Overflow; */
1043
lp->mace_stats.rcvcco++;
1045
if (status & MACE_IR_RNTPCO) {
1046
/* Runt Packet Count Overflow */
1047
lp->mace_stats.rntpco++;
1049
if (status & MACE_IR_MPCO) {
1050
/* Missed Packet Count Overflow */
1051
lp->mace_stats.mpco++;
1053
} /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1055
} while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1058
} /* mace_interrupt */
1060
/* ----------------------------------------------------------------------------
1063
---------------------------------------------------------------------------- */
1064
static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1066
mace_private *lp = netdev_priv(dev);
1067
unsigned int ioaddr = dev->base_addr;
1068
unsigned char rx_framecnt;
1069
unsigned short rx_status;
1072
((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1073
(rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1076
rx_status = inw(ioaddr + AM2150_RCV);
1078
pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1079
" 0x%X.\n", dev->name, rx_framecnt, rx_status);
1081
if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1082
lp->linux_stats.rx_errors++;
1083
if (rx_status & MACE_RCVFS_OFLO) {
1084
lp->mace_stats.oflo++;
1086
if (rx_status & MACE_RCVFS_CLSN) {
1087
lp->mace_stats.clsn++;
1089
if (rx_status & MACE_RCVFS_FRAM) {
1090
lp->mace_stats.fram++;
1092
if (rx_status & MACE_RCVFS_FCS) {
1093
lp->mace_stats.fcs++;
1096
short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1097
/* Auto Strip is off, always subtract 4 */
1098
struct sk_buff *skb;
1100
lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1101
/* runt packet count */
1102
lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1103
/* rcv collision count */
1105
pr_debug(" receiving packet size 0x%X rx_status"
1106
" 0x%X.\n", pkt_len, rx_status);
1108
skb = dev_alloc_skb(pkt_len+2);
1111
skb_reserve(skb, 2);
1112
insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1114
*(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1115
skb->protocol = eth_type_trans(skb, dev);
1117
netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1119
lp->linux_stats.rx_packets++;
1120
lp->linux_stats.rx_bytes += pkt_len;
1121
outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1124
pr_debug("%s: couldn't allocate a sk_buff of size"
1125
" %d.\n", dev->name, pkt_len);
1126
lp->linux_stats.rx_dropped++;
1129
outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1135
/* ----------------------------------------------------------------------------
1137
---------------------------------------------------------------------------- */
1138
static void pr_linux_stats(struct net_device_stats *pstats)
1140
pr_debug("pr_linux_stats\n");
1141
pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1142
(long)pstats->rx_packets, (long)pstats->tx_packets);
1143
pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1144
(long)pstats->rx_errors, (long)pstats->tx_errors);
1145
pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1146
(long)pstats->rx_dropped, (long)pstats->tx_dropped);
1147
pr_debug(" multicast=%-7ld collisions=%ld\n",
1148
(long)pstats->multicast, (long)pstats->collisions);
1150
pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1151
(long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1152
pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1153
(long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1154
pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1155
(long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1157
pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1158
(long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1159
pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1160
(long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1161
pr_debug(" tx_window_errors=%ld\n",
1162
(long)pstats->tx_window_errors);
1163
} /* pr_linux_stats */
1165
/* ----------------------------------------------------------------------------
1167
---------------------------------------------------------------------------- */
1168
static void pr_mace_stats(mace_statistics *pstats)
1170
pr_debug("pr_mace_stats\n");
1172
pr_debug(" xmtsv=%-7d uflo=%d\n",
1173
pstats->xmtsv, pstats->uflo);
1174
pr_debug(" lcol=%-7d more=%d\n",
1175
pstats->lcol, pstats->more);
1176
pr_debug(" one=%-7d defer=%d\n",
1177
pstats->one, pstats->defer);
1178
pr_debug(" lcar=%-7d rtry=%d\n",
1179
pstats->lcar, pstats->rtry);
1182
pr_debug(" exdef=%-7d xmtrc=%d\n",
1183
pstats->exdef, pstats->xmtrc);
1185
/* RFS1--Receive Status (RCVSTS) */
1186
pr_debug(" oflo=%-7d clsn=%d\n",
1187
pstats->oflo, pstats->clsn);
1188
pr_debug(" fram=%-7d fcs=%d\n",
1189
pstats->fram, pstats->fcs);
1191
/* RFS2--Runt Packet Count (RNTPC) */
1192
/* RFS3--Receive Collision Count (RCVCC) */
1193
pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1194
pstats->rfs_rntpc, pstats->rfs_rcvcc);
1197
pr_debug(" jab=%-7d babl=%d\n",
1198
pstats->jab, pstats->babl);
1199
pr_debug(" cerr=%-7d rcvcco=%d\n",
1200
pstats->cerr, pstats->rcvcco);
1201
pr_debug(" rntpco=%-7d mpco=%d\n",
1202
pstats->rntpco, pstats->mpco);
1205
pr_debug(" mpc=%d\n", pstats->mpc);
1208
pr_debug(" rntpc=%d\n", pstats->rntpc);
1211
pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1213
} /* pr_mace_stats */
1215
/* ----------------------------------------------------------------------------
1217
Update statistics. We change to register window 1, so this
1218
should be run single-threaded if the device is active. This is
1219
expected to be a rare operation, and it's simpler for the rest
1220
of the driver to assume that window 0 is always valid rather
1221
than use a special window-state variable.
1223
oflo & uflo should _never_ occur since it would mean the Xilinx
1224
was not able to transfer data between the MACE FIFO and the
1225
card's SRAM fast enough. If this happens, something is
1226
seriously wrong with the hardware.
1227
---------------------------------------------------------------------------- */
1228
static void update_stats(unsigned int ioaddr, struct net_device *dev)
1230
mace_private *lp = netdev_priv(dev);
1232
lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1233
lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1234
lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1235
/* At this point, mace_stats is fully updated for this call.
1236
We may now update the linux_stats. */
1238
/* The MACE has no equivalent for linux_stats field which are commented
1241
/* lp->linux_stats.multicast; */
1242
lp->linux_stats.collisions =
1243
lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1244
/* Collision: The MACE may retry sending a packet 15 times
1245
before giving up. The retry count is in XMTRC.
1246
Does each retry constitute a collision?
1247
If so, why doesn't the RCVCC record these collisions? */
1249
/* detailed rx_errors: */
1250
lp->linux_stats.rx_length_errors =
1251
lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1252
/* lp->linux_stats.rx_over_errors */
1253
lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1254
lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1255
lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1256
lp->linux_stats.rx_missed_errors =
1257
lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1259
/* detailed tx_errors */
1260
lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1261
lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1262
/* LCAR usually results from bad cabling. */
1263
lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1264
lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1265
/* lp->linux_stats.tx_window_errors; */
1266
} /* update_stats */
1268
/* ----------------------------------------------------------------------------
1270
Gathers ethernet statistics from the MACE chip.
1271
---------------------------------------------------------------------------- */
1272
static struct net_device_stats *mace_get_stats(struct net_device *dev)
1274
mace_private *lp = netdev_priv(dev);
1276
update_stats(dev->base_addr, dev);
1278
pr_debug("%s: updating the statistics.\n", dev->name);
1279
pr_linux_stats(&lp->linux_stats);
1280
pr_mace_stats(&lp->mace_stats);
1282
return &lp->linux_stats;
1283
} /* net_device_stats */
1285
/* ----------------------------------------------------------------------------
1287
Modified from Am79C90 data sheet.
1288
---------------------------------------------------------------------------- */
1290
#ifdef BROKEN_MULTICAST
1292
static void updateCRC(int *CRC, int bit)
1294
static const int poly[]={
1299
}; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1300
CRC generator polynomial. */
1304
/* shift CRC and control bit (CRC[32]) */
1305
for (j = 32; j > 0; j--)
1309
/* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1311
for (j = 0; j < 32; j++)
1315
/* ----------------------------------------------------------------------------
1317
Build logical address filter.
1318
Modified from Am79C90 data sheet.
1321
ladrf: logical address filter (contents initialized to 0)
1322
adr: ethernet address
1323
---------------------------------------------------------------------------- */
1324
static void BuildLAF(int *ladrf, int *adr)
1326
int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1328
int i, byte; /* temporary array indices */
1329
int hashcode; /* the output object */
1333
for (byte = 0; byte < 6; byte++)
1334
for (i = 0; i < 8; i++)
1335
updateCRC(CRC, (adr[byte] >> i) & 1);
1338
for (i = 0; i < 6; i++)
1339
hashcode = (hashcode << 1) + CRC[i];
1341
byte = hashcode >> 3;
1342
ladrf[byte] |= (1 << (hashcode & 7));
1346
printk(KERN_DEBUG " adr =%pM\n", adr);
1347
printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1348
for (i = 0; i < 8; i++)
1349
pr_cont(" %02X", ladrf[i]);
1354
/* ----------------------------------------------------------------------------
1355
restore_multicast_list
1356
Restores the multicast filter for MACE chip to the last
1357
set_multicast_list() call.
1362
---------------------------------------------------------------------------- */
1363
static void restore_multicast_list(struct net_device *dev)
1365
mace_private *lp = netdev_priv(dev);
1366
int num_addrs = lp->multicast_num_addrs;
1367
int *ladrf = lp->multicast_ladrf;
1368
unsigned int ioaddr = dev->base_addr;
1371
pr_debug("%s: restoring Rx mode to %d addresses.\n",
1372
dev->name, num_addrs);
1374
if (num_addrs > 0) {
1376
pr_debug("Attempt to restore multicast list detected.\n");
1378
mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1379
/* Poll ADDRCHG bit */
1380
while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1382
/* Set LADRF register */
1383
for (i = 0; i < MACE_LADRF_LEN; i++)
1384
mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1386
mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1387
mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1389
} else if (num_addrs < 0) {
1391
/* Promiscuous mode: receive all packets */
1392
mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1393
mace_write(lp, ioaddr, MACE_MACCC,
1394
MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1400
mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1401
mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1404
} /* restore_multicast_list */
1406
/* ----------------------------------------------------------------------------
1408
Set or clear the multicast filter for this adaptor.
1411
num_addrs == -1 Promiscuous mode, receive all packets
1412
num_addrs == 0 Normal mode, clear multicast list
1413
num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1414
best-effort filtering.
1418
---------------------------------------------------------------------------- */
1420
static void set_multicast_list(struct net_device *dev)
1422
mace_private *lp = netdev_priv(dev);
1423
int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1424
struct netdev_hw_addr *ha;
1429
if (netdev_mc_count(dev) != old) {
1430
old = netdev_mc_count(dev);
1431
pr_debug("%s: setting Rx mode to %d addresses.\n",
1437
/* Set multicast_num_addrs. */
1438
lp->multicast_num_addrs = netdev_mc_count(dev);
1440
/* Set multicast_ladrf. */
1441
if (num_addrs > 0) {
1442
/* Calculate multicast logical address filter */
1443
memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1444
netdev_for_each_mc_addr(ha, dev) {
1445
memcpy(adr, ha->addr, ETHER_ADDR_LEN);
1446
BuildLAF(lp->multicast_ladrf, adr);
1450
restore_multicast_list(dev);
1452
} /* set_multicast_list */
1454
#endif /* BROKEN_MULTICAST */
1456
static void restore_multicast_list(struct net_device *dev)
1458
unsigned int ioaddr = dev->base_addr;
1459
mace_private *lp = netdev_priv(dev);
1461
pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1462
lp->multicast_num_addrs);
1464
if (dev->flags & IFF_PROMISC) {
1465
/* Promiscuous mode: receive all packets */
1466
mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1467
mace_write(lp, ioaddr, MACE_MACCC,
1468
MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1472
mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1473
mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1475
} /* restore_multicast_list */
1477
static void set_multicast_list(struct net_device *dev)
1479
mace_private *lp = netdev_priv(dev);
1484
if (netdev_mc_count(dev) != old) {
1485
old = netdev_mc_count(dev);
1486
pr_debug("%s: setting Rx mode to %d addresses.\n",
1492
lp->multicast_num_addrs = netdev_mc_count(dev);
1493
restore_multicast_list(dev);
1495
} /* set_multicast_list */
1497
static const struct pcmcia_device_id nmclan_ids[] = {
1498
PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1499
PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1502
MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1504
static struct pcmcia_driver nmclan_cs_driver = {
1505
.owner = THIS_MODULE,
1506
.name = "nmclan_cs",
1507
.probe = nmclan_probe,
1508
.remove = nmclan_detach,
1509
.id_table = nmclan_ids,
1510
.suspend = nmclan_suspend,
1511
.resume = nmclan_resume,
1514
static int __init init_nmclan_cs(void)
1516
return pcmcia_register_driver(&nmclan_cs_driver);
1519
static void __exit exit_nmclan_cs(void)
1521
pcmcia_unregister_driver(&nmclan_cs_driver);
1524
module_init(init_nmclan_cs);
1525
module_exit(exit_nmclan_cs);