1
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
3
* Copyright 2005-2006 Fen Systems Ltd.
4
* Copyright 2006-2010 Solarflare Communications Inc.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include "net_driver.h"
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#include "workarounds.h"
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#include "mcdi_pcol.h"
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/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
32
static void siena_init_wol(struct efx_nic *efx);
35
static void siena_push_irq_moderation(struct efx_channel *channel)
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efx_dword_t timer_cmd;
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BUILD_BUG_ON(EFX_IRQ_MOD_MAX > (1 << FRF_CZ_TC_TIMER_VAL_WIDTH));
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if (channel->irq_moderation)
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EFX_POPULATE_DWORD_2(timer_cmd,
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FFE_CZ_TIMER_MODE_INT_HLDOFF,
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channel->irq_moderation - 1);
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EFX_POPULATE_DWORD_2(timer_cmd,
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FFE_CZ_TIMER_MODE_DIS,
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FRF_CZ_TC_TIMER_VAL, 0);
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efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
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static void siena_push_multicast_hash(struct efx_nic *efx)
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WARN_ON(!mutex_is_locked(&efx->mac_lock));
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efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
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efx->multicast_hash.byte, sizeof(efx->multicast_hash),
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static int siena_mdio_write(struct net_device *net_dev,
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int prtad, int devad, u16 addr, u16 value)
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struct efx_nic *efx = netdev_priv(net_dev);
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rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
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addr, value, &status);
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if (status != MC_CMD_MDIO_STATUS_GOOD)
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static int siena_mdio_read(struct net_device *net_dev,
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int prtad, int devad, u16 addr)
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struct efx_nic *efx = netdev_priv(net_dev);
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rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
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addr, &value, &status);
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if (status != MC_CMD_MDIO_STATUS_GOOD)
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/* This call is responsible for hooking in the MAC and PHY operations */
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static int siena_probe_port(struct efx_nic *efx)
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/* Hook in PHY operations table */
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efx->phy_op = &efx_mcdi_phy_ops;
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/* Set up MDIO structure for PHY */
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efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
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efx->mdio.mdio_read = siena_mdio_read;
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efx->mdio.mdio_write = siena_mdio_write;
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/* Fill out MDIO structure, loopback modes, and initial link state */
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rc = efx->phy_op->probe(efx);
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/* Allocate buffer for stats */
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rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
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MC_CMD_MAC_NSTATS * sizeof(u64));
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netif_dbg(efx, probe, efx->net_dev,
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"stats buffer at %llx (virt %p phys %llx)\n",
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(u64)efx->stats_buffer.dma_addr,
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efx->stats_buffer.addr,
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(u64)virt_to_phys(efx->stats_buffer.addr));
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efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
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static void siena_remove_port(struct efx_nic *efx)
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efx->phy_op->remove(efx);
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efx_nic_free_buffer(efx, &efx->stats_buffer);
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static const struct efx_nic_register_test siena_register_tests[] = {
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EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
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EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
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EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
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EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
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EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
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{ FR_AZ_SRM_TX_DC_CFG,
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EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
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EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
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EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
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EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
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{ FR_CZ_RX_RSS_IPV6_REG1,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
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{ FR_CZ_RX_RSS_IPV6_REG2,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
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{ FR_CZ_RX_RSS_IPV6_REG3,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
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static int siena_test_registers(struct efx_nic *efx)
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return efx_nic_test_registers(efx, siena_register_tests,
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ARRAY_SIZE(siena_register_tests));
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/**************************************************************************
179
**************************************************************************
182
static enum reset_type siena_map_reset_reason(enum reset_type reason)
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return RESET_TYPE_ALL;
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static int siena_map_reset_flags(u32 *flags)
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SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
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ETH_RESET_OFFLOAD | ETH_RESET_MAC |
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SIENA_RESET_MC = (SIENA_RESET_PORT |
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ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
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if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
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*flags &= ~SIENA_RESET_MC;
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return RESET_TYPE_WORLD;
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if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
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*flags &= ~SIENA_RESET_PORT;
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return RESET_TYPE_ALL;
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/* no invisible reset implemented */
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static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
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/* Recover from a failed assertion pre-reset */
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rc = efx_mcdi_handle_assertion(efx);
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if (method == RESET_TYPE_WORLD)
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return efx_mcdi_reset_mc(efx);
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return efx_mcdi_reset_port(efx);
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static int siena_probe_nvconfig(struct efx_nic *efx)
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return efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL);
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static int siena_probe_nic(struct efx_nic *efx)
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struct siena_nic_data *nic_data;
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bool already_attached = 0;
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/* Allocate storage for hardware specific data */
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nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
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efx->nic_data = nic_data;
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if (efx_nic_fpga_ver(efx) != 0) {
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netif_err(efx, probe, efx->net_dev,
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"Siena FPGA not supported\n");
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efx_reado(efx, ®, FR_AZ_CS_DEBUG);
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efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
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/* Recover from a failed assertion before probing */
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rc = efx_mcdi_handle_assertion(efx);
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/* Let the BMC know that the driver is now in charge of link and
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* filter settings. We must do this before we reset the NIC */
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rc = efx_mcdi_drv_attach(efx, true, &already_attached);
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netif_err(efx, probe, efx->net_dev,
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"Unable to register driver with MCPU\n");
270
if (already_attached)
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/* Not a fatal error */
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netif_err(efx, probe, efx->net_dev,
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"Host already registered with MCPU\n");
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/* Now we can reset the NIC */
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rc = siena_reset_hw(efx, RESET_TYPE_ALL);
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netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
284
/* Allocate memory for INT_KER */
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rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
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BUG_ON(efx->irq_status.dma_addr & 0x0f);
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netif_dbg(efx, probe, efx->net_dev,
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"INT_KER at %llx (virt %p phys %llx)\n",
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(unsigned long long)efx->irq_status.dma_addr,
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efx->irq_status.addr,
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(unsigned long long)virt_to_phys(efx->irq_status.addr));
296
/* Read in the non-volatile configuration */
297
rc = siena_probe_nvconfig(efx);
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netif_err(efx, probe, efx->net_dev,
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"NVRAM is invalid therefore using defaults\n");
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efx->phy_type = PHY_TYPE_NONE;
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efx->mdio.prtad = MDIO_PRTAD_NONE;
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efx_nic_free_buffer(efx, &efx->irq_status);
313
efx_mcdi_drv_attach(efx, false, NULL);
316
kfree(efx->nic_data);
320
/* This call performs hardware-specific global initialisation, such as
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* defining the descriptor cache sizes and number of RSS channels.
322
* It does not set up any buffers, descriptor rings or event queues.
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static int siena_init_nic(struct efx_nic *efx)
329
/* Recover from a failed assertion post-reset */
330
rc = efx_mcdi_handle_assertion(efx);
334
/* Squash TX of packets of 16 bytes or less */
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efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
336
EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
337
efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
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/* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
340
* descriptors (which is bad).
342
efx_reado(efx, &temp, FR_AZ_TX_CFG);
343
EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
344
EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
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efx_writeo(efx, &temp, FR_AZ_TX_CFG);
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efx_reado(efx, &temp, FR_AZ_RX_CFG);
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
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/* Enable hash insertion. This is broken for the 'Falcon' hash
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* if IPv6 hashing is also enabled, so also select Toeplitz
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* TCP/IPv4 and IPv4 hashes. */
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
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efx_writeo(efx, &temp, FR_AZ_RX_CFG);
358
/* Set hash key for IPv4 */
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memcpy(&temp, efx->rx_hash_key, sizeof(temp));
360
efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
362
/* Enable IPv6 RSS */
363
BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
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2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
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FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
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memcpy(&temp, efx->rx_hash_key, sizeof(temp));
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efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
368
memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
369
efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
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EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
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FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
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memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
373
FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
374
efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
376
/* Enable event logging */
377
rc = efx_mcdi_log_ctrl(efx, true, false, 0);
381
/* Set destination of both TX and RX Flush events */
382
EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
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efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
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EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
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efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
388
efx_nic_init_common(efx);
392
static void siena_remove_nic(struct efx_nic *efx)
394
efx_nic_free_buffer(efx, &efx->irq_status);
396
siena_reset_hw(efx, RESET_TYPE_ALL);
398
/* Relinquish the device back to the BMC */
399
if (efx_nic_has_mc(efx))
400
efx_mcdi_drv_attach(efx, false, NULL);
402
/* Tear down the private nic state */
403
kfree(efx->nic_data);
404
efx->nic_data = NULL;
407
#define STATS_GENERATION_INVALID ((__force __le64)(-1))
409
static int siena_try_update_nic_stats(struct efx_nic *efx)
412
struct efx_mac_stats *mac_stats;
413
__le64 generation_start, generation_end;
415
mac_stats = &efx->mac_stats;
416
dma_stats = efx->stats_buffer.addr;
418
generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
419
if (generation_end == STATS_GENERATION_INVALID)
423
#define MAC_STAT(M, D) \
424
mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
426
MAC_STAT(tx_bytes, TX_BYTES);
427
MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
428
mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
429
mac_stats->tx_bad_bytes);
430
MAC_STAT(tx_packets, TX_PKTS);
431
MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
432
MAC_STAT(tx_pause, TX_PAUSE_PKTS);
433
MAC_STAT(tx_control, TX_CONTROL_PKTS);
434
MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
435
MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
436
MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
437
MAC_STAT(tx_lt64, TX_LT64_PKTS);
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MAC_STAT(tx_64, TX_64_PKTS);
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MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
440
MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
441
MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
442
MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
443
MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
444
MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
445
MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
446
mac_stats->tx_collision = 0;
447
MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
448
MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
449
MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
450
MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
451
MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
452
mac_stats->tx_collision = (mac_stats->tx_single_collision +
453
mac_stats->tx_multiple_collision +
454
mac_stats->tx_excessive_collision +
455
mac_stats->tx_late_collision);
456
MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
457
MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
458
MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
459
MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
460
MAC_STAT(rx_bytes, RX_BYTES);
461
MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
462
mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
463
mac_stats->rx_bad_bytes);
464
MAC_STAT(rx_packets, RX_PKTS);
465
MAC_STAT(rx_good, RX_GOOD_PKTS);
466
MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
467
MAC_STAT(rx_pause, RX_PAUSE_PKTS);
468
MAC_STAT(rx_control, RX_CONTROL_PKTS);
469
MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
470
MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
471
MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
472
MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
473
MAC_STAT(rx_64, RX_64_PKTS);
474
MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
475
MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
476
MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
477
MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
478
MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
479
MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
480
MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
481
mac_stats->rx_bad_lt64 = 0;
482
mac_stats->rx_bad_64_to_15xx = 0;
483
mac_stats->rx_bad_15xx_to_jumbo = 0;
484
MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
485
MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
486
mac_stats->rx_missed = 0;
487
MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
488
MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
489
MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
490
MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
491
MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
492
mac_stats->rx_good_lt64 = 0;
494
efx->n_rx_nodesc_drop_cnt =
495
le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
500
generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
501
if (generation_end != generation_start)
507
static void siena_update_nic_stats(struct efx_nic *efx)
511
/* If we're unlucky enough to read statistics wduring the DMA, wait
512
* up to 10ms for it to finish (typically takes <500us) */
513
for (retry = 0; retry < 100; ++retry) {
514
if (siena_try_update_nic_stats(efx) == 0)
519
/* Use the old values instead */
522
static void siena_start_nic_stats(struct efx_nic *efx)
524
__le64 *dma_stats = efx->stats_buffer.addr;
526
dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
528
efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
529
MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
532
static void siena_stop_nic_stats(struct efx_nic *efx)
534
efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
537
/**************************************************************************
541
**************************************************************************
544
static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
546
struct siena_nic_data *nic_data = efx->nic_data;
548
wol->supported = WAKE_MAGIC;
549
if (nic_data->wol_filter_id != -1)
550
wol->wolopts = WAKE_MAGIC;
553
memset(&wol->sopass, 0, sizeof(wol->sopass));
557
static int siena_set_wol(struct efx_nic *efx, u32 type)
559
struct siena_nic_data *nic_data = efx->nic_data;
562
if (type & ~WAKE_MAGIC)
565
if (type & WAKE_MAGIC) {
566
if (nic_data->wol_filter_id != -1)
567
efx_mcdi_wol_filter_remove(efx,
568
nic_data->wol_filter_id);
569
rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
570
&nic_data->wol_filter_id);
574
pci_wake_from_d3(efx->pci_dev, true);
576
rc = efx_mcdi_wol_filter_reset(efx);
577
nic_data->wol_filter_id = -1;
578
pci_wake_from_d3(efx->pci_dev, false);
585
netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
591
static void siena_init_wol(struct efx_nic *efx)
593
struct siena_nic_data *nic_data = efx->nic_data;
596
rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
599
/* If it failed, attempt to get into a synchronised
600
* state with MC by resetting any set WoL filters */
601
efx_mcdi_wol_filter_reset(efx);
602
nic_data->wol_filter_id = -1;
603
} else if (nic_data->wol_filter_id != -1) {
604
pci_wake_from_d3(efx->pci_dev, true);
609
/**************************************************************************
611
* Revision-dependent attributes used by efx.c and nic.c
613
**************************************************************************
616
const struct efx_nic_type siena_a0_nic_type = {
617
.probe = siena_probe_nic,
618
.remove = siena_remove_nic,
619
.init = siena_init_nic,
620
.fini = efx_port_dummy_op_void,
622
.map_reset_reason = siena_map_reset_reason,
623
.map_reset_flags = siena_map_reset_flags,
624
.reset = siena_reset_hw,
625
.probe_port = siena_probe_port,
626
.remove_port = siena_remove_port,
627
.prepare_flush = efx_port_dummy_op_void,
628
.update_stats = siena_update_nic_stats,
629
.start_stats = siena_start_nic_stats,
630
.stop_stats = siena_stop_nic_stats,
631
.set_id_led = efx_mcdi_set_id_led,
632
.push_irq_moderation = siena_push_irq_moderation,
633
.push_multicast_hash = siena_push_multicast_hash,
634
.reconfigure_port = efx_mcdi_phy_reconfigure,
635
.get_wol = siena_get_wol,
636
.set_wol = siena_set_wol,
637
.resume_wol = siena_init_wol,
638
.test_registers = siena_test_registers,
639
.test_nvram = efx_mcdi_nvram_test_all,
640
.default_mac_ops = &efx_mcdi_mac_operations,
642
.revision = EFX_REV_SIENA_A0,
643
.mem_map_size = (FR_CZ_MC_TREG_SMEM +
644
FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
645
.txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
646
.rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
647
.buf_tbl_base = FR_BZ_BUF_FULL_TBL,
648
.evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
649
.evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
650
.max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
651
.rx_buffer_hash_size = 0x10,
652
.rx_buffer_padding = 0,
653
.max_interrupt_mode = EFX_INT_MODE_MSIX,
654
.phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
655
* interrupt handler only supports 32
657
.tx_dc_base = 0x88000,
658
.rx_dc_base = 0x68000,
659
.offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
660
NETIF_F_RXHASH | NETIF_F_NTUPLE),