2
* tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
4
* Based on skelton.c by Donald Becker.
6
* This driver is a replacement of older and less maintained version.
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* This is a header of the older version:
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ahennessy@mvista.com
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* Copyright (C) 2000-2001 Toshiba Corporation
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* static const char *version =
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* "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* (C) Copyright TOSHIBA CORPORATION 2004-2005
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* All Rights Reserved.
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#define DRV_VERSION "1.39"
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static const char *version = "tc35815.c:v" DRV_VERSION "\n";
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#define MODNAME "tc35815"
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/fcntl.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/if_vlan.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/workqueue.h>
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#include <linux/platform_device.h>
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#include <linux/prefetch.h>
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#include <asm/byteorder.h>
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enum tc35815_chiptype {
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/* indexed by tc35815_chiptype, above */
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} chip_info[] __devinitdata = {
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{ "TOSHIBA TC35815CF 10/100BaseTX" },
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{ "TOSHIBA TC35815 with Wake on LAN" },
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{ "TOSHIBA TC35815/TX4939" },
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static DEFINE_PCI_DEVICE_TABLE(tc35815_pci_tbl) = {
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{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
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{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
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{PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
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MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
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/* see MODULE_PARM_DESC */
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static struct tc35815_options {
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__u32 DMA_Ctl; /* 0x00 */
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__u32 FDA_Lim; /* 0x20 */
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__u32 MAC_Ctl; /* 0x40 */
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__u32 CAM_Adr; /* 0x60 */
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/* DMA_Ctl bit assign ------------------------------------------------------- */
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#define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
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#define DMA_RxAlign_1 0x00400000
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#define DMA_RxAlign_2 0x00800000
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#define DMA_RxAlign_3 0x00c00000
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#define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
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#define DMA_IntMask 0x00040000 /* 1:Interrupt mask */
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#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
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#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
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#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
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#define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
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#define DMA_TestMode 0x00002000 /* 1:Test Mode */
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#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
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#define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
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/* RxFragSize bit assign ---------------------------------------------------- */
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#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
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#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
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/* MAC_Ctl bit assign ------------------------------------------------------- */
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#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
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#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
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#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
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#define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
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#define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
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#define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
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#define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
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#define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
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#define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
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#define MAC_Reset 0x00000004 /* 1:Software Reset */
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#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
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#define MAC_HaltReq 0x00000001 /* 1:Halt request */
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/* PROM_Ctl bit assign ------------------------------------------------------ */
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#define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
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#define PROM_Read 0x00004000 /*10:Read operation */
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#define PROM_Write 0x00002000 /*01:Write operation */
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#define PROM_Erase 0x00006000 /*11:Erase operation */
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/*00:Enable or Disable Writting, */
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/* as specified in PROM_Addr. */
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#define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
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/* CAM_Ctl bit assign ------------------------------------------------------- */
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#define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
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#define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
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#define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
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#define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
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#define CAM_StationAcc 0x00000001 /* 1:unicast accept */
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/* CAM_Ena bit assign ------------------------------------------------------- */
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#define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
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#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
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#define CAM_Ena_Bit(index) (1 << (index))
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#define CAM_ENTRY_DESTINATION 0
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#define CAM_ENTRY_SOURCE 1
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#define CAM_ENTRY_MACCTL 20
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/* Tx_Ctl bit assign -------------------------------------------------------- */
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#define Tx_En 0x00000001 /* 1:Transmit enable */
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#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
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#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
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#define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
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#define Tx_FBack 0x00000010 /* 1:Fast Back-off */
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#define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
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#define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
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#define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
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#define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
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#define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
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#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
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#define Tx_EnComp 0x00004000 /* 1:Enable Completion */
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/* Tx_Stat bit assign ------------------------------------------------------- */
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#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
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#define Tx_ExColl 0x00000010 /* Excessive Collision */
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#define Tx_TXDefer 0x00000020 /* Transmit Defered */
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#define Tx_Paused 0x00000040 /* Transmit Paused */
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#define Tx_IntTx 0x00000080 /* Interrupt on Tx */
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#define Tx_Under 0x00000100 /* Underrun */
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#define Tx_Defer 0x00000200 /* Deferral */
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#define Tx_NCarr 0x00000400 /* No Carrier */
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#define Tx_10Stat 0x00000800 /* 10Mbps Status */
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#define Tx_LateColl 0x00001000 /* Late Collision */
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#define Tx_TxPar 0x00002000 /* Tx Parity Error */
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#define Tx_Comp 0x00004000 /* Completion */
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#define Tx_Halted 0x00008000 /* Tx Halted */
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#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
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/* Rx_Ctl bit assign -------------------------------------------------------- */
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#define Rx_EnGood 0x00004000 /* 1:Enable Good */
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#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
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#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
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#define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
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#define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
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#define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
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#define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
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#define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
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#define Rx_ShortEn 0x00000008 /* 1:Short Enable */
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#define Rx_LongEn 0x00000004 /* 1:Long Enable */
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#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
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#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
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/* Rx_Stat bit assign ------------------------------------------------------- */
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#define Rx_Halted 0x00008000 /* Rx Halted */
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#define Rx_Good 0x00004000 /* Rx Good */
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#define Rx_RxPar 0x00002000 /* Rx Parity Error */
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#define Rx_TypePkt 0x00001000 /* Rx Type Packet */
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#define Rx_LongErr 0x00000800 /* Rx Long Error */
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#define Rx_Over 0x00000400 /* Rx Overflow */
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#define Rx_CRCErr 0x00000200 /* Rx CRC Error */
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#define Rx_Align 0x00000100 /* Rx Alignment Error */
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#define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
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#define Rx_IntRx 0x00000040 /* Rx Interrupt */
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#define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
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#define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */
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#define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */
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/* Int_En bit assign -------------------------------------------------------- */
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#define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
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#define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
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#define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
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#define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
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#define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
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#define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
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#define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
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#define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
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#define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
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#define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
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#define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
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#define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
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/* Exhausted Enable */
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/* Int_Src bit assign ------------------------------------------------------- */
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#define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
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#define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
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#define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
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#define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
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#define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
263
#define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
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#define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
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#define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
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#define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
267
#define Int_SWInt 0x00000020 /* 1:Software request & Clear */
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#define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
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#define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
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#define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
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#define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
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#define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
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/* MD_CA bit assign --------------------------------------------------------- */
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#define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */
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#define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
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#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
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/* Frame descripter */
286
volatile __u32 FDNext;
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volatile __u32 FDSystem;
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volatile __u32 FDStat;
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volatile __u32 FDCtl;
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/* Buffer descripter */
294
volatile __u32 BuffData;
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volatile __u32 BDCtl;
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/* Frame Descripter bit assign ---------------------------------------------- */
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#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
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#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
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#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
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#define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
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#define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
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#define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
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#define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
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#define FD_FrmOpt_Packing 0x04000000 /* Rx only */
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#define FD_CownsFD 0x80000000 /* FD Controller owner bit */
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#define FD_Next_EOL 0x00000001 /* FD EOL indicator */
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#define FD_BDCnt_SHIFT 16
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/* Buffer Descripter bit assign --------------------------------------------- */
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#define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */
315
#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
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#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
317
#define BD_CownsBD 0x80000000 /* BD Controller owner bit */
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#define BD_RxBDID_SHIFT 16
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#define BD_RxBDSeqN_SHIFT 24
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/* Some useful constants. */
324
#define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \
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Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
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Tx_En) /* maybe 0x7b01 */
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/* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
328
#define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
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| Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
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#define INT_EN_CMD (Int_NRAbtEn | \
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Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
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Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
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Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
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#define DMA_CTL_CMD DMA_BURST_SIZE
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#define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
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/* Tuning parameters */
339
#define DMA_BURST_SIZE 32
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#define TX_THRESHOLD 1024
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/* used threshold with packet max byte for low pci transfer ability.*/
342
#define TX_THRESHOLD_MAX 1536
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/* setting threshold max value when overrun error occurred this count. */
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#define TX_THRESHOLD_KEEP_LIMIT 10
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/* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
347
#define FD_PAGE_NUM 4
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#define RX_BUF_NUM 128 /* < 256 */
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#define RX_FD_NUM 256 /* >= 32 */
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#define TX_FD_NUM 128
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#if RX_CTL_CMD & Rx_LongEn
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#define RX_BUF_SIZE PAGE_SIZE
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#elif RX_CTL_CMD & Rx_StripCRC
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#define RX_BUF_SIZE \
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L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
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#define RX_BUF_SIZE \
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L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
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#define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
361
#define NAPI_WEIGHT 16
371
struct BDesc bd[0]; /* variable length */
376
struct BDesc bd[RX_BUF_NUM];
380
#define tc_readl(addr) ioread32(addr)
381
#define tc_writel(d, addr) iowrite32(d, addr)
383
#define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
385
/* Information that need to be kept for each controller. */
386
struct tc35815_local {
387
struct pci_dev *pci_dev;
389
struct net_device *dev;
390
struct napi_struct napi;
400
/* Tx control lock. This protects the transmit buffer ring
401
* state along with the "tx full" state of the driver. This
402
* means all netif_queue flow control actions are protected
403
* by this lock as well.
408
struct mii_bus *mii_bus;
409
struct phy_device *phy_dev;
413
struct work_struct restart_work;
416
* Transmitting: Batch Mode.
418
* Receiving: Non-Packing Mode.
419
* 1 circular FD for Free Buffer List.
420
* RX_BUF_NUM BD in Free Buffer FD.
421
* One Free Buffer BD has ETH_FRAME_LEN data buffer.
423
void *fd_buf; /* for TxFD, RxFD, FrFD */
424
dma_addr_t fd_buf_dma;
425
struct TxFD *tfd_base;
426
unsigned int tfd_start;
427
unsigned int tfd_end;
428
struct RxFD *rfd_base;
429
struct RxFD *rfd_limit;
430
struct RxFD *rfd_cur;
431
struct FrFD *fbl_ptr;
432
unsigned int fbl_count;
436
} tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
438
enum tc35815_chiptype chiptype;
441
static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
443
return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
446
static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
448
return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
451
static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
452
struct pci_dev *hwdev,
453
dma_addr_t *dma_handle)
456
skb = dev_alloc_skb(RX_BUF_SIZE);
459
*dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
461
if (pci_dma_mapping_error(hwdev, *dma_handle)) {
462
dev_kfree_skb_any(skb);
465
skb_reserve(skb, 2); /* make IP header 4byte aligned */
469
static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
471
pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
473
dev_kfree_skb_any(skb);
476
/* Index to functions, as function prototypes. */
478
static int tc35815_open(struct net_device *dev);
479
static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
480
static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
481
static int tc35815_rx(struct net_device *dev, int limit);
482
static int tc35815_poll(struct napi_struct *napi, int budget);
483
static void tc35815_txdone(struct net_device *dev);
484
static int tc35815_close(struct net_device *dev);
485
static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
486
static void tc35815_set_multicast_list(struct net_device *dev);
487
static void tc35815_tx_timeout(struct net_device *dev);
488
static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
489
#ifdef CONFIG_NET_POLL_CONTROLLER
490
static void tc35815_poll_controller(struct net_device *dev);
492
static const struct ethtool_ops tc35815_ethtool_ops;
494
/* Example routines you must write ;->. */
495
static void tc35815_chip_reset(struct net_device *dev);
496
static void tc35815_chip_init(struct net_device *dev);
499
static void panic_queues(struct net_device *dev);
502
static void tc35815_restart_work(struct work_struct *work);
504
static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
506
struct net_device *dev = bus->priv;
507
struct tc35815_regs __iomem *tr =
508
(struct tc35815_regs __iomem *)dev->base_addr;
509
unsigned long timeout = jiffies + HZ;
511
tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
512
udelay(12); /* it takes 32 x 400ns at least */
513
while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
514
if (time_after(jiffies, timeout))
518
return tc_readl(&tr->MD_Data) & 0xffff;
521
static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
523
struct net_device *dev = bus->priv;
524
struct tc35815_regs __iomem *tr =
525
(struct tc35815_regs __iomem *)dev->base_addr;
526
unsigned long timeout = jiffies + HZ;
528
tc_writel(val, &tr->MD_Data);
529
tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
531
udelay(12); /* it takes 32 x 400ns at least */
532
while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
533
if (time_after(jiffies, timeout))
540
static void tc_handle_link_change(struct net_device *dev)
542
struct tc35815_local *lp = netdev_priv(dev);
543
struct phy_device *phydev = lp->phy_dev;
545
int status_change = 0;
547
spin_lock_irqsave(&lp->lock, flags);
549
(lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
550
struct tc35815_regs __iomem *tr =
551
(struct tc35815_regs __iomem *)dev->base_addr;
554
reg = tc_readl(&tr->MAC_Ctl);
556
tc_writel(reg, &tr->MAC_Ctl);
557
if (phydev->duplex == DUPLEX_FULL)
561
tc_writel(reg, &tr->MAC_Ctl);
563
tc_writel(reg, &tr->MAC_Ctl);
566
* TX4939 PCFG.SPEEDn bit will be changed on
567
* NETDEV_CHANGE event.
570
* WORKAROUND: enable LostCrS only if half duplex
572
* (TX4939 does not have EnLCarr)
574
if (phydev->duplex == DUPLEX_HALF &&
575
lp->chiptype != TC35815_TX4939)
576
tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
579
lp->speed = phydev->speed;
580
lp->duplex = phydev->duplex;
584
if (phydev->link != lp->link) {
586
/* delayed promiscuous enabling */
587
if (dev->flags & IFF_PROMISC)
588
tc35815_set_multicast_list(dev);
593
lp->link = phydev->link;
597
spin_unlock_irqrestore(&lp->lock, flags);
599
if (status_change && netif_msg_link(lp)) {
600
phy_print_status(phydev);
601
pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
603
phy_read(phydev, MII_BMCR),
604
phy_read(phydev, MII_BMSR),
605
phy_read(phydev, MII_LPA));
609
static int tc_mii_probe(struct net_device *dev)
611
struct tc35815_local *lp = netdev_priv(dev);
612
struct phy_device *phydev = NULL;
616
/* find the first phy */
617
for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
618
if (lp->mii_bus->phy_map[phy_addr]) {
620
printk(KERN_ERR "%s: multiple PHYs found\n",
624
phydev = lp->mii_bus->phy_map[phy_addr];
630
printk(KERN_ERR "%s: no PHY found\n", dev->name);
634
/* attach the mac to the phy */
635
phydev = phy_connect(dev, dev_name(&phydev->dev),
636
&tc_handle_link_change, 0,
637
lp->chiptype == TC35815_TX4939 ?
638
PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
639
if (IS_ERR(phydev)) {
640
printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
641
return PTR_ERR(phydev);
643
printk(KERN_INFO "%s: attached PHY driver [%s] "
644
"(mii_bus:phy_addr=%s, id=%x)\n",
645
dev->name, phydev->drv->name, dev_name(&phydev->dev),
648
/* mask with MAC supported features */
649
phydev->supported &= PHY_BASIC_FEATURES;
651
if (options.speed == 10)
652
dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
653
else if (options.speed == 100)
654
dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
655
if (options.duplex == 1)
656
dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
657
else if (options.duplex == 2)
658
dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
659
phydev->supported &= ~dropmask;
660
phydev->advertising = phydev->supported;
665
lp->phy_dev = phydev;
670
static int tc_mii_init(struct net_device *dev)
672
struct tc35815_local *lp = netdev_priv(dev);
676
lp->mii_bus = mdiobus_alloc();
677
if (lp->mii_bus == NULL) {
682
lp->mii_bus->name = "tc35815_mii_bus";
683
lp->mii_bus->read = tc_mdio_read;
684
lp->mii_bus->write = tc_mdio_write;
685
snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
686
(lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
687
lp->mii_bus->priv = dev;
688
lp->mii_bus->parent = &lp->pci_dev->dev;
689
lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
690
if (!lp->mii_bus->irq) {
692
goto err_out_free_mii_bus;
695
for (i = 0; i < PHY_MAX_ADDR; i++)
696
lp->mii_bus->irq[i] = PHY_POLL;
698
err = mdiobus_register(lp->mii_bus);
700
goto err_out_free_mdio_irq;
701
err = tc_mii_probe(dev);
703
goto err_out_unregister_bus;
706
err_out_unregister_bus:
707
mdiobus_unregister(lp->mii_bus);
708
err_out_free_mdio_irq:
709
kfree(lp->mii_bus->irq);
710
err_out_free_mii_bus:
711
mdiobus_free(lp->mii_bus);
716
#ifdef CONFIG_CPU_TX49XX
718
* Find a platform_device providing a MAC address. The platform code
719
* should provide a "tc35815-mac" device with a MAC address in its
722
static int __devinit tc35815_mac_match(struct device *dev, void *data)
724
struct platform_device *plat_dev = to_platform_device(dev);
725
struct pci_dev *pci_dev = data;
726
unsigned int id = pci_dev->irq;
727
return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
730
static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
732
struct tc35815_local *lp = netdev_priv(dev);
733
struct device *pd = bus_find_device(&platform_bus_type, NULL,
734
lp->pci_dev, tc35815_mac_match);
736
if (pd->platform_data)
737
memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
739
return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
744
static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
750
static int __devinit tc35815_init_dev_addr(struct net_device *dev)
752
struct tc35815_regs __iomem *tr =
753
(struct tc35815_regs __iomem *)dev->base_addr;
756
while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
758
for (i = 0; i < 6; i += 2) {
760
tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
761
while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
763
data = tc_readl(&tr->PROM_Data);
764
dev->dev_addr[i] = data & 0xff;
765
dev->dev_addr[i+1] = data >> 8;
767
if (!is_valid_ether_addr(dev->dev_addr))
768
return tc35815_read_plat_dev_addr(dev);
772
static const struct net_device_ops tc35815_netdev_ops = {
773
.ndo_open = tc35815_open,
774
.ndo_stop = tc35815_close,
775
.ndo_start_xmit = tc35815_send_packet,
776
.ndo_get_stats = tc35815_get_stats,
777
.ndo_set_rx_mode = tc35815_set_multicast_list,
778
.ndo_tx_timeout = tc35815_tx_timeout,
779
.ndo_do_ioctl = tc35815_ioctl,
780
.ndo_validate_addr = eth_validate_addr,
781
.ndo_change_mtu = eth_change_mtu,
782
.ndo_set_mac_address = eth_mac_addr,
783
#ifdef CONFIG_NET_POLL_CONTROLLER
784
.ndo_poll_controller = tc35815_poll_controller,
788
static int __devinit tc35815_init_one(struct pci_dev *pdev,
789
const struct pci_device_id *ent)
791
void __iomem *ioaddr = NULL;
792
struct net_device *dev;
793
struct tc35815_local *lp;
796
static int printed_version;
797
if (!printed_version++) {
799
dev_printk(KERN_DEBUG, &pdev->dev,
800
"speed:%d duplex:%d\n",
801
options.speed, options.duplex);
805
dev_warn(&pdev->dev, "no IRQ assigned.\n");
809
/* dev zeroed in alloc_etherdev */
810
dev = alloc_etherdev(sizeof(*lp));
812
dev_err(&pdev->dev, "unable to alloc new ethernet\n");
815
SET_NETDEV_DEV(dev, &pdev->dev);
816
lp = netdev_priv(dev);
819
/* enable device (incl. PCI PM wakeup), and bus-mastering */
820
rc = pcim_enable_device(pdev);
823
rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
826
pci_set_master(pdev);
827
ioaddr = pcim_iomap_table(pdev)[1];
829
/* Initialize the device structure. */
830
dev->netdev_ops = &tc35815_netdev_ops;
831
dev->ethtool_ops = &tc35815_ethtool_ops;
832
dev->watchdog_timeo = TC35815_TX_TIMEOUT;
833
netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
835
dev->irq = pdev->irq;
836
dev->base_addr = (unsigned long)ioaddr;
838
INIT_WORK(&lp->restart_work, tc35815_restart_work);
839
spin_lock_init(&lp->lock);
840
spin_lock_init(&lp->rx_lock);
842
lp->chiptype = ent->driver_data;
844
lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
845
pci_set_drvdata(pdev, dev);
847
/* Soft reset the chip. */
848
tc35815_chip_reset(dev);
850
/* Retrieve the ethernet address. */
851
if (tc35815_init_dev_addr(dev)) {
852
dev_warn(&pdev->dev, "not valid ether addr\n");
853
random_ether_addr(dev->dev_addr);
856
rc = register_netdev(dev);
860
memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
861
printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
863
chip_info[ent->driver_data].name,
868
rc = tc_mii_init(dev);
870
goto err_out_unregister;
875
unregister_netdev(dev);
882
static void __devexit tc35815_remove_one(struct pci_dev *pdev)
884
struct net_device *dev = pci_get_drvdata(pdev);
885
struct tc35815_local *lp = netdev_priv(dev);
887
phy_disconnect(lp->phy_dev);
888
mdiobus_unregister(lp->mii_bus);
889
kfree(lp->mii_bus->irq);
890
mdiobus_free(lp->mii_bus);
891
unregister_netdev(dev);
893
pci_set_drvdata(pdev, NULL);
897
tc35815_init_queues(struct net_device *dev)
899
struct tc35815_local *lp = netdev_priv(dev);
901
unsigned long fd_addr;
904
BUG_ON(sizeof(struct FDesc) +
905
sizeof(struct BDesc) * RX_BUF_NUM +
906
sizeof(struct FDesc) * RX_FD_NUM +
907
sizeof(struct TxFD) * TX_FD_NUM >
908
PAGE_SIZE * FD_PAGE_NUM);
910
lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
911
PAGE_SIZE * FD_PAGE_NUM,
915
for (i = 0; i < RX_BUF_NUM; i++) {
917
alloc_rxbuf_skb(dev, lp->pci_dev,
918
&lp->rx_skbs[i].skb_dma);
919
if (!lp->rx_skbs[i].skb) {
921
free_rxbuf_skb(lp->pci_dev,
923
lp->rx_skbs[i].skb_dma);
924
lp->rx_skbs[i].skb = NULL;
926
pci_free_consistent(lp->pci_dev,
927
PAGE_SIZE * FD_PAGE_NUM,
934
printk(KERN_DEBUG "%s: FD buf %p DataBuf",
935
dev->name, lp->fd_buf);
938
for (i = 0; i < FD_PAGE_NUM; i++)
939
clear_page((void *)((unsigned long)lp->fd_buf +
942
fd_addr = (unsigned long)lp->fd_buf;
944
/* Free Descriptors (for Receive) */
945
lp->rfd_base = (struct RxFD *)fd_addr;
946
fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
947
for (i = 0; i < RX_FD_NUM; i++)
948
lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
949
lp->rfd_cur = lp->rfd_base;
950
lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
952
/* Transmit Descriptors */
953
lp->tfd_base = (struct TxFD *)fd_addr;
954
fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
955
for (i = 0; i < TX_FD_NUM; i++) {
956
lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
957
lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
958
lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
960
lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
964
/* Buffer List (for Receive) */
965
lp->fbl_ptr = (struct FrFD *)fd_addr;
966
lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
967
lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
969
* move all allocated skbs to head of rx_skbs[] array.
970
* fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
971
* tc35815_rx() had failed.
974
for (i = 0; i < RX_BUF_NUM; i++) {
975
if (lp->rx_skbs[i].skb) {
976
if (i != lp->fbl_count) {
977
lp->rx_skbs[lp->fbl_count].skb =
979
lp->rx_skbs[lp->fbl_count].skb_dma =
980
lp->rx_skbs[i].skb_dma;
985
for (i = 0; i < RX_BUF_NUM; i++) {
986
if (i >= lp->fbl_count) {
987
lp->fbl_ptr->bd[i].BuffData = 0;
988
lp->fbl_ptr->bd[i].BDCtl = 0;
991
lp->fbl_ptr->bd[i].BuffData =
992
cpu_to_le32(lp->rx_skbs[i].skb_dma);
993
/* BDID is index of FrFD.bd[] */
994
lp->fbl_ptr->bd[i].BDCtl =
995
cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
999
printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
1000
dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
1005
tc35815_clear_queues(struct net_device *dev)
1007
struct tc35815_local *lp = netdev_priv(dev);
1010
for (i = 0; i < TX_FD_NUM; i++) {
1011
u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1012
struct sk_buff *skb =
1013
fdsystem != 0xffffffff ?
1014
lp->tx_skbs[fdsystem].skb : NULL;
1016
if (lp->tx_skbs[i].skb != skb) {
1017
printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1021
BUG_ON(lp->tx_skbs[i].skb != skb);
1024
pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1025
lp->tx_skbs[i].skb = NULL;
1026
lp->tx_skbs[i].skb_dma = 0;
1027
dev_kfree_skb_any(skb);
1029
lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1032
tc35815_init_queues(dev);
1036
tc35815_free_queues(struct net_device *dev)
1038
struct tc35815_local *lp = netdev_priv(dev);
1042
for (i = 0; i < TX_FD_NUM; i++) {
1043
u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1044
struct sk_buff *skb =
1045
fdsystem != 0xffffffff ?
1046
lp->tx_skbs[fdsystem].skb : NULL;
1048
if (lp->tx_skbs[i].skb != skb) {
1049
printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1053
BUG_ON(lp->tx_skbs[i].skb != skb);
1057
pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1058
lp->tx_skbs[i].skb = NULL;
1059
lp->tx_skbs[i].skb_dma = 0;
1061
lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1065
lp->rfd_base = NULL;
1066
lp->rfd_limit = NULL;
1070
for (i = 0; i < RX_BUF_NUM; i++) {
1071
if (lp->rx_skbs[i].skb) {
1072
free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1073
lp->rx_skbs[i].skb_dma);
1074
lp->rx_skbs[i].skb = NULL;
1078
pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1079
lp->fd_buf, lp->fd_buf_dma);
1085
dump_txfd(struct TxFD *fd)
1087
printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1088
le32_to_cpu(fd->fd.FDNext),
1089
le32_to_cpu(fd->fd.FDSystem),
1090
le32_to_cpu(fd->fd.FDStat),
1091
le32_to_cpu(fd->fd.FDCtl));
1093
printk(" %08x %08x",
1094
le32_to_cpu(fd->bd.BuffData),
1095
le32_to_cpu(fd->bd.BDCtl));
1100
dump_rxfd(struct RxFD *fd)
1102
int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1105
printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1106
le32_to_cpu(fd->fd.FDNext),
1107
le32_to_cpu(fd->fd.FDSystem),
1108
le32_to_cpu(fd->fd.FDStat),
1109
le32_to_cpu(fd->fd.FDCtl));
1110
if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1113
for (i = 0; i < bd_count; i++)
1114
printk(" %08x %08x",
1115
le32_to_cpu(fd->bd[i].BuffData),
1116
le32_to_cpu(fd->bd[i].BDCtl));
1123
dump_frfd(struct FrFD *fd)
1126
printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1127
le32_to_cpu(fd->fd.FDNext),
1128
le32_to_cpu(fd->fd.FDSystem),
1129
le32_to_cpu(fd->fd.FDStat),
1130
le32_to_cpu(fd->fd.FDCtl));
1132
for (i = 0; i < RX_BUF_NUM; i++)
1133
printk(" %08x %08x",
1134
le32_to_cpu(fd->bd[i].BuffData),
1135
le32_to_cpu(fd->bd[i].BDCtl));
1140
panic_queues(struct net_device *dev)
1142
struct tc35815_local *lp = netdev_priv(dev);
1145
printk("TxFD base %p, start %u, end %u\n",
1146
lp->tfd_base, lp->tfd_start, lp->tfd_end);
1147
printk("RxFD base %p limit %p cur %p\n",
1148
lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1149
printk("FrFD %p\n", lp->fbl_ptr);
1150
for (i = 0; i < TX_FD_NUM; i++)
1151
dump_txfd(&lp->tfd_base[i]);
1152
for (i = 0; i < RX_FD_NUM; i++) {
1153
int bd_count = dump_rxfd(&lp->rfd_base[i]);
1154
i += (bd_count + 1) / 2; /* skip BDs */
1156
dump_frfd(lp->fbl_ptr);
1157
panic("%s: Illegal queue state.", dev->name);
1161
static void print_eth(const u8 *add)
1163
printk(KERN_DEBUG "print_eth(%p)\n", add);
1164
printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1165
add + 6, add, add[12], add[13]);
1168
static int tc35815_tx_full(struct net_device *dev)
1170
struct tc35815_local *lp = netdev_priv(dev);
1171
return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end;
1174
static void tc35815_restart(struct net_device *dev)
1176
struct tc35815_local *lp = netdev_priv(dev);
1181
phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
1184
if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
1189
printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
1192
spin_lock_bh(&lp->rx_lock);
1193
spin_lock_irq(&lp->lock);
1194
tc35815_chip_reset(dev);
1195
tc35815_clear_queues(dev);
1196
tc35815_chip_init(dev);
1197
/* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1198
tc35815_set_multicast_list(dev);
1199
spin_unlock_irq(&lp->lock);
1200
spin_unlock_bh(&lp->rx_lock);
1202
netif_wake_queue(dev);
1205
static void tc35815_restart_work(struct work_struct *work)
1207
struct tc35815_local *lp =
1208
container_of(work, struct tc35815_local, restart_work);
1209
struct net_device *dev = lp->dev;
1211
tc35815_restart(dev);
1214
static void tc35815_schedule_restart(struct net_device *dev)
1216
struct tc35815_local *lp = netdev_priv(dev);
1217
struct tc35815_regs __iomem *tr =
1218
(struct tc35815_regs __iomem *)dev->base_addr;
1219
unsigned long flags;
1221
/* disable interrupts */
1222
spin_lock_irqsave(&lp->lock, flags);
1223
tc_writel(0, &tr->Int_En);
1224
tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1225
schedule_work(&lp->restart_work);
1226
spin_unlock_irqrestore(&lp->lock, flags);
1229
static void tc35815_tx_timeout(struct net_device *dev)
1231
struct tc35815_regs __iomem *tr =
1232
(struct tc35815_regs __iomem *)dev->base_addr;
1234
printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1235
dev->name, tc_readl(&tr->Tx_Stat));
1237
/* Try to restart the adaptor. */
1238
tc35815_schedule_restart(dev);
1239
dev->stats.tx_errors++;
1243
* Open/initialize the controller. This is called (in the current kernel)
1244
* sometime after booting when the 'ifconfig' program is run.
1246
* This routine should set everything up anew at each open, even
1247
* registers that "should" only need to be set once at boot, so that
1248
* there is non-reboot way to recover if something goes wrong.
1251
tc35815_open(struct net_device *dev)
1253
struct tc35815_local *lp = netdev_priv(dev);
1256
* This is used if the interrupt line can turned off (shared).
1257
* See 3c503.c for an example of selecting the IRQ at config-time.
1259
if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
1263
tc35815_chip_reset(dev);
1265
if (tc35815_init_queues(dev) != 0) {
1266
free_irq(dev->irq, dev);
1270
napi_enable(&lp->napi);
1272
/* Reset the hardware here. Don't forget to set the station address. */
1273
spin_lock_irq(&lp->lock);
1274
tc35815_chip_init(dev);
1275
spin_unlock_irq(&lp->lock);
1277
netif_carrier_off(dev);
1278
/* schedule a link state check */
1279
phy_start(lp->phy_dev);
1281
/* We are now ready to accept transmit requeusts from
1282
* the queueing layer of the networking.
1284
netif_start_queue(dev);
1289
/* This will only be invoked if your driver is _not_ in XOFF state.
1290
* What this means is that you need not check it, and that this
1291
* invariant will hold if you make sure that the netif_*_queue()
1292
* calls are done at the proper times.
1294
static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1296
struct tc35815_local *lp = netdev_priv(dev);
1298
unsigned long flags;
1300
/* If some error occurs while trying to transmit this
1301
* packet, you should return '1' from this function.
1302
* In such a case you _may not_ do anything to the
1303
* SKB, it is still owned by the network queueing
1304
* layer when an error is returned. This means you
1305
* may not modify any SKB fields, you may not free
1309
/* This is the most common case for modern hardware.
1310
* The spinlock protects this code from the TX complete
1311
* hardware interrupt handler. Queue flow control is
1312
* thus managed under this lock as well.
1314
spin_lock_irqsave(&lp->lock, flags);
1316
/* failsafe... (handle txdone now if half of FDs are used) */
1317
if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1319
tc35815_txdone(dev);
1321
if (netif_msg_pktdata(lp))
1322
print_eth(skb->data);
1324
if (lp->tx_skbs[lp->tfd_start].skb) {
1325
printk("%s: tx_skbs conflict.\n", dev->name);
1329
BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1331
lp->tx_skbs[lp->tfd_start].skb = skb;
1332
lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1335
txfd = &lp->tfd_base[lp->tfd_start];
1336
txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1337
txfd->bd.BDCtl = cpu_to_le32(skb->len);
1338
txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1339
txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1341
if (lp->tfd_start == lp->tfd_end) {
1342
struct tc35815_regs __iomem *tr =
1343
(struct tc35815_regs __iomem *)dev->base_addr;
1344
/* Start DMA Transmitter. */
1345
txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1346
txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1347
if (netif_msg_tx_queued(lp)) {
1348
printk("%s: starting TxFD.\n", dev->name);
1351
tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1353
txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1354
if (netif_msg_tx_queued(lp)) {
1355
printk("%s: queueing TxFD.\n", dev->name);
1359
lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1361
/* If we just used up the very last entry in the
1362
* TX ring on this device, tell the queueing
1363
* layer to send no more.
1365
if (tc35815_tx_full(dev)) {
1366
if (netif_msg_tx_queued(lp))
1367
printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1368
netif_stop_queue(dev);
1371
/* When the TX completion hw interrupt arrives, this
1372
* is when the transmit statistics are updated.
1375
spin_unlock_irqrestore(&lp->lock, flags);
1376
return NETDEV_TX_OK;
1379
#define FATAL_ERROR_INT \
1380
(Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1381
static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1384
printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1386
if (status & Int_IntPCI)
1388
if (status & Int_DmParErr)
1389
printk(" DmParErr");
1390
if (status & Int_IntNRAbt)
1391
printk(" IntNRAbt");
1394
panic("%s: Too many fatal errors.", dev->name);
1395
printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1396
/* Try to restart the adaptor. */
1397
tc35815_schedule_restart(dev);
1400
static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1402
struct tc35815_local *lp = netdev_priv(dev);
1405
/* Fatal errors... */
1406
if (status & FATAL_ERROR_INT) {
1407
tc35815_fatal_error_interrupt(dev, status);
1410
/* recoverable errors */
1411
if (status & Int_IntFDAEx) {
1412
if (netif_msg_rx_err(lp))
1414
"Free Descriptor Area Exhausted (%#x).\n",
1416
dev->stats.rx_dropped++;
1419
if (status & Int_IntBLEx) {
1420
if (netif_msg_rx_err(lp))
1422
"Buffer List Exhausted (%#x).\n",
1424
dev->stats.rx_dropped++;
1427
if (status & Int_IntExBD) {
1428
if (netif_msg_rx_err(lp))
1430
"Excessive Buffer Descriptiors (%#x).\n",
1432
dev->stats.rx_length_errors++;
1436
/* normal notification */
1437
if (status & Int_IntMacRx) {
1438
/* Got a packet(s). */
1439
ret = tc35815_rx(dev, limit);
1440
lp->lstats.rx_ints++;
1442
if (status & Int_IntMacTx) {
1443
/* Transmit complete. */
1444
lp->lstats.tx_ints++;
1445
spin_lock_irq(&lp->lock);
1446
tc35815_txdone(dev);
1447
spin_unlock_irq(&lp->lock);
1455
* The typical workload of the driver:
1456
* Handle the network interface interrupts.
1458
static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1460
struct net_device *dev = dev_id;
1461
struct tc35815_local *lp = netdev_priv(dev);
1462
struct tc35815_regs __iomem *tr =
1463
(struct tc35815_regs __iomem *)dev->base_addr;
1464
u32 dmactl = tc_readl(&tr->DMA_Ctl);
1466
if (!(dmactl & DMA_IntMask)) {
1467
/* disable interrupts */
1468
tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1469
if (napi_schedule_prep(&lp->napi))
1470
__napi_schedule(&lp->napi);
1472
printk(KERN_ERR "%s: interrupt taken in poll\n",
1476
(void)tc_readl(&tr->Int_Src); /* flush */
1482
#ifdef CONFIG_NET_POLL_CONTROLLER
1483
static void tc35815_poll_controller(struct net_device *dev)
1485
disable_irq(dev->irq);
1486
tc35815_interrupt(dev->irq, dev);
1487
enable_irq(dev->irq);
1491
/* We have a good packet(s), get it/them out of the buffers. */
1493
tc35815_rx(struct net_device *dev, int limit)
1495
struct tc35815_local *lp = netdev_priv(dev);
1500
while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1501
int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1502
int pkt_len = fdctl & FD_FDLength_MASK;
1503
int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1505
struct RxFD *next_rfd;
1507
#if (RX_CTL_CMD & Rx_StripCRC) == 0
1508
pkt_len -= ETH_FCS_LEN;
1511
if (netif_msg_rx_status(lp))
1512
dump_rxfd(lp->rfd_cur);
1513
if (status & Rx_Good) {
1514
struct sk_buff *skb;
1515
unsigned char *data;
1520
BUG_ON(bd_count > 1);
1521
cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1522
& BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1524
if (cur_bd >= RX_BUF_NUM) {
1525
printk("%s: invalid BDID.\n", dev->name);
1528
BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1529
(le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1530
if (!lp->rx_skbs[cur_bd].skb) {
1531
printk("%s: NULL skb.\n", dev->name);
1535
BUG_ON(cur_bd >= RX_BUF_NUM);
1537
skb = lp->rx_skbs[cur_bd].skb;
1538
prefetch(skb->data);
1539
lp->rx_skbs[cur_bd].skb = NULL;
1540
pci_unmap_single(lp->pci_dev,
1541
lp->rx_skbs[cur_bd].skb_dma,
1542
RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1543
if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1544
memmove(skb->data, skb->data - NET_IP_ALIGN,
1546
data = skb_put(skb, pkt_len);
1547
if (netif_msg_pktdata(lp))
1549
skb->protocol = eth_type_trans(skb, dev);
1550
netif_receive_skb(skb);
1552
dev->stats.rx_packets++;
1553
dev->stats.rx_bytes += pkt_len;
1555
dev->stats.rx_errors++;
1556
if (netif_msg_rx_err(lp))
1557
dev_info(&dev->dev, "Rx error (status %x)\n",
1558
status & Rx_Stat_Mask);
1559
/* WORKAROUND: LongErr and CRCErr means Overflow. */
1560
if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1561
status &= ~(Rx_LongErr|Rx_CRCErr);
1564
if (status & Rx_LongErr)
1565
dev->stats.rx_length_errors++;
1566
if (status & Rx_Over)
1567
dev->stats.rx_fifo_errors++;
1568
if (status & Rx_CRCErr)
1569
dev->stats.rx_crc_errors++;
1570
if (status & Rx_Align)
1571
dev->stats.rx_frame_errors++;
1575
/* put Free Buffer back to controller */
1576
int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1578
(bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1580
if (id >= RX_BUF_NUM) {
1581
printk("%s: invalid BDID.\n", dev->name);
1585
BUG_ON(id >= RX_BUF_NUM);
1587
/* free old buffers */
1589
while (lp->fbl_count < RX_BUF_NUM)
1591
unsigned char curid =
1592
(id + 1 + lp->fbl_count) % RX_BUF_NUM;
1593
struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1595
bdctl = le32_to_cpu(bd->BDCtl);
1596
if (bdctl & BD_CownsBD) {
1597
printk("%s: Freeing invalid BD.\n",
1602
/* pass BD to controller */
1603
if (!lp->rx_skbs[curid].skb) {
1604
lp->rx_skbs[curid].skb =
1605
alloc_rxbuf_skb(dev,
1607
&lp->rx_skbs[curid].skb_dma);
1608
if (!lp->rx_skbs[curid].skb)
1609
break; /* try on next reception */
1610
bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1612
/* Note: BDLength was modified by chip. */
1613
bd->BDCtl = cpu_to_le32(BD_CownsBD |
1614
(curid << BD_RxBDID_SHIFT) |
1620
/* put RxFD back to controller */
1622
next_rfd = fd_bus_to_virt(lp,
1623
le32_to_cpu(lp->rfd_cur->fd.FDNext));
1624
if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1625
printk("%s: RxFD FDNext invalid.\n", dev->name);
1629
for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1630
/* pass FD to controller */
1632
lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1634
lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1636
lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1639
if (lp->rfd_cur > lp->rfd_limit)
1640
lp->rfd_cur = lp->rfd_base;
1642
if (lp->rfd_cur != next_rfd)
1643
printk("rfd_cur = %p, next_rfd %p\n",
1644
lp->rfd_cur, next_rfd);
1651
static int tc35815_poll(struct napi_struct *napi, int budget)
1653
struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1654
struct net_device *dev = lp->dev;
1655
struct tc35815_regs __iomem *tr =
1656
(struct tc35815_regs __iomem *)dev->base_addr;
1657
int received = 0, handled;
1660
spin_lock(&lp->rx_lock);
1661
status = tc_readl(&tr->Int_Src);
1663
/* BLEx, FDAEx will be cleared later */
1664
tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1665
&tr->Int_Src); /* write to clear */
1667
handled = tc35815_do_interrupt(dev, status, budget - received);
1668
if (status & (Int_BLEx | Int_FDAEx))
1669
tc_writel(status & (Int_BLEx | Int_FDAEx),
1672
received += handled;
1673
if (received >= budget)
1676
status = tc_readl(&tr->Int_Src);
1678
spin_unlock(&lp->rx_lock);
1680
if (received < budget) {
1681
napi_complete(napi);
1682
/* enable interrupts */
1683
tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1688
#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1691
tc35815_check_tx_stat(struct net_device *dev, int status)
1693
struct tc35815_local *lp = netdev_priv(dev);
1694
const char *msg = NULL;
1696
/* count collisions */
1697
if (status & Tx_ExColl)
1698
dev->stats.collisions += 16;
1699
if (status & Tx_TxColl_MASK)
1700
dev->stats.collisions += status & Tx_TxColl_MASK;
1702
/* TX4939 does not have NCarr */
1703
if (lp->chiptype == TC35815_TX4939)
1704
status &= ~Tx_NCarr;
1705
/* WORKAROUND: ignore LostCrS in full duplex operation */
1706
if (!lp->link || lp->duplex == DUPLEX_FULL)
1707
status &= ~Tx_NCarr;
1709
if (!(status & TX_STA_ERR)) {
1711
dev->stats.tx_packets++;
1715
dev->stats.tx_errors++;
1716
if (status & Tx_ExColl) {
1717
dev->stats.tx_aborted_errors++;
1718
msg = "Excessive Collision.";
1720
if (status & Tx_Under) {
1721
dev->stats.tx_fifo_errors++;
1722
msg = "Tx FIFO Underrun.";
1723
if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1724
lp->lstats.tx_underrun++;
1725
if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1726
struct tc35815_regs __iomem *tr =
1727
(struct tc35815_regs __iomem *)dev->base_addr;
1728
tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1729
msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1733
if (status & Tx_Defer) {
1734
dev->stats.tx_fifo_errors++;
1735
msg = "Excessive Deferral.";
1737
if (status & Tx_NCarr) {
1738
dev->stats.tx_carrier_errors++;
1739
msg = "Lost Carrier Sense.";
1741
if (status & Tx_LateColl) {
1742
dev->stats.tx_aborted_errors++;
1743
msg = "Late Collision.";
1745
if (status & Tx_TxPar) {
1746
dev->stats.tx_fifo_errors++;
1747
msg = "Transmit Parity Error.";
1749
if (status & Tx_SQErr) {
1750
dev->stats.tx_heartbeat_errors++;
1751
msg = "Signal Quality Error.";
1753
if (msg && netif_msg_tx_err(lp))
1754
printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1757
/* This handles TX complete events posted by the device
1761
tc35815_txdone(struct net_device *dev)
1763
struct tc35815_local *lp = netdev_priv(dev);
1767
txfd = &lp->tfd_base[lp->tfd_end];
1768
while (lp->tfd_start != lp->tfd_end &&
1769
!((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1770
int status = le32_to_cpu(txfd->fd.FDStat);
1771
struct sk_buff *skb;
1772
unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1773
u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1775
if (netif_msg_tx_done(lp)) {
1776
printk("%s: complete TxFD.\n", dev->name);
1779
tc35815_check_tx_stat(dev, status);
1781
skb = fdsystem != 0xffffffff ?
1782
lp->tx_skbs[fdsystem].skb : NULL;
1784
if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1785
printk("%s: tx_skbs mismatch.\n", dev->name);
1789
BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1792
dev->stats.tx_bytes += skb->len;
1793
pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
1794
lp->tx_skbs[lp->tfd_end].skb = NULL;
1795
lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1796
dev_kfree_skb_any(skb);
1798
txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1800
lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1801
txfd = &lp->tfd_base[lp->tfd_end];
1803
if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1804
printk("%s: TxFD FDNext invalid.\n", dev->name);
1808
if (fdnext & FD_Next_EOL) {
1809
/* DMA Transmitter has been stopping... */
1810
if (lp->tfd_end != lp->tfd_start) {
1811
struct tc35815_regs __iomem *tr =
1812
(struct tc35815_regs __iomem *)dev->base_addr;
1813
int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1814
struct TxFD *txhead = &lp->tfd_base[head];
1815
int qlen = (lp->tfd_start + TX_FD_NUM
1816
- lp->tfd_end) % TX_FD_NUM;
1819
if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1820
printk("%s: TxFD FDCtl invalid.\n", dev->name);
1824
/* log max queue length */
1825
if (lp->lstats.max_tx_qlen < qlen)
1826
lp->lstats.max_tx_qlen = qlen;
1829
/* start DMA Transmitter again */
1830
txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1831
txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1832
if (netif_msg_tx_queued(lp)) {
1833
printk("%s: start TxFD on queue.\n",
1837
tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1843
/* If we had stopped the queue due to a "tx full"
1844
* condition, and space has now been made available,
1845
* wake up the queue.
1847
if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
1848
netif_wake_queue(dev);
1851
/* The inverse routine to tc35815_open(). */
1853
tc35815_close(struct net_device *dev)
1855
struct tc35815_local *lp = netdev_priv(dev);
1857
netif_stop_queue(dev);
1858
napi_disable(&lp->napi);
1860
phy_stop(lp->phy_dev);
1861
cancel_work_sync(&lp->restart_work);
1863
/* Flush the Tx and disable Rx here. */
1864
tc35815_chip_reset(dev);
1865
free_irq(dev->irq, dev);
1867
tc35815_free_queues(dev);
1874
* Get the current statistics.
1875
* This may be called with the card open or closed.
1877
static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1879
struct tc35815_regs __iomem *tr =
1880
(struct tc35815_regs __iomem *)dev->base_addr;
1881
if (netif_running(dev))
1882
/* Update the statistics from the device registers. */
1883
dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1888
static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1890
struct tc35815_local *lp = netdev_priv(dev);
1891
struct tc35815_regs __iomem *tr =
1892
(struct tc35815_regs __iomem *)dev->base_addr;
1893
int cam_index = index * 6;
1897
saved_addr = tc_readl(&tr->CAM_Adr);
1899
if (netif_msg_hw(lp))
1900
printk(KERN_DEBUG "%s: CAM %d: %pM\n",
1901
dev->name, index, addr);
1903
/* read modify write */
1904
tc_writel(cam_index - 2, &tr->CAM_Adr);
1905
cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1906
cam_data |= addr[0] << 8 | addr[1];
1907
tc_writel(cam_data, &tr->CAM_Data);
1908
/* write whole word */
1909
tc_writel(cam_index + 2, &tr->CAM_Adr);
1910
cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1911
tc_writel(cam_data, &tr->CAM_Data);
1913
/* write whole word */
1914
tc_writel(cam_index, &tr->CAM_Adr);
1915
cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1916
tc_writel(cam_data, &tr->CAM_Data);
1917
/* read modify write */
1918
tc_writel(cam_index + 4, &tr->CAM_Adr);
1919
cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1920
cam_data |= addr[4] << 24 | (addr[5] << 16);
1921
tc_writel(cam_data, &tr->CAM_Data);
1924
tc_writel(saved_addr, &tr->CAM_Adr);
1929
* Set or clear the multicast filter for this adaptor.
1930
* num_addrs == -1 Promiscuous mode, receive all packets
1931
* num_addrs == 0 Normal mode, clear multicast list
1932
* num_addrs > 0 Multicast mode, receive normal and MC packets,
1933
* and do best-effort filtering.
1936
tc35815_set_multicast_list(struct net_device *dev)
1938
struct tc35815_regs __iomem *tr =
1939
(struct tc35815_regs __iomem *)dev->base_addr;
1941
if (dev->flags & IFF_PROMISC) {
1942
/* With some (all?) 100MHalf HUB, controller will hang
1943
* if we enabled promiscuous mode before linkup... */
1944
struct tc35815_local *lp = netdev_priv(dev);
1948
/* Enable promiscuous mode */
1949
tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1950
} else if ((dev->flags & IFF_ALLMULTI) ||
1951
netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
1952
/* CAM 0, 1, 20 are reserved. */
1953
/* Disable promiscuous mode, use normal mode. */
1954
tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1955
} else if (!netdev_mc_empty(dev)) {
1956
struct netdev_hw_addr *ha;
1958
int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1960
tc_writel(0, &tr->CAM_Ctl);
1961
/* Walk the address list, and load the filter */
1963
netdev_for_each_mc_addr(ha, dev) {
1964
/* entry 0,1 is reserved. */
1965
tc35815_set_cam_entry(dev, i + 2, ha->addr);
1966
ena_bits |= CAM_Ena_Bit(i + 2);
1969
tc_writel(ena_bits, &tr->CAM_Ena);
1970
tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1972
tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1973
tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1977
static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1979
struct tc35815_local *lp = netdev_priv(dev);
1980
strcpy(info->driver, MODNAME);
1981
strcpy(info->version, DRV_VERSION);
1982
strcpy(info->bus_info, pci_name(lp->pci_dev));
1985
static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1987
struct tc35815_local *lp = netdev_priv(dev);
1991
return phy_ethtool_gset(lp->phy_dev, cmd);
1994
static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1996
struct tc35815_local *lp = netdev_priv(dev);
2000
return phy_ethtool_sset(lp->phy_dev, cmd);
2003
static u32 tc35815_get_msglevel(struct net_device *dev)
2005
struct tc35815_local *lp = netdev_priv(dev);
2006
return lp->msg_enable;
2009
static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2011
struct tc35815_local *lp = netdev_priv(dev);
2012
lp->msg_enable = datum;
2015
static int tc35815_get_sset_count(struct net_device *dev, int sset)
2017
struct tc35815_local *lp = netdev_priv(dev);
2021
return sizeof(lp->lstats) / sizeof(int);
2027
static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2029
struct tc35815_local *lp = netdev_priv(dev);
2030
data[0] = lp->lstats.max_tx_qlen;
2031
data[1] = lp->lstats.tx_ints;
2032
data[2] = lp->lstats.rx_ints;
2033
data[3] = lp->lstats.tx_underrun;
2037
const char str[ETH_GSTRING_LEN];
2038
} ethtool_stats_keys[] = {
2045
static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2047
memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2050
static const struct ethtool_ops tc35815_ethtool_ops = {
2051
.get_drvinfo = tc35815_get_drvinfo,
2052
.get_settings = tc35815_get_settings,
2053
.set_settings = tc35815_set_settings,
2054
.get_link = ethtool_op_get_link,
2055
.get_msglevel = tc35815_get_msglevel,
2056
.set_msglevel = tc35815_set_msglevel,
2057
.get_strings = tc35815_get_strings,
2058
.get_sset_count = tc35815_get_sset_count,
2059
.get_ethtool_stats = tc35815_get_ethtool_stats,
2062
static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2064
struct tc35815_local *lp = netdev_priv(dev);
2066
if (!netif_running(dev))
2070
return phy_mii_ioctl(lp->phy_dev, rq, cmd);
2073
static void tc35815_chip_reset(struct net_device *dev)
2075
struct tc35815_regs __iomem *tr =
2076
(struct tc35815_regs __iomem *)dev->base_addr;
2078
/* reset the controller */
2079
tc_writel(MAC_Reset, &tr->MAC_Ctl);
2080
udelay(4); /* 3200ns */
2082
while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2084
printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2089
tc_writel(0, &tr->MAC_Ctl);
2091
/* initialize registers to default value */
2092
tc_writel(0, &tr->DMA_Ctl);
2093
tc_writel(0, &tr->TxThrsh);
2094
tc_writel(0, &tr->TxPollCtr);
2095
tc_writel(0, &tr->RxFragSize);
2096
tc_writel(0, &tr->Int_En);
2097
tc_writel(0, &tr->FDA_Bas);
2098
tc_writel(0, &tr->FDA_Lim);
2099
tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2100
tc_writel(0, &tr->CAM_Ctl);
2101
tc_writel(0, &tr->Tx_Ctl);
2102
tc_writel(0, &tr->Rx_Ctl);
2103
tc_writel(0, &tr->CAM_Ena);
2104
(void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2106
/* initialize internal SRAM */
2107
tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2108
for (i = 0; i < 0x1000; i += 4) {
2109
tc_writel(i, &tr->CAM_Adr);
2110
tc_writel(0, &tr->CAM_Data);
2112
tc_writel(0, &tr->DMA_Ctl);
2115
static void tc35815_chip_init(struct net_device *dev)
2117
struct tc35815_local *lp = netdev_priv(dev);
2118
struct tc35815_regs __iomem *tr =
2119
(struct tc35815_regs __iomem *)dev->base_addr;
2120
unsigned long txctl = TX_CTL_CMD;
2122
/* load station address to CAM */
2123
tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2125
/* Enable CAM (broadcast and unicast) */
2126
tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2127
tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2129
/* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2130
if (HAVE_DMA_RXALIGN(lp))
2131
tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2133
tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2134
tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2135
tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2136
tc_writel(INT_EN_CMD, &tr->Int_En);
2139
tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2140
tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2143
* Activation method:
2144
* First, enable the MAC Transmitter and the DMA Receive circuits.
2145
* Then enable the DMA Transmitter and the MAC Receive circuits.
2147
tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
2148
tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
2150
/* start MAC transmitter */
2151
/* TX4939 does not have EnLCarr */
2152
if (lp->chiptype == TC35815_TX4939)
2153
txctl &= ~Tx_EnLCarr;
2154
/* WORKAROUND: ignore LostCrS in full duplex operation */
2155
if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
2156
txctl &= ~Tx_EnLCarr;
2157
tc_writel(txctl, &tr->Tx_Ctl);
2161
static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2163
struct net_device *dev = pci_get_drvdata(pdev);
2164
struct tc35815_local *lp = netdev_priv(dev);
2165
unsigned long flags;
2167
pci_save_state(pdev);
2168
if (!netif_running(dev))
2170
netif_device_detach(dev);
2172
phy_stop(lp->phy_dev);
2173
spin_lock_irqsave(&lp->lock, flags);
2174
tc35815_chip_reset(dev);
2175
spin_unlock_irqrestore(&lp->lock, flags);
2176
pci_set_power_state(pdev, PCI_D3hot);
2180
static int tc35815_resume(struct pci_dev *pdev)
2182
struct net_device *dev = pci_get_drvdata(pdev);
2183
struct tc35815_local *lp = netdev_priv(dev);
2185
pci_restore_state(pdev);
2186
if (!netif_running(dev))
2188
pci_set_power_state(pdev, PCI_D0);
2189
tc35815_restart(dev);
2190
netif_carrier_off(dev);
2192
phy_start(lp->phy_dev);
2193
netif_device_attach(dev);
2196
#endif /* CONFIG_PM */
2198
static struct pci_driver tc35815_pci_driver = {
2200
.id_table = tc35815_pci_tbl,
2201
.probe = tc35815_init_one,
2202
.remove = __devexit_p(tc35815_remove_one),
2204
.suspend = tc35815_suspend,
2205
.resume = tc35815_resume,
2209
module_param_named(speed, options.speed, int, 0);
2210
MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2211
module_param_named(duplex, options.duplex, int, 0);
2212
MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2214
static int __init tc35815_init_module(void)
2216
return pci_register_driver(&tc35815_pci_driver);
2219
static void __exit tc35815_cleanup_module(void)
2221
pci_unregister_driver(&tc35815_pci_driver);
2224
module_init(tc35815_init_module);
2225
module_exit(tc35815_cleanup_module);
2227
MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2228
MODULE_LICENSE("GPL");
added
removed
drivers/net/ethernet/toshiba/tc35815.c
